From afb5e0d13cd8981320368cd5dbff156e48bcb6b4 Mon Sep 17 00:00:00 2001 From: Darius Rad Date: Mon, 22 Apr 2019 13:55:36 -0400 Subject: [PATCH] Update compiled output. --- src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkBht.v | 2 +- src_SSITH_P3/Verilog_RTL/mkCore.v | 13390 ++++++++-------- src_SSITH_P3/Verilog_RTL/mkCoreW.v | 52 +- src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDebug_Module.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDirPredictor.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDivExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v | 4050 ++++- src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v | 2054 ++- src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v | 5598 ++++++- src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/Verilog_RTL/mkEpochManager.v | 2 +- src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v | 2 +- src_SSITH_P3/Verilog_RTL/mkFetchStage.v | 12 +- src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v | 2 +- .../Verilog_RTL/mkFpuMulDivDispToRegFifo.v | 2 +- .../Verilog_RTL/mkFpuMulDivRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSelectPred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSharePred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkICoCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkITlb.v | 2 +- src_SSITH_P3/Verilog_RTL/mkL2Tlb.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLLCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLLPipeline.v | 140 +- src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMMIOInst.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemLoader.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMulExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkNullTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkP3_Core.v | 8 +- src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v | 2 +- src_SSITH_P3/Verilog_RTL/mkProc.v | 46 +- src_SSITH_P3/Verilog_RTL/mkRFileSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRas.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v | 2 +- .../Verilog_RTL/mkReorderBufferSynth.v | 2 +- .../Verilog_RTL/mkReservationStationAlu.v | 132 +- .../mkReservationStationFpuMulDiv.v | 2 +- .../Verilog_RTL/mkReservationStationMem.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSoC_Map.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourPred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v | 2 +- src_SSITH_P3/Verilog_RTL/module_alu.v | 2 +- src_SSITH_P3/Verilog_RTL/module_aluBr.v | 2 +- src_SSITH_P3/Verilog_RTL/module_amoExec.v | 2 +- src_SSITH_P3/Verilog_RTL/module_basicExec.v | 2 +- src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v | 2 +- .../Verilog_RTL/module_checkForException.v | 2 +- src_SSITH_P3/Verilog_RTL/module_decode.v | 2 +- .../Verilog_RTL/module_decodeBrPred.v | 2 +- .../Verilog_RTL/module_execFpuSimple.v | 2 +- .../Verilog_RTL/module_getControlFlow.v | 2 +- .../xilinx_ip/hdl/mkAluDispToRegFifo.v | 2 +- .../xilinx_ip/hdl/mkAluExeToFinFifo.v | 2 +- .../xilinx_ip/hdl/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkBht.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 13390 ++++++++-------- src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v | 52 +- .../xilinx_ip/hdl/mkDCRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v | 2 +- .../xilinx_ip/hdl/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v | 4050 ++++- src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v | 2054 ++- src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v | 5598 ++++++- .../xilinx_ip/hdl/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v | 12 +- src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v | 2 +- .../xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v | 2 +- .../xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v | 2 +- .../xilinx_ip/hdl/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v | 2 +- .../xilinx_ip/hdl/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v | 2 +- .../xilinx_ip/hdl/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkITlb.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v | 140 +- src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v | 2 +- .../xilinx_ip/hdl/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v | 2 +- .../xilinx_ip/hdl/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v | 8 +- src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 46 +- src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkRas.v | 2 +- .../xilinx_ip/hdl/mkRegRenamingTable.v | 2 +- .../xilinx_ip/hdl/mkReorderBufferSynth.v | 2 +- .../xilinx_ip/hdl/mkReservationStationAlu.v | 132 +- .../hdl/mkReservationStationFpuMulDiv.v | 2 +- .../xilinx_ip/hdl/mkReservationStationMem.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v | 2 +- .../xilinx_ip/hdl/mkSplitTransCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_alu.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v | 2 +- .../xilinx_ip/hdl/module_brAddrCalc.v | 2 +- .../xilinx_ip/hdl/module_checkForException.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_decode.v | 2 +- .../xilinx_ip/hdl/module_decodeBrPred.v | 2 +- .../xilinx_ip/hdl/module_execFpuSimple.v | 2 +- .../xilinx_ip/hdl/module_getControlFlow.v | 2 +- 158 files changed, 37132 insertions(+), 14108 deletions(-) diff --git a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v index 7aac7c0..71be41e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v index 580b173..b9fa4af 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v index a4c7e30..e1e9a5b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkBht.v b/src_SSITH_P3/Verilog_RTL/mkBht.v index bbc0dff..d689f0a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL/mkBht.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 8457547..0165684 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -3939,7 +3939,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3, @@ -4028,7 +4028,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_4, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -4060,33 +4060,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287286, - curData__h190136, - rVal1__h605865, - rVal1__h629397, - trap_val__h693211, - x__h194346; + addr__h287289, + curData__h190139, + rVal1__h605870, + rVal1__h629405, + trap_val__h693220, + x__h194349; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211, - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212, - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209, - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210, - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197, - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198, - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199, - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200, - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201, - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202, - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213, - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214, - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215, - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216, - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217, - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218, - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207, - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208, + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211, + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212, + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209, + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210, + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197, + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198, + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199, + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200, + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201, + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202, + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213, + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214, + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215, + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216, + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217, + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218, + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207, + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624, @@ -4098,45 +4098,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78, - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79, - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80, - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81, - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111, - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112, - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41, - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42, - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109, - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110, - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39, - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40, - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113, - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114, - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43, - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44, - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115, - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116, - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45, - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46, - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76, - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77, - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74, - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75, - _theResult___fst_sfd__h343282, - _theResult___fst_sfd__h352005, - _theResult___fst_sfd__h360587, - _theResult___fst_sfd__h369771, - _theResult___fst_sfd__h378407, - _theResult___fst_sfd__h388974, - _theResult___fst_sfd__h397695, - _theResult___fst_sfd__h406277, - _theResult___fst_sfd__h415461, - _theResult___fst_sfd__h424097, - _theResult___fst_sfd__h434662, - _theResult___fst_sfd__h443383, - _theResult___fst_sfd__h451965, - _theResult___fst_sfd__h461149, - _theResult___fst_sfd__h469785; + reg [22 : 0] CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78, + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79, + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80, + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81, + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111, + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112, + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41, + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42, + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109, + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110, + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39, + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40, + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113, + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114, + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43, + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44, + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115, + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116, + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45, + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46, + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76, + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77, + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74, + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75, + _theResult___fst_sfd__h343285, + _theResult___fst_sfd__h352008, + _theResult___fst_sfd__h360590, + _theResult___fst_sfd__h369774, + _theResult___fst_sfd__h378410, + _theResult___fst_sfd__h388977, + _theResult___fst_sfd__h397698, + _theResult___fst_sfd__h406280, + _theResult___fst_sfd__h415464, + _theResult___fst_sfd__h424100, + _theResult___fst_sfd__h434665, + _theResult___fst_sfd__h443386, + _theResult___fst_sfd__h451968, + _theResult___fst_sfd__h461152, + _theResult___fst_sfd__h469788; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4160,24 +4160,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203, - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204, - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205, - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206, - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175, - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176, - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177, - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178, - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179, - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180, - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152, - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153, - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183, - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184, - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181, - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182, - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135, - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136, + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203, + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204, + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205, + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206, + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175, + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176, + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177, + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178, + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179, + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180, + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152, + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153, + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183, + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184, + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181, + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182, + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135, + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553, @@ -4187,47 +4187,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790; - reg [7 : 0] CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67, - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68, - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72, - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73, - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96, - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97, - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26, - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27, - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94, - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95, - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24, - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25, - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102, - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103, - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32, - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33, - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107, - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108, - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37, - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38, - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61, - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62, - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59, - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60, + reg [7 : 0] CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67, + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68, + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72, + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73, + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96, + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97, + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26, + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27, + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94, + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95, + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24, + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25, + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102, + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103, + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32, + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33, + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107, + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108, + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37, + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38, + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61, + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62, + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59, + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343281, - _theResult___fst_exp__h352004, - _theResult___fst_exp__h360586, - _theResult___fst_exp__h369770, - _theResult___fst_exp__h378406, - _theResult___fst_exp__h388973, - _theResult___fst_exp__h397694, - _theResult___fst_exp__h406276, - _theResult___fst_exp__h415460, - _theResult___fst_exp__h424096, - _theResult___fst_exp__h434661, - _theResult___fst_exp__h443382, - _theResult___fst_exp__h451964, - _theResult___fst_exp__h461148, - _theResult___fst_exp__h469784; + _theResult___fst_exp__h343284, + _theResult___fst_exp__h352007, + _theResult___fst_exp__h360589, + _theResult___fst_exp__h369773, + _theResult___fst_exp__h378409, + _theResult___fst_exp__h388976, + _theResult___fst_exp__h397697, + _theResult___fst_exp__h406279, + _theResult___fst_exp__h415463, + _theResult___fst_exp__h424099, + _theResult___fst_exp__h434664, + _theResult___fst_exp__h443385, + _theResult___fst_exp__h451967, + _theResult___fst_exp__h461151, + _theResult___fst_exp__h469787; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262, @@ -4238,15 +4238,15 @@ module mkCore(CLK, CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995, - i__h692195, - i__h692355; + i__h692204, + i__h692364; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266, @@ -4260,8 +4260,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695, - x__h283065, - x__h288835; + x__h283068, + x__h288838; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, @@ -4292,46 +4292,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, @@ -4448,152 +4448,152 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663, - _theResult___fst__h600257, - _theResult___snd__h600258, - a___1__h599976, - a___1__h600262, - a__h599835, + _theResult___fst__h600261, + _theResult___snd__h600262, + a___1__h599980, + a___1__h600266, + a__h599839, amoExec___d880, - b___1__h599977, - b___1__h600307, - b__h599836, - base__h694782, - base__h694985, - data___1__h472204, - data___1__h473012, - data__h472478, - fcsr_csr__read__h606143, - fflags_csr__read__h606118, - frm_csr__read__h606129, - mcause_csr__read__h607790, - mcounteren_csr__read__h607535, - medeleg_csr__read__h607135, - mideleg_csr__read__h607230, - mie_csr__read__h607361, - mip_csr__read__h608030, - mstatus_csr__read__h606987, - mtvec_csr__read__h607443, - n___1__h195749, - n__h191674, - n__read__h608134, - n__read__h608325, + b___1__h599981, + b___1__h600311, + b__h599840, + base__h694791, + base__h694994, + data___1__h472207, + data___1__h473015, + data__h472481, + fcsr_csr__read__h606148, + fflags_csr__read__h606123, + frm_csr__read__h606134, + mcause_csr__read__h607795, + mcounteren_csr__read__h607540, + medeleg_csr__read__h607140, + mideleg_csr__read__h607235, + mie_csr__read__h607366, + mip_csr__read__h608035, + mstatus_csr__read__h606992, + mtvec_csr__read__h607448, + n___1__h195752, + n__h191677, + n__read__h608139, + n__read__h608330, n__read__h6134, - n__read__h703190, - next_pc__h702533, - q___1__h473077, - rVal1__h478957, - rVal2__h478958, - r___1__h473103, - res_data__h335086, - res_data__h335091, - res_data__h380781, - res_data__h380786, - res_data__h426469, - res_data__h426474, - resp_addr__h289190, + n__read__h703199, + next_pc__h702542, + q___1__h473080, + rVal1__h478961, + rVal2__h478962, + r___1__h473106, + res_data__h335089, + res_data__h335094, + res_data__h380784, + res_data__h380789, + res_data__h426472, + res_data__h426477, + resp_addr__h289193, robdeqPort_0_deq_data_BITS_95_TO_32__q261, - satp_csr__read__h606844, - scause_csr__read__h606642, - scounteren_csr__read__h606504, - shiftData__h180513, - sie_csr__read__h606408, - sip_csr__read__h606781, - sstatus_csr__read__h606339, - stvec_csr__read__h606451, + satp_csr__read__h606849, + scause_csr__read__h606647, + scounteren_csr__read__h606509, + shiftData__h180516, + sie_csr__read__h606413, + sip_csr__read__h606786, + sstatus_csr__read__h606344, + stvec_csr__read__h606456, upd__h3639, upd__h4956, - v__h604750, - v__h628436, - vaddr__h180508, - x__h152889, - x__h156436, - x__h159250, - x__h161098, + v__h604754, + v__h628444, + vaddr__h180511, + x__h152890, + x__h156437, + x__h159251, + x__h161099, x__h17672, - x__h180422, - x__h180423, + x__h180425, + x__h180426, x__h20210, - x__h284510, - x__h286364, + x__h284513, + x__h286367, x__h45579, - x__h478866, - x__h478867, - x__h478868, + x__h478870, + x__h478871, + x__h478872, x__h48115, - x__h613028, - x__h613029, - x__h634247, - x__h634248, - x__h688716, - x_addr__h311294, - x_quotient__h472392, - x_reg_ifc__read__h606248, - x_remainder__h472393, - y__h705641, - y_avValue__h179510, - y_avValue__h180116, - y_avValue__h476002, - y_avValue__h476610, - y_avValue__h477212, - y_avValue__h605655, - y_avValue__h610917, - y_avValue__h629189, - y_avValue__h632146, - y_avValue__h693058, - y_avValue__h694819, - y_avValue_snd_snd_snd_snd_snd__h705141, - y_avValue_snd_snd_snd_snd_snd__h705694, - y_avValue_snd_snd_snd_snd_snd__h705723; + x__h613033, + x__h613034, + x__h634256, + x__h634257, + x__h688725, + x_addr__h311296, + x_quotient__h472395, + x_reg_ifc__read__h606253, + x_remainder__h472396, + y__h705650, + y_avValue__h179513, + y_avValue__h180119, + y_avValue__h476006, + y_avValue__h476614, + y_avValue__h477216, + y_avValue__h605660, + y_avValue__h610922, + y_avValue__h629197, + y_avValue__h632155, + y_avValue__h693067, + y_avValue__h694828, + y_avValue_snd_snd_snd_snd_snd__h705150, + y_avValue_snd_snd_snd_snd_snd__h705703, + y_avValue_snd_snd_snd_snd_snd__h705732; wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869, - r1__read__h608832, - r1__read__h609236, - r1__read__h609766, + r1__read__h608837, + r1__read__h609241, r1__read__h609771, - r1__read__h609790, - r1__read__h610043, - r1__read__h610221, - r1__read__h610339, + r1__read__h609776, + r1__read__h609795, + r1__read__h610048, + r1__read__h610226, r1__read__h610344, - r1__read__h610363; - wire [61 : 0] r1__read__h608834, - r1__read__h609238, - r1__read__h609773, - r1__read__h609792, - r1__read__h610045, - r1__read__h610197, - r1__read__h610223, - r1__read__h610346, - r1__read__h610365; - wire [60 : 0] r1__read__h610047, - r1__read__h610199, - r1__read__h610225, - r1__read__h610367; - wire [59 : 0] r1__read__h608836, - r1__read__h609240, - r1__read__h609784, - r1__read__h609794, - r1__read__h610049, - r1__read__h610227, - r1__read__h610357, - r1__read__h610369; - wire [58 : 0] r1__read__h608838, - r1__read__h609242, - r1__read__h609796, - r1__read__h610051, - r1__read__h610229, - r1__read__h610371; + r1__read__h610349, + r1__read__h610368; + wire [61 : 0] r1__read__h608839, + r1__read__h609243, + r1__read__h609778, + r1__read__h609797, + r1__read__h610050, + r1__read__h610202, + r1__read__h610228, + r1__read__h610351, + r1__read__h610370; + wire [60 : 0] r1__read__h610052, + r1__read__h610204, + r1__read__h610230, + r1__read__h610372; + wire [59 : 0] r1__read__h608841, + r1__read__h609245, + r1__read__h609789, + r1__read__h609799, + r1__read__h610054, + r1__read__h610232, + r1__read__h610362, + r1__read__h610374; + wire [58 : 0] r1__read__h608843, + r1__read__h609247, + r1__read__h609801, + r1__read__h610056, + r1__read__h610234, + r1__read__h610376; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h608840, - r1__read__h609244, - r1__read__h609798, - r1__read__h610053, - r1__read__h610201, - r1__read__h610231, - r1__read__h610373, - y__h252023; + r1__read__h608845, + r1__read__h609249, + r1__read__h609803, + r1__read__h610058, + r1__read__h610206, + r1__read__h610236, + r1__read__h610378, + y__h252026; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90, @@ -4621,187 +4621,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355, - _theResult____h343299, - _theResult____h360938, - _theResult____h388991, - _theResult____h406628, - _theResult____h434679, - _theResult____h452316, - _theResult____h500013, - _theResult____h538814, - _theResult____h578015, - _theResult___snd__h351421, - _theResult___snd__h351432, - _theResult___snd__h351434, - _theResult___snd__h351444, - _theResult___snd__h351450, - _theResult___snd__h351473, - _theResult___snd__h360017, - _theResult___snd__h360019, - _theResult___snd__h360026, - _theResult___snd__h360032, - _theResult___snd__h360055, - _theResult___snd__h369187, - _theResult___snd__h369198, - _theResult___snd__h369200, - _theResult___snd__h369210, - _theResult___snd__h369216, - _theResult___snd__h369239, - _theResult___snd__h377807, - _theResult___snd__h377821, - _theResult___snd__h377827, - _theResult___snd__h377845, - _theResult___snd__h397111, - _theResult___snd__h397122, - _theResult___snd__h397124, - _theResult___snd__h397134, - _theResult___snd__h397140, - _theResult___snd__h397163, - _theResult___snd__h405707, - _theResult___snd__h405709, - _theResult___snd__h405716, - _theResult___snd__h405722, - _theResult___snd__h405745, - _theResult___snd__h414877, - _theResult___snd__h414888, - _theResult___snd__h414890, - _theResult___snd__h414900, - _theResult___snd__h414906, - _theResult___snd__h414929, - _theResult___snd__h423497, - _theResult___snd__h423511, - _theResult___snd__h423517, - _theResult___snd__h423535, - _theResult___snd__h442799, - _theResult___snd__h442810, - _theResult___snd__h442812, - _theResult___snd__h442822, - _theResult___snd__h442828, - _theResult___snd__h442851, - _theResult___snd__h451395, - _theResult___snd__h451397, - _theResult___snd__h451404, - _theResult___snd__h451410, - _theResult___snd__h451433, - _theResult___snd__h460565, - _theResult___snd__h460576, - _theResult___snd__h460578, - _theResult___snd__h460588, - _theResult___snd__h460594, - _theResult___snd__h460617, - _theResult___snd__h469185, - _theResult___snd__h469199, - _theResult___snd__h469205, - _theResult___snd__h469223, - _theResult___snd__h498623, - _theResult___snd__h498625, - _theResult___snd__h498632, - _theResult___snd__h498638, - _theResult___snd__h498661, - _theResult___snd__h508260, - _theResult___snd__h508271, - _theResult___snd__h508273, - _theResult___snd__h508283, - _theResult___snd__h508289, - _theResult___snd__h508312, - _theResult___snd__h517028, - _theResult___snd__h517042, - _theResult___snd__h517048, - _theResult___snd__h517066, - _theResult___snd__h537424, - _theResult___snd__h537426, - _theResult___snd__h537433, - _theResult___snd__h537439, - _theResult___snd__h537462, - _theResult___snd__h547061, - _theResult___snd__h547072, - _theResult___snd__h547074, - _theResult___snd__h547084, - _theResult___snd__h547090, - _theResult___snd__h547113, - _theResult___snd__h555829, - _theResult___snd__h555843, - _theResult___snd__h555849, - _theResult___snd__h555867, - _theResult___snd__h576625, - _theResult___snd__h576627, - _theResult___snd__h576634, - _theResult___snd__h576640, - _theResult___snd__h576663, - _theResult___snd__h586262, - _theResult___snd__h586273, - _theResult___snd__h586275, - _theResult___snd__h586285, - _theResult___snd__h586291, - _theResult___snd__h586314, - _theResult___snd__h595030, - _theResult___snd__h595044, - _theResult___snd__h595050, - _theResult___snd__h595068, - r1__read__h610055, - r1__read__h610203, - r1__read__h610233, - r1__read__h610375, - result__h361551, - result__h407241, - result__h452929, - result__h500626, - result__h539427, - result__h578628, - sfd__h335694, - sfd__h381389, - sfd__h427077, - sfd__h479671, - sfd__h518613, - sfd__h557814, - sfdin__h351404, - sfdin__h369170, - sfdin__h397094, - sfdin__h414860, - sfdin__h442782, - sfdin__h460548, - sfdin__h508243, - sfdin__h547044, - sfdin__h586245, - x__h361648, - x__h407338, - x__h453026, - x__h500721, - x__h539522, - x__h578723; - wire [55 : 0] r1__read__h608842, - r1__read__h609246, - r1__read__h609800, - r1__read__h610057, - r1__read__h610235, - r1__read__h610377; - wire [54 : 0] r1__read__h608844, - r1__read__h609248, - r1__read__h609802, - r1__read__h610059, - r1__read__h610237, - r1__read__h610379; - wire [53 : 0] r1__read__h610180, - r1__read__h610205, - r1__read__h610239, - r1__read__h610381, - sfd__h498690, - sfd__h508341, - sfd__h517101, - sfd__h537491, - sfd__h547142, - sfd__h555902, - sfd__h576692, - sfd__h586343, - sfd__h595103, - value__h343921, - value__h389611, - value__h435299; - wire [52 : 0] r1__read__h610061, - r1__read__h610182, - r1__read__h610207, - r1__read__h610241, - r1__read__h610383; + _theResult____h343302, + _theResult____h360941, + _theResult____h388994, + _theResult____h406631, + _theResult____h434682, + _theResult____h452319, + _theResult____h500017, + _theResult____h538818, + _theResult____h578019, + _theResult___snd__h351424, + _theResult___snd__h351435, + _theResult___snd__h351437, + _theResult___snd__h351447, + _theResult___snd__h351453, + _theResult___snd__h351476, + _theResult___snd__h360020, + _theResult___snd__h360022, + _theResult___snd__h360029, + _theResult___snd__h360035, + _theResult___snd__h360058, + _theResult___snd__h369190, + _theResult___snd__h369201, + _theResult___snd__h369203, + _theResult___snd__h369213, + _theResult___snd__h369219, + _theResult___snd__h369242, + _theResult___snd__h377810, + _theResult___snd__h377824, + _theResult___snd__h377830, + _theResult___snd__h377848, + _theResult___snd__h397114, + _theResult___snd__h397125, + _theResult___snd__h397127, + _theResult___snd__h397137, + _theResult___snd__h397143, + _theResult___snd__h397166, + _theResult___snd__h405710, + _theResult___snd__h405712, + _theResult___snd__h405719, + _theResult___snd__h405725, + _theResult___snd__h405748, + _theResult___snd__h414880, + _theResult___snd__h414891, + _theResult___snd__h414893, + _theResult___snd__h414903, + _theResult___snd__h414909, + _theResult___snd__h414932, + _theResult___snd__h423500, + _theResult___snd__h423514, + _theResult___snd__h423520, + _theResult___snd__h423538, + _theResult___snd__h442802, + _theResult___snd__h442813, + _theResult___snd__h442815, + _theResult___snd__h442825, + _theResult___snd__h442831, + _theResult___snd__h442854, + _theResult___snd__h451398, + _theResult___snd__h451400, + _theResult___snd__h451407, + _theResult___snd__h451413, + _theResult___snd__h451436, + _theResult___snd__h460568, + _theResult___snd__h460579, + _theResult___snd__h460581, + _theResult___snd__h460591, + _theResult___snd__h460597, + _theResult___snd__h460620, + _theResult___snd__h469188, + _theResult___snd__h469202, + _theResult___snd__h469208, + _theResult___snd__h469226, + _theResult___snd__h498627, + _theResult___snd__h498629, + _theResult___snd__h498636, + _theResult___snd__h498642, + _theResult___snd__h498665, + _theResult___snd__h508264, + _theResult___snd__h508275, + _theResult___snd__h508277, + _theResult___snd__h508287, + _theResult___snd__h508293, + _theResult___snd__h508316, + _theResult___snd__h517032, + _theResult___snd__h517046, + _theResult___snd__h517052, + _theResult___snd__h517070, + _theResult___snd__h537428, + _theResult___snd__h537430, + _theResult___snd__h537437, + _theResult___snd__h537443, + _theResult___snd__h537466, + _theResult___snd__h547065, + _theResult___snd__h547076, + _theResult___snd__h547078, + _theResult___snd__h547088, + _theResult___snd__h547094, + _theResult___snd__h547117, + _theResult___snd__h555833, + _theResult___snd__h555847, + _theResult___snd__h555853, + _theResult___snd__h555871, + _theResult___snd__h576629, + _theResult___snd__h576631, + _theResult___snd__h576638, + _theResult___snd__h576644, + _theResult___snd__h576667, + _theResult___snd__h586266, + _theResult___snd__h586277, + _theResult___snd__h586279, + _theResult___snd__h586289, + _theResult___snd__h586295, + _theResult___snd__h586318, + _theResult___snd__h595034, + _theResult___snd__h595048, + _theResult___snd__h595054, + _theResult___snd__h595072, + r1__read__h610060, + r1__read__h610208, + r1__read__h610238, + r1__read__h610380, + result__h361554, + result__h407244, + result__h452932, + result__h500630, + result__h539431, + result__h578632, + sfd__h335697, + sfd__h381392, + sfd__h427080, + sfd__h479675, + sfd__h518617, + sfd__h557818, + sfdin__h351407, + sfdin__h369173, + sfdin__h397097, + sfdin__h414863, + sfdin__h442785, + sfdin__h460551, + sfdin__h508247, + sfdin__h547048, + sfdin__h586249, + x__h361651, + x__h407341, + x__h453029, + x__h500725, + x__h539526, + x__h578727; + wire [55 : 0] r1__read__h608847, + r1__read__h609251, + r1__read__h609805, + r1__read__h610062, + r1__read__h610240, + r1__read__h610382; + wire [54 : 0] r1__read__h608849, + r1__read__h609253, + r1__read__h609807, + r1__read__h610064, + r1__read__h610242, + r1__read__h610384; + wire [53 : 0] r1__read__h610185, + r1__read__h610210, + r1__read__h610244, + r1__read__h610386, + sfd__h498694, + sfd__h508345, + sfd__h517105, + sfd__h537495, + sfd__h547146, + sfd__h555906, + sfd__h576696, + sfd__h586347, + sfd__h595107, + value__h343924, + value__h389614, + value__h435302; + wire [52 : 0] r1__read__h610066, + r1__read__h610187, + r1__read__h610212, + r1__read__h610246, + r1__read__h610388; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132, @@ -4820,110 +4820,110 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857, - _theResult___fst_sfd__h483600, - _theResult___fst_sfd__h499428, - _theResult___fst_sfd__h499431, - _theResult___fst_sfd__h509079, - _theResult___fst_sfd__h509082, - _theResult___fst_sfd__h517863, - _theResult___fst_sfd__h517866, - _theResult___fst_sfd__h517875, - _theResult___fst_sfd__h517881, - _theResult___fst_sfd__h522401, - _theResult___fst_sfd__h538229, - _theResult___fst_sfd__h538232, - _theResult___fst_sfd__h547880, - _theResult___fst_sfd__h547883, - _theResult___fst_sfd__h556664, - _theResult___fst_sfd__h556667, - _theResult___fst_sfd__h556676, - _theResult___fst_sfd__h556682, - _theResult___fst_sfd__h561602, - _theResult___fst_sfd__h577430, - _theResult___fst_sfd__h577433, - _theResult___fst_sfd__h587081, - _theResult___fst_sfd__h587084, - _theResult___fst_sfd__h595865, - _theResult___fst_sfd__h595868, - _theResult___fst_sfd__h595877, - _theResult___fst_sfd__h595883, - _theResult___sfd__h499328, - _theResult___sfd__h508979, - _theResult___sfd__h517763, - _theResult___sfd__h538129, - _theResult___sfd__h547780, - _theResult___sfd__h556564, - _theResult___sfd__h577330, - _theResult___sfd__h586981, - _theResult___sfd__h595765, - _theResult___snd_fst_sfd__h479625, - _theResult___snd_fst_sfd__h499434, - _theResult___snd_fst_sfd__h517869, - _theResult___snd_fst_sfd__h518567, - _theResult___snd_fst_sfd__h538235, - _theResult___snd_fst_sfd__h556670, - _theResult___snd_fst_sfd__h557768, - _theResult___snd_fst_sfd__h577436, - _theResult___snd_fst_sfd__h595871, - out___1_sfd__h479374, - out___1_sfd__h518316, - out___1_sfd__h557517, - out_sfd__h499331, - out_sfd__h508982, - out_sfd__h517766, - out_sfd__h538132, - out_sfd__h547783, - out_sfd__h556567, - out_sfd__h577333, - out_sfd__h586984, - out_sfd__h595768, - r1__read__h610385; - wire [50 : 0] r1__read__h608846, r1__read__h610063; - wire [49 : 0] r1__read__h610184, r1__read__h610387; - wire [48 : 0] r1__read__h608848, r1__read__h610065, r1__read__h610186; - wire [46 : 0] r1__read__h608850, r1__read__h610067; - wire [45 : 0] r1__read__h608852, r1__read__h610069; - wire [44 : 0] r1__read__h608854, r1__read__h610071; - wire [43 : 0] r1__read__h608856, r1__read__h610073; - wire [42 : 0] r1__read__h610075; - wire [41 : 0] r1__read__h610077; - wire [40 : 0] r1__read__h610079; + _theResult___fst_sfd__h483604, + _theResult___fst_sfd__h499432, + _theResult___fst_sfd__h499435, + _theResult___fst_sfd__h509083, + _theResult___fst_sfd__h509086, + _theResult___fst_sfd__h517867, + _theResult___fst_sfd__h517870, + _theResult___fst_sfd__h517879, + _theResult___fst_sfd__h517885, + _theResult___fst_sfd__h522405, + _theResult___fst_sfd__h538233, + _theResult___fst_sfd__h538236, + _theResult___fst_sfd__h547884, + _theResult___fst_sfd__h547887, + _theResult___fst_sfd__h556668, + _theResult___fst_sfd__h556671, + _theResult___fst_sfd__h556680, + _theResult___fst_sfd__h556686, + _theResult___fst_sfd__h561606, + _theResult___fst_sfd__h577434, + _theResult___fst_sfd__h577437, + _theResult___fst_sfd__h587085, + _theResult___fst_sfd__h587088, + _theResult___fst_sfd__h595869, + _theResult___fst_sfd__h595872, + _theResult___fst_sfd__h595881, + _theResult___fst_sfd__h595887, + _theResult___sfd__h499332, + _theResult___sfd__h508983, + _theResult___sfd__h517767, + _theResult___sfd__h538133, + _theResult___sfd__h547784, + _theResult___sfd__h556568, + _theResult___sfd__h577334, + _theResult___sfd__h586985, + _theResult___sfd__h595769, + _theResult___snd_fst_sfd__h479629, + _theResult___snd_fst_sfd__h499438, + _theResult___snd_fst_sfd__h517873, + _theResult___snd_fst_sfd__h518571, + _theResult___snd_fst_sfd__h538239, + _theResult___snd_fst_sfd__h556674, + _theResult___snd_fst_sfd__h557772, + _theResult___snd_fst_sfd__h577440, + _theResult___snd_fst_sfd__h595875, + out___1_sfd__h479378, + out___1_sfd__h518320, + out___1_sfd__h557521, + out_sfd__h499335, + out_sfd__h508986, + out_sfd__h517770, + out_sfd__h538136, + out_sfd__h547787, + out_sfd__h556571, + out_sfd__h577337, + out_sfd__h586988, + out_sfd__h595772, + r1__read__h610390; + wire [50 : 0] r1__read__h608851, r1__read__h610068; + wire [49 : 0] r1__read__h610189, r1__read__h610392; + wire [48 : 0] r1__read__h608853, r1__read__h610070, r1__read__h610191; + wire [46 : 0] r1__read__h608855, r1__read__h610072; + wire [45 : 0] r1__read__h608857, r1__read__h610074; + wire [44 : 0] r1__read__h608859, r1__read__h610076; + wire [43 : 0] r1__read__h608861, r1__read__h610078; + wire [42 : 0] r1__read__h610080; + wire [41 : 0] r1__read__h610082; + wire [40 : 0] r1__read__h610084; wire [37 : 0] IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4, - data72478_BITS_31_TO_0__q5, - imm__h649445, - r1__read__h608858, - r1__read__h610081, - x__h190899, - x__h335098, - x__h380793, - x__h426481, + data72481_BITS_31_TO_0__q5, + imm__h649454, + r1__read__h608863, + r1__read__h610086, + x__h190902, + x__h335101, + x__h380796, + x__h426484, x__h75524, x_data__h65373, - x_data_imm__h667940, - x_data_imm__h682683; - wire [29 : 0] r1__read__h608860, r1__read__h610083; - wire [27 : 0] r1__read__h610085; + x_data_imm__h667949, + x_data_imm__h682692; + wire [29 : 0] r1__read__h608865, r1__read__h610088; + wire [27 : 0] r1__read__h610090; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903, - sfd__h351502, - sfd__h360084, - sfd__h369268, - sfd__h377880, - sfd__h397192, - sfd__h405774, - sfd__h414958, - sfd__h423570, - sfd__h442880, - sfd__h451462, - sfd__h460646, - sfd__h469258, - value__h484229, - value__h523030, - value__h562231; + sfd__h351505, + sfd__h360087, + sfd__h369271, + sfd__h377883, + sfd__h397195, + sfd__h405777, + sfd__h414961, + sfd__h423573, + sfd__h442883, + sfd__h451465, + sfd__h460649, + sfd__h469261, + value__h484233, + value__h523034, + value__h562235; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, @@ -4948,72 +4948,72 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352008, - _theResult___fst_sfd__h360590, - _theResult___fst_sfd__h369774, - _theResult___fst_sfd__h378410, - _theResult___fst_sfd__h378419, - _theResult___fst_sfd__h378425, - _theResult___fst_sfd__h397698, - _theResult___fst_sfd__h406280, - _theResult___fst_sfd__h415464, - _theResult___fst_sfd__h424100, - _theResult___fst_sfd__h424109, - _theResult___fst_sfd__h424115, - _theResult___fst_sfd__h443386, - _theResult___fst_sfd__h451968, - _theResult___fst_sfd__h461152, - _theResult___fst_sfd__h469788, - _theResult___fst_sfd__h469797, - _theResult___fst_sfd__h469803, - _theResult___sfd__h351927, - _theResult___sfd__h360509, - _theResult___sfd__h369693, - _theResult___sfd__h378329, - _theResult___sfd__h378431, - _theResult___sfd__h397617, - _theResult___sfd__h406199, - _theResult___sfd__h415383, - _theResult___sfd__h424019, - _theResult___sfd__h424121, - _theResult___sfd__h443305, - _theResult___sfd__h451887, - _theResult___sfd__h461071, - _theResult___sfd__h469707, - _theResult___sfd__h469809, - _theResult___snd_fst_sfd__h335644, - _theResult___snd_fst_sfd__h360593, - _theResult___snd_fst_sfd__h378413, - _theResult___snd_fst_sfd__h381339, - _theResult___snd_fst_sfd__h406283, - _theResult___snd_fst_sfd__h424103, - _theResult___snd_fst_sfd__h427027, - _theResult___snd_fst_sfd__h451971, - _theResult___snd_fst_sfd__h469791, - out_f_sfd__h378708, - out_f_sfd__h424398, - out_f_sfd__h470086, - out_sfd__h351930, - out_sfd__h360512, - out_sfd__h369696, - out_sfd__h378332, - out_sfd__h397620, - out_sfd__h406202, - out_sfd__h415386, - out_sfd__h424022, - out_sfd__h443308, - out_sfd__h451890, - out_sfd__h461074, - out_sfd__h469710; - wire [19 : 0] r1__read__h610020; + _theResult___fst_sfd__h352011, + _theResult___fst_sfd__h360593, + _theResult___fst_sfd__h369777, + _theResult___fst_sfd__h378413, + _theResult___fst_sfd__h378422, + _theResult___fst_sfd__h378428, + _theResult___fst_sfd__h397701, + _theResult___fst_sfd__h406283, + _theResult___fst_sfd__h415467, + _theResult___fst_sfd__h424103, + _theResult___fst_sfd__h424112, + _theResult___fst_sfd__h424118, + _theResult___fst_sfd__h443389, + _theResult___fst_sfd__h451971, + _theResult___fst_sfd__h461155, + _theResult___fst_sfd__h469791, + _theResult___fst_sfd__h469800, + _theResult___fst_sfd__h469806, + _theResult___sfd__h351930, + _theResult___sfd__h360512, + _theResult___sfd__h369696, + _theResult___sfd__h378332, + _theResult___sfd__h378434, + _theResult___sfd__h397620, + _theResult___sfd__h406202, + _theResult___sfd__h415386, + _theResult___sfd__h424022, + _theResult___sfd__h424124, + _theResult___sfd__h443308, + _theResult___sfd__h451890, + _theResult___sfd__h461074, + _theResult___sfd__h469710, + _theResult___sfd__h469812, + _theResult___snd_fst_sfd__h335647, + _theResult___snd_fst_sfd__h360596, + _theResult___snd_fst_sfd__h378416, + _theResult___snd_fst_sfd__h381342, + _theResult___snd_fst_sfd__h406286, + _theResult___snd_fst_sfd__h424106, + _theResult___snd_fst_sfd__h427030, + _theResult___snd_fst_sfd__h451974, + _theResult___snd_fst_sfd__h469794, + out_f_sfd__h378711, + out_f_sfd__h424401, + out_f_sfd__h470089, + out_sfd__h351933, + out_sfd__h360515, + out_sfd__h369699, + out_sfd__h378335, + out_sfd__h397623, + out_sfd__h406205, + out_sfd__h415389, + out_sfd__h424025, + out_sfd__h443311, + out_sfd__h451893, + out_sfd__h461077, + out_sfd__h469713; + wire [19 : 0] r1__read__h610025; wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674, - _theResult____h645389, - enabled_ints___1__h645886, - enabled_ints__h645933, - pend_ints__h645387, - y__h645898; + _theResult____h645398, + enabled_ints___1__h645895, + enabled_ints__h645942, + pend_ints__h645396, + y__h645907; wire [12 : 0] fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - r1__read_BITS_12_TO_0___h645909; + r1__read_BITS_12_TO_0___h645918; wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648, @@ -5043,24 +5043,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h675339, - result__h641096, - result__h641147, - spec_bits__h678434, - w__h641091, - x__h361681, - x__h407371, - x__h453059, - x__h500754, - x__h539555, - x__h578756, - x__h641095, - x__h641146, - y__h641125, - y__h678447, - y_avValue_fst__h671831, - y_avValue_snd_fst__h672105, - y_avValue_snd_fst__h672140; + renaming_spec_bits__h675348, + result__h641105, + result__h641156, + spec_bits__h678443, + w__h641100, + x__h361684, + x__h407374, + x__h453062, + x__h500758, + x__h539559, + x__h578760, + x__h641104, + x__h641155, + y__h641134, + y__h678456, + y_avValue_fst__h671840, + y_avValue_snd_fst__h672114, + y_avValue_snd_fst__h672149; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048, @@ -5082,103 +5082,103 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172, - _theResult___exp__h499327, - _theResult___exp__h508978, - _theResult___exp__h517762, - _theResult___exp__h538128, - _theResult___exp__h547779, - _theResult___exp__h556563, - _theResult___exp__h577329, - _theResult___exp__h586980, - _theResult___exp__h595764, - _theResult___fst_exp__h483599, - _theResult___fst_exp__h498663, - _theResult___fst_exp__h498669, - _theResult___fst_exp__h498672, - _theResult___fst_exp__h499427, - _theResult___fst_exp__h499430, - _theResult___fst_exp__h508249, - _theResult___fst_exp__h508314, - _theResult___fst_exp__h508320, - _theResult___fst_exp__h508323, - _theResult___fst_exp__h509078, - _theResult___fst_exp__h509081, - _theResult___fst_exp__h517034, - _theResult___fst_exp__h517073, - _theResult___fst_exp__h517079, - _theResult___fst_exp__h517082, - _theResult___fst_exp__h517862, - _theResult___fst_exp__h517865, - _theResult___fst_exp__h517874, - _theResult___fst_exp__h517877, - _theResult___fst_exp__h522400, - _theResult___fst_exp__h537464, - _theResult___fst_exp__h537470, - _theResult___fst_exp__h537473, - _theResult___fst_exp__h538228, - _theResult___fst_exp__h538231, - _theResult___fst_exp__h547050, - _theResult___fst_exp__h547115, - _theResult___fst_exp__h547121, - _theResult___fst_exp__h547124, - _theResult___fst_exp__h547879, - _theResult___fst_exp__h547882, - _theResult___fst_exp__h555835, - _theResult___fst_exp__h555874, - _theResult___fst_exp__h555880, - _theResult___fst_exp__h555883, - _theResult___fst_exp__h556663, - _theResult___fst_exp__h556666, - _theResult___fst_exp__h556675, - _theResult___fst_exp__h556678, - _theResult___fst_exp__h561601, - _theResult___fst_exp__h576665, - _theResult___fst_exp__h576671, - _theResult___fst_exp__h576674, - _theResult___fst_exp__h577429, - _theResult___fst_exp__h577432, - _theResult___fst_exp__h586251, - _theResult___fst_exp__h586316, - _theResult___fst_exp__h586322, - _theResult___fst_exp__h586325, - _theResult___fst_exp__h587080, - _theResult___fst_exp__h587083, - _theResult___fst_exp__h595036, - _theResult___fst_exp__h595075, - _theResult___fst_exp__h595081, - _theResult___fst_exp__h595084, - _theResult___fst_exp__h595864, - _theResult___fst_exp__h595867, - _theResult___fst_exp__h595876, - _theResult___fst_exp__h595879, - _theResult___snd_fst_exp__h499433, - _theResult___snd_fst_exp__h517868, - _theResult___snd_fst_exp__h538234, - _theResult___snd_fst_exp__h556669, - _theResult___snd_fst_exp__h577435, - _theResult___snd_fst_exp__h595870, + _theResult___exp__h499331, + _theResult___exp__h508982, + _theResult___exp__h517766, + _theResult___exp__h538132, + _theResult___exp__h547783, + _theResult___exp__h556567, + _theResult___exp__h577333, + _theResult___exp__h586984, + _theResult___exp__h595768, + _theResult___fst_exp__h483603, + _theResult___fst_exp__h498667, + _theResult___fst_exp__h498673, + _theResult___fst_exp__h498676, + _theResult___fst_exp__h499431, + _theResult___fst_exp__h499434, + _theResult___fst_exp__h508253, + _theResult___fst_exp__h508318, + _theResult___fst_exp__h508324, + _theResult___fst_exp__h508327, + _theResult___fst_exp__h509082, + _theResult___fst_exp__h509085, + _theResult___fst_exp__h517038, + _theResult___fst_exp__h517077, + _theResult___fst_exp__h517083, + _theResult___fst_exp__h517086, + _theResult___fst_exp__h517866, + _theResult___fst_exp__h517869, + _theResult___fst_exp__h517878, + _theResult___fst_exp__h517881, + _theResult___fst_exp__h522404, + _theResult___fst_exp__h537468, + _theResult___fst_exp__h537474, + _theResult___fst_exp__h537477, + _theResult___fst_exp__h538232, + _theResult___fst_exp__h538235, + _theResult___fst_exp__h547054, + _theResult___fst_exp__h547119, + _theResult___fst_exp__h547125, + _theResult___fst_exp__h547128, + _theResult___fst_exp__h547883, + _theResult___fst_exp__h547886, + _theResult___fst_exp__h555839, + _theResult___fst_exp__h555878, + _theResult___fst_exp__h555884, + _theResult___fst_exp__h555887, + _theResult___fst_exp__h556667, + _theResult___fst_exp__h556670, + _theResult___fst_exp__h556679, + _theResult___fst_exp__h556682, + _theResult___fst_exp__h561605, + _theResult___fst_exp__h576669, + _theResult___fst_exp__h576675, + _theResult___fst_exp__h576678, + _theResult___fst_exp__h577433, + _theResult___fst_exp__h577436, + _theResult___fst_exp__h586255, + _theResult___fst_exp__h586320, + _theResult___fst_exp__h586326, + _theResult___fst_exp__h586329, + _theResult___fst_exp__h587084, + _theResult___fst_exp__h587087, + _theResult___fst_exp__h595040, + _theResult___fst_exp__h595079, + _theResult___fst_exp__h595085, + _theResult___fst_exp__h595088, + _theResult___fst_exp__h595868, + _theResult___fst_exp__h595871, + _theResult___fst_exp__h595880, + _theResult___fst_exp__h595883, + _theResult___snd_fst_exp__h499437, + _theResult___snd_fst_exp__h517872, + _theResult___snd_fst_exp__h538238, + _theResult___snd_fst_exp__h556673, + _theResult___snd_fst_exp__h577439, + _theResult___snd_fst_exp__h595874, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98, csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, - din_inc___2_exp__h517922, - din_inc___2_exp__h517957, - din_inc___2_exp__h517983, - din_inc___2_exp__h556723, - din_inc___2_exp__h556758, - din_inc___2_exp__h556784, - din_inc___2_exp__h595924, - din_inc___2_exp__h595959, - din_inc___2_exp__h595985, - out_exp__h499330, - out_exp__h508981, - out_exp__h517765, - out_exp__h538131, - out_exp__h547782, - out_exp__h556566, - out_exp__h577332, - out_exp__h586983, - out_exp__h595767; + din_inc___2_exp__h517926, + din_inc___2_exp__h517961, + din_inc___2_exp__h517987, + din_inc___2_exp__h556727, + din_inc___2_exp__h556762, + din_inc___2_exp__h556788, + din_inc___2_exp__h595928, + din_inc___2_exp__h595963, + din_inc___2_exp__h595989, + out_exp__h499334, + out_exp__h508985, + out_exp__h517769, + out_exp__h538135, + out_exp__h547786, + out_exp__h556570, + out_exp__h577336, + out_exp__h586987, + out_exp__h595771; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; @@ -5209,121 +5209,121 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104, - _theResult___exp__h351926, - _theResult___exp__h360508, - _theResult___exp__h369692, - _theResult___exp__h378328, - _theResult___exp__h378430, - _theResult___exp__h397616, - _theResult___exp__h406198, - _theResult___exp__h415382, - _theResult___exp__h424018, - _theResult___exp__h424120, - _theResult___exp__h443304, - _theResult___exp__h451886, - _theResult___exp__h461070, - _theResult___exp__h469706, - _theResult___exp__h469808, - _theResult___fst_exp__h351410, - _theResult___fst_exp__h351475, - _theResult___fst_exp__h351481, + _theResult___exp__h351929, + _theResult___exp__h360511, + _theResult___exp__h369695, + _theResult___exp__h378331, + _theResult___exp__h378433, + _theResult___exp__h397619, + _theResult___exp__h406201, + _theResult___exp__h415385, + _theResult___exp__h424021, + _theResult___exp__h424123, + _theResult___exp__h443307, + _theResult___exp__h451889, + _theResult___exp__h461073, + _theResult___exp__h469709, + _theResult___exp__h469811, + _theResult___fst_exp__h351413, + _theResult___fst_exp__h351478, _theResult___fst_exp__h351484, - _theResult___fst_exp__h352007, - _theResult___fst_exp__h360057, - _theResult___fst_exp__h360063, + _theResult___fst_exp__h351487, + _theResult___fst_exp__h352010, + _theResult___fst_exp__h360060, _theResult___fst_exp__h360066, - _theResult___fst_exp__h360589, - _theResult___fst_exp__h369176, - _theResult___fst_exp__h369241, - _theResult___fst_exp__h369247, + _theResult___fst_exp__h360069, + _theResult___fst_exp__h360592, + _theResult___fst_exp__h369179, + _theResult___fst_exp__h369244, _theResult___fst_exp__h369250, - _theResult___fst_exp__h369773, - _theResult___fst_exp__h377813, - _theResult___fst_exp__h377852, - _theResult___fst_exp__h377858, + _theResult___fst_exp__h369253, + _theResult___fst_exp__h369776, + _theResult___fst_exp__h377816, + _theResult___fst_exp__h377855, _theResult___fst_exp__h377861, - _theResult___fst_exp__h378409, - _theResult___fst_exp__h378418, + _theResult___fst_exp__h377864, + _theResult___fst_exp__h378412, _theResult___fst_exp__h378421, - _theResult___fst_exp__h397100, - _theResult___fst_exp__h397165, - _theResult___fst_exp__h397171, + _theResult___fst_exp__h378424, + _theResult___fst_exp__h397103, + _theResult___fst_exp__h397168, _theResult___fst_exp__h397174, - _theResult___fst_exp__h397697, - _theResult___fst_exp__h405747, - _theResult___fst_exp__h405753, + _theResult___fst_exp__h397177, + _theResult___fst_exp__h397700, + _theResult___fst_exp__h405750, _theResult___fst_exp__h405756, - _theResult___fst_exp__h406279, - _theResult___fst_exp__h414866, - _theResult___fst_exp__h414931, - _theResult___fst_exp__h414937, + _theResult___fst_exp__h405759, + _theResult___fst_exp__h406282, + _theResult___fst_exp__h414869, + _theResult___fst_exp__h414934, _theResult___fst_exp__h414940, - _theResult___fst_exp__h415463, - _theResult___fst_exp__h423503, - _theResult___fst_exp__h423542, - _theResult___fst_exp__h423548, + _theResult___fst_exp__h414943, + _theResult___fst_exp__h415466, + _theResult___fst_exp__h423506, + _theResult___fst_exp__h423545, _theResult___fst_exp__h423551, - _theResult___fst_exp__h424099, - _theResult___fst_exp__h424108, + _theResult___fst_exp__h423554, + _theResult___fst_exp__h424102, _theResult___fst_exp__h424111, - _theResult___fst_exp__h442788, - _theResult___fst_exp__h442853, - _theResult___fst_exp__h442859, + _theResult___fst_exp__h424114, + _theResult___fst_exp__h442791, + _theResult___fst_exp__h442856, _theResult___fst_exp__h442862, - _theResult___fst_exp__h443385, - _theResult___fst_exp__h451435, - _theResult___fst_exp__h451441, + _theResult___fst_exp__h442865, + _theResult___fst_exp__h443388, + _theResult___fst_exp__h451438, _theResult___fst_exp__h451444, - _theResult___fst_exp__h451967, - _theResult___fst_exp__h460554, - _theResult___fst_exp__h460619, - _theResult___fst_exp__h460625, + _theResult___fst_exp__h451447, + _theResult___fst_exp__h451970, + _theResult___fst_exp__h460557, + _theResult___fst_exp__h460622, _theResult___fst_exp__h460628, - _theResult___fst_exp__h461151, - _theResult___fst_exp__h469191, - _theResult___fst_exp__h469230, - _theResult___fst_exp__h469236, + _theResult___fst_exp__h460631, + _theResult___fst_exp__h461154, + _theResult___fst_exp__h469194, + _theResult___fst_exp__h469233, _theResult___fst_exp__h469239, - _theResult___fst_exp__h469787, - _theResult___fst_exp__h469796, + _theResult___fst_exp__h469242, + _theResult___fst_exp__h469790, _theResult___fst_exp__h469799, - _theResult___snd_fst_exp__h360592, - _theResult___snd_fst_exp__h378412, - _theResult___snd_fst_exp__h406282, - _theResult___snd_fst_exp__h424102, - _theResult___snd_fst_exp__h451970, - _theResult___snd_fst_exp__h469790, + _theResult___fst_exp__h469802, + _theResult___snd_fst_exp__h360595, + _theResult___snd_fst_exp__h378415, + _theResult___snd_fst_exp__h406285, + _theResult___snd_fst_exp__h424105, + _theResult___snd_fst_exp__h451973, + _theResult___snd_fst_exp__h469793, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145, - din_inc___2_exp__h378443, - din_inc___2_exp__h378467, - din_inc___2_exp__h378497, - din_inc___2_exp__h378521, - din_inc___2_exp__h424133, - din_inc___2_exp__h424157, - din_inc___2_exp__h424187, - din_inc___2_exp__h424211, - din_inc___2_exp__h469821, - din_inc___2_exp__h469845, - din_inc___2_exp__h469875, - din_inc___2_exp__h469899, - out_exp__h351929, - out_exp__h360511, - out_exp__h369695, - out_exp__h378331, - out_exp__h397619, - out_exp__h406201, - out_exp__h415385, - out_exp__h424021, - out_exp__h443307, - out_exp__h451889, - out_exp__h461073, - out_exp__h469709, - out_f_exp__h378707, - out_f_exp__h424397, - out_f_exp__h470085, - x__h608817; + din_inc___2_exp__h378446, + din_inc___2_exp__h378470, + din_inc___2_exp__h378500, + din_inc___2_exp__h378524, + din_inc___2_exp__h424136, + din_inc___2_exp__h424160, + din_inc___2_exp__h424190, + din_inc___2_exp__h424214, + din_inc___2_exp__h469824, + din_inc___2_exp__h469848, + din_inc___2_exp__h469878, + din_inc___2_exp__h469902, + out_exp__h351932, + out_exp__h360514, + out_exp__h369698, + out_exp__h378334, + out_exp__h397622, + out_exp__h406204, + out_exp__h415388, + out_exp__h424024, + out_exp__h443310, + out_exp__h451892, + out_exp__h461076, + out_exp__h469712, + out_f_exp__h378710, + out_f_exp__h424400, + out_f_exp__h470088, + x__h608822; wire [6 : 0] csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, @@ -5345,8 +5345,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890, - x__h180645, - x__h694797; + x__h180648, + x__h694806; wire [4 : 0] IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, @@ -5366,18 +5366,18 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804, checkForException___d12839, checkForException___d13458, - fflags__h705618, - res_fflags__h335087, - res_fflags__h380782, - res_fflags__h426470, - rs1__h649444, - x__h152883, - x__h156430, - x__h159246, - x__h284498, - y_avValue_snd_fst__h705125, - y_avValue_snd_fst__h705678, - y_avValue_snd_fst__h705707; + fflags__h705627, + res_fflags__h335090, + res_fflags__h380785, + res_fflags__h426473, + rs1__h649453, + x__h152884, + x__h156431, + x__h159247, + x__h284501, + y_avValue_snd_fst__h705134, + y_avValue_snd_fst__h705687, + y_avValue_snd_fst__h705716; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, @@ -5404,74 +5404,74 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074, - cause_code__h692180, - vm_mode_reg__read__h610026; + cause_code__h692189, + vm_mode_reg__read__h610031; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h293741, - next_deqP___1__h294020, - v__h293161, - v__h293392, - x__h299371, - x_decodeInfo_frm__h649128; + _theResult_____2__h293743, + next_deqP___1__h294022, + v__h293163, + v__h293394, + x__h299373, + x_decodeInfo_frm__h649137; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771, - IF_sfdin08243_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin14860_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin42782_BIT_33_THEN_2_ELSE_0__q91, - IF_sfdin47044_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin51404_BIT_33_THEN_2_ELSE_0__q21, - IF_sfdin60548_BIT_33_THEN_2_ELSE_0__q101, - IF_sfdin69170_BIT_33_THEN_2_ELSE_0__q31, - IF_sfdin86245_BIT_4_THEN_2_ELSE_0__q148, - IF_sfdin97094_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd05707_BIT_33_THEN_2_ELSE_0__q58, - IF_theResult___snd17028_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd23497_BIT_33_THEN_2_ELSE_0__q71, - IF_theResult___snd37424_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd51395_BIT_33_THEN_2_ELSE_0__q93, - IF_theResult___snd55829_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd60017_BIT_33_THEN_2_ELSE_0__q23, - IF_theResult___snd69185_BIT_33_THEN_2_ELSE_0__q106, - IF_theResult___snd76625_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd77807_BIT_33_THEN_2_ELSE_0__q36, - IF_theResult___snd95030_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd98623_BIT_4_THEN_2_ELSE_0__q127, - guard__h343309, - guard__h352018, - guard__h360948, - guard__h369784, - guard__h389001, - guard__h397708, - guard__h406638, - guard__h415474, - guard__h434689, - guard__h443396, - guard__h452326, - guard__h461162, - guard__h490711, - guard__h500023, - guard__h509092, - guard__h529512, - guard__h538824, - guard__h547893, - guard__h568713, - guard__h578025, - guard__h587094, - prv__h707133, - prv__h707177, - r1__read_BITS_13_TO_12___h649313, - sbIdx__h156309, - v__h600770, - v__h600780, - v__h601415, - x__h702593, - x__h705866, - y_avValue_snd_snd_snd_fst__h705135, - y_avValue_snd_snd_snd_fst__h705688, - y_avValue_snd_snd_snd_fst__h705717; + IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66, + IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91, + IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21, + IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101, + IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31, + IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148, + IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58, + IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71, + IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93, + IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23, + IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106, + IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36, + IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127, + guard__h343312, + guard__h352021, + guard__h360951, + guard__h369787, + guard__h389004, + guard__h397711, + guard__h406641, + guard__h415477, + guard__h434692, + guard__h443399, + guard__h452329, + guard__h461165, + guard__h490715, + guard__h500027, + guard__h509096, + guard__h529516, + guard__h538828, + guard__h547897, + guard__h568717, + guard__h578029, + guard__h587098, + prv__h707142, + prv__h707186, + r1__read_BITS_13_TO_12___h649322, + sbIdx__h156310, + v__h600774, + v__h600784, + v__h601419, + x__h702602, + x__h705875, + y_avValue_snd_snd_snd_fst__h705144, + y_avValue_snd_snd_snd_fst__h705697, + y_avValue_snd_snd_snd_fst__h705726; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, @@ -5872,7 +5872,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo26, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -5898,11 +5898,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h301737, - _theResult_____2__h307731, - _theResult_____2__h315585, - _theResult_____2__h325929, - _theResult_____2__h329154, + _theResult_____2__h301739, + _theResult_____2__h307733, + _theResult_____2__h315587, + _theResult_____2__h325931, + _theResult_____2__h329156, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140, coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114, @@ -6036,14 +6036,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2614_BITS_194_TO_ETC___d13720, fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555, fetchStage_pipelines_1_first__2614_BIT_68_3335_ETC___d13724, - guard__h361546, - guard__h407236, - guard__h452924, - guard__h500621, - guard__h539422, - guard__h578623, - idx__h675470, - k__h661036, + guard__h361549, + guard__h407239, + guard__h452927, + guard__h500625, + guard__h539426, + guard__h578627, + idx__h675479, + k__h661045, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6055,13 +6055,13 @@ module mkCore(CLK, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75409, - next_deqP___1__h302016, - next_deqP___1__h308297, - next_deqP___1__h316151, - next_deqP___1__h326208, - next_deqP___1__h329433, - r1__read_BIT_20___h649941, - r__h608864, + next_deqP___1__h302018, + next_deqP___1__h308299, + next_deqP___1__h316153, + next_deqP___1__h326210, + next_deqP___1__h329435, + r1__read_BIT_20___h649950, + r__h608869, regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688, regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762, regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258, @@ -6082,17 +6082,17 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631, - v__h296506, - v__h297024, - v__h307020, - v__h307251, - v__h310896, - v__h311127, - v__h325497, - v__h325728, - v__h328722, - v__h328953, - x__h600271; + v__h296508, + v__h297026, + v__h307022, + v__h307253, + v__h310898, + v__h311129, + v__h325499, + v__h325730, + v__h328724, + v__h328955, + x__h600275; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -9449,7 +9449,6 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9499,7 +9498,6 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9597,7 +9595,6 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9628,7 +9625,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -10423,7 +10419,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$RDY_first && IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && + !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = @@ -10783,7 +10783,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -10795,7 +10795,7 @@ module mkCore(CLK, assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = @@ -10803,7 +10803,7 @@ module mkCore(CLK, (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -10837,7 +10837,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; assign MUX_rf$write_3_wr_2__SEL_5 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -10860,7 +10860,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h688716, + x__h688725, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 : @@ -10868,9 +10868,9 @@ module mkCore(CLK, assign MUX_commitStage_rg_instret$write_1__VAL_1 = commitStage_rg_instret + 64'd1 ; assign MUX_commitStage_rg_instret$write_1__VAL_2 = - commitStage_rg_instret + y__h705641 ; + commitStage_rg_instret + y__h705650 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h661036 == 1'd0 && + (k__h661045 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -10891,7 +10891,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -10994,7 +10994,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, @@ -11008,10 +11008,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283065 } ; + x__h283068 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h284510, + x__h284513, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11019,7 +11019,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287286, + addr__h287289, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11032,12 +11032,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h152883, x__h152889, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h152884, x__h152890, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h156430, x__h156436, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h156431, x__h156437, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h159246, - x__h159250, + { x__h159247, + x__h159251, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -11048,7 +11048,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161098, + x__h161099, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -11061,7 +11061,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289190, + resp_addr__h289193, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11141,7 +11141,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h194346 } ; + x__h194349 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11176,8 +11176,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190136 : - { {32{x__h190899[31]}}, x__h190899 } } ; + curData__h190139 : + { {32{x__h190902[31]}}, x__h190902 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[325:321], @@ -11206,7 +11206,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h705618 ; + csrf_fflags_reg | fflags__h705627 ; always@(IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 or robdeqPort_0_deq_data_BITS_95_TO_32__q261) begin @@ -11232,9 +11232,9 @@ module mkCore(CLK, csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h703190 + 64'd1 ; + n__read__h703199 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h703190 + { 62'd0, x__h705866 } ; + n__read__h703199 + { 62'd0, x__h705875 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == @@ -11242,7 +11242,7 @@ module mkCore(CLK, MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h693211 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h693220 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || @@ -11258,7 +11258,7 @@ module mkCore(CLK, MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h702593 : + x__h702602 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? @@ -11278,15 +11278,15 @@ module mkCore(CLK, MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? - y_avValue__h693058 : - y_avValue__h694819 ; + y_avValue__h693067 : + y_avValue__h694828 ; always@(rob$deqPort_0_deq_data or - next_pc__h702533 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h702542 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702533; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702542; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11321,23 +11321,23 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473012 : - data__h472478 ; + data___1__h473015 : + data__h472481 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335091 : - res_data__h335086 ; + res_data__h335094 : + res_data__h335089 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h380786 : - res_data__h380781 ; + res_data__h380789 : + res_data__h380784 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h426474 : - res_data__h426469 ; + res_data__h426477 : + res_data__h426472 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472204 : + data___1__h472207 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? @@ -11407,24 +11407,24 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335087 ; + res_fflags__h335090 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h380782 ; + res_fflags__h380785 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h426470 ; + res_fflags__h426473 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -11739,8 +11739,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h601415 : - v__h600770 ; + v__h601419 : + v__h600774 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -11847,7 +11847,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h293741 ; + _theResult_____2__h293743 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -11869,7 +11869,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h293161 ; + v__h293163 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -11915,7 +11915,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h301737 ; + _theResult_____2__h301739 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -11933,7 +11933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h296506 ; + v__h296508 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12033,7 +12033,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h307731 ; + _theResult_____2__h307733 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12051,7 +12051,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307020 ; + v__h307022 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12072,7 +12072,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311294, + { x_addr__h311296, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12102,7 +12102,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h315585 ; + _theResult_____2__h315587 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12120,7 +12120,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h310896 ; + v__h310898 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12197,7 +12197,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329154 ; + _theResult_____2__h329156 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12215,7 +12215,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h328722 ; + v__h328724 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12258,7 +12258,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h325929 ; + _theResult_____2__h325931 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12276,7 +12276,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h325497 ; + v__h325499 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12554,7 +12554,7 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_1 && MUX_csrf_ie_vec_1$write_1__VAL_1 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12570,7 +12570,7 @@ module mkCore(CLK, // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h692180 : + cause_code__h692189 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12787,7 +12787,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : csrf_ie_vec_1 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12815,7 +12815,7 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h692180 : + cause_code__h692189 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12933,7 +12933,7 @@ module mkCore(CLK, MUX_csrf_spp_reg$write_1__VAL_1 : csrf_prv_reg[0] ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -13472,8 +13472,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h634247, - x__h634248, + x__h634256, + x__h634257, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -13762,8 +13762,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h613028, - x__h613029, + x__h613033, + x__h613034, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -13805,7 +13805,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h661036 == 1'd1 && + (k__h661045 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -13826,7 +13826,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -13924,7 +13924,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h661036 == 1'd1 && + (k__h661045 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd1 && @@ -14310,19 +14310,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h600257 : - a__h599835 ; + _theResult___fst__h600261 : + a__h599839 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h599836 == 64'd0, - a__h599835, + { b__h599840 == 64'd0, + a__h599839, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h600271, - a__h599835[63], + x__h600275, + a__h599839[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h600258 : - b__h599836 ; + _theResult___snd__h600262 : + b__h599840 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14383,20 +14383,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599835 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599836 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599839 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599840 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h599835 ; + a__h599839 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h599836 ; + b__h599840 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h599835 ; + a__h599839 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h599836 ; + b__h599840 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -14425,9 +14425,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h478866, - x__h478867, - x__h478868, + x__h478870, + x__h478871, + x__h478872, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -14456,7 +14456,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -14479,7 +14479,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14633,8 +14633,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h284498, - x__h284510, + { x__h284501, + x__h284513, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, @@ -14645,13 +14645,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h286364, + x__h286367, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283065 ; + x__h283068 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15288,13 +15288,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h180508[2:0], - vaddr__h180508, + coreFix_memExe_lsq$getOrigBE << vaddr__h180511[2:0], + vaddr__h180511, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h180508[2:0] != 3'd0 : + vaddr__h180511[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h180508[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180508[0]), + vaddr__h180511[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180511[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15324,8 +15324,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h707177, - prv__h707177 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h707186, + prv__h707186 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15450,7 +15450,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675339 ; + renaming_spec_bits__h675348 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? @@ -15470,7 +15470,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675339 ; + renaming_spec_bits__h675348 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15550,7 +15550,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h180513 ; + shiftData__h180516 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15650,8 +15650,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h180422, - x__h180423, + x__h180425, + x__h180426, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15915,7 +15915,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16624,7 +16624,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h675339 ; + renaming_spec_bits__h675348 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -16883,7 +16883,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, 7'd32, - renaming_spec_bits__h675339 } ; + renaming_spec_bits__h675348 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -16893,24 +16893,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -17102,16 +17102,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -17385,10 +17385,10 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190136), + .amoExec_current_data(curData__h190139), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h191674)); + .amoExec(n__h191677)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, @@ -17425,7 +17425,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 }, fetchStage$pipelines_0_first[160], - x_data_imm__h667940 } }), + x_data_imm__h667949 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17434,12 +17434,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649128, - r1__read_BITS_13_TO_12___h649313 != + .checkForException_csrState({ x_decodeInfo_frm__h649137, + r1__read_BITS_13_TO_12___h649322 != 2'd0, - { prv__h707133, + { prv__h707142, csrf_tvm_reg, - { r1__read_BIT_20___h649941, + { r1__read_BIT_20___h649950, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17455,7 +17455,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, { fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, fetchStage$pipelines_1_first[160], - x_data_imm__h682683 } }), + x_data_imm__h682692 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17464,12 +17464,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649128, - r1__read_BITS_13_TO_12___h649313 != + .checkForException_csrState({ x_decodeInfo_frm__h649137, + r1__read_BITS_13_TO_12___h649322 != 2'd0, - { prv__h707133, + { prv__h707142, csrf_tvm_reg, - { r1__read_BIT_20___h649941, + { r1__read_BIT_20___h649950, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17484,139 +17484,139 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h478957), - .execFpuSimple_rVal2(rVal2__h478958), + .execFpuSimple_rVal1(rVal1__h478961), + .execFpuSimple_rVal2(rVal2__h478962), .execFpuSimple(execFpuSimple___d11034)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h351473 : - _theResult____h343299 ; + _theResult___snd__h351476 : + _theResult____h343302 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397163 : - _theResult____h388991 ; + _theResult___snd__h397166 : + _theResult____h388994 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h442851 : - _theResult____h434679 ; + _theResult___snd__h442854 : + _theResult____h434682 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 ? - _theResult___snd__h508312 : - _theResult____h500013 ; + _theResult___snd__h508316 : + _theResult____h500017 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599 ? - _theResult___snd__h586314 : - _theResult____h578015 ; + _theResult___snd__h586318 : + _theResult____h578019 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 ? - _theResult___snd__h547113 : - _theResult____h538814 ; + _theResult___snd__h547117 : + _theResult____h538818 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h460617 : - _theResult____h452316 ; + _theResult___snd__h460620 : + _theResult____h452319 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369239 : - _theResult____h360938 ; + _theResult___snd__h369242 : + _theResult____h360941 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h414929 : - _theResult____h406628 ; + _theResult___snd__h414932 : + _theResult____h406631 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h451433 : - _theResult___snd__h469223 ; + _theResult___snd__h451436 : + _theResult___snd__h469226 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360055 : + _theResult___snd__h360058 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360055 : - _theResult___snd__h377845 ; + _theResult___snd__h360058 : + _theResult___snd__h377848 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h405745 : + _theResult___snd__h405748 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h405745 : - _theResult___snd__h423535 ; + _theResult___snd__h405748 : + _theResult___snd__h423538 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h451433 : + _theResult___snd__h451436 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 ? - _theResult___snd__h498661 : + _theResult___snd__h498665 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939 ? - _theResult___snd__h498661 : - _theResult___snd__h517066 ; + _theResult___snd__h498665 : + _theResult___snd__h517070 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302 ? - _theResult___snd__h576663 : + _theResult___snd__h576667 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649 ? - _theResult___snd__h576663 : - _theResult___snd__h595068 ; + _theResult___snd__h576667 : + _theResult___snd__h595072 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 ? - _theResult___snd__h537462 : + _theResult___snd__h537466 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412 ? - _theResult___snd__h537462 : - _theResult___snd__h555867 ; + _theResult___snd__h537466 : + _theResult___snd__h555871 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351410 == 8'd255) ? + ((_theResult___fst_exp__h351413 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360066 == 8'd255) ? + ((_theResult___fst_exp__h360069 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351410 == 8'd255) ? + ((_theResult___fst_exp__h351413 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360066 == 8'd255) ? + ((_theResult___fst_exp__h360069 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397100 == 8'd255) ? + ((_theResult___fst_exp__h397103 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h405756 == 8'd255) ? + ((_theResult___fst_exp__h405759 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397100 == 8'd255) ? + ((_theResult___fst_exp__h397103 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h405756 == 8'd255) ? + ((_theResult___fst_exp__h405759 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442788 == 8'd255) ? + ((_theResult___fst_exp__h442791 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h451444 == 8'd255) ? + ((_theResult___fst_exp__h451447 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442788 == 8'd255) ? + ((_theResult___fst_exp__h442791 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h451444 == 8'd255) ? + ((_theResult___fst_exp__h451447 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657 = @@ -17632,1571 +17632,1571 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892) : !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343299[56] ? + (_theResult____h343302[56] ? 6'd0 : - (_theResult____h343299[55] ? + (_theResult____h343302[55] ? 6'd1 : - (_theResult____h343299[54] ? + (_theResult____h343302[54] ? 6'd2 : - (_theResult____h343299[53] ? + (_theResult____h343302[53] ? 6'd3 : - (_theResult____h343299[52] ? + (_theResult____h343302[52] ? 6'd4 : - (_theResult____h343299[51] ? + (_theResult____h343302[51] ? 6'd5 : - (_theResult____h343299[50] ? + (_theResult____h343302[50] ? 6'd6 : - (_theResult____h343299[49] ? + (_theResult____h343302[49] ? 6'd7 : - (_theResult____h343299[48] ? + (_theResult____h343302[48] ? 6'd8 : - (_theResult____h343299[47] ? + (_theResult____h343302[47] ? 6'd9 : - (_theResult____h343299[46] ? + (_theResult____h343302[46] ? 6'd10 : - (_theResult____h343299[45] ? + (_theResult____h343302[45] ? 6'd11 : - (_theResult____h343299[44] ? + (_theResult____h343302[44] ? 6'd12 : - (_theResult____h343299[43] ? + (_theResult____h343302[43] ? 6'd13 : - (_theResult____h343299[42] ? + (_theResult____h343302[42] ? 6'd14 : - (_theResult____h343299[41] ? + (_theResult____h343302[41] ? 6'd15 : - (_theResult____h343299[40] ? + (_theResult____h343302[40] ? 6'd16 : - (_theResult____h343299[39] ? + (_theResult____h343302[39] ? 6'd17 : - (_theResult____h343299[38] ? + (_theResult____h343302[38] ? 6'd18 : - (_theResult____h343299[37] ? + (_theResult____h343302[37] ? 6'd19 : - (_theResult____h343299[36] ? + (_theResult____h343302[36] ? 6'd20 : - (_theResult____h343299[35] ? + (_theResult____h343302[35] ? 6'd21 : - (_theResult____h343299[34] ? + (_theResult____h343302[34] ? 6'd22 : - (_theResult____h343299[33] ? + (_theResult____h343302[33] ? 6'd23 : - (_theResult____h343299[32] ? + (_theResult____h343302[32] ? 6'd24 : - (_theResult____h343299[31] ? + (_theResult____h343302[31] ? 6'd25 : - (_theResult____h343299[30] ? + (_theResult____h343302[30] ? 6'd26 : - (_theResult____h343299[29] ? + (_theResult____h343302[29] ? 6'd27 : - (_theResult____h343299[28] ? + (_theResult____h343302[28] ? 6'd28 : - (_theResult____h343299[27] ? + (_theResult____h343302[27] ? 6'd29 : - (_theResult____h343299[26] ? + (_theResult____h343302[26] ? 6'd30 : - (_theResult____h343299[25] ? + (_theResult____h343302[25] ? 6'd31 : - (_theResult____h343299[24] ? + (_theResult____h343302[24] ? 6'd32 : - (_theResult____h343299[23] ? + (_theResult____h343302[23] ? 6'd33 : - (_theResult____h343299[22] ? + (_theResult____h343302[22] ? 6'd34 : - (_theResult____h343299[21] ? + (_theResult____h343302[21] ? 6'd35 : - (_theResult____h343299[20] ? + (_theResult____h343302[20] ? 6'd36 : - (_theResult____h343299[19] ? + (_theResult____h343302[19] ? 6'd37 : - (_theResult____h343299[18] ? + (_theResult____h343302[18] ? 6'd38 : - (_theResult____h343299[17] ? + (_theResult____h343302[17] ? 6'd39 : - (_theResult____h343299[16] ? + (_theResult____h343302[16] ? 6'd40 : - (_theResult____h343299[15] ? + (_theResult____h343302[15] ? 6'd41 : - (_theResult____h343299[14] ? + (_theResult____h343302[14] ? 6'd42 : - (_theResult____h343299[13] ? + (_theResult____h343302[13] ? 6'd43 : - (_theResult____h343299[12] ? + (_theResult____h343302[12] ? 6'd44 : - (_theResult____h343299[11] ? + (_theResult____h343302[11] ? 6'd45 : - (_theResult____h343299[10] ? + (_theResult____h343302[10] ? 6'd46 : - (_theResult____h343299[9] ? + (_theResult____h343302[9] ? 6'd47 : - (_theResult____h343299[8] ? + (_theResult____h343302[8] ? 6'd48 : - (_theResult____h343299[7] ? + (_theResult____h343302[7] ? 6'd49 : - (_theResult____h343299[6] ? + (_theResult____h343302[6] ? 6'd50 : - (_theResult____h343299[5] ? + (_theResult____h343302[5] ? 6'd51 : - (_theResult____h343299[4] ? + (_theResult____h343302[4] ? 6'd52 : - (_theResult____h343299[3] ? + (_theResult____h343302[3] ? 6'd53 : - (_theResult____h343299[2] ? + (_theResult____h343302[2] ? 6'd54 : - (_theResult____h343299[1] ? + (_theResult____h343302[1] ? 6'd55 : - (_theResult____h343299[0] ? + (_theResult____h343302[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h388991[56] ? + (_theResult____h388994[56] ? 6'd0 : - (_theResult____h388991[55] ? + (_theResult____h388994[55] ? 6'd1 : - (_theResult____h388991[54] ? + (_theResult____h388994[54] ? 6'd2 : - (_theResult____h388991[53] ? + (_theResult____h388994[53] ? 6'd3 : - (_theResult____h388991[52] ? + (_theResult____h388994[52] ? 6'd4 : - (_theResult____h388991[51] ? + (_theResult____h388994[51] ? 6'd5 : - (_theResult____h388991[50] ? + (_theResult____h388994[50] ? 6'd6 : - (_theResult____h388991[49] ? + (_theResult____h388994[49] ? 6'd7 : - (_theResult____h388991[48] ? + (_theResult____h388994[48] ? 6'd8 : - (_theResult____h388991[47] ? + (_theResult____h388994[47] ? 6'd9 : - (_theResult____h388991[46] ? + (_theResult____h388994[46] ? 6'd10 : - (_theResult____h388991[45] ? + (_theResult____h388994[45] ? 6'd11 : - (_theResult____h388991[44] ? + (_theResult____h388994[44] ? 6'd12 : - (_theResult____h388991[43] ? + (_theResult____h388994[43] ? 6'd13 : - (_theResult____h388991[42] ? + (_theResult____h388994[42] ? 6'd14 : - (_theResult____h388991[41] ? + (_theResult____h388994[41] ? 6'd15 : - (_theResult____h388991[40] ? + (_theResult____h388994[40] ? 6'd16 : - (_theResult____h388991[39] ? + (_theResult____h388994[39] ? 6'd17 : - (_theResult____h388991[38] ? + (_theResult____h388994[38] ? 6'd18 : - (_theResult____h388991[37] ? + (_theResult____h388994[37] ? 6'd19 : - (_theResult____h388991[36] ? + (_theResult____h388994[36] ? 6'd20 : - (_theResult____h388991[35] ? + (_theResult____h388994[35] ? 6'd21 : - (_theResult____h388991[34] ? + (_theResult____h388994[34] ? 6'd22 : - (_theResult____h388991[33] ? + (_theResult____h388994[33] ? 6'd23 : - (_theResult____h388991[32] ? + (_theResult____h388994[32] ? 6'd24 : - (_theResult____h388991[31] ? + (_theResult____h388994[31] ? 6'd25 : - (_theResult____h388991[30] ? + (_theResult____h388994[30] ? 6'd26 : - (_theResult____h388991[29] ? + (_theResult____h388994[29] ? 6'd27 : - (_theResult____h388991[28] ? + (_theResult____h388994[28] ? 6'd28 : - (_theResult____h388991[27] ? + (_theResult____h388994[27] ? 6'd29 : - (_theResult____h388991[26] ? + (_theResult____h388994[26] ? 6'd30 : - (_theResult____h388991[25] ? + (_theResult____h388994[25] ? 6'd31 : - (_theResult____h388991[24] ? + (_theResult____h388994[24] ? 6'd32 : - (_theResult____h388991[23] ? + (_theResult____h388994[23] ? 6'd33 : - (_theResult____h388991[22] ? + (_theResult____h388994[22] ? 6'd34 : - (_theResult____h388991[21] ? + (_theResult____h388994[21] ? 6'd35 : - (_theResult____h388991[20] ? + (_theResult____h388994[20] ? 6'd36 : - (_theResult____h388991[19] ? + (_theResult____h388994[19] ? 6'd37 : - (_theResult____h388991[18] ? + (_theResult____h388994[18] ? 6'd38 : - (_theResult____h388991[17] ? + (_theResult____h388994[17] ? 6'd39 : - (_theResult____h388991[16] ? + (_theResult____h388994[16] ? 6'd40 : - (_theResult____h388991[15] ? + (_theResult____h388994[15] ? 6'd41 : - (_theResult____h388991[14] ? + (_theResult____h388994[14] ? 6'd42 : - (_theResult____h388991[13] ? + (_theResult____h388994[13] ? 6'd43 : - (_theResult____h388991[12] ? + (_theResult____h388994[12] ? 6'd44 : - (_theResult____h388991[11] ? + (_theResult____h388994[11] ? 6'd45 : - (_theResult____h388991[10] ? + (_theResult____h388994[10] ? 6'd46 : - (_theResult____h388991[9] ? + (_theResult____h388994[9] ? 6'd47 : - (_theResult____h388991[8] ? + (_theResult____h388994[8] ? 6'd48 : - (_theResult____h388991[7] ? + (_theResult____h388994[7] ? 6'd49 : - (_theResult____h388991[6] ? + (_theResult____h388994[6] ? 6'd50 : - (_theResult____h388991[5] ? + (_theResult____h388994[5] ? 6'd51 : - (_theResult____h388991[4] ? + (_theResult____h388994[4] ? 6'd52 : - (_theResult____h388991[3] ? + (_theResult____h388994[3] ? 6'd53 : - (_theResult____h388991[2] ? + (_theResult____h388994[2] ? 6'd54 : - (_theResult____h388991[1] ? + (_theResult____h388994[1] ? 6'd55 : - (_theResult____h388991[0] ? + (_theResult____h388994[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h434679[56] ? + (_theResult____h434682[56] ? 6'd0 : - (_theResult____h434679[55] ? + (_theResult____h434682[55] ? 6'd1 : - (_theResult____h434679[54] ? + (_theResult____h434682[54] ? 6'd2 : - (_theResult____h434679[53] ? + (_theResult____h434682[53] ? 6'd3 : - (_theResult____h434679[52] ? + (_theResult____h434682[52] ? 6'd4 : - (_theResult____h434679[51] ? + (_theResult____h434682[51] ? 6'd5 : - (_theResult____h434679[50] ? + (_theResult____h434682[50] ? 6'd6 : - (_theResult____h434679[49] ? + (_theResult____h434682[49] ? 6'd7 : - (_theResult____h434679[48] ? + (_theResult____h434682[48] ? 6'd8 : - (_theResult____h434679[47] ? + (_theResult____h434682[47] ? 6'd9 : - (_theResult____h434679[46] ? + (_theResult____h434682[46] ? 6'd10 : - (_theResult____h434679[45] ? + (_theResult____h434682[45] ? 6'd11 : - (_theResult____h434679[44] ? + (_theResult____h434682[44] ? 6'd12 : - (_theResult____h434679[43] ? + (_theResult____h434682[43] ? 6'd13 : - (_theResult____h434679[42] ? + (_theResult____h434682[42] ? 6'd14 : - (_theResult____h434679[41] ? + (_theResult____h434682[41] ? 6'd15 : - (_theResult____h434679[40] ? + (_theResult____h434682[40] ? 6'd16 : - (_theResult____h434679[39] ? + (_theResult____h434682[39] ? 6'd17 : - (_theResult____h434679[38] ? + (_theResult____h434682[38] ? 6'd18 : - (_theResult____h434679[37] ? + (_theResult____h434682[37] ? 6'd19 : - (_theResult____h434679[36] ? + (_theResult____h434682[36] ? 6'd20 : - (_theResult____h434679[35] ? + (_theResult____h434682[35] ? 6'd21 : - (_theResult____h434679[34] ? + (_theResult____h434682[34] ? 6'd22 : - (_theResult____h434679[33] ? + (_theResult____h434682[33] ? 6'd23 : - (_theResult____h434679[32] ? + (_theResult____h434682[32] ? 6'd24 : - (_theResult____h434679[31] ? + (_theResult____h434682[31] ? 6'd25 : - (_theResult____h434679[30] ? + (_theResult____h434682[30] ? 6'd26 : - (_theResult____h434679[29] ? + (_theResult____h434682[29] ? 6'd27 : - (_theResult____h434679[28] ? + (_theResult____h434682[28] ? 6'd28 : - (_theResult____h434679[27] ? + (_theResult____h434682[27] ? 6'd29 : - (_theResult____h434679[26] ? + (_theResult____h434682[26] ? 6'd30 : - (_theResult____h434679[25] ? + (_theResult____h434682[25] ? 6'd31 : - (_theResult____h434679[24] ? + (_theResult____h434682[24] ? 6'd32 : - (_theResult____h434679[23] ? + (_theResult____h434682[23] ? 6'd33 : - (_theResult____h434679[22] ? + (_theResult____h434682[22] ? 6'd34 : - (_theResult____h434679[21] ? + (_theResult____h434682[21] ? 6'd35 : - (_theResult____h434679[20] ? + (_theResult____h434682[20] ? 6'd36 : - (_theResult____h434679[19] ? + (_theResult____h434682[19] ? 6'd37 : - (_theResult____h434679[18] ? + (_theResult____h434682[18] ? 6'd38 : - (_theResult____h434679[17] ? + (_theResult____h434682[17] ? 6'd39 : - (_theResult____h434679[16] ? + (_theResult____h434682[16] ? 6'd40 : - (_theResult____h434679[15] ? + (_theResult____h434682[15] ? 6'd41 : - (_theResult____h434679[14] ? + (_theResult____h434682[14] ? 6'd42 : - (_theResult____h434679[13] ? + (_theResult____h434682[13] ? 6'd43 : - (_theResult____h434679[12] ? + (_theResult____h434682[12] ? 6'd44 : - (_theResult____h434679[11] ? + (_theResult____h434682[11] ? 6'd45 : - (_theResult____h434679[10] ? + (_theResult____h434682[10] ? 6'd46 : - (_theResult____h434679[9] ? + (_theResult____h434682[9] ? 6'd47 : - (_theResult____h434679[8] ? + (_theResult____h434682[8] ? 6'd48 : - (_theResult____h434679[7] ? + (_theResult____h434682[7] ? 6'd49 : - (_theResult____h434679[6] ? + (_theResult____h434682[6] ? 6'd50 : - (_theResult____h434679[5] ? + (_theResult____h434682[5] ? 6'd51 : - (_theResult____h434679[4] ? + (_theResult____h434682[4] ? 6'd52 : - (_theResult____h434679[3] ? + (_theResult____h434682[3] ? 6'd53 : - (_theResult____h434679[2] ? + (_theResult____h434682[2] ? 6'd54 : - (_theResult____h434679[1] ? + (_theResult____h434682[1] ? 6'd55 : - (_theResult____h434679[0] ? + (_theResult____h434682[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 = - (_theResult____h538814[56] ? + (_theResult____h538818[56] ? 6'd0 : - (_theResult____h538814[55] ? + (_theResult____h538818[55] ? 6'd1 : - (_theResult____h538814[54] ? + (_theResult____h538818[54] ? 6'd2 : - (_theResult____h538814[53] ? + (_theResult____h538818[53] ? 6'd3 : - (_theResult____h538814[52] ? + (_theResult____h538818[52] ? 6'd4 : - (_theResult____h538814[51] ? + (_theResult____h538818[51] ? 6'd5 : - (_theResult____h538814[50] ? + (_theResult____h538818[50] ? 6'd6 : - (_theResult____h538814[49] ? + (_theResult____h538818[49] ? 6'd7 : - (_theResult____h538814[48] ? + (_theResult____h538818[48] ? 6'd8 : - (_theResult____h538814[47] ? + (_theResult____h538818[47] ? 6'd9 : - (_theResult____h538814[46] ? + (_theResult____h538818[46] ? 6'd10 : - (_theResult____h538814[45] ? + (_theResult____h538818[45] ? 6'd11 : - (_theResult____h538814[44] ? + (_theResult____h538818[44] ? 6'd12 : - (_theResult____h538814[43] ? + (_theResult____h538818[43] ? 6'd13 : - (_theResult____h538814[42] ? + (_theResult____h538818[42] ? 6'd14 : - (_theResult____h538814[41] ? + (_theResult____h538818[41] ? 6'd15 : - (_theResult____h538814[40] ? + (_theResult____h538818[40] ? 6'd16 : - (_theResult____h538814[39] ? + (_theResult____h538818[39] ? 6'd17 : - (_theResult____h538814[38] ? + (_theResult____h538818[38] ? 6'd18 : - (_theResult____h538814[37] ? + (_theResult____h538818[37] ? 6'd19 : - (_theResult____h538814[36] ? + (_theResult____h538818[36] ? 6'd20 : - (_theResult____h538814[35] ? + (_theResult____h538818[35] ? 6'd21 : - (_theResult____h538814[34] ? + (_theResult____h538818[34] ? 6'd22 : - (_theResult____h538814[33] ? + (_theResult____h538818[33] ? 6'd23 : - (_theResult____h538814[32] ? + (_theResult____h538818[32] ? 6'd24 : - (_theResult____h538814[31] ? + (_theResult____h538818[31] ? 6'd25 : - (_theResult____h538814[30] ? + (_theResult____h538818[30] ? 6'd26 : - (_theResult____h538814[29] ? + (_theResult____h538818[29] ? 6'd27 : - (_theResult____h538814[28] ? + (_theResult____h538818[28] ? 6'd28 : - (_theResult____h538814[27] ? + (_theResult____h538818[27] ? 6'd29 : - (_theResult____h538814[26] ? + (_theResult____h538818[26] ? 6'd30 : - (_theResult____h538814[25] ? + (_theResult____h538818[25] ? 6'd31 : - (_theResult____h538814[24] ? + (_theResult____h538818[24] ? 6'd32 : - (_theResult____h538814[23] ? + (_theResult____h538818[23] ? 6'd33 : - (_theResult____h538814[22] ? + (_theResult____h538818[22] ? 6'd34 : - (_theResult____h538814[21] ? + (_theResult____h538818[21] ? 6'd35 : - (_theResult____h538814[20] ? + (_theResult____h538818[20] ? 6'd36 : - (_theResult____h538814[19] ? + (_theResult____h538818[19] ? 6'd37 : - (_theResult____h538814[18] ? + (_theResult____h538818[18] ? 6'd38 : - (_theResult____h538814[17] ? + (_theResult____h538818[17] ? 6'd39 : - (_theResult____h538814[16] ? + (_theResult____h538818[16] ? 6'd40 : - (_theResult____h538814[15] ? + (_theResult____h538818[15] ? 6'd41 : - (_theResult____h538814[14] ? + (_theResult____h538818[14] ? 6'd42 : - (_theResult____h538814[13] ? + (_theResult____h538818[13] ? 6'd43 : - (_theResult____h538814[12] ? + (_theResult____h538818[12] ? 6'd44 : - (_theResult____h538814[11] ? + (_theResult____h538818[11] ? 6'd45 : - (_theResult____h538814[10] ? + (_theResult____h538818[10] ? 6'd46 : - (_theResult____h538814[9] ? + (_theResult____h538818[9] ? 6'd47 : - (_theResult____h538814[8] ? + (_theResult____h538818[8] ? 6'd48 : - (_theResult____h538814[7] ? + (_theResult____h538818[7] ? 6'd49 : - (_theResult____h538814[6] ? + (_theResult____h538818[6] ? 6'd50 : - (_theResult____h538814[5] ? + (_theResult____h538818[5] ? 6'd51 : - (_theResult____h538814[4] ? + (_theResult____h538818[4] ? 6'd52 : - (_theResult____h538814[3] ? + (_theResult____h538818[3] ? 6'd53 : - (_theResult____h538814[2] ? + (_theResult____h538818[2] ? 6'd54 : - (_theResult____h538814[1] ? + (_theResult____h538818[1] ? 6'd55 : - (_theResult____h538814[0] ? + (_theResult____h538818[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 = - (_theResult____h500013[56] ? + (_theResult____h500017[56] ? 6'd0 : - (_theResult____h500013[55] ? + (_theResult____h500017[55] ? 6'd1 : - (_theResult____h500013[54] ? + (_theResult____h500017[54] ? 6'd2 : - (_theResult____h500013[53] ? + (_theResult____h500017[53] ? 6'd3 : - (_theResult____h500013[52] ? + (_theResult____h500017[52] ? 6'd4 : - (_theResult____h500013[51] ? + (_theResult____h500017[51] ? 6'd5 : - (_theResult____h500013[50] ? + (_theResult____h500017[50] ? 6'd6 : - (_theResult____h500013[49] ? + (_theResult____h500017[49] ? 6'd7 : - (_theResult____h500013[48] ? + (_theResult____h500017[48] ? 6'd8 : - (_theResult____h500013[47] ? + (_theResult____h500017[47] ? 6'd9 : - (_theResult____h500013[46] ? + (_theResult____h500017[46] ? 6'd10 : - (_theResult____h500013[45] ? + (_theResult____h500017[45] ? 6'd11 : - (_theResult____h500013[44] ? + (_theResult____h500017[44] ? 6'd12 : - (_theResult____h500013[43] ? + (_theResult____h500017[43] ? 6'd13 : - (_theResult____h500013[42] ? + (_theResult____h500017[42] ? 6'd14 : - (_theResult____h500013[41] ? + (_theResult____h500017[41] ? 6'd15 : - (_theResult____h500013[40] ? + (_theResult____h500017[40] ? 6'd16 : - (_theResult____h500013[39] ? + (_theResult____h500017[39] ? 6'd17 : - (_theResult____h500013[38] ? + (_theResult____h500017[38] ? 6'd18 : - (_theResult____h500013[37] ? + (_theResult____h500017[37] ? 6'd19 : - (_theResult____h500013[36] ? + (_theResult____h500017[36] ? 6'd20 : - (_theResult____h500013[35] ? + (_theResult____h500017[35] ? 6'd21 : - (_theResult____h500013[34] ? + (_theResult____h500017[34] ? 6'd22 : - (_theResult____h500013[33] ? + (_theResult____h500017[33] ? 6'd23 : - (_theResult____h500013[32] ? + (_theResult____h500017[32] ? 6'd24 : - (_theResult____h500013[31] ? + (_theResult____h500017[31] ? 6'd25 : - (_theResult____h500013[30] ? + (_theResult____h500017[30] ? 6'd26 : - (_theResult____h500013[29] ? + (_theResult____h500017[29] ? 6'd27 : - (_theResult____h500013[28] ? + (_theResult____h500017[28] ? 6'd28 : - (_theResult____h500013[27] ? + (_theResult____h500017[27] ? 6'd29 : - (_theResult____h500013[26] ? + (_theResult____h500017[26] ? 6'd30 : - (_theResult____h500013[25] ? + (_theResult____h500017[25] ? 6'd31 : - (_theResult____h500013[24] ? + (_theResult____h500017[24] ? 6'd32 : - (_theResult____h500013[23] ? + (_theResult____h500017[23] ? 6'd33 : - (_theResult____h500013[22] ? + (_theResult____h500017[22] ? 6'd34 : - (_theResult____h500013[21] ? + (_theResult____h500017[21] ? 6'd35 : - (_theResult____h500013[20] ? + (_theResult____h500017[20] ? 6'd36 : - (_theResult____h500013[19] ? + (_theResult____h500017[19] ? 6'd37 : - (_theResult____h500013[18] ? + (_theResult____h500017[18] ? 6'd38 : - (_theResult____h500013[17] ? + (_theResult____h500017[17] ? 6'd39 : - (_theResult____h500013[16] ? + (_theResult____h500017[16] ? 6'd40 : - (_theResult____h500013[15] ? + (_theResult____h500017[15] ? 6'd41 : - (_theResult____h500013[14] ? + (_theResult____h500017[14] ? 6'd42 : - (_theResult____h500013[13] ? + (_theResult____h500017[13] ? 6'd43 : - (_theResult____h500013[12] ? + (_theResult____h500017[12] ? 6'd44 : - (_theResult____h500013[11] ? + (_theResult____h500017[11] ? 6'd45 : - (_theResult____h500013[10] ? + (_theResult____h500017[10] ? 6'd46 : - (_theResult____h500013[9] ? + (_theResult____h500017[9] ? 6'd47 : - (_theResult____h500013[8] ? + (_theResult____h500017[8] ? 6'd48 : - (_theResult____h500013[7] ? + (_theResult____h500017[7] ? 6'd49 : - (_theResult____h500013[6] ? + (_theResult____h500017[6] ? 6'd50 : - (_theResult____h500013[5] ? + (_theResult____h500017[5] ? 6'd51 : - (_theResult____h500013[4] ? + (_theResult____h500017[4] ? 6'd52 : - (_theResult____h500013[3] ? + (_theResult____h500017[3] ? 6'd53 : - (_theResult____h500013[2] ? + (_theResult____h500017[2] ? 6'd54 : - (_theResult____h500013[1] ? + (_theResult____h500017[1] ? 6'd55 : - (_theResult____h500013[0] ? + (_theResult____h500017[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 = - (_theResult____h578015[56] ? + (_theResult____h578019[56] ? 6'd0 : - (_theResult____h578015[55] ? + (_theResult____h578019[55] ? 6'd1 : - (_theResult____h578015[54] ? + (_theResult____h578019[54] ? 6'd2 : - (_theResult____h578015[53] ? + (_theResult____h578019[53] ? 6'd3 : - (_theResult____h578015[52] ? + (_theResult____h578019[52] ? 6'd4 : - (_theResult____h578015[51] ? + (_theResult____h578019[51] ? 6'd5 : - (_theResult____h578015[50] ? + (_theResult____h578019[50] ? 6'd6 : - (_theResult____h578015[49] ? + (_theResult____h578019[49] ? 6'd7 : - (_theResult____h578015[48] ? + (_theResult____h578019[48] ? 6'd8 : - (_theResult____h578015[47] ? + (_theResult____h578019[47] ? 6'd9 : - (_theResult____h578015[46] ? + (_theResult____h578019[46] ? 6'd10 : - (_theResult____h578015[45] ? + (_theResult____h578019[45] ? 6'd11 : - (_theResult____h578015[44] ? + (_theResult____h578019[44] ? 6'd12 : - (_theResult____h578015[43] ? + (_theResult____h578019[43] ? 6'd13 : - (_theResult____h578015[42] ? + (_theResult____h578019[42] ? 6'd14 : - (_theResult____h578015[41] ? + (_theResult____h578019[41] ? 6'd15 : - (_theResult____h578015[40] ? + (_theResult____h578019[40] ? 6'd16 : - (_theResult____h578015[39] ? + (_theResult____h578019[39] ? 6'd17 : - (_theResult____h578015[38] ? + (_theResult____h578019[38] ? 6'd18 : - (_theResult____h578015[37] ? + (_theResult____h578019[37] ? 6'd19 : - (_theResult____h578015[36] ? + (_theResult____h578019[36] ? 6'd20 : - (_theResult____h578015[35] ? + (_theResult____h578019[35] ? 6'd21 : - (_theResult____h578015[34] ? + (_theResult____h578019[34] ? 6'd22 : - (_theResult____h578015[33] ? + (_theResult____h578019[33] ? 6'd23 : - (_theResult____h578015[32] ? + (_theResult____h578019[32] ? 6'd24 : - (_theResult____h578015[31] ? + (_theResult____h578019[31] ? 6'd25 : - (_theResult____h578015[30] ? + (_theResult____h578019[30] ? 6'd26 : - (_theResult____h578015[29] ? + (_theResult____h578019[29] ? 6'd27 : - (_theResult____h578015[28] ? + (_theResult____h578019[28] ? 6'd28 : - (_theResult____h578015[27] ? + (_theResult____h578019[27] ? 6'd29 : - (_theResult____h578015[26] ? + (_theResult____h578019[26] ? 6'd30 : - (_theResult____h578015[25] ? + (_theResult____h578019[25] ? 6'd31 : - (_theResult____h578015[24] ? + (_theResult____h578019[24] ? 6'd32 : - (_theResult____h578015[23] ? + (_theResult____h578019[23] ? 6'd33 : - (_theResult____h578015[22] ? + (_theResult____h578019[22] ? 6'd34 : - (_theResult____h578015[21] ? + (_theResult____h578019[21] ? 6'd35 : - (_theResult____h578015[20] ? + (_theResult____h578019[20] ? 6'd36 : - (_theResult____h578015[19] ? + (_theResult____h578019[19] ? 6'd37 : - (_theResult____h578015[18] ? + (_theResult____h578019[18] ? 6'd38 : - (_theResult____h578015[17] ? + (_theResult____h578019[17] ? 6'd39 : - (_theResult____h578015[16] ? + (_theResult____h578019[16] ? 6'd40 : - (_theResult____h578015[15] ? + (_theResult____h578019[15] ? 6'd41 : - (_theResult____h578015[14] ? + (_theResult____h578019[14] ? 6'd42 : - (_theResult____h578015[13] ? + (_theResult____h578019[13] ? 6'd43 : - (_theResult____h578015[12] ? + (_theResult____h578019[12] ? 6'd44 : - (_theResult____h578015[11] ? + (_theResult____h578019[11] ? 6'd45 : - (_theResult____h578015[10] ? + (_theResult____h578019[10] ? 6'd46 : - (_theResult____h578015[9] ? + (_theResult____h578019[9] ? 6'd47 : - (_theResult____h578015[8] ? + (_theResult____h578019[8] ? 6'd48 : - (_theResult____h578015[7] ? + (_theResult____h578019[7] ? 6'd49 : - (_theResult____h578015[6] ? + (_theResult____h578019[6] ? 6'd50 : - (_theResult____h578015[5] ? + (_theResult____h578019[5] ? 6'd51 : - (_theResult____h578015[4] ? + (_theResult____h578019[4] ? 6'd52 : - (_theResult____h578015[3] ? + (_theResult____h578019[3] ? 6'd53 : - (_theResult____h578015[2] ? + (_theResult____h578019[2] ? 6'd54 : - (_theResult____h578015[1] ? + (_theResult____h578019[1] ? 6'd55 : - (_theResult____h578015[0] ? + (_theResult____h578019[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h360938[56] ? + (_theResult____h360941[56] ? 6'd0 : - (_theResult____h360938[55] ? + (_theResult____h360941[55] ? 6'd1 : - (_theResult____h360938[54] ? + (_theResult____h360941[54] ? 6'd2 : - (_theResult____h360938[53] ? + (_theResult____h360941[53] ? 6'd3 : - (_theResult____h360938[52] ? + (_theResult____h360941[52] ? 6'd4 : - (_theResult____h360938[51] ? + (_theResult____h360941[51] ? 6'd5 : - (_theResult____h360938[50] ? + (_theResult____h360941[50] ? 6'd6 : - (_theResult____h360938[49] ? + (_theResult____h360941[49] ? 6'd7 : - (_theResult____h360938[48] ? + (_theResult____h360941[48] ? 6'd8 : - (_theResult____h360938[47] ? + (_theResult____h360941[47] ? 6'd9 : - (_theResult____h360938[46] ? + (_theResult____h360941[46] ? 6'd10 : - (_theResult____h360938[45] ? + (_theResult____h360941[45] ? 6'd11 : - (_theResult____h360938[44] ? + (_theResult____h360941[44] ? 6'd12 : - (_theResult____h360938[43] ? + (_theResult____h360941[43] ? 6'd13 : - (_theResult____h360938[42] ? + (_theResult____h360941[42] ? 6'd14 : - (_theResult____h360938[41] ? + (_theResult____h360941[41] ? 6'd15 : - (_theResult____h360938[40] ? + (_theResult____h360941[40] ? 6'd16 : - (_theResult____h360938[39] ? + (_theResult____h360941[39] ? 6'd17 : - (_theResult____h360938[38] ? + (_theResult____h360941[38] ? 6'd18 : - (_theResult____h360938[37] ? + (_theResult____h360941[37] ? 6'd19 : - (_theResult____h360938[36] ? + (_theResult____h360941[36] ? 6'd20 : - (_theResult____h360938[35] ? + (_theResult____h360941[35] ? 6'd21 : - (_theResult____h360938[34] ? + (_theResult____h360941[34] ? 6'd22 : - (_theResult____h360938[33] ? + (_theResult____h360941[33] ? 6'd23 : - (_theResult____h360938[32] ? + (_theResult____h360941[32] ? 6'd24 : - (_theResult____h360938[31] ? + (_theResult____h360941[31] ? 6'd25 : - (_theResult____h360938[30] ? + (_theResult____h360941[30] ? 6'd26 : - (_theResult____h360938[29] ? + (_theResult____h360941[29] ? 6'd27 : - (_theResult____h360938[28] ? + (_theResult____h360941[28] ? 6'd28 : - (_theResult____h360938[27] ? + (_theResult____h360941[27] ? 6'd29 : - (_theResult____h360938[26] ? + (_theResult____h360941[26] ? 6'd30 : - (_theResult____h360938[25] ? + (_theResult____h360941[25] ? 6'd31 : - (_theResult____h360938[24] ? + (_theResult____h360941[24] ? 6'd32 : - (_theResult____h360938[23] ? + (_theResult____h360941[23] ? 6'd33 : - (_theResult____h360938[22] ? + (_theResult____h360941[22] ? 6'd34 : - (_theResult____h360938[21] ? + (_theResult____h360941[21] ? 6'd35 : - (_theResult____h360938[20] ? + (_theResult____h360941[20] ? 6'd36 : - (_theResult____h360938[19] ? + (_theResult____h360941[19] ? 6'd37 : - (_theResult____h360938[18] ? + (_theResult____h360941[18] ? 6'd38 : - (_theResult____h360938[17] ? + (_theResult____h360941[17] ? 6'd39 : - (_theResult____h360938[16] ? + (_theResult____h360941[16] ? 6'd40 : - (_theResult____h360938[15] ? + (_theResult____h360941[15] ? 6'd41 : - (_theResult____h360938[14] ? + (_theResult____h360941[14] ? 6'd42 : - (_theResult____h360938[13] ? + (_theResult____h360941[13] ? 6'd43 : - (_theResult____h360938[12] ? + (_theResult____h360941[12] ? 6'd44 : - (_theResult____h360938[11] ? + (_theResult____h360941[11] ? 6'd45 : - (_theResult____h360938[10] ? + (_theResult____h360941[10] ? 6'd46 : - (_theResult____h360938[9] ? + (_theResult____h360941[9] ? 6'd47 : - (_theResult____h360938[8] ? + (_theResult____h360941[8] ? 6'd48 : - (_theResult____h360938[7] ? + (_theResult____h360941[7] ? 6'd49 : - (_theResult____h360938[6] ? + (_theResult____h360941[6] ? 6'd50 : - (_theResult____h360938[5] ? + (_theResult____h360941[5] ? 6'd51 : - (_theResult____h360938[4] ? + (_theResult____h360941[4] ? 6'd52 : - (_theResult____h360938[3] ? + (_theResult____h360941[3] ? 6'd53 : - (_theResult____h360938[2] ? + (_theResult____h360941[2] ? 6'd54 : - (_theResult____h360938[1] ? + (_theResult____h360941[1] ? 6'd55 : - (_theResult____h360938[0] ? + (_theResult____h360941[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h406628[56] ? + (_theResult____h406631[56] ? 6'd0 : - (_theResult____h406628[55] ? + (_theResult____h406631[55] ? 6'd1 : - (_theResult____h406628[54] ? + (_theResult____h406631[54] ? 6'd2 : - (_theResult____h406628[53] ? + (_theResult____h406631[53] ? 6'd3 : - (_theResult____h406628[52] ? + (_theResult____h406631[52] ? 6'd4 : - (_theResult____h406628[51] ? + (_theResult____h406631[51] ? 6'd5 : - (_theResult____h406628[50] ? + (_theResult____h406631[50] ? 6'd6 : - (_theResult____h406628[49] ? + (_theResult____h406631[49] ? 6'd7 : - (_theResult____h406628[48] ? + (_theResult____h406631[48] ? 6'd8 : - (_theResult____h406628[47] ? + (_theResult____h406631[47] ? 6'd9 : - (_theResult____h406628[46] ? + (_theResult____h406631[46] ? 6'd10 : - (_theResult____h406628[45] ? + (_theResult____h406631[45] ? 6'd11 : - (_theResult____h406628[44] ? + (_theResult____h406631[44] ? 6'd12 : - (_theResult____h406628[43] ? + (_theResult____h406631[43] ? 6'd13 : - (_theResult____h406628[42] ? + (_theResult____h406631[42] ? 6'd14 : - (_theResult____h406628[41] ? + (_theResult____h406631[41] ? 6'd15 : - (_theResult____h406628[40] ? + (_theResult____h406631[40] ? 6'd16 : - (_theResult____h406628[39] ? + (_theResult____h406631[39] ? 6'd17 : - (_theResult____h406628[38] ? + (_theResult____h406631[38] ? 6'd18 : - (_theResult____h406628[37] ? + (_theResult____h406631[37] ? 6'd19 : - (_theResult____h406628[36] ? + (_theResult____h406631[36] ? 6'd20 : - (_theResult____h406628[35] ? + (_theResult____h406631[35] ? 6'd21 : - (_theResult____h406628[34] ? + (_theResult____h406631[34] ? 6'd22 : - (_theResult____h406628[33] ? + (_theResult____h406631[33] ? 6'd23 : - (_theResult____h406628[32] ? + (_theResult____h406631[32] ? 6'd24 : - (_theResult____h406628[31] ? + (_theResult____h406631[31] ? 6'd25 : - (_theResult____h406628[30] ? + (_theResult____h406631[30] ? 6'd26 : - (_theResult____h406628[29] ? + (_theResult____h406631[29] ? 6'd27 : - (_theResult____h406628[28] ? + (_theResult____h406631[28] ? 6'd28 : - (_theResult____h406628[27] ? + (_theResult____h406631[27] ? 6'd29 : - (_theResult____h406628[26] ? + (_theResult____h406631[26] ? 6'd30 : - (_theResult____h406628[25] ? + (_theResult____h406631[25] ? 6'd31 : - (_theResult____h406628[24] ? + (_theResult____h406631[24] ? 6'd32 : - (_theResult____h406628[23] ? + (_theResult____h406631[23] ? 6'd33 : - (_theResult____h406628[22] ? + (_theResult____h406631[22] ? 6'd34 : - (_theResult____h406628[21] ? + (_theResult____h406631[21] ? 6'd35 : - (_theResult____h406628[20] ? + (_theResult____h406631[20] ? 6'd36 : - (_theResult____h406628[19] ? + (_theResult____h406631[19] ? 6'd37 : - (_theResult____h406628[18] ? + (_theResult____h406631[18] ? 6'd38 : - (_theResult____h406628[17] ? + (_theResult____h406631[17] ? 6'd39 : - (_theResult____h406628[16] ? + (_theResult____h406631[16] ? 6'd40 : - (_theResult____h406628[15] ? + (_theResult____h406631[15] ? 6'd41 : - (_theResult____h406628[14] ? + (_theResult____h406631[14] ? 6'd42 : - (_theResult____h406628[13] ? + (_theResult____h406631[13] ? 6'd43 : - (_theResult____h406628[12] ? + (_theResult____h406631[12] ? 6'd44 : - (_theResult____h406628[11] ? + (_theResult____h406631[11] ? 6'd45 : - (_theResult____h406628[10] ? + (_theResult____h406631[10] ? 6'd46 : - (_theResult____h406628[9] ? + (_theResult____h406631[9] ? 6'd47 : - (_theResult____h406628[8] ? + (_theResult____h406631[8] ? 6'd48 : - (_theResult____h406628[7] ? + (_theResult____h406631[7] ? 6'd49 : - (_theResult____h406628[6] ? + (_theResult____h406631[6] ? 6'd50 : - (_theResult____h406628[5] ? + (_theResult____h406631[5] ? 6'd51 : - (_theResult____h406628[4] ? + (_theResult____h406631[4] ? 6'd52 : - (_theResult____h406628[3] ? + (_theResult____h406631[3] ? 6'd53 : - (_theResult____h406628[2] ? + (_theResult____h406631[2] ? 6'd54 : - (_theResult____h406628[1] ? + (_theResult____h406631[1] ? 6'd55 : - (_theResult____h406628[0] ? + (_theResult____h406631[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452316[56] ? + (_theResult____h452319[56] ? 6'd0 : - (_theResult____h452316[55] ? + (_theResult____h452319[55] ? 6'd1 : - (_theResult____h452316[54] ? + (_theResult____h452319[54] ? 6'd2 : - (_theResult____h452316[53] ? + (_theResult____h452319[53] ? 6'd3 : - (_theResult____h452316[52] ? + (_theResult____h452319[52] ? 6'd4 : - (_theResult____h452316[51] ? + (_theResult____h452319[51] ? 6'd5 : - (_theResult____h452316[50] ? + (_theResult____h452319[50] ? 6'd6 : - (_theResult____h452316[49] ? + (_theResult____h452319[49] ? 6'd7 : - (_theResult____h452316[48] ? + (_theResult____h452319[48] ? 6'd8 : - (_theResult____h452316[47] ? + (_theResult____h452319[47] ? 6'd9 : - (_theResult____h452316[46] ? + (_theResult____h452319[46] ? 6'd10 : - (_theResult____h452316[45] ? + (_theResult____h452319[45] ? 6'd11 : - (_theResult____h452316[44] ? + (_theResult____h452319[44] ? 6'd12 : - (_theResult____h452316[43] ? + (_theResult____h452319[43] ? 6'd13 : - (_theResult____h452316[42] ? + (_theResult____h452319[42] ? 6'd14 : - (_theResult____h452316[41] ? + (_theResult____h452319[41] ? 6'd15 : - (_theResult____h452316[40] ? + (_theResult____h452319[40] ? 6'd16 : - (_theResult____h452316[39] ? + (_theResult____h452319[39] ? 6'd17 : - (_theResult____h452316[38] ? + (_theResult____h452319[38] ? 6'd18 : - (_theResult____h452316[37] ? + (_theResult____h452319[37] ? 6'd19 : - (_theResult____h452316[36] ? + (_theResult____h452319[36] ? 6'd20 : - (_theResult____h452316[35] ? + (_theResult____h452319[35] ? 6'd21 : - (_theResult____h452316[34] ? + (_theResult____h452319[34] ? 6'd22 : - (_theResult____h452316[33] ? + (_theResult____h452319[33] ? 6'd23 : - (_theResult____h452316[32] ? + (_theResult____h452319[32] ? 6'd24 : - (_theResult____h452316[31] ? + (_theResult____h452319[31] ? 6'd25 : - (_theResult____h452316[30] ? + (_theResult____h452319[30] ? 6'd26 : - (_theResult____h452316[29] ? + (_theResult____h452319[29] ? 6'd27 : - (_theResult____h452316[28] ? + (_theResult____h452319[28] ? 6'd28 : - (_theResult____h452316[27] ? + (_theResult____h452319[27] ? 6'd29 : - (_theResult____h452316[26] ? + (_theResult____h452319[26] ? 6'd30 : - (_theResult____h452316[25] ? + (_theResult____h452319[25] ? 6'd31 : - (_theResult____h452316[24] ? + (_theResult____h452319[24] ? 6'd32 : - (_theResult____h452316[23] ? + (_theResult____h452319[23] ? 6'd33 : - (_theResult____h452316[22] ? + (_theResult____h452319[22] ? 6'd34 : - (_theResult____h452316[21] ? + (_theResult____h452319[21] ? 6'd35 : - (_theResult____h452316[20] ? + (_theResult____h452319[20] ? 6'd36 : - (_theResult____h452316[19] ? + (_theResult____h452319[19] ? 6'd37 : - (_theResult____h452316[18] ? + (_theResult____h452319[18] ? 6'd38 : - (_theResult____h452316[17] ? + (_theResult____h452319[17] ? 6'd39 : - (_theResult____h452316[16] ? + (_theResult____h452319[16] ? 6'd40 : - (_theResult____h452316[15] ? + (_theResult____h452319[15] ? 6'd41 : - (_theResult____h452316[14] ? + (_theResult____h452319[14] ? 6'd42 : - (_theResult____h452316[13] ? + (_theResult____h452319[13] ? 6'd43 : - (_theResult____h452316[12] ? + (_theResult____h452319[12] ? 6'd44 : - (_theResult____h452316[11] ? + (_theResult____h452319[11] ? 6'd45 : - (_theResult____h452316[10] ? + (_theResult____h452319[10] ? 6'd46 : - (_theResult____h452316[9] ? + (_theResult____h452319[9] ? 6'd47 : - (_theResult____h452316[8] ? + (_theResult____h452319[8] ? 6'd48 : - (_theResult____h452316[7] ? + (_theResult____h452319[7] ? 6'd49 : - (_theResult____h452316[6] ? + (_theResult____h452319[6] ? 6'd50 : - (_theResult____h452316[5] ? + (_theResult____h452319[5] ? 6'd51 : - (_theResult____h452316[4] ? + (_theResult____h452319[4] ? 6'd52 : - (_theResult____h452316[3] ? + (_theResult____h452319[3] ? 6'd53 : - (_theResult____h452316[2] ? + (_theResult____h452319[2] ? 6'd54 : - (_theResult____h452316[1] ? + (_theResult____h452319[1] ? 6'd55 : - (_theResult____h452316[0] ? + (_theResult____h452319[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404 = - (_theResult___fst_exp__h547050 == 11'd2047) ? + (_theResult___fst_exp__h547054 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669 = - (_theResult___fst_exp__h547050 == 11'd2047) ? + (_theResult___fst_exp__h547054 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931 = - (_theResult___fst_exp__h508249 == 11'd2047) ? + (_theResult___fst_exp__h508253 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641 = - (_theResult___fst_exp__h586251 == 11'd2047) ? + (_theResult___fst_exp__h586255 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907 = - (_theResult___fst_exp__h586251 == 11'd2047) ? + (_theResult___fst_exp__h586255 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343309 == 2'b0 || + (guard__h343312 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h351410 : - _theResult___exp__h351926 ; + _theResult___fst_exp__h351413 : + _theResult___exp__h351929 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343309 == 2'b0) ? - _theResult___fst_exp__h351410 : + (guard__h343312 == 2'b0) ? + _theResult___fst_exp__h351413 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h351926 : - _theResult___fst_exp__h351410) ; + _theResult___exp__h351929 : + _theResult___fst_exp__h351413) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343309 == 2'b0 || + (guard__h343312 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h351404[56:34] : - _theResult___sfd__h351927 ; + sfdin__h351407[56:34] : + _theResult___sfd__h351930 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343309 == 2'b0) ? - sfdin__h351404[56:34] : + (guard__h343312 == 2'b0) ? + sfdin__h351407[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h351927 : - sfdin__h351404[56:34]) ; + _theResult___sfd__h351930 : + sfdin__h351407[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389001 == 2'b0 || + (guard__h389004 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397100 : - _theResult___exp__h397616 ; + _theResult___fst_exp__h397103 : + _theResult___exp__h397619 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389001 == 2'b0) ? - _theResult___fst_exp__h397100 : + (guard__h389004 == 2'b0) ? + _theResult___fst_exp__h397103 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h397616 : - _theResult___fst_exp__h397100) ; + _theResult___exp__h397619 : + _theResult___fst_exp__h397103) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389001 == 2'b0 || + (guard__h389004 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397094[56:34] : - _theResult___sfd__h397617 ; + sfdin__h397097[56:34] : + _theResult___sfd__h397620 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389001 == 2'b0) ? - sfdin__h397094[56:34] : + (guard__h389004 == 2'b0) ? + sfdin__h397097[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h397617 : - sfdin__h397094[56:34]) ; + _theResult___sfd__h397620 : + sfdin__h397097[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h434689 == 2'b0 || + (guard__h434692 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h442788 : - _theResult___exp__h443304 ; + _theResult___fst_exp__h442791 : + _theResult___exp__h443307 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h434689 == 2'b0) ? - _theResult___fst_exp__h442788 : + (guard__h434692 == 2'b0) ? + _theResult___fst_exp__h442791 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443304 : - _theResult___fst_exp__h442788) ; + _theResult___exp__h443307 : + _theResult___fst_exp__h442791) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h434689 == 2'b0 || + (guard__h434692 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h442782[56:34] : - _theResult___sfd__h443305 ; + sfdin__h442785[56:34] : + _theResult___sfd__h443308 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h434689 == 2'b0) ? - sfdin__h442782[56:34] : + (guard__h434692 == 2'b0) ? + sfdin__h442785[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443305 : - sfdin__h442782[56:34]) ; + _theResult___sfd__h443308 : + sfdin__h442785[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 = - (guard__h538824 == 2'b0 || + (guard__h538828 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547050 : - _theResult___exp__h547779 ; + _theResult___fst_exp__h547054 : + _theResult___exp__h547783 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 = - (guard__h538824 == 2'b0) ? - _theResult___fst_exp__h547050 : + (guard__h538828 == 2'b0) ? + _theResult___fst_exp__h547054 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h547779 : - _theResult___fst_exp__h547050) ; + _theResult___exp__h547783 : + _theResult___fst_exp__h547054) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 = - (guard__h538824 == 2'b0 || + (guard__h538828 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547044[56:5] : - _theResult___sfd__h547780 ; + sfdin__h547048[56:5] : + _theResult___sfd__h547784 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 = - (guard__h538824 == 2'b0) ? - sfdin__h547044[56:5] : + (guard__h538828 == 2'b0) ? + sfdin__h547048[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h547780 : - sfdin__h547044[56:5]) ; + _theResult___sfd__h547784 : + sfdin__h547048[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 = - (guard__h500023 == 2'b0 || + (guard__h500027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508249 : - _theResult___exp__h508978 ; + _theResult___fst_exp__h508253 : + _theResult___exp__h508982 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 = - (guard__h500023 == 2'b0) ? - _theResult___fst_exp__h508249 : + (guard__h500027 == 2'b0) ? + _theResult___fst_exp__h508253 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h508978 : - _theResult___fst_exp__h508249) ; + _theResult___exp__h508982 : + _theResult___fst_exp__h508253) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 = - (guard__h500023 == 2'b0 || + (guard__h500027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508243[56:5] : - _theResult___sfd__h508979 ; + sfdin__h508247[56:5] : + _theResult___sfd__h508983 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 = - (guard__h500023 == 2'b0) ? - sfdin__h508243[56:5] : + (guard__h500027 == 2'b0) ? + sfdin__h508247[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h508979 : - sfdin__h508243[56:5]) ; + _theResult___sfd__h508983 : + sfdin__h508247[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 = - (guard__h578025 == 2'b0 || + (guard__h578029 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h586251 : - _theResult___exp__h586980 ; + _theResult___fst_exp__h586255 : + _theResult___exp__h586984 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 = - (guard__h578025 == 2'b0) ? - _theResult___fst_exp__h586251 : + (guard__h578029 == 2'b0) ? + _theResult___fst_exp__h586255 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h586980 : - _theResult___fst_exp__h586251) ; + _theResult___exp__h586984 : + _theResult___fst_exp__h586255) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 = - (guard__h578025 == 2'b0 || + (guard__h578029 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h586245[56:5] : - _theResult___sfd__h586981 ; + sfdin__h586249[56:5] : + _theResult___sfd__h586985 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 = - (guard__h578025 == 2'b0) ? - sfdin__h586245[56:5] : + (guard__h578029 == 2'b0) ? + sfdin__h586249[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h586981 : - sfdin__h586245[56:5]) ; + _theResult___sfd__h586985 : + sfdin__h586249[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h360948 == 2'b0 || + (guard__h360951 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369176 : - _theResult___exp__h369692 ; + _theResult___fst_exp__h369179 : + _theResult___exp__h369695 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h360948 == 2'b0) ? - _theResult___fst_exp__h369176 : + (guard__h360951 == 2'b0) ? + _theResult___fst_exp__h369179 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h369692 : - _theResult___fst_exp__h369176) ; + _theResult___exp__h369695 : + _theResult___fst_exp__h369179) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h360948 == 2'b0 || + (guard__h360951 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369170[56:34] : - _theResult___sfd__h369693 ; + sfdin__h369173[56:34] : + _theResult___sfd__h369696 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h360948 == 2'b0) ? - sfdin__h369170[56:34] : + (guard__h360951 == 2'b0) ? + sfdin__h369173[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h369693 : - sfdin__h369170[56:34]) ; + _theResult___sfd__h369696 : + sfdin__h369173[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h406638 == 2'b0 || + (guard__h406641 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h414866 : - _theResult___exp__h415382 ; + _theResult___fst_exp__h414869 : + _theResult___exp__h415385 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h406638 == 2'b0) ? - _theResult___fst_exp__h414866 : + (guard__h406641 == 2'b0) ? + _theResult___fst_exp__h414869 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h415382 : - _theResult___fst_exp__h414866) ; + _theResult___exp__h415385 : + _theResult___fst_exp__h414869) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h406638 == 2'b0 || + (guard__h406641 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h414860[56:34] : - _theResult___sfd__h415383 ; + sfdin__h414863[56:34] : + _theResult___sfd__h415386 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h406638 == 2'b0) ? - sfdin__h414860[56:34] : + (guard__h406641 == 2'b0) ? + sfdin__h414863[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h415383 : - sfdin__h414860[56:34]) ; + _theResult___sfd__h415386 : + sfdin__h414863[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h452326 == 2'b0 || + (guard__h452329 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h460554 : - _theResult___exp__h461070 ; + _theResult___fst_exp__h460557 : + _theResult___exp__h461073 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h452326 == 2'b0) ? - _theResult___fst_exp__h460554 : + (guard__h452329 == 2'b0) ? + _theResult___fst_exp__h460557 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461070 : - _theResult___fst_exp__h460554) ; + _theResult___exp__h461073 : + _theResult___fst_exp__h460557) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h452326 == 2'b0 || + (guard__h452329 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h460548[56:34] : - _theResult___sfd__h461071 ; + sfdin__h460551[56:34] : + _theResult___sfd__h461074 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h452326 == 2'b0) ? - sfdin__h460548[56:34] : + (guard__h452329 == 2'b0) ? + sfdin__h460551[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461071 : - sfdin__h460548[56:34]) ; + _theResult___sfd__h461074 : + sfdin__h460551[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352018 == 2'b0 || + (guard__h352021 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360066 : - _theResult___exp__h360508 ; + _theResult___fst_exp__h360069 : + _theResult___exp__h360511 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352018 == 2'b0) ? - _theResult___fst_exp__h360066 : + (guard__h352021 == 2'b0) ? + _theResult___fst_exp__h360069 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h360508 : - _theResult___fst_exp__h360066) ; + _theResult___exp__h360511 : + _theResult___fst_exp__h360069) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h369784 == 2'b0 || + (guard__h369787 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h377861 : - _theResult___exp__h378328 ; + _theResult___fst_exp__h377864 : + _theResult___exp__h378331 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h369784 == 2'b0) ? - _theResult___fst_exp__h377861 : + (guard__h369787 == 2'b0) ? + _theResult___fst_exp__h377864 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378328 : - _theResult___fst_exp__h377861) ; + _theResult___exp__h378331 : + _theResult___fst_exp__h377864) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352018 == 2'b0 || + (guard__h352021 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360017[56:34] : - _theResult___sfd__h360509 ; + _theResult___snd__h360020[56:34] : + _theResult___sfd__h360512 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352018 == 2'b0) ? - _theResult___snd__h360017[56:34] : + (guard__h352021 == 2'b0) ? + _theResult___snd__h360020[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h360509 : - _theResult___snd__h360017[56:34]) ; + _theResult___sfd__h360512 : + _theResult___snd__h360020[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h369784 == 2'b0 || + (guard__h369787 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h377807[56:34] : - _theResult___sfd__h378329 ; + _theResult___snd__h377810[56:34] : + _theResult___sfd__h378332 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h369784 == 2'b0) ? - _theResult___snd__h377807[56:34] : + (guard__h369787 == 2'b0) ? + _theResult___snd__h377810[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378329 : - _theResult___snd__h377807[56:34]) ; + _theResult___sfd__h378332 : + _theResult___snd__h377810[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h397708 == 2'b0 || + (guard__h397711 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h405756 : - _theResult___exp__h406198 ; + _theResult___fst_exp__h405759 : + _theResult___exp__h406201 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h397708 == 2'b0) ? - _theResult___fst_exp__h405756 : + (guard__h397711 == 2'b0) ? + _theResult___fst_exp__h405759 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406198 : - _theResult___fst_exp__h405756) ; + _theResult___exp__h406201 : + _theResult___fst_exp__h405759) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h415474 == 2'b0 || + (guard__h415477 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h423551 : - _theResult___exp__h424018 ; + _theResult___fst_exp__h423554 : + _theResult___exp__h424021 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h415474 == 2'b0) ? - _theResult___fst_exp__h423551 : + (guard__h415477 == 2'b0) ? + _theResult___fst_exp__h423554 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424018 : - _theResult___fst_exp__h423551) ; + _theResult___exp__h424021 : + _theResult___fst_exp__h423554) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h397708 == 2'b0 || + (guard__h397711 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h405707[56:34] : - _theResult___sfd__h406199 ; + _theResult___snd__h405710[56:34] : + _theResult___sfd__h406202 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h397708 == 2'b0) ? - _theResult___snd__h405707[56:34] : + (guard__h397711 == 2'b0) ? + _theResult___snd__h405710[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406199 : - _theResult___snd__h405707[56:34]) ; + _theResult___sfd__h406202 : + _theResult___snd__h405710[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h415474 == 2'b0 || + (guard__h415477 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h423497[56:34] : - _theResult___sfd__h424019 ; + _theResult___snd__h423500[56:34] : + _theResult___sfd__h424022 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h415474 == 2'b0) ? - _theResult___snd__h423497[56:34] : + (guard__h415477 == 2'b0) ? + _theResult___snd__h423500[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424019 : - _theResult___snd__h423497[56:34]) ; + _theResult___sfd__h424022 : + _theResult___snd__h423500[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h443396 == 2'b0 || + (guard__h443399 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h451444 : - _theResult___exp__h451886 ; + _theResult___fst_exp__h451447 : + _theResult___exp__h451889 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h443396 == 2'b0) ? - _theResult___fst_exp__h451444 : + (guard__h443399 == 2'b0) ? + _theResult___fst_exp__h451447 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h451886 : - _theResult___fst_exp__h451444) ; + _theResult___exp__h451889 : + _theResult___fst_exp__h451447) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461162 == 2'b0 || + (guard__h461165 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469239 : - _theResult___exp__h469706 ; + _theResult___fst_exp__h469242 : + _theResult___exp__h469709 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461162 == 2'b0) ? - _theResult___fst_exp__h469239 : + (guard__h461165 == 2'b0) ? + _theResult___fst_exp__h469242 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h469706 : - _theResult___fst_exp__h469239) ; + _theResult___exp__h469709 : + _theResult___fst_exp__h469242) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h443396 == 2'b0 || + (guard__h443399 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h451395[56:34] : - _theResult___sfd__h451887 ; + _theResult___snd__h451398[56:34] : + _theResult___sfd__h451890 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h443396 == 2'b0) ? - _theResult___snd__h451395[56:34] : + (guard__h443399 == 2'b0) ? + _theResult___snd__h451398[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h451887 : - _theResult___snd__h451395[56:34]) ; + _theResult___sfd__h451890 : + _theResult___snd__h451398[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461162 == 2'b0 || + (guard__h461165 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469185[56:34] : - _theResult___sfd__h469707 ; + _theResult___snd__h469188[56:34] : + _theResult___sfd__h469710 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461162 == 2'b0) ? - _theResult___snd__h469185[56:34] : + (guard__h461165 == 2'b0) ? + _theResult___snd__h469188[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h469707 : - _theResult___snd__h469185[56:34]) ; + _theResult___sfd__h469710 : + _theResult___snd__h469188[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 = - (guard__h529512 == 2'b0 || + (guard__h529516 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h537473 : - _theResult___exp__h538128 ; + _theResult___fst_exp__h537477 : + _theResult___exp__h538132 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 = - (guard__h529512 == 2'b0) ? - _theResult___fst_exp__h537473 : + (guard__h529516 == 2'b0) ? + _theResult___fst_exp__h537477 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h538128 : - _theResult___fst_exp__h537473) ; + _theResult___exp__h538132 : + _theResult___fst_exp__h537477) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 = - (guard__h547893 == 2'b0 || + (guard__h547897 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555883 : - _theResult___exp__h556563 ; + _theResult___fst_exp__h555887 : + _theResult___exp__h556567 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 = - (guard__h547893 == 2'b0) ? - _theResult___fst_exp__h555883 : + (guard__h547897 == 2'b0) ? + _theResult___fst_exp__h555887 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h556563 : - _theResult___fst_exp__h555883) ; + _theResult___exp__h556567 : + _theResult___fst_exp__h555887) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 = - (guard__h529512 == 2'b0 || + (guard__h529516 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h537424[56:5] : - _theResult___sfd__h538129 ; + _theResult___snd__h537428[56:5] : + _theResult___sfd__h538133 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 = - (guard__h529512 == 2'b0) ? - _theResult___snd__h537424[56:5] : + (guard__h529516 == 2'b0) ? + _theResult___snd__h537428[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h538129 : - _theResult___snd__h537424[56:5]) ; + _theResult___sfd__h538133 : + _theResult___snd__h537428[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 = - (guard__h547893 == 2'b0 || + (guard__h547897 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h555829[56:5] : - _theResult___sfd__h556564 ; + _theResult___snd__h555833[56:5] : + _theResult___sfd__h556568 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 = - (guard__h547893 == 2'b0) ? - _theResult___snd__h555829[56:5] : + (guard__h547897 == 2'b0) ? + _theResult___snd__h555833[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h556564 : - _theResult___snd__h555829[56:5]) ; + _theResult___sfd__h556568 : + _theResult___snd__h555833[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 = - (guard__h490711 == 2'b0 || + (guard__h490715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h498672 : - _theResult___exp__h499327 ; + _theResult___fst_exp__h498676 : + _theResult___exp__h499331 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 = - (guard__h490711 == 2'b0) ? - _theResult___fst_exp__h498672 : + (guard__h490715 == 2'b0) ? + _theResult___fst_exp__h498676 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h499327 : - _theResult___fst_exp__h498672) ; + _theResult___exp__h499331 : + _theResult___fst_exp__h498676) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 = - (guard__h509092 == 2'b0 || + (guard__h509096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517082 : - _theResult___exp__h517762 ; + _theResult___fst_exp__h517086 : + _theResult___exp__h517766 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 = - (guard__h509092 == 2'b0) ? - _theResult___fst_exp__h517082 : + (guard__h509096 == 2'b0) ? + _theResult___fst_exp__h517086 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h517762 : - _theResult___fst_exp__h517082) ; + _theResult___exp__h517766 : + _theResult___fst_exp__h517086) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 = - (guard__h490711 == 2'b0 || + (guard__h490715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h498623[56:5] : - _theResult___sfd__h499328 ; + _theResult___snd__h498627[56:5] : + _theResult___sfd__h499332 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 = - (guard__h490711 == 2'b0) ? - _theResult___snd__h498623[56:5] : + (guard__h490715 == 2'b0) ? + _theResult___snd__h498627[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h499328 : - _theResult___snd__h498623[56:5]) ; + _theResult___sfd__h499332 : + _theResult___snd__h498627[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 = - (guard__h509092 == 2'b0 || + (guard__h509096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517028[56:5] : - _theResult___sfd__h517763 ; + _theResult___snd__h517032[56:5] : + _theResult___sfd__h517767 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 = - (guard__h509092 == 2'b0) ? - _theResult___snd__h517028[56:5] : + (guard__h509096 == 2'b0) ? + _theResult___snd__h517032[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h517763 : - _theResult___snd__h517028[56:5]) ; + _theResult___sfd__h517767 : + _theResult___snd__h517032[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 = - (guard__h568713 == 2'b0 || + (guard__h568717 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h576674 : - _theResult___exp__h577329 ; + _theResult___fst_exp__h576678 : + _theResult___exp__h577333 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 = - (guard__h568713 == 2'b0) ? - _theResult___fst_exp__h576674 : + (guard__h568717 == 2'b0) ? + _theResult___fst_exp__h576678 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h577329 : - _theResult___fst_exp__h576674) ; + _theResult___exp__h577333 : + _theResult___fst_exp__h576678) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 = - (guard__h587094 == 2'b0 || + (guard__h587098 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595084 : - _theResult___exp__h595764 ; + _theResult___fst_exp__h595088 : + _theResult___exp__h595768 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 = - (guard__h587094 == 2'b0) ? - _theResult___fst_exp__h595084 : + (guard__h587098 == 2'b0) ? + _theResult___fst_exp__h595088 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h595764 : - _theResult___fst_exp__h595084) ; + _theResult___exp__h595768 : + _theResult___fst_exp__h595088) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 = - (guard__h568713 == 2'b0 || + (guard__h568717 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h576625[56:5] : - _theResult___sfd__h577330 ; + _theResult___snd__h576629[56:5] : + _theResult___sfd__h577334 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 = - (guard__h568713 == 2'b0) ? - _theResult___snd__h576625[56:5] : + (guard__h568717 == 2'b0) ? + _theResult___snd__h576629[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h577330 : - _theResult___snd__h576625[56:5]) ; + _theResult___sfd__h577334 : + _theResult___snd__h576629[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 = - (guard__h587094 == 2'b0 || + (guard__h587098 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595030[56:5] : - _theResult___sfd__h595765 ; + _theResult___snd__h595034[56:5] : + _theResult___sfd__h595769 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 = - (guard__h587094 == 2'b0) ? - _theResult___snd__h595030[56:5] : + (guard__h587098 == 2'b0) ? + _theResult___snd__h595034[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h595765 : - _theResult___snd__h595030[56:5]) ; + _theResult___sfd__h595769 : + _theResult___snd__h595034[56:5]) ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674 = - (_theResult____h645389 == 15'd0 && + (_theResult____h645398 == 15'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h645933 : - _theResult____h645389 ; + enabled_ints__h645942 : + _theResult____h645398 ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || @@ -19255,67 +19255,67 @@ module mkCore(CLK, checkForException___d13458[4] || csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450 = - (_theResult___fst_exp__h555883 == 11'd2047) ? + (_theResult___fst_exp__h555887 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654 = - (_theResult___fst_exp__h537473 == 11'd2047) ? + (_theResult___fst_exp__h537477 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681 = - (_theResult___fst_exp__h555883 == 11'd2047) ? + (_theResult___fst_exp__h555887 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977 = - (_theResult___fst_exp__h517082 == 11'd2047) ? + (_theResult___fst_exp__h517086 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687 = - (_theResult___fst_exp__h595084 == 11'd2047) ? + (_theResult___fst_exp__h595088 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892 = - (_theResult___fst_exp__h576674 == 11'd2047) ? + (_theResult___fst_exp__h576678 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919 = - (_theResult___fst_exp__h595084 == 11'd2047) ? + (_theResult___fst_exp__h595088 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 = IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ? @@ -19521,35 +19521,35 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 || - _theResult___fst_exp__h537473 == 11'd2047) ? + _theResult___fst_exp__h537477 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 || - _theResult___fst_exp__h498672 == 11'd2047) ? + _theResult___fst_exp__h498676 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 || - _theResult___fst_exp__h576674 == 11'd2047) ? + _theResult___fst_exp__h576678 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] ? @@ -19987,35 +19987,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369176 == 8'd255) ? + ((_theResult___fst_exp__h369179 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h377861 == 8'd255) ? + ((_theResult___fst_exp__h377864 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369176 == 8'd255) ? + ((_theResult___fst_exp__h369179 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h377861 == 8'd255) ? + ((_theResult___fst_exp__h377864 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h378409 == 8'd255 && - _theResult___fst_sfd__h378410 == 23'd0 ; + _theResult___fst_exp__h378412 == 8'd255 && + _theResult___fst_sfd__h378413 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h377861 == 8'd0 && - guard__h369784 != 2'b0 ; + _theResult___fst_exp__h377864 == 8'd0 && + guard__h369787 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h377861 != 8'd255 && - guard__h369784 != 2'b0 ; + _theResult___fst_exp__h377864 != 8'd255 && + guard__h369787 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? @@ -20025,35 +20025,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414866 == 8'd255) ? + ((_theResult___fst_exp__h414869 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h423551 == 8'd255) ? + ((_theResult___fst_exp__h423554 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414866 == 8'd255) ? + ((_theResult___fst_exp__h414869 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h423551 == 8'd255) ? + ((_theResult___fst_exp__h423554 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424099 == 8'd255 && - _theResult___fst_sfd__h424100 == 23'd0 ; + _theResult___fst_exp__h424102 == 8'd255 && + _theResult___fst_sfd__h424103 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h423551 == 8'd0 && - guard__h415474 != 2'b0 ; + _theResult___fst_exp__h423554 == 8'd0 && + guard__h415477 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h423551 != 8'd255 && - guard__h415474 != 2'b0 ; + _theResult___fst_exp__h423554 != 8'd255 && + guard__h415477 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? @@ -20063,35 +20063,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460554 == 8'd255) ? + ((_theResult___fst_exp__h460557 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469239 == 8'd255) ? + ((_theResult___fst_exp__h469242 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460554 == 8'd255) ? + ((_theResult___fst_exp__h460557 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469239 == 8'd255) ? + ((_theResult___fst_exp__h469242 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h469787 == 8'd255 && - _theResult___fst_sfd__h469788 == 23'd0 ; + _theResult___fst_exp__h469790 == 8'd255 && + _theResult___fst_sfd__h469791 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469239 == 8'd0 && - guard__h461162 != 2'b0 ; + _theResult___fst_exp__h469242 == 8'd0 && + guard__h461165 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469239 != 8'd255 && - guard__h461162 != 2'b0 ; + _theResult___fst_exp__h469242 != 8'd255 && + guard__h461165 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? @@ -20114,48 +20114,48 @@ module mkCore(CLK, assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[2] : - _theResult___fst_exp__h517865 == 11'd2047 && - _theResult___fst_sfd__h517866 == 52'd0 ; + _theResult___fst_exp__h517869 == 11'd2047 && + _theResult___fst_sfd__h517870 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[2] : - _theResult___fst_exp__h556666 == 11'd2047 && - _theResult___fst_sfd__h556667 == 52'd0 ; + _theResult___fst_exp__h556670 == 11'd2047 && + _theResult___fst_sfd__h556671 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[2] : - _theResult___fst_exp__h595867 == 11'd2047 && - _theResult___fst_sfd__h595868 == 52'd0 ; + _theResult___fst_exp__h595871 == 11'd2047 && + _theResult___fst_sfd__h595872 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[1] : - _theResult___fst_exp__h517082 == 11'd0 && - guard__h509092 != 2'b0 ; + _theResult___fst_exp__h517086 == 11'd0 && + guard__h509096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[1] : - _theResult___fst_exp__h555883 == 11'd0 && - guard__h547893 != 2'b0 ; + _theResult___fst_exp__h555887 == 11'd0 && + guard__h547897 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[1] : - _theResult___fst_exp__h595084 == 11'd0 && - guard__h587094 != 2'b0 ; + _theResult___fst_exp__h595088 == 11'd0 && + guard__h587098 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[0] : - _theResult___fst_exp__h517082 != 11'd2047 && - guard__h509092 != 2'b0 ; + _theResult___fst_exp__h517086 != 11'd2047 && + guard__h509096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[0] : - _theResult___fst_exp__h555883 != 11'd2047 && - guard__h547893 != 2'b0 ; + _theResult___fst_exp__h555887 != 11'd2047 && + guard__h547897 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[0] : - _theResult___fst_exp__h595084 != 11'd2047 && - guard__h587094 != 2'b0 ; + _theResult___fst_exp__h595088 != 11'd2047 && + guard__h587098 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? @@ -20877,11 +20877,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h556678, + _theResult___fst_exp__h556682, (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ? - _theResult___snd_fst_sfd__h518567 : - _theResult___fst_sfd__h556682 } ; + _theResult___snd_fst_sfd__h518571 : + _theResult___fst_sfd__h556686 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : @@ -21079,11 +21079,11 @@ module mkCore(CLK, { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8981, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h517877, + _theResult___fst_exp__h517881, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ? - _theResult___snd_fst_sfd__h479625 : - _theResult___fst_sfd__h517881 } ; + _theResult___snd_fst_sfd__h479629 : + _theResult___fst_sfd__h517885 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] : @@ -21152,11 +21152,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h595879, + _theResult___fst_exp__h595883, (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ? - _theResult___snd_fst_sfd__h557768 : - _theResult___fst_sfd__h595883 } ; + _theResult___snd_fst_sfd__h557772 : + _theResult___fst_sfd__h595887 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : @@ -21180,8 +21180,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h641096 : - w__h641091 ; + result__h641105 : + w__h641100 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21203,39 +21203,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21288,7 +21288,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h194346 : + x__h194349 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? 64'd0 : 64'd1) ; @@ -21300,7 +21300,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h293741 == v__h293161 ; + _theResult_____2__h293743 == v__h293163 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21309,7 +21309,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h301737 == v__h296506 ; + _theResult_____2__h301739 == v__h296508 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21338,7 +21338,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h299371 } ; + x__h299373 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21436,35 +21436,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21492,7 +21492,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h307731 == v__h307020 ; + _theResult_____2__h307733 == v__h307022 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21501,7 +21501,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h315585 == v__h310896 ; + _theResult_____2__h315587 == v__h310898 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21653,7 +21653,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329154 == v__h328722 ; + _theResult_____2__h329156 == v__h328724 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -21702,7 +21702,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h325929 == v__h325497 ; + _theResult_____2__h325931 == v__h325499 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -21849,60 +21849,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h705141 : + y_avValue_snd_snd_snd_snd_snd__h705150 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705125 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705134 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h705135 : + y_avValue_snd_snd_snd_fst__h705144 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08243_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h508243[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin14860_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h414860[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin42782_BIT_33_THEN_2_ELSE_0__q91 = - sfdin__h442782[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47044_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h547044[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin51404_BIT_33_THEN_2_ELSE_0__q21 = - sfdin__h351404[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin60548_BIT_33_THEN_2_ELSE_0__q101 = - sfdin__h460548[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69170_BIT_33_THEN_2_ELSE_0__q31 = - sfdin__h369170[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin86245_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h586245[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97094_BIT_33_THEN_2_ELSE_0__q56 = - sfdin__h397094[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05707_BIT_33_THEN_2_ELSE_0__q58 = - _theResult___snd__h405707[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17028_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h517028[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd23497_BIT_33_THEN_2_ELSE_0__q71 = - _theResult___snd__h423497[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37424_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h537424[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd51395_BIT_33_THEN_2_ELSE_0__q93 = - _theResult___snd__h451395[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd55829_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h555829[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60017_BIT_33_THEN_2_ELSE_0__q23 = - _theResult___snd__h360017[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69185_BIT_33_THEN_2_ELSE_0__q106 = - _theResult___snd__h469185[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76625_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h576625[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77807_BIT_33_THEN_2_ELSE_0__q36 = - _theResult___snd__h377807[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95030_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h595030[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98623_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h498623[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h508247[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66 = + sfdin__h414863[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91 = + sfdin__h442785[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h547048[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21 = + sfdin__h351407[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101 = + sfdin__h460551[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31 = + sfdin__h369173[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h586249[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56 = + sfdin__h397097[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58 = + _theResult___snd__h405710[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h517032[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71 = + _theResult___snd__h423500[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h537428[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93 = + _theResult___snd__h451398[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h555833[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23 = + _theResult___snd__h360020[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106 = + _theResult___snd__h469188[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h576629[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36 = + _theResult___snd__h377810[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h595034[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h498627[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? @@ -21991,10 +21991,10 @@ module mkCore(CLK, !checkForException___d13458[4] && NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 = - (fflags__h705618 & csrf_fflags_reg) != fflags__h705618 || - !r__h608864 && + (fflags__h705627 & csrf_fflags_reg) != fflags__h705627 || + !r__h608869 && (IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 || - fflags__h705618 != 5'd0) ; + fflags__h705627 != 5'd0) ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -22806,8 +22806,8 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13117 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h649444 == 5'd0 && - imm__h649445 == 32'd0 || + rs1__h649453 == 5'd0 && + imm__h649454 == 32'd0 || IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 = @@ -23142,7 +23142,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h288835 } ; + x__h288838 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -23275,15 +23275,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = { 3'd0, - _theResult___fst_exp__h351410 == 8'd0 && - (sfdin__h351404[56:34] == 23'd0 || guard__h343309 != 2'b0), + _theResult___fst_exp__h351413 == 8'd0 && + (sfdin__h351407[56:34] == 23'd0 || guard__h343312 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352007 == 8'd255 && - _theResult___fst_sfd__h352008 == 23'd0, + _theResult___fst_exp__h352010 == 8'd255 && + _theResult___fst_sfd__h352011 == 23'd0, 1'd0, - _theResult___fst_exp__h351410 != 8'd255 && - guard__h343309 != 2'b0 } ; + _theResult___fst_exp__h351413 != 8'd255 && + guard__h343312 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ @@ -23291,15 +23291,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = { 3'd0, - _theResult___fst_exp__h397100 == 8'd0 && - (sfdin__h397094[56:34] == 23'd0 || guard__h389001 != 2'b0), + _theResult___fst_exp__h397103 == 8'd0 && + (sfdin__h397097[56:34] == 23'd0 || guard__h389004 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h397697 == 8'd255 && - _theResult___fst_sfd__h397698 == 23'd0, + _theResult___fst_exp__h397700 == 8'd255 && + _theResult___fst_sfd__h397701 == 23'd0, 1'd0, - _theResult___fst_exp__h397100 != 8'd255 && - guard__h389001 != 2'b0 } ; + _theResult___fst_exp__h397103 != 8'd255 && + guard__h389004 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ @@ -23307,15 +23307,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = { 3'd0, - _theResult___fst_exp__h442788 == 8'd0 && - (sfdin__h442782[56:34] == 23'd0 || guard__h434689 != 2'b0), + _theResult___fst_exp__h442791 == 8'd0 && + (sfdin__h442785[56:34] == 23'd0 || guard__h434692 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h443385 == 8'd255 && - _theResult___fst_sfd__h443386 == 23'd0, + _theResult___fst_exp__h443388 == 8'd255 && + _theResult___fst_sfd__h443389 == 23'd0, 1'd0, - _theResult___fst_exp__h442788 != 8'd255 && - guard__h434689 != 2'b0 } ; + _theResult___fst_exp__h442791 != 8'd255 && + guard__h434692 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ^ @@ -23323,37 +23323,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736 = { 3'd0, - _theResult___fst_exp__h508249 == 11'd0 && - (sfdin__h508243[56:5] == 52'd0 || guard__h500023 != 2'b0), + _theResult___fst_exp__h508253 == 11'd0 && + (sfdin__h508247[56:5] == 52'd0 || guard__h500027 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h509081 == 11'd2047 && - _theResult___fst_sfd__h509082 == 52'd0, + _theResult___fst_exp__h509085 == 11'd2047 && + _theResult___fst_sfd__h509086 == 52'd0, 1'd0, - _theResult___fst_exp__h508249 != 11'd2047 && - guard__h500023 != 2'b0 } ; + _theResult___fst_exp__h508253 != 11'd2047 && + guard__h500027 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777 = { 3'd0, - _theResult___fst_exp__h547050 == 11'd0 && - (sfdin__h547044[56:5] == 52'd0 || guard__h538824 != 2'b0), + _theResult___fst_exp__h547054 == 11'd0 && + (sfdin__h547048[56:5] == 52'd0 || guard__h538828 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h547882 == 11'd2047 && - _theResult___fst_sfd__h547883 == 52'd0, + _theResult___fst_exp__h547886 == 11'd2047 && + _theResult___fst_sfd__h547887 == 52'd0, 1'd0, - _theResult___fst_exp__h547050 != 11'd2047 && - guard__h538824 != 2'b0 } ; + _theResult___fst_exp__h547054 != 11'd2047 && + guard__h538828 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821 = { 3'd0, - _theResult___fst_exp__h586251 == 11'd0 && - (sfdin__h586245[56:5] == 52'd0 || guard__h578025 != 2'b0), + _theResult___fst_exp__h586255 == 11'd0 && + (sfdin__h586249[56:5] == 52'd0 || guard__h578029 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h587083 == 11'd2047 && - _theResult___fst_sfd__h587084 == 52'd0, + _theResult___fst_exp__h587087 == 11'd2047 && + _theResult___fst_sfd__h587088 == 52'd0, 1'd0, - _theResult___fst_exp__h586251 != 11'd2047 && - guard__h578025 != 2'b0 } ; + _theResult___fst_exp__h586255 != 11'd2047 && + guard__h578029 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ^ @@ -23371,15 +23371,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = { 3'd0, - _theResult___fst_exp__h369176 == 8'd0 && - (sfdin__h369170[56:34] == 23'd0 || guard__h360948 != 2'b0), + _theResult___fst_exp__h369179 == 8'd0 && + (sfdin__h369173[56:34] == 23'd0 || guard__h360951 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h369773 == 8'd255 && - _theResult___fst_sfd__h369774 == 23'd0, + _theResult___fst_exp__h369776 == 8'd255 && + _theResult___fst_sfd__h369777 == 23'd0, 1'd0, - _theResult___fst_exp__h369176 != 8'd255 && - guard__h360948 != 2'b0 } ; + _theResult___fst_exp__h369179 != 8'd255 && + guard__h360951 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ @@ -23387,15 +23387,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = { 3'd0, - _theResult___fst_exp__h414866 == 8'd0 && - (sfdin__h414860[56:34] == 23'd0 || guard__h406638 != 2'b0), + _theResult___fst_exp__h414869 == 8'd0 && + (sfdin__h414863[56:34] == 23'd0 || guard__h406641 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h415463 == 8'd255 && - _theResult___fst_sfd__h415464 == 23'd0, + _theResult___fst_exp__h415466 == 8'd255 && + _theResult___fst_sfd__h415467 == 23'd0, 1'd0, - _theResult___fst_exp__h414866 != 8'd255 && - guard__h406638 != 2'b0 } ; + _theResult___fst_exp__h414869 != 8'd255 && + guard__h406641 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ @@ -23403,15 +23403,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = { 3'd0, - _theResult___fst_exp__h460554 == 8'd0 && - (sfdin__h460548[56:34] == 23'd0 || guard__h452326 != 2'b0), + _theResult___fst_exp__h460557 == 8'd0 && + (sfdin__h460551[56:34] == 23'd0 || guard__h452329 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461151 == 8'd255 && - _theResult___fst_sfd__h461152 == 23'd0, + _theResult___fst_exp__h461154 == 8'd255 && + _theResult___fst_sfd__h461155 == 23'd0, 1'd0, - _theResult___fst_exp__h460554 != 8'd255 && - guard__h452326 != 2'b0 } ; + _theResult___fst_exp__h460557 != 8'd255 && + guard__h452329 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^ @@ -23425,15 +23425,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = { 3'd0, - _theResult___fst_exp__h360066 == 8'd0 && - guard__h352018 != 2'b0, + _theResult___fst_exp__h360069 == 8'd0 && + guard__h352021 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h360589 == 8'd255 && - _theResult___fst_sfd__h360590 == 23'd0, + _theResult___fst_exp__h360592 == 8'd255 && + _theResult___fst_sfd__h360593 == 23'd0, 1'd0, - _theResult___fst_exp__h360066 != 8'd255 && - guard__h352018 != 2'b0 } ; + _theResult___fst_exp__h360069 != 8'd255 && + guard__h352021 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ @@ -23447,15 +23447,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = { 3'd0, - _theResult___fst_exp__h405756 == 8'd0 && - guard__h397708 != 2'b0, + _theResult___fst_exp__h405759 == 8'd0 && + guard__h397711 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h406279 == 8'd255 && - _theResult___fst_sfd__h406280 == 23'd0, + _theResult___fst_exp__h406282 == 8'd255 && + _theResult___fst_sfd__h406283 == 23'd0, 1'd0, - _theResult___fst_exp__h405756 != 8'd255 && - guard__h397708 != 2'b0 } ; + _theResult___fst_exp__h405759 != 8'd255 && + guard__h397711 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ @@ -23469,15 +23469,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = { 3'd0, - _theResult___fst_exp__h451444 == 8'd0 && - guard__h443396 != 2'b0, + _theResult___fst_exp__h451447 == 8'd0 && + guard__h443399 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h451967 == 8'd255 && - _theResult___fst_sfd__h451968 == 23'd0, + _theResult___fst_exp__h451970 == 8'd255 && + _theResult___fst_sfd__h451971 == 23'd0, 1'd0, - _theResult___fst_exp__h451444 != 8'd255 && - guard__h443396 != 2'b0 } ; + _theResult___fst_exp__h451447 != 8'd255 && + guard__h443399 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ^ @@ -23491,37 +23491,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719 = { 3'd0, - _theResult___fst_exp__h498672 == 11'd0 && - guard__h490711 != 2'b0, + _theResult___fst_exp__h498676 == 11'd0 && + guard__h490715 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h499430 == 11'd2047 && - _theResult___fst_sfd__h499431 == 52'd0, + _theResult___fst_exp__h499434 == 11'd2047 && + _theResult___fst_sfd__h499435 == 52'd0, 1'd0, - _theResult___fst_exp__h498672 != 11'd2047 && - guard__h490711 != 2'b0 } ; + _theResult___fst_exp__h498676 != 11'd2047 && + guard__h490715 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760 = { 3'd0, - _theResult___fst_exp__h537473 == 11'd0 && - guard__h529512 != 2'b0, + _theResult___fst_exp__h537477 == 11'd0 && + guard__h529516 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h538231 == 11'd2047 && - _theResult___fst_sfd__h538232 == 52'd0, + _theResult___fst_exp__h538235 == 11'd2047 && + _theResult___fst_sfd__h538236 == 52'd0, 1'd0, - _theResult___fst_exp__h537473 != 11'd2047 && - guard__h529512 != 2'b0 } ; + _theResult___fst_exp__h537477 != 11'd2047 && + guard__h529516 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804 = { 3'd0, - _theResult___fst_exp__h576674 == 11'd0 && - guard__h568713 != 2'b0, + _theResult___fst_exp__h576678 == 11'd0 && + guard__h568717 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h577432 == 11'd2047 && - _theResult___fst_sfd__h577433 == 52'd0, + _theResult___fst_exp__h577436 == 11'd2047 && + _theResult___fst_sfd__h577437 == 52'd0, 1'd0, - _theResult___fst_exp__h576674 != 11'd2047 && - guard__h568713 != 2'b0 } ; + _theResult___fst_exp__h576678 != 11'd2047 && + guard__h568717 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ^ @@ -23547,7 +23547,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2614_BI_ETC___d13760 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -23559,33 +23559,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h335694 >> + sfd__h335697 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h381389 >> + sfd__h381392 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427077 >> + sfd__h427080 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118 = - sfd__h518613 >> + sfd__h518617 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645 = - sfd__h479671 >> + sfd__h479675 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355 = - sfd__h557814 >> + sfd__h557818 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227 = - medeleg_csr__read__h607135[i__h692195] ; + medeleg_csr__read__h607140[i__h692204] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 = - mideleg_csr__read__h607230[i__h692355] ; + mideleg_csr__read__h607235[i__h692364] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = 12'd3074 - { 6'd0, @@ -24180,7 +24180,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h661036 == 1'd0 && + k__h661045 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd0 && @@ -24199,7 +24199,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo28 = + assign _dfoo26 = rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd8 || @@ -24287,1430 +24287,1430 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h293741 = + assign _theResult_____2__h293743 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294020 : + next_deqP___1__h294022 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h301737 = + assign _theResult_____2__h301739 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302016 : + next_deqP___1__h302018 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h307731 = + assign _theResult_____2__h307733 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308297 : + next_deqP___1__h308299 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h315585 = + assign _theResult_____2__h315587 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316151 : + next_deqP___1__h316153 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h325929 = + assign _theResult_____2__h325931 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326208 : + next_deqP___1__h326210 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329154 = + assign _theResult_____2__h329156 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h329433 : + next_deqP___1__h329435 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343299 = - (value__h343921 == 54'd0) ? sfd__h335694 : 57'd1 ; - assign _theResult____h360938 = + assign _theResult____h343302 = + (value__h343924 == 54'd0) ? sfd__h335697 : 57'd1 ; + assign _theResult____h360941 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ 12'h800) < 12'd2105) ? - result__h361551 : - _theResult____h343299 ; - assign _theResult____h388991 = - (value__h389611 == 54'd0) ? sfd__h381389 : 57'd1 ; - assign _theResult____h406628 = + result__h361554 : + _theResult____h343302 ; + assign _theResult____h388994 = + (value__h389614 == 54'd0) ? sfd__h381392 : 57'd1 ; + assign _theResult____h406631 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ 12'h800) < 12'd2105) ? - result__h407241 : - _theResult____h388991 ; - assign _theResult____h434679 = - (value__h435299 == 54'd0) ? sfd__h427077 : 57'd1 ; - assign _theResult____h452316 = + result__h407244 : + _theResult____h388994 ; + assign _theResult____h434682 = + (value__h435302 == 54'd0) ? sfd__h427080 : 57'd1 ; + assign _theResult____h452319 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ 12'h800) < 12'd2105) ? - result__h452929 : - _theResult____h434679 ; - assign _theResult____h500013 = + result__h452932 : + _theResult____h434682 ; + assign _theResult____h500017 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ^ 12'h800) < 12'd2105) ? - result__h500626 : - ((value__h484229 == 25'd0) ? sfd__h479671 : 57'd1) ; - assign _theResult____h538814 = + result__h500630 : + ((value__h484233 == 25'd0) ? sfd__h479675 : 57'd1) ; + assign _theResult____h538818 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ^ 12'h800) < 12'd2105) ? - result__h539427 : - ((value__h523030 == 25'd0) ? sfd__h518613 : 57'd1) ; - assign _theResult____h578015 = + result__h539431 : + ((value__h523034 == 25'd0) ? sfd__h518617 : 57'd1) ; + assign _theResult____h578019 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ^ 12'h800) < 12'd2105) ? - result__h578628 : - ((value__h562231 == 25'd0) ? sfd__h557814 : 57'd1) ; - assign _theResult____h645389 = + result__h578632 : + ((value__h562235 == 25'd0) ? sfd__h557818 : 57'd1) ; + assign _theResult____h645398 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h645886 : + enabled_ints___1__h645895 : 15'd0 ; - assign _theResult___exp__h351926 = - sfd__h351502[24] ? - ((_theResult___fst_exp__h351410 == 8'd254) ? + assign _theResult___exp__h351929 = + sfd__h351505[24] ? + ((_theResult___fst_exp__h351413 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378443) : - ((_theResult___fst_exp__h351410 == 8'd0 && - sfd__h351502[24:23] == 2'b01) ? + din_inc___2_exp__h378446) : + ((_theResult___fst_exp__h351413 == 8'd0 && + sfd__h351505[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h351410) ; - assign _theResult___exp__h360508 = - sfd__h360084[24] ? - ((_theResult___fst_exp__h360066 == 8'd254) ? + _theResult___fst_exp__h351413) ; + assign _theResult___exp__h360511 = + sfd__h360087[24] ? + ((_theResult___fst_exp__h360069 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378467) : - ((_theResult___fst_exp__h360066 == 8'd0 && - sfd__h360084[24:23] == 2'b01) ? + din_inc___2_exp__h378470) : + ((_theResult___fst_exp__h360069 == 8'd0 && + sfd__h360087[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360066) ; - assign _theResult___exp__h369692 = - sfd__h369268[24] ? - ((_theResult___fst_exp__h369176 == 8'd254) ? + _theResult___fst_exp__h360069) ; + assign _theResult___exp__h369695 = + sfd__h369271[24] ? + ((_theResult___fst_exp__h369179 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378497) : - ((_theResult___fst_exp__h369176 == 8'd0 && - sfd__h369268[24:23] == 2'b01) ? + din_inc___2_exp__h378500) : + ((_theResult___fst_exp__h369179 == 8'd0 && + sfd__h369271[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369176) ; - assign _theResult___exp__h378328 = - sfd__h377880[24] ? - ((_theResult___fst_exp__h377861 == 8'd254) ? + _theResult___fst_exp__h369179) ; + assign _theResult___exp__h378331 = + sfd__h377883[24] ? + ((_theResult___fst_exp__h377864 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378521) : - ((_theResult___fst_exp__h377861 == 8'd0 && - sfd__h377880[24:23] == 2'b01) ? + din_inc___2_exp__h378524) : + ((_theResult___fst_exp__h377864 == 8'd0 && + sfd__h377883[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h377861) ; - assign _theResult___exp__h378430 = + _theResult___fst_exp__h377864) ; + assign _theResult___exp__h378433 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378421 ; - assign _theResult___exp__h397616 = - sfd__h397192[24] ? - ((_theResult___fst_exp__h397100 == 8'd254) ? + _theResult___fst_exp__h378424 ; + assign _theResult___exp__h397619 = + sfd__h397195[24] ? + ((_theResult___fst_exp__h397103 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424133) : - ((_theResult___fst_exp__h397100 == 8'd0 && - sfd__h397192[24:23] == 2'b01) ? + din_inc___2_exp__h424136) : + ((_theResult___fst_exp__h397103 == 8'd0 && + sfd__h397195[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397100) ; - assign _theResult___exp__h406198 = - sfd__h405774[24] ? - ((_theResult___fst_exp__h405756 == 8'd254) ? + _theResult___fst_exp__h397103) ; + assign _theResult___exp__h406201 = + sfd__h405777[24] ? + ((_theResult___fst_exp__h405759 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424157) : - ((_theResult___fst_exp__h405756 == 8'd0 && - sfd__h405774[24:23] == 2'b01) ? + din_inc___2_exp__h424160) : + ((_theResult___fst_exp__h405759 == 8'd0 && + sfd__h405777[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h405756) ; - assign _theResult___exp__h415382 = - sfd__h414958[24] ? - ((_theResult___fst_exp__h414866 == 8'd254) ? + _theResult___fst_exp__h405759) ; + assign _theResult___exp__h415385 = + sfd__h414961[24] ? + ((_theResult___fst_exp__h414869 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424187) : - ((_theResult___fst_exp__h414866 == 8'd0 && - sfd__h414958[24:23] == 2'b01) ? + din_inc___2_exp__h424190) : + ((_theResult___fst_exp__h414869 == 8'd0 && + sfd__h414961[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h414866) ; - assign _theResult___exp__h424018 = - sfd__h423570[24] ? - ((_theResult___fst_exp__h423551 == 8'd254) ? + _theResult___fst_exp__h414869) ; + assign _theResult___exp__h424021 = + sfd__h423573[24] ? + ((_theResult___fst_exp__h423554 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424211) : - ((_theResult___fst_exp__h423551 == 8'd0 && - sfd__h423570[24:23] == 2'b01) ? + din_inc___2_exp__h424214) : + ((_theResult___fst_exp__h423554 == 8'd0 && + sfd__h423573[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h423551) ; - assign _theResult___exp__h424120 = + _theResult___fst_exp__h423554) ; + assign _theResult___exp__h424123 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424111 ; - assign _theResult___exp__h443304 = - sfd__h442880[24] ? - ((_theResult___fst_exp__h442788 == 8'd254) ? + _theResult___fst_exp__h424114 ; + assign _theResult___exp__h443307 = + sfd__h442883[24] ? + ((_theResult___fst_exp__h442791 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469821) : - ((_theResult___fst_exp__h442788 == 8'd0 && - sfd__h442880[24:23] == 2'b01) ? + din_inc___2_exp__h469824) : + ((_theResult___fst_exp__h442791 == 8'd0 && + sfd__h442883[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h442788) ; - assign _theResult___exp__h451886 = - sfd__h451462[24] ? - ((_theResult___fst_exp__h451444 == 8'd254) ? + _theResult___fst_exp__h442791) ; + assign _theResult___exp__h451889 = + sfd__h451465[24] ? + ((_theResult___fst_exp__h451447 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469845) : - ((_theResult___fst_exp__h451444 == 8'd0 && - sfd__h451462[24:23] == 2'b01) ? + din_inc___2_exp__h469848) : + ((_theResult___fst_exp__h451447 == 8'd0 && + sfd__h451465[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h451444) ; - assign _theResult___exp__h461070 = - sfd__h460646[24] ? - ((_theResult___fst_exp__h460554 == 8'd254) ? + _theResult___fst_exp__h451447) ; + assign _theResult___exp__h461073 = + sfd__h460649[24] ? + ((_theResult___fst_exp__h460557 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469875) : - ((_theResult___fst_exp__h460554 == 8'd0 && - sfd__h460646[24:23] == 2'b01) ? + din_inc___2_exp__h469878) : + ((_theResult___fst_exp__h460557 == 8'd0 && + sfd__h460649[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h460554) ; - assign _theResult___exp__h469706 = - sfd__h469258[24] ? - ((_theResult___fst_exp__h469239 == 8'd254) ? + _theResult___fst_exp__h460557) ; + assign _theResult___exp__h469709 = + sfd__h469261[24] ? + ((_theResult___fst_exp__h469242 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469899) : - ((_theResult___fst_exp__h469239 == 8'd0 && - sfd__h469258[24:23] == 2'b01) ? + din_inc___2_exp__h469902) : + ((_theResult___fst_exp__h469242 == 8'd0 && + sfd__h469261[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469239) ; - assign _theResult___exp__h469808 = + _theResult___fst_exp__h469242) ; + assign _theResult___exp__h469811 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469799 ; - assign _theResult___exp__h499327 = - sfd__h498690[53] ? - ((_theResult___fst_exp__h498672 == 11'd2046) ? + _theResult___fst_exp__h469802 ; + assign _theResult___exp__h499331 = + sfd__h498694[53] ? + ((_theResult___fst_exp__h498676 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517922) : - ((_theResult___fst_exp__h498672 == 11'd0 && - sfd__h498690[53:52] == 2'b01) ? + din_inc___2_exp__h517926) : + ((_theResult___fst_exp__h498676 == 11'd0 && + sfd__h498694[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h498672) ; - assign _theResult___exp__h508978 = - sfd__h508341[53] ? - ((_theResult___fst_exp__h508249 == 11'd2046) ? + _theResult___fst_exp__h498676) ; + assign _theResult___exp__h508982 = + sfd__h508345[53] ? + ((_theResult___fst_exp__h508253 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517957) : - ((_theResult___fst_exp__h508249 == 11'd0 && - sfd__h508341[53:52] == 2'b01) ? + din_inc___2_exp__h517961) : + ((_theResult___fst_exp__h508253 == 11'd0 && + sfd__h508345[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508249) ; - assign _theResult___exp__h517762 = - sfd__h517101[53] ? - ((_theResult___fst_exp__h517082 == 11'd2046) ? + _theResult___fst_exp__h508253) ; + assign _theResult___exp__h517766 = + sfd__h517105[53] ? + ((_theResult___fst_exp__h517086 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517983) : - ((_theResult___fst_exp__h517082 == 11'd0 && - sfd__h517101[53:52] == 2'b01) ? + din_inc___2_exp__h517987) : + ((_theResult___fst_exp__h517086 == 11'd0 && + sfd__h517105[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517082) ; - assign _theResult___exp__h538128 = - sfd__h537491[53] ? - ((_theResult___fst_exp__h537473 == 11'd2046) ? + _theResult___fst_exp__h517086) ; + assign _theResult___exp__h538132 = + sfd__h537495[53] ? + ((_theResult___fst_exp__h537477 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556723) : - ((_theResult___fst_exp__h537473 == 11'd0 && - sfd__h537491[53:52] == 2'b01) ? + din_inc___2_exp__h556727) : + ((_theResult___fst_exp__h537477 == 11'd0 && + sfd__h537495[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h537473) ; - assign _theResult___exp__h547779 = - sfd__h547142[53] ? - ((_theResult___fst_exp__h547050 == 11'd2046) ? + _theResult___fst_exp__h537477) ; + assign _theResult___exp__h547783 = + sfd__h547146[53] ? + ((_theResult___fst_exp__h547054 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556758) : - ((_theResult___fst_exp__h547050 == 11'd0 && - sfd__h547142[53:52] == 2'b01) ? + din_inc___2_exp__h556762) : + ((_theResult___fst_exp__h547054 == 11'd0 && + sfd__h547146[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547050) ; - assign _theResult___exp__h556563 = - sfd__h555902[53] ? - ((_theResult___fst_exp__h555883 == 11'd2046) ? + _theResult___fst_exp__h547054) ; + assign _theResult___exp__h556567 = + sfd__h555906[53] ? + ((_theResult___fst_exp__h555887 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556784) : - ((_theResult___fst_exp__h555883 == 11'd0 && - sfd__h555902[53:52] == 2'b01) ? + din_inc___2_exp__h556788) : + ((_theResult___fst_exp__h555887 == 11'd0 && + sfd__h555906[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555883) ; - assign _theResult___exp__h577329 = - sfd__h576692[53] ? - ((_theResult___fst_exp__h576674 == 11'd2046) ? + _theResult___fst_exp__h555887) ; + assign _theResult___exp__h577333 = + sfd__h576696[53] ? + ((_theResult___fst_exp__h576678 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595924) : - ((_theResult___fst_exp__h576674 == 11'd0 && - sfd__h576692[53:52] == 2'b01) ? + din_inc___2_exp__h595928) : + ((_theResult___fst_exp__h576678 == 11'd0 && + sfd__h576696[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h576674) ; - assign _theResult___exp__h586980 = - sfd__h586343[53] ? - ((_theResult___fst_exp__h586251 == 11'd2046) ? + _theResult___fst_exp__h576678) ; + assign _theResult___exp__h586984 = + sfd__h586347[53] ? + ((_theResult___fst_exp__h586255 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595959) : - ((_theResult___fst_exp__h586251 == 11'd0 && - sfd__h586343[53:52] == 2'b01) ? + din_inc___2_exp__h595963) : + ((_theResult___fst_exp__h586255 == 11'd0 && + sfd__h586347[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h586251) ; - assign _theResult___exp__h595764 = - sfd__h595103[53] ? - ((_theResult___fst_exp__h595084 == 11'd2046) ? + _theResult___fst_exp__h586255) ; + assign _theResult___exp__h595768 = + sfd__h595107[53] ? + ((_theResult___fst_exp__h595088 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595985) : - ((_theResult___fst_exp__h595084 == 11'd0 && - sfd__h595103[53:52] == 2'b01) ? + din_inc___2_exp__h595989) : + ((_theResult___fst_exp__h595088 == 11'd0 && + sfd__h595107[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595084) ; - assign _theResult___fst__h600257 = - a__h599835[63] ? a___1__h600262 : a__h599835 ; - assign _theResult___fst_exp__h351410 = - _theResult____h343299[56] ? + _theResult___fst_exp__h595088) ; + assign _theResult___fst__h600261 = + a__h599839[63] ? a___1__h600266 : a__h599839 ; + assign _theResult___fst_exp__h351413 = + _theResult____h343302[56] ? 8'd2 : - _theResult___fst_exp__h351484 ; - assign _theResult___fst_exp__h351475 = + _theResult___fst_exp__h351487 ; + assign _theResult___fst_exp__h351478 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h351481 = - (!_theResult____h343299[56] && !_theResult____h343299[55] && - !_theResult____h343299[54] && - !_theResult____h343299[53] && - !_theResult____h343299[52] && - !_theResult____h343299[51] && - !_theResult____h343299[50] && - !_theResult____h343299[49] && - !_theResult____h343299[48] && - !_theResult____h343299[47] && - !_theResult____h343299[46] && - !_theResult____h343299[45] && - !_theResult____h343299[44] && - !_theResult____h343299[43] && - !_theResult____h343299[42] && - !_theResult____h343299[41] && - !_theResult____h343299[40] && - !_theResult____h343299[39] && - !_theResult____h343299[38] && - !_theResult____h343299[37] && - !_theResult____h343299[36] && - !_theResult____h343299[35] && - !_theResult____h343299[34] && - !_theResult____h343299[33] && - !_theResult____h343299[32] && - !_theResult____h343299[31] && - !_theResult____h343299[30] && - !_theResult____h343299[29] && - !_theResult____h343299[28] && - !_theResult____h343299[27] && - !_theResult____h343299[26] && - !_theResult____h343299[25] && - !_theResult____h343299[24] && - !_theResult____h343299[23] && - !_theResult____h343299[22] && - !_theResult____h343299[21] && - !_theResult____h343299[20] && - !_theResult____h343299[19] && - !_theResult____h343299[18] && - !_theResult____h343299[17] && - !_theResult____h343299[16] && - !_theResult____h343299[15] && - !_theResult____h343299[14] && - !_theResult____h343299[13] && - !_theResult____h343299[12] && - !_theResult____h343299[11] && - !_theResult____h343299[10] && - !_theResult____h343299[9] && - !_theResult____h343299[8] && - !_theResult____h343299[7] && - !_theResult____h343299[6] && - !_theResult____h343299[5] && - !_theResult____h343299[4] && - !_theResult____h343299[3] && - !_theResult____h343299[2] && - !_theResult____h343299[1] && - !_theResult____h343299[0] || + assign _theResult___fst_exp__h351484 = + (!_theResult____h343302[56] && !_theResult____h343302[55] && + !_theResult____h343302[54] && + !_theResult____h343302[53] && + !_theResult____h343302[52] && + !_theResult____h343302[51] && + !_theResult____h343302[50] && + !_theResult____h343302[49] && + !_theResult____h343302[48] && + !_theResult____h343302[47] && + !_theResult____h343302[46] && + !_theResult____h343302[45] && + !_theResult____h343302[44] && + !_theResult____h343302[43] && + !_theResult____h343302[42] && + !_theResult____h343302[41] && + !_theResult____h343302[40] && + !_theResult____h343302[39] && + !_theResult____h343302[38] && + !_theResult____h343302[37] && + !_theResult____h343302[36] && + !_theResult____h343302[35] && + !_theResult____h343302[34] && + !_theResult____h343302[33] && + !_theResult____h343302[32] && + !_theResult____h343302[31] && + !_theResult____h343302[30] && + !_theResult____h343302[29] && + !_theResult____h343302[28] && + !_theResult____h343302[27] && + !_theResult____h343302[26] && + !_theResult____h343302[25] && + !_theResult____h343302[24] && + !_theResult____h343302[23] && + !_theResult____h343302[22] && + !_theResult____h343302[21] && + !_theResult____h343302[20] && + !_theResult____h343302[19] && + !_theResult____h343302[18] && + !_theResult____h343302[17] && + !_theResult____h343302[16] && + !_theResult____h343302[15] && + !_theResult____h343302[14] && + !_theResult____h343302[13] && + !_theResult____h343302[12] && + !_theResult____h343302[11] && + !_theResult____h343302[10] && + !_theResult____h343302[9] && + !_theResult____h343302[8] && + !_theResult____h343302[7] && + !_theResult____h343302[6] && + !_theResult____h343302[5] && + !_theResult____h343302[4] && + !_theResult____h343302[3] && + !_theResult____h343302[2] && + !_theResult____h343302[1] && + !_theResult____h343302[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? 8'd0 : - _theResult___fst_exp__h351475 ; - assign _theResult___fst_exp__h351484 = - (!_theResult____h343299[56] && _theResult____h343299[55]) ? + _theResult___fst_exp__h351478 ; + assign _theResult___fst_exp__h351487 = + (!_theResult____h343302[56] && _theResult____h343302[55]) ? 8'd1 : - _theResult___fst_exp__h351481 ; - assign _theResult___fst_exp__h352007 = - (_theResult___fst_exp__h351410 == 8'd255) ? - _theResult___fst_exp__h351410 : - _theResult___fst_exp__h352004 ; - assign _theResult___fst_exp__h360057 = + _theResult___fst_exp__h351484 ; + assign _theResult___fst_exp__h352010 = + (_theResult___fst_exp__h351413 == 8'd255) ? + _theResult___fst_exp__h351413 : + _theResult___fst_exp__h352007 ; + assign _theResult___fst_exp__h360060 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360063 = + assign _theResult___fst_exp__h360066 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? 8'd0 : - _theResult___fst_exp__h360057 ; - assign _theResult___fst_exp__h360066 = + _theResult___fst_exp__h360060 ; + assign _theResult___fst_exp__h360069 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360063 : - 8'd129 ; - assign _theResult___fst_exp__h360589 = - (_theResult___fst_exp__h360066 == 8'd255) ? _theResult___fst_exp__h360066 : - _theResult___fst_exp__h360586 ; - assign _theResult___fst_exp__h369176 = - _theResult____h360938[56] ? + 8'd129 ; + assign _theResult___fst_exp__h360592 = + (_theResult___fst_exp__h360069 == 8'd255) ? + _theResult___fst_exp__h360069 : + _theResult___fst_exp__h360589 ; + assign _theResult___fst_exp__h369179 = + _theResult____h360941[56] ? 8'd2 : - _theResult___fst_exp__h369250 ; - assign _theResult___fst_exp__h369241 = + _theResult___fst_exp__h369253 ; + assign _theResult___fst_exp__h369244 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369247 = - (!_theResult____h360938[56] && !_theResult____h360938[55] && - !_theResult____h360938[54] && - !_theResult____h360938[53] && - !_theResult____h360938[52] && - !_theResult____h360938[51] && - !_theResult____h360938[50] && - !_theResult____h360938[49] && - !_theResult____h360938[48] && - !_theResult____h360938[47] && - !_theResult____h360938[46] && - !_theResult____h360938[45] && - !_theResult____h360938[44] && - !_theResult____h360938[43] && - !_theResult____h360938[42] && - !_theResult____h360938[41] && - !_theResult____h360938[40] && - !_theResult____h360938[39] && - !_theResult____h360938[38] && - !_theResult____h360938[37] && - !_theResult____h360938[36] && - !_theResult____h360938[35] && - !_theResult____h360938[34] && - !_theResult____h360938[33] && - !_theResult____h360938[32] && - !_theResult____h360938[31] && - !_theResult____h360938[30] && - !_theResult____h360938[29] && - !_theResult____h360938[28] && - !_theResult____h360938[27] && - !_theResult____h360938[26] && - !_theResult____h360938[25] && - !_theResult____h360938[24] && - !_theResult____h360938[23] && - !_theResult____h360938[22] && - !_theResult____h360938[21] && - !_theResult____h360938[20] && - !_theResult____h360938[19] && - !_theResult____h360938[18] && - !_theResult____h360938[17] && - !_theResult____h360938[16] && - !_theResult____h360938[15] && - !_theResult____h360938[14] && - !_theResult____h360938[13] && - !_theResult____h360938[12] && - !_theResult____h360938[11] && - !_theResult____h360938[10] && - !_theResult____h360938[9] && - !_theResult____h360938[8] && - !_theResult____h360938[7] && - !_theResult____h360938[6] && - !_theResult____h360938[5] && - !_theResult____h360938[4] && - !_theResult____h360938[3] && - !_theResult____h360938[2] && - !_theResult____h360938[1] && - !_theResult____h360938[0] || + assign _theResult___fst_exp__h369250 = + (!_theResult____h360941[56] && !_theResult____h360941[55] && + !_theResult____h360941[54] && + !_theResult____h360941[53] && + !_theResult____h360941[52] && + !_theResult____h360941[51] && + !_theResult____h360941[50] && + !_theResult____h360941[49] && + !_theResult____h360941[48] && + !_theResult____h360941[47] && + !_theResult____h360941[46] && + !_theResult____h360941[45] && + !_theResult____h360941[44] && + !_theResult____h360941[43] && + !_theResult____h360941[42] && + !_theResult____h360941[41] && + !_theResult____h360941[40] && + !_theResult____h360941[39] && + !_theResult____h360941[38] && + !_theResult____h360941[37] && + !_theResult____h360941[36] && + !_theResult____h360941[35] && + !_theResult____h360941[34] && + !_theResult____h360941[33] && + !_theResult____h360941[32] && + !_theResult____h360941[31] && + !_theResult____h360941[30] && + !_theResult____h360941[29] && + !_theResult____h360941[28] && + !_theResult____h360941[27] && + !_theResult____h360941[26] && + !_theResult____h360941[25] && + !_theResult____h360941[24] && + !_theResult____h360941[23] && + !_theResult____h360941[22] && + !_theResult____h360941[21] && + !_theResult____h360941[20] && + !_theResult____h360941[19] && + !_theResult____h360941[18] && + !_theResult____h360941[17] && + !_theResult____h360941[16] && + !_theResult____h360941[15] && + !_theResult____h360941[14] && + !_theResult____h360941[13] && + !_theResult____h360941[12] && + !_theResult____h360941[11] && + !_theResult____h360941[10] && + !_theResult____h360941[9] && + !_theResult____h360941[8] && + !_theResult____h360941[7] && + !_theResult____h360941[6] && + !_theResult____h360941[5] && + !_theResult____h360941[4] && + !_theResult____h360941[3] && + !_theResult____h360941[2] && + !_theResult____h360941[1] && + !_theResult____h360941[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? 8'd0 : - _theResult___fst_exp__h369241 ; - assign _theResult___fst_exp__h369250 = - (!_theResult____h360938[56] && _theResult____h360938[55]) ? + _theResult___fst_exp__h369244 ; + assign _theResult___fst_exp__h369253 = + (!_theResult____h360941[56] && _theResult____h360941[55]) ? 8'd1 : - _theResult___fst_exp__h369247 ; - assign _theResult___fst_exp__h369773 = - (_theResult___fst_exp__h369176 == 8'd255) ? - _theResult___fst_exp__h369176 : - _theResult___fst_exp__h369770 ; - assign _theResult___fst_exp__h377813 = + _theResult___fst_exp__h369250 ; + assign _theResult___fst_exp__h369776 = + (_theResult___fst_exp__h369179 == 8'd255) ? + _theResult___fst_exp__h369179 : + _theResult___fst_exp__h369773 ; + assign _theResult___fst_exp__h377816 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ; - assign _theResult___fst_exp__h377852 = + assign _theResult___fst_exp__h377855 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h377858 = + assign _theResult___fst_exp__h377861 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? 8'd0 : - _theResult___fst_exp__h377852 ; - assign _theResult___fst_exp__h377861 = + _theResult___fst_exp__h377855 ; + assign _theResult___fst_exp__h377864 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h377858 : - _theResult___fst_exp__h377813 ; - assign _theResult___fst_exp__h378409 = - (_theResult___fst_exp__h377861 == 8'd255) ? _theResult___fst_exp__h377861 : - _theResult___fst_exp__h378406 ; - assign _theResult___fst_exp__h378418 = + _theResult___fst_exp__h377816 ; + assign _theResult___fst_exp__h378412 = + (_theResult___fst_exp__h377864 == 8'd255) ? + _theResult___fst_exp__h377864 : + _theResult___fst_exp__h378409 ; + assign _theResult___fst_exp__h378421 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h360592 : - _theResult___fst_exp__h343281) : + _theResult___snd_fst_exp__h360595 : + _theResult___fst_exp__h343284) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h378412 : - _theResult___fst_exp__h343281) ; - assign _theResult___fst_exp__h378421 = + _theResult___snd_fst_exp__h378415 : + _theResult___fst_exp__h343284) ; + assign _theResult___fst_exp__h378424 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h378418 ; - assign _theResult___fst_exp__h397100 = - _theResult____h388991[56] ? + _theResult___fst_exp__h378421 ; + assign _theResult___fst_exp__h397103 = + _theResult____h388994[56] ? 8'd2 : - _theResult___fst_exp__h397174 ; - assign _theResult___fst_exp__h397165 = + _theResult___fst_exp__h397177 ; + assign _theResult___fst_exp__h397168 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397171 = - (!_theResult____h388991[56] && !_theResult____h388991[55] && - !_theResult____h388991[54] && - !_theResult____h388991[53] && - !_theResult____h388991[52] && - !_theResult____h388991[51] && - !_theResult____h388991[50] && - !_theResult____h388991[49] && - !_theResult____h388991[48] && - !_theResult____h388991[47] && - !_theResult____h388991[46] && - !_theResult____h388991[45] && - !_theResult____h388991[44] && - !_theResult____h388991[43] && - !_theResult____h388991[42] && - !_theResult____h388991[41] && - !_theResult____h388991[40] && - !_theResult____h388991[39] && - !_theResult____h388991[38] && - !_theResult____h388991[37] && - !_theResult____h388991[36] && - !_theResult____h388991[35] && - !_theResult____h388991[34] && - !_theResult____h388991[33] && - !_theResult____h388991[32] && - !_theResult____h388991[31] && - !_theResult____h388991[30] && - !_theResult____h388991[29] && - !_theResult____h388991[28] && - !_theResult____h388991[27] && - !_theResult____h388991[26] && - !_theResult____h388991[25] && - !_theResult____h388991[24] && - !_theResult____h388991[23] && - !_theResult____h388991[22] && - !_theResult____h388991[21] && - !_theResult____h388991[20] && - !_theResult____h388991[19] && - !_theResult____h388991[18] && - !_theResult____h388991[17] && - !_theResult____h388991[16] && - !_theResult____h388991[15] && - !_theResult____h388991[14] && - !_theResult____h388991[13] && - !_theResult____h388991[12] && - !_theResult____h388991[11] && - !_theResult____h388991[10] && - !_theResult____h388991[9] && - !_theResult____h388991[8] && - !_theResult____h388991[7] && - !_theResult____h388991[6] && - !_theResult____h388991[5] && - !_theResult____h388991[4] && - !_theResult____h388991[3] && - !_theResult____h388991[2] && - !_theResult____h388991[1] && - !_theResult____h388991[0] || + assign _theResult___fst_exp__h397174 = + (!_theResult____h388994[56] && !_theResult____h388994[55] && + !_theResult____h388994[54] && + !_theResult____h388994[53] && + !_theResult____h388994[52] && + !_theResult____h388994[51] && + !_theResult____h388994[50] && + !_theResult____h388994[49] && + !_theResult____h388994[48] && + !_theResult____h388994[47] && + !_theResult____h388994[46] && + !_theResult____h388994[45] && + !_theResult____h388994[44] && + !_theResult____h388994[43] && + !_theResult____h388994[42] && + !_theResult____h388994[41] && + !_theResult____h388994[40] && + !_theResult____h388994[39] && + !_theResult____h388994[38] && + !_theResult____h388994[37] && + !_theResult____h388994[36] && + !_theResult____h388994[35] && + !_theResult____h388994[34] && + !_theResult____h388994[33] && + !_theResult____h388994[32] && + !_theResult____h388994[31] && + !_theResult____h388994[30] && + !_theResult____h388994[29] && + !_theResult____h388994[28] && + !_theResult____h388994[27] && + !_theResult____h388994[26] && + !_theResult____h388994[25] && + !_theResult____h388994[24] && + !_theResult____h388994[23] && + !_theResult____h388994[22] && + !_theResult____h388994[21] && + !_theResult____h388994[20] && + !_theResult____h388994[19] && + !_theResult____h388994[18] && + !_theResult____h388994[17] && + !_theResult____h388994[16] && + !_theResult____h388994[15] && + !_theResult____h388994[14] && + !_theResult____h388994[13] && + !_theResult____h388994[12] && + !_theResult____h388994[11] && + !_theResult____h388994[10] && + !_theResult____h388994[9] && + !_theResult____h388994[8] && + !_theResult____h388994[7] && + !_theResult____h388994[6] && + !_theResult____h388994[5] && + !_theResult____h388994[4] && + !_theResult____h388994[3] && + !_theResult____h388994[2] && + !_theResult____h388994[1] && + !_theResult____h388994[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? 8'd0 : - _theResult___fst_exp__h397165 ; - assign _theResult___fst_exp__h397174 = - (!_theResult____h388991[56] && _theResult____h388991[55]) ? + _theResult___fst_exp__h397168 ; + assign _theResult___fst_exp__h397177 = + (!_theResult____h388994[56] && _theResult____h388994[55]) ? 8'd1 : - _theResult___fst_exp__h397171 ; - assign _theResult___fst_exp__h397697 = - (_theResult___fst_exp__h397100 == 8'd255) ? - _theResult___fst_exp__h397100 : - _theResult___fst_exp__h397694 ; - assign _theResult___fst_exp__h405747 = + _theResult___fst_exp__h397174 ; + assign _theResult___fst_exp__h397700 = + (_theResult___fst_exp__h397103 == 8'd255) ? + _theResult___fst_exp__h397103 : + _theResult___fst_exp__h397697 ; + assign _theResult___fst_exp__h405750 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h405753 = + assign _theResult___fst_exp__h405756 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? 8'd0 : - _theResult___fst_exp__h405747 ; - assign _theResult___fst_exp__h405756 = + _theResult___fst_exp__h405750 ; + assign _theResult___fst_exp__h405759 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h405753 : - 8'd129 ; - assign _theResult___fst_exp__h406279 = - (_theResult___fst_exp__h405756 == 8'd255) ? _theResult___fst_exp__h405756 : - _theResult___fst_exp__h406276 ; - assign _theResult___fst_exp__h414866 = - _theResult____h406628[56] ? + 8'd129 ; + assign _theResult___fst_exp__h406282 = + (_theResult___fst_exp__h405759 == 8'd255) ? + _theResult___fst_exp__h405759 : + _theResult___fst_exp__h406279 ; + assign _theResult___fst_exp__h414869 = + _theResult____h406631[56] ? 8'd2 : - _theResult___fst_exp__h414940 ; - assign _theResult___fst_exp__h414931 = + _theResult___fst_exp__h414943 ; + assign _theResult___fst_exp__h414934 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h414937 = - (!_theResult____h406628[56] && !_theResult____h406628[55] && - !_theResult____h406628[54] && - !_theResult____h406628[53] && - !_theResult____h406628[52] && - !_theResult____h406628[51] && - !_theResult____h406628[50] && - !_theResult____h406628[49] && - !_theResult____h406628[48] && - !_theResult____h406628[47] && - !_theResult____h406628[46] && - !_theResult____h406628[45] && - !_theResult____h406628[44] && - !_theResult____h406628[43] && - !_theResult____h406628[42] && - !_theResult____h406628[41] && - !_theResult____h406628[40] && - !_theResult____h406628[39] && - !_theResult____h406628[38] && - !_theResult____h406628[37] && - !_theResult____h406628[36] && - !_theResult____h406628[35] && - !_theResult____h406628[34] && - !_theResult____h406628[33] && - !_theResult____h406628[32] && - !_theResult____h406628[31] && - !_theResult____h406628[30] && - !_theResult____h406628[29] && - !_theResult____h406628[28] && - !_theResult____h406628[27] && - !_theResult____h406628[26] && - !_theResult____h406628[25] && - !_theResult____h406628[24] && - !_theResult____h406628[23] && - !_theResult____h406628[22] && - !_theResult____h406628[21] && - !_theResult____h406628[20] && - !_theResult____h406628[19] && - !_theResult____h406628[18] && - !_theResult____h406628[17] && - !_theResult____h406628[16] && - !_theResult____h406628[15] && - !_theResult____h406628[14] && - !_theResult____h406628[13] && - !_theResult____h406628[12] && - !_theResult____h406628[11] && - !_theResult____h406628[10] && - !_theResult____h406628[9] && - !_theResult____h406628[8] && - !_theResult____h406628[7] && - !_theResult____h406628[6] && - !_theResult____h406628[5] && - !_theResult____h406628[4] && - !_theResult____h406628[3] && - !_theResult____h406628[2] && - !_theResult____h406628[1] && - !_theResult____h406628[0] || + assign _theResult___fst_exp__h414940 = + (!_theResult____h406631[56] && !_theResult____h406631[55] && + !_theResult____h406631[54] && + !_theResult____h406631[53] && + !_theResult____h406631[52] && + !_theResult____h406631[51] && + !_theResult____h406631[50] && + !_theResult____h406631[49] && + !_theResult____h406631[48] && + !_theResult____h406631[47] && + !_theResult____h406631[46] && + !_theResult____h406631[45] && + !_theResult____h406631[44] && + !_theResult____h406631[43] && + !_theResult____h406631[42] && + !_theResult____h406631[41] && + !_theResult____h406631[40] && + !_theResult____h406631[39] && + !_theResult____h406631[38] && + !_theResult____h406631[37] && + !_theResult____h406631[36] && + !_theResult____h406631[35] && + !_theResult____h406631[34] && + !_theResult____h406631[33] && + !_theResult____h406631[32] && + !_theResult____h406631[31] && + !_theResult____h406631[30] && + !_theResult____h406631[29] && + !_theResult____h406631[28] && + !_theResult____h406631[27] && + !_theResult____h406631[26] && + !_theResult____h406631[25] && + !_theResult____h406631[24] && + !_theResult____h406631[23] && + !_theResult____h406631[22] && + !_theResult____h406631[21] && + !_theResult____h406631[20] && + !_theResult____h406631[19] && + !_theResult____h406631[18] && + !_theResult____h406631[17] && + !_theResult____h406631[16] && + !_theResult____h406631[15] && + !_theResult____h406631[14] && + !_theResult____h406631[13] && + !_theResult____h406631[12] && + !_theResult____h406631[11] && + !_theResult____h406631[10] && + !_theResult____h406631[9] && + !_theResult____h406631[8] && + !_theResult____h406631[7] && + !_theResult____h406631[6] && + !_theResult____h406631[5] && + !_theResult____h406631[4] && + !_theResult____h406631[3] && + !_theResult____h406631[2] && + !_theResult____h406631[1] && + !_theResult____h406631[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? 8'd0 : - _theResult___fst_exp__h414931 ; - assign _theResult___fst_exp__h414940 = - (!_theResult____h406628[56] && _theResult____h406628[55]) ? + _theResult___fst_exp__h414934 ; + assign _theResult___fst_exp__h414943 = + (!_theResult____h406631[56] && _theResult____h406631[55]) ? 8'd1 : - _theResult___fst_exp__h414937 ; - assign _theResult___fst_exp__h415463 = - (_theResult___fst_exp__h414866 == 8'd255) ? - _theResult___fst_exp__h414866 : - _theResult___fst_exp__h415460 ; - assign _theResult___fst_exp__h423503 = + _theResult___fst_exp__h414940 ; + assign _theResult___fst_exp__h415466 = + (_theResult___fst_exp__h414869 == 8'd255) ? + _theResult___fst_exp__h414869 : + _theResult___fst_exp__h415463 ; + assign _theResult___fst_exp__h423506 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ; - assign _theResult___fst_exp__h423542 = + assign _theResult___fst_exp__h423545 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h423548 = + assign _theResult___fst_exp__h423551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? 8'd0 : - _theResult___fst_exp__h423542 ; - assign _theResult___fst_exp__h423551 = + _theResult___fst_exp__h423545 ; + assign _theResult___fst_exp__h423554 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h423548 : - _theResult___fst_exp__h423503 ; - assign _theResult___fst_exp__h424099 = - (_theResult___fst_exp__h423551 == 8'd255) ? _theResult___fst_exp__h423551 : - _theResult___fst_exp__h424096 ; - assign _theResult___fst_exp__h424108 = + _theResult___fst_exp__h423506 ; + assign _theResult___fst_exp__h424102 = + (_theResult___fst_exp__h423554 == 8'd255) ? + _theResult___fst_exp__h423554 : + _theResult___fst_exp__h424099 ; + assign _theResult___fst_exp__h424111 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406282 : - _theResult___fst_exp__h388973) : + _theResult___snd_fst_exp__h406285 : + _theResult___fst_exp__h388976) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424102 : - _theResult___fst_exp__h388973) ; - assign _theResult___fst_exp__h424111 = + _theResult___snd_fst_exp__h424105 : + _theResult___fst_exp__h388976) ; + assign _theResult___fst_exp__h424114 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424108 ; - assign _theResult___fst_exp__h442788 = - _theResult____h434679[56] ? + _theResult___fst_exp__h424111 ; + assign _theResult___fst_exp__h442791 = + _theResult____h434682[56] ? 8'd2 : - _theResult___fst_exp__h442862 ; - assign _theResult___fst_exp__h442853 = + _theResult___fst_exp__h442865 ; + assign _theResult___fst_exp__h442856 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h442859 = - (!_theResult____h434679[56] && !_theResult____h434679[55] && - !_theResult____h434679[54] && - !_theResult____h434679[53] && - !_theResult____h434679[52] && - !_theResult____h434679[51] && - !_theResult____h434679[50] && - !_theResult____h434679[49] && - !_theResult____h434679[48] && - !_theResult____h434679[47] && - !_theResult____h434679[46] && - !_theResult____h434679[45] && - !_theResult____h434679[44] && - !_theResult____h434679[43] && - !_theResult____h434679[42] && - !_theResult____h434679[41] && - !_theResult____h434679[40] && - !_theResult____h434679[39] && - !_theResult____h434679[38] && - !_theResult____h434679[37] && - !_theResult____h434679[36] && - !_theResult____h434679[35] && - !_theResult____h434679[34] && - !_theResult____h434679[33] && - !_theResult____h434679[32] && - !_theResult____h434679[31] && - !_theResult____h434679[30] && - !_theResult____h434679[29] && - !_theResult____h434679[28] && - !_theResult____h434679[27] && - !_theResult____h434679[26] && - !_theResult____h434679[25] && - !_theResult____h434679[24] && - !_theResult____h434679[23] && - !_theResult____h434679[22] && - !_theResult____h434679[21] && - !_theResult____h434679[20] && - !_theResult____h434679[19] && - !_theResult____h434679[18] && - !_theResult____h434679[17] && - !_theResult____h434679[16] && - !_theResult____h434679[15] && - !_theResult____h434679[14] && - !_theResult____h434679[13] && - !_theResult____h434679[12] && - !_theResult____h434679[11] && - !_theResult____h434679[10] && - !_theResult____h434679[9] && - !_theResult____h434679[8] && - !_theResult____h434679[7] && - !_theResult____h434679[6] && - !_theResult____h434679[5] && - !_theResult____h434679[4] && - !_theResult____h434679[3] && - !_theResult____h434679[2] && - !_theResult____h434679[1] && - !_theResult____h434679[0] || + assign _theResult___fst_exp__h442862 = + (!_theResult____h434682[56] && !_theResult____h434682[55] && + !_theResult____h434682[54] && + !_theResult____h434682[53] && + !_theResult____h434682[52] && + !_theResult____h434682[51] && + !_theResult____h434682[50] && + !_theResult____h434682[49] && + !_theResult____h434682[48] && + !_theResult____h434682[47] && + !_theResult____h434682[46] && + !_theResult____h434682[45] && + !_theResult____h434682[44] && + !_theResult____h434682[43] && + !_theResult____h434682[42] && + !_theResult____h434682[41] && + !_theResult____h434682[40] && + !_theResult____h434682[39] && + !_theResult____h434682[38] && + !_theResult____h434682[37] && + !_theResult____h434682[36] && + !_theResult____h434682[35] && + !_theResult____h434682[34] && + !_theResult____h434682[33] && + !_theResult____h434682[32] && + !_theResult____h434682[31] && + !_theResult____h434682[30] && + !_theResult____h434682[29] && + !_theResult____h434682[28] && + !_theResult____h434682[27] && + !_theResult____h434682[26] && + !_theResult____h434682[25] && + !_theResult____h434682[24] && + !_theResult____h434682[23] && + !_theResult____h434682[22] && + !_theResult____h434682[21] && + !_theResult____h434682[20] && + !_theResult____h434682[19] && + !_theResult____h434682[18] && + !_theResult____h434682[17] && + !_theResult____h434682[16] && + !_theResult____h434682[15] && + !_theResult____h434682[14] && + !_theResult____h434682[13] && + !_theResult____h434682[12] && + !_theResult____h434682[11] && + !_theResult____h434682[10] && + !_theResult____h434682[9] && + !_theResult____h434682[8] && + !_theResult____h434682[7] && + !_theResult____h434682[6] && + !_theResult____h434682[5] && + !_theResult____h434682[4] && + !_theResult____h434682[3] && + !_theResult____h434682[2] && + !_theResult____h434682[1] && + !_theResult____h434682[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? 8'd0 : - _theResult___fst_exp__h442853 ; - assign _theResult___fst_exp__h442862 = - (!_theResult____h434679[56] && _theResult____h434679[55]) ? + _theResult___fst_exp__h442856 ; + assign _theResult___fst_exp__h442865 = + (!_theResult____h434682[56] && _theResult____h434682[55]) ? 8'd1 : - _theResult___fst_exp__h442859 ; - assign _theResult___fst_exp__h443385 = - (_theResult___fst_exp__h442788 == 8'd255) ? - _theResult___fst_exp__h442788 : - _theResult___fst_exp__h443382 ; - assign _theResult___fst_exp__h451435 = + _theResult___fst_exp__h442862 ; + assign _theResult___fst_exp__h443388 = + (_theResult___fst_exp__h442791 == 8'd255) ? + _theResult___fst_exp__h442791 : + _theResult___fst_exp__h443385 ; + assign _theResult___fst_exp__h451438 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h451441 = + assign _theResult___fst_exp__h451444 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? 8'd0 : - _theResult___fst_exp__h451435 ; - assign _theResult___fst_exp__h451444 = + _theResult___fst_exp__h451438 ; + assign _theResult___fst_exp__h451447 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h451441 : - 8'd129 ; - assign _theResult___fst_exp__h451967 = - (_theResult___fst_exp__h451444 == 8'd255) ? _theResult___fst_exp__h451444 : - _theResult___fst_exp__h451964 ; - assign _theResult___fst_exp__h460554 = - _theResult____h452316[56] ? + 8'd129 ; + assign _theResult___fst_exp__h451970 = + (_theResult___fst_exp__h451447 == 8'd255) ? + _theResult___fst_exp__h451447 : + _theResult___fst_exp__h451967 ; + assign _theResult___fst_exp__h460557 = + _theResult____h452319[56] ? 8'd2 : - _theResult___fst_exp__h460628 ; - assign _theResult___fst_exp__h460619 = + _theResult___fst_exp__h460631 ; + assign _theResult___fst_exp__h460622 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h460625 = - (!_theResult____h452316[56] && !_theResult____h452316[55] && - !_theResult____h452316[54] && - !_theResult____h452316[53] && - !_theResult____h452316[52] && - !_theResult____h452316[51] && - !_theResult____h452316[50] && - !_theResult____h452316[49] && - !_theResult____h452316[48] && - !_theResult____h452316[47] && - !_theResult____h452316[46] && - !_theResult____h452316[45] && - !_theResult____h452316[44] && - !_theResult____h452316[43] && - !_theResult____h452316[42] && - !_theResult____h452316[41] && - !_theResult____h452316[40] && - !_theResult____h452316[39] && - !_theResult____h452316[38] && - !_theResult____h452316[37] && - !_theResult____h452316[36] && - !_theResult____h452316[35] && - !_theResult____h452316[34] && - !_theResult____h452316[33] && - !_theResult____h452316[32] && - !_theResult____h452316[31] && - !_theResult____h452316[30] && - !_theResult____h452316[29] && - !_theResult____h452316[28] && - !_theResult____h452316[27] && - !_theResult____h452316[26] && - !_theResult____h452316[25] && - !_theResult____h452316[24] && - !_theResult____h452316[23] && - !_theResult____h452316[22] && - !_theResult____h452316[21] && - !_theResult____h452316[20] && - !_theResult____h452316[19] && - !_theResult____h452316[18] && - !_theResult____h452316[17] && - !_theResult____h452316[16] && - !_theResult____h452316[15] && - !_theResult____h452316[14] && - !_theResult____h452316[13] && - !_theResult____h452316[12] && - !_theResult____h452316[11] && - !_theResult____h452316[10] && - !_theResult____h452316[9] && - !_theResult____h452316[8] && - !_theResult____h452316[7] && - !_theResult____h452316[6] && - !_theResult____h452316[5] && - !_theResult____h452316[4] && - !_theResult____h452316[3] && - !_theResult____h452316[2] && - !_theResult____h452316[1] && - !_theResult____h452316[0] || + assign _theResult___fst_exp__h460628 = + (!_theResult____h452319[56] && !_theResult____h452319[55] && + !_theResult____h452319[54] && + !_theResult____h452319[53] && + !_theResult____h452319[52] && + !_theResult____h452319[51] && + !_theResult____h452319[50] && + !_theResult____h452319[49] && + !_theResult____h452319[48] && + !_theResult____h452319[47] && + !_theResult____h452319[46] && + !_theResult____h452319[45] && + !_theResult____h452319[44] && + !_theResult____h452319[43] && + !_theResult____h452319[42] && + !_theResult____h452319[41] && + !_theResult____h452319[40] && + !_theResult____h452319[39] && + !_theResult____h452319[38] && + !_theResult____h452319[37] && + !_theResult____h452319[36] && + !_theResult____h452319[35] && + !_theResult____h452319[34] && + !_theResult____h452319[33] && + !_theResult____h452319[32] && + !_theResult____h452319[31] && + !_theResult____h452319[30] && + !_theResult____h452319[29] && + !_theResult____h452319[28] && + !_theResult____h452319[27] && + !_theResult____h452319[26] && + !_theResult____h452319[25] && + !_theResult____h452319[24] && + !_theResult____h452319[23] && + !_theResult____h452319[22] && + !_theResult____h452319[21] && + !_theResult____h452319[20] && + !_theResult____h452319[19] && + !_theResult____h452319[18] && + !_theResult____h452319[17] && + !_theResult____h452319[16] && + !_theResult____h452319[15] && + !_theResult____h452319[14] && + !_theResult____h452319[13] && + !_theResult____h452319[12] && + !_theResult____h452319[11] && + !_theResult____h452319[10] && + !_theResult____h452319[9] && + !_theResult____h452319[8] && + !_theResult____h452319[7] && + !_theResult____h452319[6] && + !_theResult____h452319[5] && + !_theResult____h452319[4] && + !_theResult____h452319[3] && + !_theResult____h452319[2] && + !_theResult____h452319[1] && + !_theResult____h452319[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? 8'd0 : - _theResult___fst_exp__h460619 ; - assign _theResult___fst_exp__h460628 = - (!_theResult____h452316[56] && _theResult____h452316[55]) ? + _theResult___fst_exp__h460622 ; + assign _theResult___fst_exp__h460631 = + (!_theResult____h452319[56] && _theResult____h452319[55]) ? 8'd1 : - _theResult___fst_exp__h460625 ; - assign _theResult___fst_exp__h461151 = - (_theResult___fst_exp__h460554 == 8'd255) ? - _theResult___fst_exp__h460554 : - _theResult___fst_exp__h461148 ; - assign _theResult___fst_exp__h469191 = + _theResult___fst_exp__h460628 ; + assign _theResult___fst_exp__h461154 = + (_theResult___fst_exp__h460557 == 8'd255) ? + _theResult___fst_exp__h460557 : + _theResult___fst_exp__h461151 ; + assign _theResult___fst_exp__h469194 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ; - assign _theResult___fst_exp__h469230 = + assign _theResult___fst_exp__h469233 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469236 = + assign _theResult___fst_exp__h469239 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? 8'd0 : - _theResult___fst_exp__h469230 ; - assign _theResult___fst_exp__h469239 = + _theResult___fst_exp__h469233 ; + assign _theResult___fst_exp__h469242 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469236 : - _theResult___fst_exp__h469191 ; - assign _theResult___fst_exp__h469787 = - (_theResult___fst_exp__h469239 == 8'd255) ? _theResult___fst_exp__h469239 : - _theResult___fst_exp__h469784 ; - assign _theResult___fst_exp__h469796 = + _theResult___fst_exp__h469194 ; + assign _theResult___fst_exp__h469790 = + (_theResult___fst_exp__h469242 == 8'd255) ? + _theResult___fst_exp__h469242 : + _theResult___fst_exp__h469787 ; + assign _theResult___fst_exp__h469799 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h451970 : - _theResult___fst_exp__h434661) : + _theResult___snd_fst_exp__h451973 : + _theResult___fst_exp__h434664) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h469790 : - _theResult___fst_exp__h434661) ; - assign _theResult___fst_exp__h469799 = + _theResult___snd_fst_exp__h469793 : + _theResult___fst_exp__h434664) ; + assign _theResult___fst_exp__h469802 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h469796 ; - assign _theResult___fst_exp__h483599 = + _theResult___fst_exp__h469799 ; + assign _theResult___fst_exp__h483603 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ; - assign _theResult___fst_exp__h498663 = + assign _theResult___fst_exp__h498667 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h498669 = + assign _theResult___fst_exp__h498673 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577) ? 11'd0 : - _theResult___fst_exp__h498663 ; - assign _theResult___fst_exp__h498672 = + _theResult___fst_exp__h498667 ; + assign _theResult___fst_exp__h498676 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h498669 : + _theResult___fst_exp__h498673 : 11'd897 ; - assign _theResult___fst_exp__h499427 = + assign _theResult___fst_exp__h499431 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 : + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 ; - assign _theResult___fst_exp__h499430 = - (_theResult___fst_exp__h498672 == 11'd2047) ? - _theResult___fst_exp__h498672 : - _theResult___fst_exp__h499427 ; - assign _theResult___fst_exp__h508249 = - _theResult____h500013[56] ? + assign _theResult___fst_exp__h499434 = + (_theResult___fst_exp__h498676 == 11'd2047) ? + _theResult___fst_exp__h498676 : + _theResult___fst_exp__h499431 ; + assign _theResult___fst_exp__h508253 = + _theResult____h500017[56] ? 11'd2 : - _theResult___fst_exp__h508323 ; - assign _theResult___fst_exp__h508314 = + _theResult___fst_exp__h508327 ; + assign _theResult___fst_exp__h508318 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ; - assign _theResult___fst_exp__h508320 = - (!_theResult____h500013[56] && !_theResult____h500013[55] && - !_theResult____h500013[54] && - !_theResult____h500013[53] && - !_theResult____h500013[52] && - !_theResult____h500013[51] && - !_theResult____h500013[50] && - !_theResult____h500013[49] && - !_theResult____h500013[48] && - !_theResult____h500013[47] && - !_theResult____h500013[46] && - !_theResult____h500013[45] && - !_theResult____h500013[44] && - !_theResult____h500013[43] && - !_theResult____h500013[42] && - !_theResult____h500013[41] && - !_theResult____h500013[40] && - !_theResult____h500013[39] && - !_theResult____h500013[38] && - !_theResult____h500013[37] && - !_theResult____h500013[36] && - !_theResult____h500013[35] && - !_theResult____h500013[34] && - !_theResult____h500013[33] && - !_theResult____h500013[32] && - !_theResult____h500013[31] && - !_theResult____h500013[30] && - !_theResult____h500013[29] && - !_theResult____h500013[28] && - !_theResult____h500013[27] && - !_theResult____h500013[26] && - !_theResult____h500013[25] && - !_theResult____h500013[24] && - !_theResult____h500013[23] && - !_theResult____h500013[22] && - !_theResult____h500013[21] && - !_theResult____h500013[20] && - !_theResult____h500013[19] && - !_theResult____h500013[18] && - !_theResult____h500013[17] && - !_theResult____h500013[16] && - !_theResult____h500013[15] && - !_theResult____h500013[14] && - !_theResult____h500013[13] && - !_theResult____h500013[12] && - !_theResult____h500013[11] && - !_theResult____h500013[10] && - !_theResult____h500013[9] && - !_theResult____h500013[8] && - !_theResult____h500013[7] && - !_theResult____h500013[6] && - !_theResult____h500013[5] && - !_theResult____h500013[4] && - !_theResult____h500013[3] && - !_theResult____h500013[2] && - !_theResult____h500013[1] && - !_theResult____h500013[0] || + assign _theResult___fst_exp__h508324 = + (!_theResult____h500017[56] && !_theResult____h500017[55] && + !_theResult____h500017[54] && + !_theResult____h500017[53] && + !_theResult____h500017[52] && + !_theResult____h500017[51] && + !_theResult____h500017[50] && + !_theResult____h500017[49] && + !_theResult____h500017[48] && + !_theResult____h500017[47] && + !_theResult____h500017[46] && + !_theResult____h500017[45] && + !_theResult____h500017[44] && + !_theResult____h500017[43] && + !_theResult____h500017[42] && + !_theResult____h500017[41] && + !_theResult____h500017[40] && + !_theResult____h500017[39] && + !_theResult____h500017[38] && + !_theResult____h500017[37] && + !_theResult____h500017[36] && + !_theResult____h500017[35] && + !_theResult____h500017[34] && + !_theResult____h500017[33] && + !_theResult____h500017[32] && + !_theResult____h500017[31] && + !_theResult____h500017[30] && + !_theResult____h500017[29] && + !_theResult____h500017[28] && + !_theResult____h500017[27] && + !_theResult____h500017[26] && + !_theResult____h500017[25] && + !_theResult____h500017[24] && + !_theResult____h500017[23] && + !_theResult____h500017[22] && + !_theResult____h500017[21] && + !_theResult____h500017[20] && + !_theResult____h500017[19] && + !_theResult____h500017[18] && + !_theResult____h500017[17] && + !_theResult____h500017[16] && + !_theResult____h500017[15] && + !_theResult____h500017[14] && + !_theResult____h500017[13] && + !_theResult____h500017[12] && + !_theResult____h500017[11] && + !_theResult____h500017[10] && + !_theResult____h500017[9] && + !_theResult____h500017[8] && + !_theResult____h500017[7] && + !_theResult____h500017[6] && + !_theResult____h500017[5] && + !_theResult____h500017[4] && + !_theResult____h500017[3] && + !_theResult____h500017[2] && + !_theResult____h500017[1] && + !_theResult____h500017[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889) ? 11'd0 : - _theResult___fst_exp__h508314 ; - assign _theResult___fst_exp__h508323 = - (!_theResult____h500013[56] && _theResult____h500013[55]) ? + _theResult___fst_exp__h508318 ; + assign _theResult___fst_exp__h508327 = + (!_theResult____h500017[56] && _theResult____h500017[55]) ? 11'd1 : - _theResult___fst_exp__h508320 ; - assign _theResult___fst_exp__h509078 = + _theResult___fst_exp__h508324 ; + assign _theResult___fst_exp__h509082 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 : + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 ; - assign _theResult___fst_exp__h509081 = - (_theResult___fst_exp__h508249 == 11'd2047) ? - _theResult___fst_exp__h508249 : - _theResult___fst_exp__h509078 ; - assign _theResult___fst_exp__h517034 = + assign _theResult___fst_exp__h509085 = + (_theResult___fst_exp__h508253 == 11'd2047) ? + _theResult___fst_exp__h508253 : + _theResult___fst_exp__h509082 ; + assign _theResult___fst_exp__h517038 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ; - assign _theResult___fst_exp__h517073 = + assign _theResult___fst_exp__h517077 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h517079 = + assign _theResult___fst_exp__h517083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939) ? 11'd0 : - _theResult___fst_exp__h517073 ; - assign _theResult___fst_exp__h517082 = + _theResult___fst_exp__h517077 ; + assign _theResult___fst_exp__h517086 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h517079 : - _theResult___fst_exp__h517034 ; - assign _theResult___fst_exp__h517862 = + _theResult___fst_exp__h517083 : + _theResult___fst_exp__h517038 ; + assign _theResult___fst_exp__h517866 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 : + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 ; - assign _theResult___fst_exp__h517865 = - (_theResult___fst_exp__h517082 == 11'd2047) ? - _theResult___fst_exp__h517082 : - _theResult___fst_exp__h517862 ; - assign _theResult___fst_exp__h517874 = + assign _theResult___fst_exp__h517869 = + (_theResult___fst_exp__h517086 == 11'd2047) ? + _theResult___fst_exp__h517086 : + _theResult___fst_exp__h517866 ; + assign _theResult___fst_exp__h517878 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_exp__h499433 : - _theResult___fst_exp__h483599) : + _theResult___snd_fst_exp__h499437 : + _theResult___fst_exp__h483603) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_exp__h517868 : - _theResult___fst_exp__h483599) ; - assign _theResult___fst_exp__h517877 = + _theResult___snd_fst_exp__h517872 : + _theResult___fst_exp__h483603) ; + assign _theResult___fst_exp__h517881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h517874 ; - assign _theResult___fst_exp__h522400 = + _theResult___fst_exp__h517878 ; + assign _theResult___fst_exp__h522404 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_exp__h537464 = + assign _theResult___fst_exp__h537468 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h537470 = + assign _theResult___fst_exp__h537474 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065) ? 11'd0 : - _theResult___fst_exp__h537464 ; - assign _theResult___fst_exp__h537473 = + _theResult___fst_exp__h537468 ; + assign _theResult___fst_exp__h537477 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h537470 : + _theResult___fst_exp__h537474 : 11'd897 ; - assign _theResult___fst_exp__h538228 = + assign _theResult___fst_exp__h538232 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 : + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 ; - assign _theResult___fst_exp__h538231 = - (_theResult___fst_exp__h537473 == 11'd2047) ? - _theResult___fst_exp__h537473 : - _theResult___fst_exp__h538228 ; - assign _theResult___fst_exp__h547050 = - _theResult____h538814[56] ? + assign _theResult___fst_exp__h538235 = + (_theResult___fst_exp__h537477 == 11'd2047) ? + _theResult___fst_exp__h537477 : + _theResult___fst_exp__h538232 ; + assign _theResult___fst_exp__h547054 = + _theResult____h538818[56] ? 11'd2 : - _theResult___fst_exp__h547124 ; - assign _theResult___fst_exp__h547115 = + _theResult___fst_exp__h547128 ; + assign _theResult___fst_exp__h547119 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ; - assign _theResult___fst_exp__h547121 = - (!_theResult____h538814[56] && !_theResult____h538814[55] && - !_theResult____h538814[54] && - !_theResult____h538814[53] && - !_theResult____h538814[52] && - !_theResult____h538814[51] && - !_theResult____h538814[50] && - !_theResult____h538814[49] && - !_theResult____h538814[48] && - !_theResult____h538814[47] && - !_theResult____h538814[46] && - !_theResult____h538814[45] && - !_theResult____h538814[44] && - !_theResult____h538814[43] && - !_theResult____h538814[42] && - !_theResult____h538814[41] && - !_theResult____h538814[40] && - !_theResult____h538814[39] && - !_theResult____h538814[38] && - !_theResult____h538814[37] && - !_theResult____h538814[36] && - !_theResult____h538814[35] && - !_theResult____h538814[34] && - !_theResult____h538814[33] && - !_theResult____h538814[32] && - !_theResult____h538814[31] && - !_theResult____h538814[30] && - !_theResult____h538814[29] && - !_theResult____h538814[28] && - !_theResult____h538814[27] && - !_theResult____h538814[26] && - !_theResult____h538814[25] && - !_theResult____h538814[24] && - !_theResult____h538814[23] && - !_theResult____h538814[22] && - !_theResult____h538814[21] && - !_theResult____h538814[20] && - !_theResult____h538814[19] && - !_theResult____h538814[18] && - !_theResult____h538814[17] && - !_theResult____h538814[16] && - !_theResult____h538814[15] && - !_theResult____h538814[14] && - !_theResult____h538814[13] && - !_theResult____h538814[12] && - !_theResult____h538814[11] && - !_theResult____h538814[10] && - !_theResult____h538814[9] && - !_theResult____h538814[8] && - !_theResult____h538814[7] && - !_theResult____h538814[6] && - !_theResult____h538814[5] && - !_theResult____h538814[4] && - !_theResult____h538814[3] && - !_theResult____h538814[2] && - !_theResult____h538814[1] && - !_theResult____h538814[0] || + assign _theResult___fst_exp__h547125 = + (!_theResult____h538818[56] && !_theResult____h538818[55] && + !_theResult____h538818[54] && + !_theResult____h538818[53] && + !_theResult____h538818[52] && + !_theResult____h538818[51] && + !_theResult____h538818[50] && + !_theResult____h538818[49] && + !_theResult____h538818[48] && + !_theResult____h538818[47] && + !_theResult____h538818[46] && + !_theResult____h538818[45] && + !_theResult____h538818[44] && + !_theResult____h538818[43] && + !_theResult____h538818[42] && + !_theResult____h538818[41] && + !_theResult____h538818[40] && + !_theResult____h538818[39] && + !_theResult____h538818[38] && + !_theResult____h538818[37] && + !_theResult____h538818[36] && + !_theResult____h538818[35] && + !_theResult____h538818[34] && + !_theResult____h538818[33] && + !_theResult____h538818[32] && + !_theResult____h538818[31] && + !_theResult____h538818[30] && + !_theResult____h538818[29] && + !_theResult____h538818[28] && + !_theResult____h538818[27] && + !_theResult____h538818[26] && + !_theResult____h538818[25] && + !_theResult____h538818[24] && + !_theResult____h538818[23] && + !_theResult____h538818[22] && + !_theResult____h538818[21] && + !_theResult____h538818[20] && + !_theResult____h538818[19] && + !_theResult____h538818[18] && + !_theResult____h538818[17] && + !_theResult____h538818[16] && + !_theResult____h538818[15] && + !_theResult____h538818[14] && + !_theResult____h538818[13] && + !_theResult____h538818[12] && + !_theResult____h538818[11] && + !_theResult____h538818[10] && + !_theResult____h538818[9] && + !_theResult____h538818[8] && + !_theResult____h538818[7] && + !_theResult____h538818[6] && + !_theResult____h538818[5] && + !_theResult____h538818[4] && + !_theResult____h538818[3] && + !_theResult____h538818[2] && + !_theResult____h538818[1] && + !_theResult____h538818[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362) ? 11'd0 : - _theResult___fst_exp__h547115 ; - assign _theResult___fst_exp__h547124 = - (!_theResult____h538814[56] && _theResult____h538814[55]) ? + _theResult___fst_exp__h547119 ; + assign _theResult___fst_exp__h547128 = + (!_theResult____h538818[56] && _theResult____h538818[55]) ? 11'd1 : - _theResult___fst_exp__h547121 ; - assign _theResult___fst_exp__h547879 = + _theResult___fst_exp__h547125 ; + assign _theResult___fst_exp__h547883 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 : + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 ; - assign _theResult___fst_exp__h547882 = - (_theResult___fst_exp__h547050 == 11'd2047) ? - _theResult___fst_exp__h547050 : - _theResult___fst_exp__h547879 ; - assign _theResult___fst_exp__h555835 = + assign _theResult___fst_exp__h547886 = + (_theResult___fst_exp__h547054 == 11'd2047) ? + _theResult___fst_exp__h547054 : + _theResult___fst_exp__h547883 ; + assign _theResult___fst_exp__h555839 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ; - assign _theResult___fst_exp__h555874 = + assign _theResult___fst_exp__h555878 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h555880 = + assign _theResult___fst_exp__h555884 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412) ? 11'd0 : - _theResult___fst_exp__h555874 ; - assign _theResult___fst_exp__h555883 = + _theResult___fst_exp__h555878 ; + assign _theResult___fst_exp__h555887 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h555880 : - _theResult___fst_exp__h555835 ; - assign _theResult___fst_exp__h556663 = + _theResult___fst_exp__h555884 : + _theResult___fst_exp__h555839 ; + assign _theResult___fst_exp__h556667 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 : + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 ; - assign _theResult___fst_exp__h556666 = - (_theResult___fst_exp__h555883 == 11'd2047) ? - _theResult___fst_exp__h555883 : - _theResult___fst_exp__h556663 ; - assign _theResult___fst_exp__h556675 = + assign _theResult___fst_exp__h556670 = + (_theResult___fst_exp__h555887 == 11'd2047) ? + _theResult___fst_exp__h555887 : + _theResult___fst_exp__h556667 ; + assign _theResult___fst_exp__h556679 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_exp__h538234 : - _theResult___fst_exp__h522400) : + _theResult___snd_fst_exp__h538238 : + _theResult___fst_exp__h522404) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_exp__h556669 : - _theResult___fst_exp__h522400) ; - assign _theResult___fst_exp__h556678 = + _theResult___snd_fst_exp__h556673 : + _theResult___fst_exp__h522404) ; + assign _theResult___fst_exp__h556682 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h556675 ; - assign _theResult___fst_exp__h561601 = + _theResult___fst_exp__h556679 ; + assign _theResult___fst_exp__h561605 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_exp__h576665 = + assign _theResult___fst_exp__h576669 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h576671 = + assign _theResult___fst_exp__h576675 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302) ? 11'd0 : - _theResult___fst_exp__h576665 ; - assign _theResult___fst_exp__h576674 = + _theResult___fst_exp__h576669 ; + assign _theResult___fst_exp__h576678 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h576671 : + _theResult___fst_exp__h576675 : 11'd897 ; - assign _theResult___fst_exp__h577429 = + assign _theResult___fst_exp__h577433 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 : + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 ; - assign _theResult___fst_exp__h577432 = - (_theResult___fst_exp__h576674 == 11'd2047) ? - _theResult___fst_exp__h576674 : - _theResult___fst_exp__h577429 ; - assign _theResult___fst_exp__h586251 = - _theResult____h578015[56] ? + assign _theResult___fst_exp__h577436 = + (_theResult___fst_exp__h576678 == 11'd2047) ? + _theResult___fst_exp__h576678 : + _theResult___fst_exp__h577433 ; + assign _theResult___fst_exp__h586255 = + _theResult____h578019[56] ? 11'd2 : - _theResult___fst_exp__h586325 ; - assign _theResult___fst_exp__h586316 = + _theResult___fst_exp__h586329 ; + assign _theResult___fst_exp__h586320 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 } ; - assign _theResult___fst_exp__h586322 = - (!_theResult____h578015[56] && !_theResult____h578015[55] && - !_theResult____h578015[54] && - !_theResult____h578015[53] && - !_theResult____h578015[52] && - !_theResult____h578015[51] && - !_theResult____h578015[50] && - !_theResult____h578015[49] && - !_theResult____h578015[48] && - !_theResult____h578015[47] && - !_theResult____h578015[46] && - !_theResult____h578015[45] && - !_theResult____h578015[44] && - !_theResult____h578015[43] && - !_theResult____h578015[42] && - !_theResult____h578015[41] && - !_theResult____h578015[40] && - !_theResult____h578015[39] && - !_theResult____h578015[38] && - !_theResult____h578015[37] && - !_theResult____h578015[36] && - !_theResult____h578015[35] && - !_theResult____h578015[34] && - !_theResult____h578015[33] && - !_theResult____h578015[32] && - !_theResult____h578015[31] && - !_theResult____h578015[30] && - !_theResult____h578015[29] && - !_theResult____h578015[28] && - !_theResult____h578015[27] && - !_theResult____h578015[26] && - !_theResult____h578015[25] && - !_theResult____h578015[24] && - !_theResult____h578015[23] && - !_theResult____h578015[22] && - !_theResult____h578015[21] && - !_theResult____h578015[20] && - !_theResult____h578015[19] && - !_theResult____h578015[18] && - !_theResult____h578015[17] && - !_theResult____h578015[16] && - !_theResult____h578015[15] && - !_theResult____h578015[14] && - !_theResult____h578015[13] && - !_theResult____h578015[12] && - !_theResult____h578015[11] && - !_theResult____h578015[10] && - !_theResult____h578015[9] && - !_theResult____h578015[8] && - !_theResult____h578015[7] && - !_theResult____h578015[6] && - !_theResult____h578015[5] && - !_theResult____h578015[4] && - !_theResult____h578015[3] && - !_theResult____h578015[2] && - !_theResult____h578015[1] && - !_theResult____h578015[0] || + assign _theResult___fst_exp__h586326 = + (!_theResult____h578019[56] && !_theResult____h578019[55] && + !_theResult____h578019[54] && + !_theResult____h578019[53] && + !_theResult____h578019[52] && + !_theResult____h578019[51] && + !_theResult____h578019[50] && + !_theResult____h578019[49] && + !_theResult____h578019[48] && + !_theResult____h578019[47] && + !_theResult____h578019[46] && + !_theResult____h578019[45] && + !_theResult____h578019[44] && + !_theResult____h578019[43] && + !_theResult____h578019[42] && + !_theResult____h578019[41] && + !_theResult____h578019[40] && + !_theResult____h578019[39] && + !_theResult____h578019[38] && + !_theResult____h578019[37] && + !_theResult____h578019[36] && + !_theResult____h578019[35] && + !_theResult____h578019[34] && + !_theResult____h578019[33] && + !_theResult____h578019[32] && + !_theResult____h578019[31] && + !_theResult____h578019[30] && + !_theResult____h578019[29] && + !_theResult____h578019[28] && + !_theResult____h578019[27] && + !_theResult____h578019[26] && + !_theResult____h578019[25] && + !_theResult____h578019[24] && + !_theResult____h578019[23] && + !_theResult____h578019[22] && + !_theResult____h578019[21] && + !_theResult____h578019[20] && + !_theResult____h578019[19] && + !_theResult____h578019[18] && + !_theResult____h578019[17] && + !_theResult____h578019[16] && + !_theResult____h578019[15] && + !_theResult____h578019[14] && + !_theResult____h578019[13] && + !_theResult____h578019[12] && + !_theResult____h578019[11] && + !_theResult____h578019[10] && + !_theResult____h578019[9] && + !_theResult____h578019[8] && + !_theResult____h578019[7] && + !_theResult____h578019[6] && + !_theResult____h578019[5] && + !_theResult____h578019[4] && + !_theResult____h578019[3] && + !_theResult____h578019[2] && + !_theResult____h578019[1] && + !_theResult____h578019[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599) ? 11'd0 : - _theResult___fst_exp__h586316 ; - assign _theResult___fst_exp__h586325 = - (!_theResult____h578015[56] && _theResult____h578015[55]) ? + _theResult___fst_exp__h586320 ; + assign _theResult___fst_exp__h586329 = + (!_theResult____h578019[56] && _theResult____h578019[55]) ? 11'd1 : - _theResult___fst_exp__h586322 ; - assign _theResult___fst_exp__h587080 = + _theResult___fst_exp__h586326 ; + assign _theResult___fst_exp__h587084 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 : + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 ; - assign _theResult___fst_exp__h587083 = - (_theResult___fst_exp__h586251 == 11'd2047) ? - _theResult___fst_exp__h586251 : - _theResult___fst_exp__h587080 ; - assign _theResult___fst_exp__h595036 = + assign _theResult___fst_exp__h587087 = + (_theResult___fst_exp__h586255 == 11'd2047) ? + _theResult___fst_exp__h586255 : + _theResult___fst_exp__h587084 ; + assign _theResult___fst_exp__h595040 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ; - assign _theResult___fst_exp__h595075 = + assign _theResult___fst_exp__h595079 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h595081 = + assign _theResult___fst_exp__h595085 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649) ? 11'd0 : - _theResult___fst_exp__h595075 ; - assign _theResult___fst_exp__h595084 = + _theResult___fst_exp__h595079 ; + assign _theResult___fst_exp__h595088 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h595081 : - _theResult___fst_exp__h595036 ; - assign _theResult___fst_exp__h595864 = + _theResult___fst_exp__h595085 : + _theResult___fst_exp__h595040 ; + assign _theResult___fst_exp__h595868 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 : + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 ; - assign _theResult___fst_exp__h595867 = - (_theResult___fst_exp__h595084 == 11'd2047) ? - _theResult___fst_exp__h595084 : - _theResult___fst_exp__h595864 ; - assign _theResult___fst_exp__h595876 = + assign _theResult___fst_exp__h595871 = + (_theResult___fst_exp__h595088 == 11'd2047) ? + _theResult___fst_exp__h595088 : + _theResult___fst_exp__h595868 ; + assign _theResult___fst_exp__h595880 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_exp__h577435 : - _theResult___fst_exp__h561601) : + _theResult___snd_fst_exp__h577439 : + _theResult___fst_exp__h561605) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_exp__h595870 : - _theResult___fst_exp__h561601) ; - assign _theResult___fst_exp__h595879 = + _theResult___snd_fst_exp__h595874 : + _theResult___fst_exp__h561605) ; + assign _theResult___fst_exp__h595883 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h595876 ; - assign _theResult___fst_sfd__h352008 = - (_theResult___fst_exp__h351410 == 8'd255) ? - sfdin__h351404[56:34] : - _theResult___fst_sfd__h352005 ; - assign _theResult___fst_sfd__h360590 = - (_theResult___fst_exp__h360066 == 8'd255) ? - _theResult___snd__h360017[56:34] : - _theResult___fst_sfd__h360587 ; - assign _theResult___fst_sfd__h369774 = - (_theResult___fst_exp__h369176 == 8'd255) ? - sfdin__h369170[56:34] : - _theResult___fst_sfd__h369771 ; - assign _theResult___fst_sfd__h378410 = - (_theResult___fst_exp__h377861 == 8'd255) ? - _theResult___snd__h377807[56:34] : - _theResult___fst_sfd__h378407 ; - assign _theResult___fst_sfd__h378419 = + _theResult___fst_exp__h595880 ; + assign _theResult___fst_sfd__h352011 = + (_theResult___fst_exp__h351413 == 8'd255) ? + sfdin__h351407[56:34] : + _theResult___fst_sfd__h352008 ; + assign _theResult___fst_sfd__h360593 = + (_theResult___fst_exp__h360069 == 8'd255) ? + _theResult___snd__h360020[56:34] : + _theResult___fst_sfd__h360590 ; + assign _theResult___fst_sfd__h369777 = + (_theResult___fst_exp__h369179 == 8'd255) ? + sfdin__h369173[56:34] : + _theResult___fst_sfd__h369774 ; + assign _theResult___fst_sfd__h378413 = + (_theResult___fst_exp__h377864 == 8'd255) ? + _theResult___snd__h377810[56:34] : + _theResult___fst_sfd__h378410 ; + assign _theResult___fst_sfd__h378422 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h360593 : - _theResult___fst_sfd__h343282) : + _theResult___snd_fst_sfd__h360596 : + _theResult___fst_sfd__h343285) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h378413 : - _theResult___fst_sfd__h343282) ; - assign _theResult___fst_sfd__h378425 = + _theResult___snd_fst_sfd__h378416 : + _theResult___fst_sfd__h343285) ; + assign _theResult___fst_sfd__h378428 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -25718,33 +25718,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h378419 ; - assign _theResult___fst_sfd__h397698 = - (_theResult___fst_exp__h397100 == 8'd255) ? - sfdin__h397094[56:34] : - _theResult___fst_sfd__h397695 ; - assign _theResult___fst_sfd__h406280 = - (_theResult___fst_exp__h405756 == 8'd255) ? - _theResult___snd__h405707[56:34] : - _theResult___fst_sfd__h406277 ; - assign _theResult___fst_sfd__h415464 = - (_theResult___fst_exp__h414866 == 8'd255) ? - sfdin__h414860[56:34] : - _theResult___fst_sfd__h415461 ; - assign _theResult___fst_sfd__h424100 = - (_theResult___fst_exp__h423551 == 8'd255) ? - _theResult___snd__h423497[56:34] : - _theResult___fst_sfd__h424097 ; - assign _theResult___fst_sfd__h424109 = + _theResult___fst_sfd__h378422 ; + assign _theResult___fst_sfd__h397701 = + (_theResult___fst_exp__h397103 == 8'd255) ? + sfdin__h397097[56:34] : + _theResult___fst_sfd__h397698 ; + assign _theResult___fst_sfd__h406283 = + (_theResult___fst_exp__h405759 == 8'd255) ? + _theResult___snd__h405710[56:34] : + _theResult___fst_sfd__h406280 ; + assign _theResult___fst_sfd__h415467 = + (_theResult___fst_exp__h414869 == 8'd255) ? + sfdin__h414863[56:34] : + _theResult___fst_sfd__h415464 ; + assign _theResult___fst_sfd__h424103 = + (_theResult___fst_exp__h423554 == 8'd255) ? + _theResult___snd__h423500[56:34] : + _theResult___fst_sfd__h424100 ; + assign _theResult___fst_sfd__h424112 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406283 : - _theResult___fst_sfd__h388974) : + _theResult___snd_fst_sfd__h406286 : + _theResult___fst_sfd__h388977) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424103 : - _theResult___fst_sfd__h388974) ; - assign _theResult___fst_sfd__h424115 = + _theResult___snd_fst_sfd__h424106 : + _theResult___fst_sfd__h388977) ; + assign _theResult___fst_sfd__h424118 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -25752,33 +25752,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424109 ; - assign _theResult___fst_sfd__h443386 = - (_theResult___fst_exp__h442788 == 8'd255) ? - sfdin__h442782[56:34] : - _theResult___fst_sfd__h443383 ; - assign _theResult___fst_sfd__h451968 = - (_theResult___fst_exp__h451444 == 8'd255) ? - _theResult___snd__h451395[56:34] : - _theResult___fst_sfd__h451965 ; - assign _theResult___fst_sfd__h461152 = - (_theResult___fst_exp__h460554 == 8'd255) ? - sfdin__h460548[56:34] : - _theResult___fst_sfd__h461149 ; - assign _theResult___fst_sfd__h469788 = - (_theResult___fst_exp__h469239 == 8'd255) ? - _theResult___snd__h469185[56:34] : - _theResult___fst_sfd__h469785 ; - assign _theResult___fst_sfd__h469797 = + _theResult___fst_sfd__h424112 ; + assign _theResult___fst_sfd__h443389 = + (_theResult___fst_exp__h442791 == 8'd255) ? + sfdin__h442785[56:34] : + _theResult___fst_sfd__h443386 ; + assign _theResult___fst_sfd__h451971 = + (_theResult___fst_exp__h451447 == 8'd255) ? + _theResult___snd__h451398[56:34] : + _theResult___fst_sfd__h451968 ; + assign _theResult___fst_sfd__h461155 = + (_theResult___fst_exp__h460557 == 8'd255) ? + sfdin__h460551[56:34] : + _theResult___fst_sfd__h461152 ; + assign _theResult___fst_sfd__h469791 = + (_theResult___fst_exp__h469242 == 8'd255) ? + _theResult___snd__h469188[56:34] : + _theResult___fst_sfd__h469788 ; + assign _theResult___fst_sfd__h469800 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h451971 : - _theResult___fst_sfd__h434662) : + _theResult___snd_fst_sfd__h451974 : + _theResult___fst_sfd__h434665) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h469791 : - _theResult___fst_sfd__h434662) ; - assign _theResult___fst_sfd__h469803 = + _theResult___snd_fst_sfd__h469794 : + _theResult___fst_sfd__h434665) ; + assign _theResult___fst_sfd__h469806 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -25786,1320 +25786,1320 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h469797 ; - assign _theResult___fst_sfd__h483600 = + _theResult___fst_sfd__h469800 ; + assign _theResult___fst_sfd__h483604 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_sfd__h499428 = + assign _theResult___fst_sfd__h499432 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 : + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 ; - assign _theResult___fst_sfd__h499431 = - (_theResult___fst_exp__h498672 == 11'd2047) ? - _theResult___snd__h498623[56:5] : - _theResult___fst_sfd__h499428 ; - assign _theResult___fst_sfd__h509079 = + assign _theResult___fst_sfd__h499435 = + (_theResult___fst_exp__h498676 == 11'd2047) ? + _theResult___snd__h498627[56:5] : + _theResult___fst_sfd__h499432 ; + assign _theResult___fst_sfd__h509083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 : + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 ; - assign _theResult___fst_sfd__h509082 = - (_theResult___fst_exp__h508249 == 11'd2047) ? - sfdin__h508243[56:5] : - _theResult___fst_sfd__h509079 ; - assign _theResult___fst_sfd__h517863 = + assign _theResult___fst_sfd__h509086 = + (_theResult___fst_exp__h508253 == 11'd2047) ? + sfdin__h508247[56:5] : + _theResult___fst_sfd__h509083 ; + assign _theResult___fst_sfd__h517867 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 : + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 ; - assign _theResult___fst_sfd__h517866 = - (_theResult___fst_exp__h517082 == 11'd2047) ? - _theResult___snd__h517028[56:5] : - _theResult___fst_sfd__h517863 ; - assign _theResult___fst_sfd__h517875 = + assign _theResult___fst_sfd__h517870 = + (_theResult___fst_exp__h517086 == 11'd2047) ? + _theResult___snd__h517032[56:5] : + _theResult___fst_sfd__h517867 ; + assign _theResult___fst_sfd__h517879 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_sfd__h499434 : - _theResult___fst_sfd__h483600) : + _theResult___snd_fst_sfd__h499438 : + _theResult___fst_sfd__h483604) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_sfd__h517869 : - _theResult___fst_sfd__h483600) ; - assign _theResult___fst_sfd__h517881 = + _theResult___snd_fst_sfd__h517873 : + _theResult___fst_sfd__h483604) ; + assign _theResult___fst_sfd__h517885 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h517875 ; - assign _theResult___fst_sfd__h522401 = + _theResult___fst_sfd__h517879 ; + assign _theResult___fst_sfd__h522405 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_sfd__h538229 = + assign _theResult___fst_sfd__h538233 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 : + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 ; - assign _theResult___fst_sfd__h538232 = - (_theResult___fst_exp__h537473 == 11'd2047) ? - _theResult___snd__h537424[56:5] : - _theResult___fst_sfd__h538229 ; - assign _theResult___fst_sfd__h547880 = + assign _theResult___fst_sfd__h538236 = + (_theResult___fst_exp__h537477 == 11'd2047) ? + _theResult___snd__h537428[56:5] : + _theResult___fst_sfd__h538233 ; + assign _theResult___fst_sfd__h547884 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 ; - assign _theResult___fst_sfd__h547883 = - (_theResult___fst_exp__h547050 == 11'd2047) ? - sfdin__h547044[56:5] : - _theResult___fst_sfd__h547880 ; - assign _theResult___fst_sfd__h556664 = + assign _theResult___fst_sfd__h547887 = + (_theResult___fst_exp__h547054 == 11'd2047) ? + sfdin__h547048[56:5] : + _theResult___fst_sfd__h547884 ; + assign _theResult___fst_sfd__h556668 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 : + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 ; - assign _theResult___fst_sfd__h556667 = - (_theResult___fst_exp__h555883 == 11'd2047) ? - _theResult___snd__h555829[56:5] : - _theResult___fst_sfd__h556664 ; - assign _theResult___fst_sfd__h556676 = + assign _theResult___fst_sfd__h556671 = + (_theResult___fst_exp__h555887 == 11'd2047) ? + _theResult___snd__h555833[56:5] : + _theResult___fst_sfd__h556668 ; + assign _theResult___fst_sfd__h556680 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_sfd__h538235 : - _theResult___fst_sfd__h522401) : + _theResult___snd_fst_sfd__h538239 : + _theResult___fst_sfd__h522405) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_sfd__h556670 : - _theResult___fst_sfd__h522401) ; - assign _theResult___fst_sfd__h556682 = + _theResult___snd_fst_sfd__h556674 : + _theResult___fst_sfd__h522405) ; + assign _theResult___fst_sfd__h556686 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h556676 ; - assign _theResult___fst_sfd__h561602 = + _theResult___fst_sfd__h556680 ; + assign _theResult___fst_sfd__h561606 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_sfd__h577430 = + assign _theResult___fst_sfd__h577434 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 : + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 ; - assign _theResult___fst_sfd__h577433 = - (_theResult___fst_exp__h576674 == 11'd2047) ? - _theResult___snd__h576625[56:5] : - _theResult___fst_sfd__h577430 ; - assign _theResult___fst_sfd__h587081 = + assign _theResult___fst_sfd__h577437 = + (_theResult___fst_exp__h576678 == 11'd2047) ? + _theResult___snd__h576629[56:5] : + _theResult___fst_sfd__h577434 ; + assign _theResult___fst_sfd__h587085 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 ; - assign _theResult___fst_sfd__h587084 = - (_theResult___fst_exp__h586251 == 11'd2047) ? - sfdin__h586245[56:5] : - _theResult___fst_sfd__h587081 ; - assign _theResult___fst_sfd__h595865 = + assign _theResult___fst_sfd__h587088 = + (_theResult___fst_exp__h586255 == 11'd2047) ? + sfdin__h586249[56:5] : + _theResult___fst_sfd__h587085 ; + assign _theResult___fst_sfd__h595869 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 : + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 ; - assign _theResult___fst_sfd__h595868 = - (_theResult___fst_exp__h595084 == 11'd2047) ? - _theResult___snd__h595030[56:5] : - _theResult___fst_sfd__h595865 ; - assign _theResult___fst_sfd__h595877 = + assign _theResult___fst_sfd__h595872 = + (_theResult___fst_exp__h595088 == 11'd2047) ? + _theResult___snd__h595034[56:5] : + _theResult___fst_sfd__h595869 ; + assign _theResult___fst_sfd__h595881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_sfd__h577436 : - _theResult___fst_sfd__h561602) : + _theResult___snd_fst_sfd__h577440 : + _theResult___fst_sfd__h561606) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_sfd__h595871 : - _theResult___fst_sfd__h561602) ; - assign _theResult___fst_sfd__h595883 = + _theResult___snd_fst_sfd__h595875 : + _theResult___fst_sfd__h561606) ; + assign _theResult___fst_sfd__h595887 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h595877 ; - assign _theResult___sfd__h351927 = - sfd__h351502[24] ? - ((_theResult___fst_exp__h351410 == 8'd254) ? + _theResult___fst_sfd__h595881 ; + assign _theResult___sfd__h351930 = + sfd__h351505[24] ? + ((_theResult___fst_exp__h351413 == 8'd254) ? 23'd0 : - sfd__h351502[23:1]) : - sfd__h351502[22:0] ; - assign _theResult___sfd__h360509 = - sfd__h360084[24] ? - ((_theResult___fst_exp__h360066 == 8'd254) ? + sfd__h351505[23:1]) : + sfd__h351505[22:0] ; + assign _theResult___sfd__h360512 = + sfd__h360087[24] ? + ((_theResult___fst_exp__h360069 == 8'd254) ? 23'd0 : - sfd__h360084[23:1]) : - sfd__h360084[22:0] ; - assign _theResult___sfd__h369693 = - sfd__h369268[24] ? - ((_theResult___fst_exp__h369176 == 8'd254) ? + sfd__h360087[23:1]) : + sfd__h360087[22:0] ; + assign _theResult___sfd__h369696 = + sfd__h369271[24] ? + ((_theResult___fst_exp__h369179 == 8'd254) ? 23'd0 : - sfd__h369268[23:1]) : - sfd__h369268[22:0] ; - assign _theResult___sfd__h378329 = - sfd__h377880[24] ? - ((_theResult___fst_exp__h377861 == 8'd254) ? + sfd__h369271[23:1]) : + sfd__h369271[22:0] ; + assign _theResult___sfd__h378332 = + sfd__h377883[24] ? + ((_theResult___fst_exp__h377864 == 8'd254) ? 23'd0 : - sfd__h377880[23:1]) : - sfd__h377880[22:0] ; - assign _theResult___sfd__h378431 = + sfd__h377883[23:1]) : + sfd__h377883[22:0] ; + assign _theResult___sfd__h378434 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h335644 : - _theResult___fst_sfd__h378425 ; - assign _theResult___sfd__h397617 = - sfd__h397192[24] ? - ((_theResult___fst_exp__h397100 == 8'd254) ? + _theResult___snd_fst_sfd__h335647 : + _theResult___fst_sfd__h378428 ; + assign _theResult___sfd__h397620 = + sfd__h397195[24] ? + ((_theResult___fst_exp__h397103 == 8'd254) ? 23'd0 : - sfd__h397192[23:1]) : - sfd__h397192[22:0] ; - assign _theResult___sfd__h406199 = - sfd__h405774[24] ? - ((_theResult___fst_exp__h405756 == 8'd254) ? + sfd__h397195[23:1]) : + sfd__h397195[22:0] ; + assign _theResult___sfd__h406202 = + sfd__h405777[24] ? + ((_theResult___fst_exp__h405759 == 8'd254) ? 23'd0 : - sfd__h405774[23:1]) : - sfd__h405774[22:0] ; - assign _theResult___sfd__h415383 = - sfd__h414958[24] ? - ((_theResult___fst_exp__h414866 == 8'd254) ? + sfd__h405777[23:1]) : + sfd__h405777[22:0] ; + assign _theResult___sfd__h415386 = + sfd__h414961[24] ? + ((_theResult___fst_exp__h414869 == 8'd254) ? 23'd0 : - sfd__h414958[23:1]) : - sfd__h414958[22:0] ; - assign _theResult___sfd__h424019 = - sfd__h423570[24] ? - ((_theResult___fst_exp__h423551 == 8'd254) ? + sfd__h414961[23:1]) : + sfd__h414961[22:0] ; + assign _theResult___sfd__h424022 = + sfd__h423573[24] ? + ((_theResult___fst_exp__h423554 == 8'd254) ? 23'd0 : - sfd__h423570[23:1]) : - sfd__h423570[22:0] ; - assign _theResult___sfd__h424121 = + sfd__h423573[23:1]) : + sfd__h423573[22:0] ; + assign _theResult___sfd__h424124 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h381339 : - _theResult___fst_sfd__h424115 ; - assign _theResult___sfd__h443305 = - sfd__h442880[24] ? - ((_theResult___fst_exp__h442788 == 8'd254) ? + _theResult___snd_fst_sfd__h381342 : + _theResult___fst_sfd__h424118 ; + assign _theResult___sfd__h443308 = + sfd__h442883[24] ? + ((_theResult___fst_exp__h442791 == 8'd254) ? 23'd0 : - sfd__h442880[23:1]) : - sfd__h442880[22:0] ; - assign _theResult___sfd__h451887 = - sfd__h451462[24] ? - ((_theResult___fst_exp__h451444 == 8'd254) ? + sfd__h442883[23:1]) : + sfd__h442883[22:0] ; + assign _theResult___sfd__h451890 = + sfd__h451465[24] ? + ((_theResult___fst_exp__h451447 == 8'd254) ? 23'd0 : - sfd__h451462[23:1]) : - sfd__h451462[22:0] ; - assign _theResult___sfd__h461071 = - sfd__h460646[24] ? - ((_theResult___fst_exp__h460554 == 8'd254) ? + sfd__h451465[23:1]) : + sfd__h451465[22:0] ; + assign _theResult___sfd__h461074 = + sfd__h460649[24] ? + ((_theResult___fst_exp__h460557 == 8'd254) ? 23'd0 : - sfd__h460646[23:1]) : - sfd__h460646[22:0] ; - assign _theResult___sfd__h469707 = - sfd__h469258[24] ? - ((_theResult___fst_exp__h469239 == 8'd254) ? + sfd__h460649[23:1]) : + sfd__h460649[22:0] ; + assign _theResult___sfd__h469710 = + sfd__h469261[24] ? + ((_theResult___fst_exp__h469242 == 8'd254) ? 23'd0 : - sfd__h469258[23:1]) : - sfd__h469258[22:0] ; - assign _theResult___sfd__h469809 = + sfd__h469261[23:1]) : + sfd__h469261[22:0] ; + assign _theResult___sfd__h469812 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427027 : - _theResult___fst_sfd__h469803 ; - assign _theResult___sfd__h499328 = - sfd__h498690[53] ? - ((_theResult___fst_exp__h498672 == 11'd2046) ? + _theResult___snd_fst_sfd__h427030 : + _theResult___fst_sfd__h469806 ; + assign _theResult___sfd__h499332 = + sfd__h498694[53] ? + ((_theResult___fst_exp__h498676 == 11'd2046) ? 52'd0 : - sfd__h498690[52:1]) : - sfd__h498690[51:0] ; - assign _theResult___sfd__h508979 = - sfd__h508341[53] ? - ((_theResult___fst_exp__h508249 == 11'd2046) ? + sfd__h498694[52:1]) : + sfd__h498694[51:0] ; + assign _theResult___sfd__h508983 = + sfd__h508345[53] ? + ((_theResult___fst_exp__h508253 == 11'd2046) ? 52'd0 : - sfd__h508341[52:1]) : - sfd__h508341[51:0] ; - assign _theResult___sfd__h517763 = - sfd__h517101[53] ? - ((_theResult___fst_exp__h517082 == 11'd2046) ? + sfd__h508345[52:1]) : + sfd__h508345[51:0] ; + assign _theResult___sfd__h517767 = + sfd__h517105[53] ? + ((_theResult___fst_exp__h517086 == 11'd2046) ? 52'd0 : - sfd__h517101[52:1]) : - sfd__h517101[51:0] ; - assign _theResult___sfd__h538129 = - sfd__h537491[53] ? - ((_theResult___fst_exp__h537473 == 11'd2046) ? + sfd__h517105[52:1]) : + sfd__h517105[51:0] ; + assign _theResult___sfd__h538133 = + sfd__h537495[53] ? + ((_theResult___fst_exp__h537477 == 11'd2046) ? 52'd0 : - sfd__h537491[52:1]) : - sfd__h537491[51:0] ; - assign _theResult___sfd__h547780 = - sfd__h547142[53] ? - ((_theResult___fst_exp__h547050 == 11'd2046) ? + sfd__h537495[52:1]) : + sfd__h537495[51:0] ; + assign _theResult___sfd__h547784 = + sfd__h547146[53] ? + ((_theResult___fst_exp__h547054 == 11'd2046) ? 52'd0 : - sfd__h547142[52:1]) : - sfd__h547142[51:0] ; - assign _theResult___sfd__h556564 = - sfd__h555902[53] ? - ((_theResult___fst_exp__h555883 == 11'd2046) ? + sfd__h547146[52:1]) : + sfd__h547146[51:0] ; + assign _theResult___sfd__h556568 = + sfd__h555906[53] ? + ((_theResult___fst_exp__h555887 == 11'd2046) ? 52'd0 : - sfd__h555902[52:1]) : - sfd__h555902[51:0] ; - assign _theResult___sfd__h577330 = - sfd__h576692[53] ? - ((_theResult___fst_exp__h576674 == 11'd2046) ? + sfd__h555906[52:1]) : + sfd__h555906[51:0] ; + assign _theResult___sfd__h577334 = + sfd__h576696[53] ? + ((_theResult___fst_exp__h576678 == 11'd2046) ? 52'd0 : - sfd__h576692[52:1]) : - sfd__h576692[51:0] ; - assign _theResult___sfd__h586981 = - sfd__h586343[53] ? - ((_theResult___fst_exp__h586251 == 11'd2046) ? + sfd__h576696[52:1]) : + sfd__h576696[51:0] ; + assign _theResult___sfd__h586985 = + sfd__h586347[53] ? + ((_theResult___fst_exp__h586255 == 11'd2046) ? 52'd0 : - sfd__h586343[52:1]) : - sfd__h586343[51:0] ; - assign _theResult___sfd__h595765 = - sfd__h595103[53] ? - ((_theResult___fst_exp__h595084 == 11'd2046) ? + sfd__h586347[52:1]) : + sfd__h586347[51:0] ; + assign _theResult___sfd__h595769 = + sfd__h595107[53] ? + ((_theResult___fst_exp__h595088 == 11'd2046) ? 52'd0 : - sfd__h595103[52:1]) : - sfd__h595103[51:0] ; - assign _theResult___snd__h351421 = { _theResult____h343299[55:0], 1'd0 } ; - assign _theResult___snd__h351432 = - (!_theResult____h343299[56] && _theResult____h343299[55]) ? - _theResult___snd__h351434 : - _theResult___snd__h351444 ; - assign _theResult___snd__h351434 = { _theResult____h343299[54:0], 2'd0 } ; - assign _theResult___snd__h351444 = - (!_theResult____h343299[56] && !_theResult____h343299[55] && - !_theResult____h343299[54] && - !_theResult____h343299[53] && - !_theResult____h343299[52] && - !_theResult____h343299[51] && - !_theResult____h343299[50] && - !_theResult____h343299[49] && - !_theResult____h343299[48] && - !_theResult____h343299[47] && - !_theResult____h343299[46] && - !_theResult____h343299[45] && - !_theResult____h343299[44] && - !_theResult____h343299[43] && - !_theResult____h343299[42] && - !_theResult____h343299[41] && - !_theResult____h343299[40] && - !_theResult____h343299[39] && - !_theResult____h343299[38] && - !_theResult____h343299[37] && - !_theResult____h343299[36] && - !_theResult____h343299[35] && - !_theResult____h343299[34] && - !_theResult____h343299[33] && - !_theResult____h343299[32] && - !_theResult____h343299[31] && - !_theResult____h343299[30] && - !_theResult____h343299[29] && - !_theResult____h343299[28] && - !_theResult____h343299[27] && - !_theResult____h343299[26] && - !_theResult____h343299[25] && - !_theResult____h343299[24] && - !_theResult____h343299[23] && - !_theResult____h343299[22] && - !_theResult____h343299[21] && - !_theResult____h343299[20] && - !_theResult____h343299[19] && - !_theResult____h343299[18] && - !_theResult____h343299[17] && - !_theResult____h343299[16] && - !_theResult____h343299[15] && - !_theResult____h343299[14] && - !_theResult____h343299[13] && - !_theResult____h343299[12] && - !_theResult____h343299[11] && - !_theResult____h343299[10] && - !_theResult____h343299[9] && - !_theResult____h343299[8] && - !_theResult____h343299[7] && - !_theResult____h343299[6] && - !_theResult____h343299[5] && - !_theResult____h343299[4] && - !_theResult____h343299[3] && - !_theResult____h343299[2] && - !_theResult____h343299[1] && - !_theResult____h343299[0]) ? - _theResult____h343299 : - _theResult___snd__h351450 ; - assign _theResult___snd__h351450 = + sfd__h595107[52:1]) : + sfd__h595107[51:0] ; + assign _theResult___snd__h351424 = { _theResult____h343302[55:0], 1'd0 } ; + assign _theResult___snd__h351435 = + (!_theResult____h343302[56] && _theResult____h343302[55]) ? + _theResult___snd__h351437 : + _theResult___snd__h351447 ; + assign _theResult___snd__h351437 = { _theResult____h343302[54:0], 2'd0 } ; + assign _theResult___snd__h351447 = + (!_theResult____h343302[56] && !_theResult____h343302[55] && + !_theResult____h343302[54] && + !_theResult____h343302[53] && + !_theResult____h343302[52] && + !_theResult____h343302[51] && + !_theResult____h343302[50] && + !_theResult____h343302[49] && + !_theResult____h343302[48] && + !_theResult____h343302[47] && + !_theResult____h343302[46] && + !_theResult____h343302[45] && + !_theResult____h343302[44] && + !_theResult____h343302[43] && + !_theResult____h343302[42] && + !_theResult____h343302[41] && + !_theResult____h343302[40] && + !_theResult____h343302[39] && + !_theResult____h343302[38] && + !_theResult____h343302[37] && + !_theResult____h343302[36] && + !_theResult____h343302[35] && + !_theResult____h343302[34] && + !_theResult____h343302[33] && + !_theResult____h343302[32] && + !_theResult____h343302[31] && + !_theResult____h343302[30] && + !_theResult____h343302[29] && + !_theResult____h343302[28] && + !_theResult____h343302[27] && + !_theResult____h343302[26] && + !_theResult____h343302[25] && + !_theResult____h343302[24] && + !_theResult____h343302[23] && + !_theResult____h343302[22] && + !_theResult____h343302[21] && + !_theResult____h343302[20] && + !_theResult____h343302[19] && + !_theResult____h343302[18] && + !_theResult____h343302[17] && + !_theResult____h343302[16] && + !_theResult____h343302[15] && + !_theResult____h343302[14] && + !_theResult____h343302[13] && + !_theResult____h343302[12] && + !_theResult____h343302[11] && + !_theResult____h343302[10] && + !_theResult____h343302[9] && + !_theResult____h343302[8] && + !_theResult____h343302[7] && + !_theResult____h343302[6] && + !_theResult____h343302[5] && + !_theResult____h343302[4] && + !_theResult____h343302[3] && + !_theResult____h343302[2] && + !_theResult____h343302[1] && + !_theResult____h343302[0]) ? + _theResult____h343302 : + _theResult___snd__h351453 ; + assign _theResult___snd__h351453 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0], 2'd0 } ; - assign _theResult___snd__h351473 = - _theResult____h343299 << + assign _theResult___snd__h351476 = + _theResult____h343302 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360017 = + assign _theResult___snd__h360020 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360026 : - _theResult___snd__h360019 ; - assign _theResult___snd__h360019 = + _theResult___snd__h360029 : + _theResult___snd__h360022 ; + assign _theResult___snd__h360022 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360026 = + assign _theResult___snd__h360029 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335694 : - _theResult___snd__h360032 ; - assign _theResult___snd__h360032 = + sfd__h335697 : + _theResult___snd__h360035 ; + assign _theResult___snd__h360035 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0], 2'd0 } ; - assign _theResult___snd__h360055 = - sfd__h335694 << + assign _theResult___snd__h360058 = + sfd__h335697 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369187 = { _theResult____h360938[55:0], 1'd0 } ; - assign _theResult___snd__h369198 = - (!_theResult____h360938[56] && _theResult____h360938[55]) ? - _theResult___snd__h369200 : - _theResult___snd__h369210 ; - assign _theResult___snd__h369200 = { _theResult____h360938[54:0], 2'd0 } ; - assign _theResult___snd__h369210 = - (!_theResult____h360938[56] && !_theResult____h360938[55] && - !_theResult____h360938[54] && - !_theResult____h360938[53] && - !_theResult____h360938[52] && - !_theResult____h360938[51] && - !_theResult____h360938[50] && - !_theResult____h360938[49] && - !_theResult____h360938[48] && - !_theResult____h360938[47] && - !_theResult____h360938[46] && - !_theResult____h360938[45] && - !_theResult____h360938[44] && - !_theResult____h360938[43] && - !_theResult____h360938[42] && - !_theResult____h360938[41] && - !_theResult____h360938[40] && - !_theResult____h360938[39] && - !_theResult____h360938[38] && - !_theResult____h360938[37] && - !_theResult____h360938[36] && - !_theResult____h360938[35] && - !_theResult____h360938[34] && - !_theResult____h360938[33] && - !_theResult____h360938[32] && - !_theResult____h360938[31] && - !_theResult____h360938[30] && - !_theResult____h360938[29] && - !_theResult____h360938[28] && - !_theResult____h360938[27] && - !_theResult____h360938[26] && - !_theResult____h360938[25] && - !_theResult____h360938[24] && - !_theResult____h360938[23] && - !_theResult____h360938[22] && - !_theResult____h360938[21] && - !_theResult____h360938[20] && - !_theResult____h360938[19] && - !_theResult____h360938[18] && - !_theResult____h360938[17] && - !_theResult____h360938[16] && - !_theResult____h360938[15] && - !_theResult____h360938[14] && - !_theResult____h360938[13] && - !_theResult____h360938[12] && - !_theResult____h360938[11] && - !_theResult____h360938[10] && - !_theResult____h360938[9] && - !_theResult____h360938[8] && - !_theResult____h360938[7] && - !_theResult____h360938[6] && - !_theResult____h360938[5] && - !_theResult____h360938[4] && - !_theResult____h360938[3] && - !_theResult____h360938[2] && - !_theResult____h360938[1] && - !_theResult____h360938[0]) ? - _theResult____h360938 : - _theResult___snd__h369216 ; - assign _theResult___snd__h369216 = + assign _theResult___snd__h369190 = { _theResult____h360941[55:0], 1'd0 } ; + assign _theResult___snd__h369201 = + (!_theResult____h360941[56] && _theResult____h360941[55]) ? + _theResult___snd__h369203 : + _theResult___snd__h369213 ; + assign _theResult___snd__h369203 = { _theResult____h360941[54:0], 2'd0 } ; + assign _theResult___snd__h369213 = + (!_theResult____h360941[56] && !_theResult____h360941[55] && + !_theResult____h360941[54] && + !_theResult____h360941[53] && + !_theResult____h360941[52] && + !_theResult____h360941[51] && + !_theResult____h360941[50] && + !_theResult____h360941[49] && + !_theResult____h360941[48] && + !_theResult____h360941[47] && + !_theResult____h360941[46] && + !_theResult____h360941[45] && + !_theResult____h360941[44] && + !_theResult____h360941[43] && + !_theResult____h360941[42] && + !_theResult____h360941[41] && + !_theResult____h360941[40] && + !_theResult____h360941[39] && + !_theResult____h360941[38] && + !_theResult____h360941[37] && + !_theResult____h360941[36] && + !_theResult____h360941[35] && + !_theResult____h360941[34] && + !_theResult____h360941[33] && + !_theResult____h360941[32] && + !_theResult____h360941[31] && + !_theResult____h360941[30] && + !_theResult____h360941[29] && + !_theResult____h360941[28] && + !_theResult____h360941[27] && + !_theResult____h360941[26] && + !_theResult____h360941[25] && + !_theResult____h360941[24] && + !_theResult____h360941[23] && + !_theResult____h360941[22] && + !_theResult____h360941[21] && + !_theResult____h360941[20] && + !_theResult____h360941[19] && + !_theResult____h360941[18] && + !_theResult____h360941[17] && + !_theResult____h360941[16] && + !_theResult____h360941[15] && + !_theResult____h360941[14] && + !_theResult____h360941[13] && + !_theResult____h360941[12] && + !_theResult____h360941[11] && + !_theResult____h360941[10] && + !_theResult____h360941[9] && + !_theResult____h360941[8] && + !_theResult____h360941[7] && + !_theResult____h360941[6] && + !_theResult____h360941[5] && + !_theResult____h360941[4] && + !_theResult____h360941[3] && + !_theResult____h360941[2] && + !_theResult____h360941[1] && + !_theResult____h360941[0]) ? + _theResult____h360941 : + _theResult___snd__h369219 ; + assign _theResult___snd__h369219 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h369239 = - _theResult____h360938 << + assign _theResult___snd__h369242 = + _theResult____h360941 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h377807 = + assign _theResult___snd__h377810 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h377821 : - _theResult___snd__h360019 ; - assign _theResult___snd__h377821 = + _theResult___snd__h377824 : + _theResult___snd__h360022 ; + assign _theResult___snd__h377824 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335694 : - _theResult___snd__h377827 ; - assign _theResult___snd__h377827 = + sfd__h335697 : + _theResult___snd__h377830 ; + assign _theResult___snd__h377830 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0], 2'd0 } ; - assign _theResult___snd__h377845 = - sfd__h335694 << + assign _theResult___snd__h377848 = + sfd__h335697 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397111 = { _theResult____h388991[55:0], 1'd0 } ; - assign _theResult___snd__h397122 = - (!_theResult____h388991[56] && _theResult____h388991[55]) ? - _theResult___snd__h397124 : - _theResult___snd__h397134 ; - assign _theResult___snd__h397124 = { _theResult____h388991[54:0], 2'd0 } ; - assign _theResult___snd__h397134 = - (!_theResult____h388991[56] && !_theResult____h388991[55] && - !_theResult____h388991[54] && - !_theResult____h388991[53] && - !_theResult____h388991[52] && - !_theResult____h388991[51] && - !_theResult____h388991[50] && - !_theResult____h388991[49] && - !_theResult____h388991[48] && - !_theResult____h388991[47] && - !_theResult____h388991[46] && - !_theResult____h388991[45] && - !_theResult____h388991[44] && - !_theResult____h388991[43] && - !_theResult____h388991[42] && - !_theResult____h388991[41] && - !_theResult____h388991[40] && - !_theResult____h388991[39] && - !_theResult____h388991[38] && - !_theResult____h388991[37] && - !_theResult____h388991[36] && - !_theResult____h388991[35] && - !_theResult____h388991[34] && - !_theResult____h388991[33] && - !_theResult____h388991[32] && - !_theResult____h388991[31] && - !_theResult____h388991[30] && - !_theResult____h388991[29] && - !_theResult____h388991[28] && - !_theResult____h388991[27] && - !_theResult____h388991[26] && - !_theResult____h388991[25] && - !_theResult____h388991[24] && - !_theResult____h388991[23] && - !_theResult____h388991[22] && - !_theResult____h388991[21] && - !_theResult____h388991[20] && - !_theResult____h388991[19] && - !_theResult____h388991[18] && - !_theResult____h388991[17] && - !_theResult____h388991[16] && - !_theResult____h388991[15] && - !_theResult____h388991[14] && - !_theResult____h388991[13] && - !_theResult____h388991[12] && - !_theResult____h388991[11] && - !_theResult____h388991[10] && - !_theResult____h388991[9] && - !_theResult____h388991[8] && - !_theResult____h388991[7] && - !_theResult____h388991[6] && - !_theResult____h388991[5] && - !_theResult____h388991[4] && - !_theResult____h388991[3] && - !_theResult____h388991[2] && - !_theResult____h388991[1] && - !_theResult____h388991[0]) ? - _theResult____h388991 : - _theResult___snd__h397140 ; - assign _theResult___snd__h397140 = + assign _theResult___snd__h397114 = { _theResult____h388994[55:0], 1'd0 } ; + assign _theResult___snd__h397125 = + (!_theResult____h388994[56] && _theResult____h388994[55]) ? + _theResult___snd__h397127 : + _theResult___snd__h397137 ; + assign _theResult___snd__h397127 = { _theResult____h388994[54:0], 2'd0 } ; + assign _theResult___snd__h397137 = + (!_theResult____h388994[56] && !_theResult____h388994[55] && + !_theResult____h388994[54] && + !_theResult____h388994[53] && + !_theResult____h388994[52] && + !_theResult____h388994[51] && + !_theResult____h388994[50] && + !_theResult____h388994[49] && + !_theResult____h388994[48] && + !_theResult____h388994[47] && + !_theResult____h388994[46] && + !_theResult____h388994[45] && + !_theResult____h388994[44] && + !_theResult____h388994[43] && + !_theResult____h388994[42] && + !_theResult____h388994[41] && + !_theResult____h388994[40] && + !_theResult____h388994[39] && + !_theResult____h388994[38] && + !_theResult____h388994[37] && + !_theResult____h388994[36] && + !_theResult____h388994[35] && + !_theResult____h388994[34] && + !_theResult____h388994[33] && + !_theResult____h388994[32] && + !_theResult____h388994[31] && + !_theResult____h388994[30] && + !_theResult____h388994[29] && + !_theResult____h388994[28] && + !_theResult____h388994[27] && + !_theResult____h388994[26] && + !_theResult____h388994[25] && + !_theResult____h388994[24] && + !_theResult____h388994[23] && + !_theResult____h388994[22] && + !_theResult____h388994[21] && + !_theResult____h388994[20] && + !_theResult____h388994[19] && + !_theResult____h388994[18] && + !_theResult____h388994[17] && + !_theResult____h388994[16] && + !_theResult____h388994[15] && + !_theResult____h388994[14] && + !_theResult____h388994[13] && + !_theResult____h388994[12] && + !_theResult____h388994[11] && + !_theResult____h388994[10] && + !_theResult____h388994[9] && + !_theResult____h388994[8] && + !_theResult____h388994[7] && + !_theResult____h388994[6] && + !_theResult____h388994[5] && + !_theResult____h388994[4] && + !_theResult____h388994[3] && + !_theResult____h388994[2] && + !_theResult____h388994[1] && + !_theResult____h388994[0]) ? + _theResult____h388994 : + _theResult___snd__h397143 ; + assign _theResult___snd__h397143 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h397163 = - _theResult____h388991 << + assign _theResult___snd__h397166 = + _theResult____h388994 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h405707 = + assign _theResult___snd__h405710 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h405716 : - _theResult___snd__h405709 ; - assign _theResult___snd__h405709 = + _theResult___snd__h405719 : + _theResult___snd__h405712 ; + assign _theResult___snd__h405712 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h405716 = + assign _theResult___snd__h405719 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381389 : - _theResult___snd__h405722 ; - assign _theResult___snd__h405722 = + sfd__h381392 : + _theResult___snd__h405725 ; + assign _theResult___snd__h405725 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0], 2'd0 } ; - assign _theResult___snd__h405745 = - sfd__h381389 << + assign _theResult___snd__h405748 = + sfd__h381392 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h414877 = { _theResult____h406628[55:0], 1'd0 } ; - assign _theResult___snd__h414888 = - (!_theResult____h406628[56] && _theResult____h406628[55]) ? - _theResult___snd__h414890 : - _theResult___snd__h414900 ; - assign _theResult___snd__h414890 = { _theResult____h406628[54:0], 2'd0 } ; - assign _theResult___snd__h414900 = - (!_theResult____h406628[56] && !_theResult____h406628[55] && - !_theResult____h406628[54] && - !_theResult____h406628[53] && - !_theResult____h406628[52] && - !_theResult____h406628[51] && - !_theResult____h406628[50] && - !_theResult____h406628[49] && - !_theResult____h406628[48] && - !_theResult____h406628[47] && - !_theResult____h406628[46] && - !_theResult____h406628[45] && - !_theResult____h406628[44] && - !_theResult____h406628[43] && - !_theResult____h406628[42] && - !_theResult____h406628[41] && - !_theResult____h406628[40] && - !_theResult____h406628[39] && - !_theResult____h406628[38] && - !_theResult____h406628[37] && - !_theResult____h406628[36] && - !_theResult____h406628[35] && - !_theResult____h406628[34] && - !_theResult____h406628[33] && - !_theResult____h406628[32] && - !_theResult____h406628[31] && - !_theResult____h406628[30] && - !_theResult____h406628[29] && - !_theResult____h406628[28] && - !_theResult____h406628[27] && - !_theResult____h406628[26] && - !_theResult____h406628[25] && - !_theResult____h406628[24] && - !_theResult____h406628[23] && - !_theResult____h406628[22] && - !_theResult____h406628[21] && - !_theResult____h406628[20] && - !_theResult____h406628[19] && - !_theResult____h406628[18] && - !_theResult____h406628[17] && - !_theResult____h406628[16] && - !_theResult____h406628[15] && - !_theResult____h406628[14] && - !_theResult____h406628[13] && - !_theResult____h406628[12] && - !_theResult____h406628[11] && - !_theResult____h406628[10] && - !_theResult____h406628[9] && - !_theResult____h406628[8] && - !_theResult____h406628[7] && - !_theResult____h406628[6] && - !_theResult____h406628[5] && - !_theResult____h406628[4] && - !_theResult____h406628[3] && - !_theResult____h406628[2] && - !_theResult____h406628[1] && - !_theResult____h406628[0]) ? - _theResult____h406628 : - _theResult___snd__h414906 ; - assign _theResult___snd__h414906 = + assign _theResult___snd__h414880 = { _theResult____h406631[55:0], 1'd0 } ; + assign _theResult___snd__h414891 = + (!_theResult____h406631[56] && _theResult____h406631[55]) ? + _theResult___snd__h414893 : + _theResult___snd__h414903 ; + assign _theResult___snd__h414893 = { _theResult____h406631[54:0], 2'd0 } ; + assign _theResult___snd__h414903 = + (!_theResult____h406631[56] && !_theResult____h406631[55] && + !_theResult____h406631[54] && + !_theResult____h406631[53] && + !_theResult____h406631[52] && + !_theResult____h406631[51] && + !_theResult____h406631[50] && + !_theResult____h406631[49] && + !_theResult____h406631[48] && + !_theResult____h406631[47] && + !_theResult____h406631[46] && + !_theResult____h406631[45] && + !_theResult____h406631[44] && + !_theResult____h406631[43] && + !_theResult____h406631[42] && + !_theResult____h406631[41] && + !_theResult____h406631[40] && + !_theResult____h406631[39] && + !_theResult____h406631[38] && + !_theResult____h406631[37] && + !_theResult____h406631[36] && + !_theResult____h406631[35] && + !_theResult____h406631[34] && + !_theResult____h406631[33] && + !_theResult____h406631[32] && + !_theResult____h406631[31] && + !_theResult____h406631[30] && + !_theResult____h406631[29] && + !_theResult____h406631[28] && + !_theResult____h406631[27] && + !_theResult____h406631[26] && + !_theResult____h406631[25] && + !_theResult____h406631[24] && + !_theResult____h406631[23] && + !_theResult____h406631[22] && + !_theResult____h406631[21] && + !_theResult____h406631[20] && + !_theResult____h406631[19] && + !_theResult____h406631[18] && + !_theResult____h406631[17] && + !_theResult____h406631[16] && + !_theResult____h406631[15] && + !_theResult____h406631[14] && + !_theResult____h406631[13] && + !_theResult____h406631[12] && + !_theResult____h406631[11] && + !_theResult____h406631[10] && + !_theResult____h406631[9] && + !_theResult____h406631[8] && + !_theResult____h406631[7] && + !_theResult____h406631[6] && + !_theResult____h406631[5] && + !_theResult____h406631[4] && + !_theResult____h406631[3] && + !_theResult____h406631[2] && + !_theResult____h406631[1] && + !_theResult____h406631[0]) ? + _theResult____h406631 : + _theResult___snd__h414909 ; + assign _theResult___snd__h414909 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h414929 = - _theResult____h406628 << + assign _theResult___snd__h414932 = + _theResult____h406631 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h423497 = + assign _theResult___snd__h423500 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h423511 : - _theResult___snd__h405709 ; - assign _theResult___snd__h423511 = + _theResult___snd__h423514 : + _theResult___snd__h405712 ; + assign _theResult___snd__h423514 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381389 : - _theResult___snd__h423517 ; - assign _theResult___snd__h423517 = + sfd__h381392 : + _theResult___snd__h423520 ; + assign _theResult___snd__h423520 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0], 2'd0 } ; - assign _theResult___snd__h423535 = - sfd__h381389 << + assign _theResult___snd__h423538 = + sfd__h381392 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h442799 = { _theResult____h434679[55:0], 1'd0 } ; - assign _theResult___snd__h442810 = - (!_theResult____h434679[56] && _theResult____h434679[55]) ? - _theResult___snd__h442812 : - _theResult___snd__h442822 ; - assign _theResult___snd__h442812 = { _theResult____h434679[54:0], 2'd0 } ; - assign _theResult___snd__h442822 = - (!_theResult____h434679[56] && !_theResult____h434679[55] && - !_theResult____h434679[54] && - !_theResult____h434679[53] && - !_theResult____h434679[52] && - !_theResult____h434679[51] && - !_theResult____h434679[50] && - !_theResult____h434679[49] && - !_theResult____h434679[48] && - !_theResult____h434679[47] && - !_theResult____h434679[46] && - !_theResult____h434679[45] && - !_theResult____h434679[44] && - !_theResult____h434679[43] && - !_theResult____h434679[42] && - !_theResult____h434679[41] && - !_theResult____h434679[40] && - !_theResult____h434679[39] && - !_theResult____h434679[38] && - !_theResult____h434679[37] && - !_theResult____h434679[36] && - !_theResult____h434679[35] && - !_theResult____h434679[34] && - !_theResult____h434679[33] && - !_theResult____h434679[32] && - !_theResult____h434679[31] && - !_theResult____h434679[30] && - !_theResult____h434679[29] && - !_theResult____h434679[28] && - !_theResult____h434679[27] && - !_theResult____h434679[26] && - !_theResult____h434679[25] && - !_theResult____h434679[24] && - !_theResult____h434679[23] && - !_theResult____h434679[22] && - !_theResult____h434679[21] && - !_theResult____h434679[20] && - !_theResult____h434679[19] && - !_theResult____h434679[18] && - !_theResult____h434679[17] && - !_theResult____h434679[16] && - !_theResult____h434679[15] && - !_theResult____h434679[14] && - !_theResult____h434679[13] && - !_theResult____h434679[12] && - !_theResult____h434679[11] && - !_theResult____h434679[10] && - !_theResult____h434679[9] && - !_theResult____h434679[8] && - !_theResult____h434679[7] && - !_theResult____h434679[6] && - !_theResult____h434679[5] && - !_theResult____h434679[4] && - !_theResult____h434679[3] && - !_theResult____h434679[2] && - !_theResult____h434679[1] && - !_theResult____h434679[0]) ? - _theResult____h434679 : - _theResult___snd__h442828 ; - assign _theResult___snd__h442828 = + assign _theResult___snd__h442802 = { _theResult____h434682[55:0], 1'd0 } ; + assign _theResult___snd__h442813 = + (!_theResult____h434682[56] && _theResult____h434682[55]) ? + _theResult___snd__h442815 : + _theResult___snd__h442825 ; + assign _theResult___snd__h442815 = { _theResult____h434682[54:0], 2'd0 } ; + assign _theResult___snd__h442825 = + (!_theResult____h434682[56] && !_theResult____h434682[55] && + !_theResult____h434682[54] && + !_theResult____h434682[53] && + !_theResult____h434682[52] && + !_theResult____h434682[51] && + !_theResult____h434682[50] && + !_theResult____h434682[49] && + !_theResult____h434682[48] && + !_theResult____h434682[47] && + !_theResult____h434682[46] && + !_theResult____h434682[45] && + !_theResult____h434682[44] && + !_theResult____h434682[43] && + !_theResult____h434682[42] && + !_theResult____h434682[41] && + !_theResult____h434682[40] && + !_theResult____h434682[39] && + !_theResult____h434682[38] && + !_theResult____h434682[37] && + !_theResult____h434682[36] && + !_theResult____h434682[35] && + !_theResult____h434682[34] && + !_theResult____h434682[33] && + !_theResult____h434682[32] && + !_theResult____h434682[31] && + !_theResult____h434682[30] && + !_theResult____h434682[29] && + !_theResult____h434682[28] && + !_theResult____h434682[27] && + !_theResult____h434682[26] && + !_theResult____h434682[25] && + !_theResult____h434682[24] && + !_theResult____h434682[23] && + !_theResult____h434682[22] && + !_theResult____h434682[21] && + !_theResult____h434682[20] && + !_theResult____h434682[19] && + !_theResult____h434682[18] && + !_theResult____h434682[17] && + !_theResult____h434682[16] && + !_theResult____h434682[15] && + !_theResult____h434682[14] && + !_theResult____h434682[13] && + !_theResult____h434682[12] && + !_theResult____h434682[11] && + !_theResult____h434682[10] && + !_theResult____h434682[9] && + !_theResult____h434682[8] && + !_theResult____h434682[7] && + !_theResult____h434682[6] && + !_theResult____h434682[5] && + !_theResult____h434682[4] && + !_theResult____h434682[3] && + !_theResult____h434682[2] && + !_theResult____h434682[1] && + !_theResult____h434682[0]) ? + _theResult____h434682 : + _theResult___snd__h442831 ; + assign _theResult___snd__h442831 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h442851 = - _theResult____h434679 << + assign _theResult___snd__h442854 = + _theResult____h434682 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h451395 = + assign _theResult___snd__h451398 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h451404 : - _theResult___snd__h451397 ; - assign _theResult___snd__h451397 = + _theResult___snd__h451407 : + _theResult___snd__h451400 ; + assign _theResult___snd__h451400 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h451404 = + assign _theResult___snd__h451407 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427077 : - _theResult___snd__h451410 ; - assign _theResult___snd__h451410 = + sfd__h427080 : + _theResult___snd__h451413 ; + assign _theResult___snd__h451413 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0], 2'd0 } ; - assign _theResult___snd__h451433 = - sfd__h427077 << + assign _theResult___snd__h451436 = + sfd__h427080 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h460565 = { _theResult____h452316[55:0], 1'd0 } ; - assign _theResult___snd__h460576 = - (!_theResult____h452316[56] && _theResult____h452316[55]) ? - _theResult___snd__h460578 : - _theResult___snd__h460588 ; - assign _theResult___snd__h460578 = { _theResult____h452316[54:0], 2'd0 } ; - assign _theResult___snd__h460588 = - (!_theResult____h452316[56] && !_theResult____h452316[55] && - !_theResult____h452316[54] && - !_theResult____h452316[53] && - !_theResult____h452316[52] && - !_theResult____h452316[51] && - !_theResult____h452316[50] && - !_theResult____h452316[49] && - !_theResult____h452316[48] && - !_theResult____h452316[47] && - !_theResult____h452316[46] && - !_theResult____h452316[45] && - !_theResult____h452316[44] && - !_theResult____h452316[43] && - !_theResult____h452316[42] && - !_theResult____h452316[41] && - !_theResult____h452316[40] && - !_theResult____h452316[39] && - !_theResult____h452316[38] && - !_theResult____h452316[37] && - !_theResult____h452316[36] && - !_theResult____h452316[35] && - !_theResult____h452316[34] && - !_theResult____h452316[33] && - !_theResult____h452316[32] && - !_theResult____h452316[31] && - !_theResult____h452316[30] && - !_theResult____h452316[29] && - !_theResult____h452316[28] && - !_theResult____h452316[27] && - !_theResult____h452316[26] && - !_theResult____h452316[25] && - !_theResult____h452316[24] && - !_theResult____h452316[23] && - !_theResult____h452316[22] && - !_theResult____h452316[21] && - !_theResult____h452316[20] && - !_theResult____h452316[19] && - !_theResult____h452316[18] && - !_theResult____h452316[17] && - !_theResult____h452316[16] && - !_theResult____h452316[15] && - !_theResult____h452316[14] && - !_theResult____h452316[13] && - !_theResult____h452316[12] && - !_theResult____h452316[11] && - !_theResult____h452316[10] && - !_theResult____h452316[9] && - !_theResult____h452316[8] && - !_theResult____h452316[7] && - !_theResult____h452316[6] && - !_theResult____h452316[5] && - !_theResult____h452316[4] && - !_theResult____h452316[3] && - !_theResult____h452316[2] && - !_theResult____h452316[1] && - !_theResult____h452316[0]) ? - _theResult____h452316 : - _theResult___snd__h460594 ; - assign _theResult___snd__h460594 = + assign _theResult___snd__h460568 = { _theResult____h452319[55:0], 1'd0 } ; + assign _theResult___snd__h460579 = + (!_theResult____h452319[56] && _theResult____h452319[55]) ? + _theResult___snd__h460581 : + _theResult___snd__h460591 ; + assign _theResult___snd__h460581 = { _theResult____h452319[54:0], 2'd0 } ; + assign _theResult___snd__h460591 = + (!_theResult____h452319[56] && !_theResult____h452319[55] && + !_theResult____h452319[54] && + !_theResult____h452319[53] && + !_theResult____h452319[52] && + !_theResult____h452319[51] && + !_theResult____h452319[50] && + !_theResult____h452319[49] && + !_theResult____h452319[48] && + !_theResult____h452319[47] && + !_theResult____h452319[46] && + !_theResult____h452319[45] && + !_theResult____h452319[44] && + !_theResult____h452319[43] && + !_theResult____h452319[42] && + !_theResult____h452319[41] && + !_theResult____h452319[40] && + !_theResult____h452319[39] && + !_theResult____h452319[38] && + !_theResult____h452319[37] && + !_theResult____h452319[36] && + !_theResult____h452319[35] && + !_theResult____h452319[34] && + !_theResult____h452319[33] && + !_theResult____h452319[32] && + !_theResult____h452319[31] && + !_theResult____h452319[30] && + !_theResult____h452319[29] && + !_theResult____h452319[28] && + !_theResult____h452319[27] && + !_theResult____h452319[26] && + !_theResult____h452319[25] && + !_theResult____h452319[24] && + !_theResult____h452319[23] && + !_theResult____h452319[22] && + !_theResult____h452319[21] && + !_theResult____h452319[20] && + !_theResult____h452319[19] && + !_theResult____h452319[18] && + !_theResult____h452319[17] && + !_theResult____h452319[16] && + !_theResult____h452319[15] && + !_theResult____h452319[14] && + !_theResult____h452319[13] && + !_theResult____h452319[12] && + !_theResult____h452319[11] && + !_theResult____h452319[10] && + !_theResult____h452319[9] && + !_theResult____h452319[8] && + !_theResult____h452319[7] && + !_theResult____h452319[6] && + !_theResult____h452319[5] && + !_theResult____h452319[4] && + !_theResult____h452319[3] && + !_theResult____h452319[2] && + !_theResult____h452319[1] && + !_theResult____h452319[0]) ? + _theResult____h452319 : + _theResult___snd__h460597 ; + assign _theResult___snd__h460597 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h460617 = - _theResult____h452316 << + assign _theResult___snd__h460620 = + _theResult____h452319 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469185 = + assign _theResult___snd__h469188 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469199 : - _theResult___snd__h451397 ; - assign _theResult___snd__h469199 = + _theResult___snd__h469202 : + _theResult___snd__h451400 ; + assign _theResult___snd__h469202 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427077 : - _theResult___snd__h469205 ; - assign _theResult___snd__h469205 = + sfd__h427080 : + _theResult___snd__h469208 ; + assign _theResult___snd__h469208 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0], 2'd0 } ; - assign _theResult___snd__h469223 = - sfd__h427077 << + assign _theResult___snd__h469226 = + sfd__h427080 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h498623 = + assign _theResult___snd__h498627 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h498632 : - _theResult___snd__h498625 ; - assign _theResult___snd__h498625 = + _theResult___snd__h498636 : + _theResult___snd__h498629 ; + assign _theResult___snd__h498629 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ; - assign _theResult___snd__h498632 = + assign _theResult___snd__h498636 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479671 : - _theResult___snd__h498638 ; - assign _theResult___snd__h498638 = + sfd__h479675 : + _theResult___snd__h498642 ; + assign _theResult___snd__h498642 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h498661 = - sfd__h479671 << + assign _theResult___snd__h498665 = + sfd__h479675 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 ; - assign _theResult___snd__h508260 = { _theResult____h500013[55:0], 1'd0 } ; - assign _theResult___snd__h508271 = - (!_theResult____h500013[56] && _theResult____h500013[55]) ? - _theResult___snd__h508273 : - _theResult___snd__h508283 ; - assign _theResult___snd__h508273 = { _theResult____h500013[54:0], 2'd0 } ; - assign _theResult___snd__h508283 = - (!_theResult____h500013[56] && !_theResult____h500013[55] && - !_theResult____h500013[54] && - !_theResult____h500013[53] && - !_theResult____h500013[52] && - !_theResult____h500013[51] && - !_theResult____h500013[50] && - !_theResult____h500013[49] && - !_theResult____h500013[48] && - !_theResult____h500013[47] && - !_theResult____h500013[46] && - !_theResult____h500013[45] && - !_theResult____h500013[44] && - !_theResult____h500013[43] && - !_theResult____h500013[42] && - !_theResult____h500013[41] && - !_theResult____h500013[40] && - !_theResult____h500013[39] && - !_theResult____h500013[38] && - !_theResult____h500013[37] && - !_theResult____h500013[36] && - !_theResult____h500013[35] && - !_theResult____h500013[34] && - !_theResult____h500013[33] && - !_theResult____h500013[32] && - !_theResult____h500013[31] && - !_theResult____h500013[30] && - !_theResult____h500013[29] && - !_theResult____h500013[28] && - !_theResult____h500013[27] && - !_theResult____h500013[26] && - !_theResult____h500013[25] && - !_theResult____h500013[24] && - !_theResult____h500013[23] && - !_theResult____h500013[22] && - !_theResult____h500013[21] && - !_theResult____h500013[20] && - !_theResult____h500013[19] && - !_theResult____h500013[18] && - !_theResult____h500013[17] && - !_theResult____h500013[16] && - !_theResult____h500013[15] && - !_theResult____h500013[14] && - !_theResult____h500013[13] && - !_theResult____h500013[12] && - !_theResult____h500013[11] && - !_theResult____h500013[10] && - !_theResult____h500013[9] && - !_theResult____h500013[8] && - !_theResult____h500013[7] && - !_theResult____h500013[6] && - !_theResult____h500013[5] && - !_theResult____h500013[4] && - !_theResult____h500013[3] && - !_theResult____h500013[2] && - !_theResult____h500013[1] && - !_theResult____h500013[0]) ? - _theResult____h500013 : - _theResult___snd__h508289 ; - assign _theResult___snd__h508289 = + assign _theResult___snd__h508264 = { _theResult____h500017[55:0], 1'd0 } ; + assign _theResult___snd__h508275 = + (!_theResult____h500017[56] && _theResult____h500017[55]) ? + _theResult___snd__h508277 : + _theResult___snd__h508287 ; + assign _theResult___snd__h508277 = { _theResult____h500017[54:0], 2'd0 } ; + assign _theResult___snd__h508287 = + (!_theResult____h500017[56] && !_theResult____h500017[55] && + !_theResult____h500017[54] && + !_theResult____h500017[53] && + !_theResult____h500017[52] && + !_theResult____h500017[51] && + !_theResult____h500017[50] && + !_theResult____h500017[49] && + !_theResult____h500017[48] && + !_theResult____h500017[47] && + !_theResult____h500017[46] && + !_theResult____h500017[45] && + !_theResult____h500017[44] && + !_theResult____h500017[43] && + !_theResult____h500017[42] && + !_theResult____h500017[41] && + !_theResult____h500017[40] && + !_theResult____h500017[39] && + !_theResult____h500017[38] && + !_theResult____h500017[37] && + !_theResult____h500017[36] && + !_theResult____h500017[35] && + !_theResult____h500017[34] && + !_theResult____h500017[33] && + !_theResult____h500017[32] && + !_theResult____h500017[31] && + !_theResult____h500017[30] && + !_theResult____h500017[29] && + !_theResult____h500017[28] && + !_theResult____h500017[27] && + !_theResult____h500017[26] && + !_theResult____h500017[25] && + !_theResult____h500017[24] && + !_theResult____h500017[23] && + !_theResult____h500017[22] && + !_theResult____h500017[21] && + !_theResult____h500017[20] && + !_theResult____h500017[19] && + !_theResult____h500017[18] && + !_theResult____h500017[17] && + !_theResult____h500017[16] && + !_theResult____h500017[15] && + !_theResult____h500017[14] && + !_theResult____h500017[13] && + !_theResult____h500017[12] && + !_theResult____h500017[11] && + !_theResult____h500017[10] && + !_theResult____h500017[9] && + !_theResult____h500017[8] && + !_theResult____h500017[7] && + !_theResult____h500017[6] && + !_theResult____h500017[5] && + !_theResult____h500017[4] && + !_theResult____h500017[3] && + !_theResult____h500017[2] && + !_theResult____h500017[1] && + !_theResult____h500017[0]) ? + _theResult____h500017 : + _theResult___snd__h508293 ; + assign _theResult___snd__h508293 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h508312 = - _theResult____h500013 << + assign _theResult___snd__h508316 = + _theResult____h500017 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 ; - assign _theResult___snd__h517028 = + assign _theResult___snd__h517032 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h517042 : - _theResult___snd__h498625 ; - assign _theResult___snd__h517042 = + _theResult___snd__h517046 : + _theResult___snd__h498629 ; + assign _theResult___snd__h517046 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479671 : - _theResult___snd__h517048 ; - assign _theResult___snd__h517048 = + sfd__h479675 : + _theResult___snd__h517052 ; + assign _theResult___snd__h517052 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h517066 = - sfd__h479671 << + assign _theResult___snd__h517070 = + sfd__h479675 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 ; - assign _theResult___snd__h537424 = + assign _theResult___snd__h537428 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h537433 : - _theResult___snd__h537426 ; - assign _theResult___snd__h537426 = + _theResult___snd__h537437 : + _theResult___snd__h537430 ; + assign _theResult___snd__h537430 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ; - assign _theResult___snd__h537433 = + assign _theResult___snd__h537437 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518613 : - _theResult___snd__h537439 ; - assign _theResult___snd__h537439 = + sfd__h518617 : + _theResult___snd__h537443 ; + assign _theResult___snd__h537443 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h537462 = - sfd__h518613 << + assign _theResult___snd__h537466 = + sfd__h518617 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 ; - assign _theResult___snd__h547061 = { _theResult____h538814[55:0], 1'd0 } ; - assign _theResult___snd__h547072 = - (!_theResult____h538814[56] && _theResult____h538814[55]) ? - _theResult___snd__h547074 : - _theResult___snd__h547084 ; - assign _theResult___snd__h547074 = { _theResult____h538814[54:0], 2'd0 } ; - assign _theResult___snd__h547084 = - (!_theResult____h538814[56] && !_theResult____h538814[55] && - !_theResult____h538814[54] && - !_theResult____h538814[53] && - !_theResult____h538814[52] && - !_theResult____h538814[51] && - !_theResult____h538814[50] && - !_theResult____h538814[49] && - !_theResult____h538814[48] && - !_theResult____h538814[47] && - !_theResult____h538814[46] && - !_theResult____h538814[45] && - !_theResult____h538814[44] && - !_theResult____h538814[43] && - !_theResult____h538814[42] && - !_theResult____h538814[41] && - !_theResult____h538814[40] && - !_theResult____h538814[39] && - !_theResult____h538814[38] && - !_theResult____h538814[37] && - !_theResult____h538814[36] && - !_theResult____h538814[35] && - !_theResult____h538814[34] && - !_theResult____h538814[33] && - !_theResult____h538814[32] && - !_theResult____h538814[31] && - !_theResult____h538814[30] && - !_theResult____h538814[29] && - !_theResult____h538814[28] && - !_theResult____h538814[27] && - !_theResult____h538814[26] && - !_theResult____h538814[25] && - !_theResult____h538814[24] && - !_theResult____h538814[23] && - !_theResult____h538814[22] && - !_theResult____h538814[21] && - !_theResult____h538814[20] && - !_theResult____h538814[19] && - !_theResult____h538814[18] && - !_theResult____h538814[17] && - !_theResult____h538814[16] && - !_theResult____h538814[15] && - !_theResult____h538814[14] && - !_theResult____h538814[13] && - !_theResult____h538814[12] && - !_theResult____h538814[11] && - !_theResult____h538814[10] && - !_theResult____h538814[9] && - !_theResult____h538814[8] && - !_theResult____h538814[7] && - !_theResult____h538814[6] && - !_theResult____h538814[5] && - !_theResult____h538814[4] && - !_theResult____h538814[3] && - !_theResult____h538814[2] && - !_theResult____h538814[1] && - !_theResult____h538814[0]) ? - _theResult____h538814 : - _theResult___snd__h547090 ; - assign _theResult___snd__h547090 = + assign _theResult___snd__h547065 = { _theResult____h538818[55:0], 1'd0 } ; + assign _theResult___snd__h547076 = + (!_theResult____h538818[56] && _theResult____h538818[55]) ? + _theResult___snd__h547078 : + _theResult___snd__h547088 ; + assign _theResult___snd__h547078 = { _theResult____h538818[54:0], 2'd0 } ; + assign _theResult___snd__h547088 = + (!_theResult____h538818[56] && !_theResult____h538818[55] && + !_theResult____h538818[54] && + !_theResult____h538818[53] && + !_theResult____h538818[52] && + !_theResult____h538818[51] && + !_theResult____h538818[50] && + !_theResult____h538818[49] && + !_theResult____h538818[48] && + !_theResult____h538818[47] && + !_theResult____h538818[46] && + !_theResult____h538818[45] && + !_theResult____h538818[44] && + !_theResult____h538818[43] && + !_theResult____h538818[42] && + !_theResult____h538818[41] && + !_theResult____h538818[40] && + !_theResult____h538818[39] && + !_theResult____h538818[38] && + !_theResult____h538818[37] && + !_theResult____h538818[36] && + !_theResult____h538818[35] && + !_theResult____h538818[34] && + !_theResult____h538818[33] && + !_theResult____h538818[32] && + !_theResult____h538818[31] && + !_theResult____h538818[30] && + !_theResult____h538818[29] && + !_theResult____h538818[28] && + !_theResult____h538818[27] && + !_theResult____h538818[26] && + !_theResult____h538818[25] && + !_theResult____h538818[24] && + !_theResult____h538818[23] && + !_theResult____h538818[22] && + !_theResult____h538818[21] && + !_theResult____h538818[20] && + !_theResult____h538818[19] && + !_theResult____h538818[18] && + !_theResult____h538818[17] && + !_theResult____h538818[16] && + !_theResult____h538818[15] && + !_theResult____h538818[14] && + !_theResult____h538818[13] && + !_theResult____h538818[12] && + !_theResult____h538818[11] && + !_theResult____h538818[10] && + !_theResult____h538818[9] && + !_theResult____h538818[8] && + !_theResult____h538818[7] && + !_theResult____h538818[6] && + !_theResult____h538818[5] && + !_theResult____h538818[4] && + !_theResult____h538818[3] && + !_theResult____h538818[2] && + !_theResult____h538818[1] && + !_theResult____h538818[0]) ? + _theResult____h538818 : + _theResult___snd__h547094 ; + assign _theResult___snd__h547094 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h547113 = - _theResult____h538814 << + assign _theResult___snd__h547117 = + _theResult____h538818 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 ; - assign _theResult___snd__h555829 = + assign _theResult___snd__h555833 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h555843 : - _theResult___snd__h537426 ; - assign _theResult___snd__h555843 = + _theResult___snd__h555847 : + _theResult___snd__h537430 ; + assign _theResult___snd__h555847 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518613 : - _theResult___snd__h555849 ; - assign _theResult___snd__h555849 = + sfd__h518617 : + _theResult___snd__h555853 ; + assign _theResult___snd__h555853 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h555867 = - sfd__h518613 << + assign _theResult___snd__h555871 = + sfd__h518617 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 ; - assign _theResult___snd__h576625 = + assign _theResult___snd__h576629 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h576634 : - _theResult___snd__h576627 ; - assign _theResult___snd__h576627 = + _theResult___snd__h576638 : + _theResult___snd__h576631 ; + assign _theResult___snd__h576631 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ; - assign _theResult___snd__h576634 = + assign _theResult___snd__h576638 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557814 : - _theResult___snd__h576640 ; - assign _theResult___snd__h576640 = + sfd__h557818 : + _theResult___snd__h576644 ; + assign _theResult___snd__h576644 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h576663 = - sfd__h557814 << + assign _theResult___snd__h576667 = + sfd__h557818 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 ; - assign _theResult___snd__h586262 = { _theResult____h578015[55:0], 1'd0 } ; - assign _theResult___snd__h586273 = - (!_theResult____h578015[56] && _theResult____h578015[55]) ? - _theResult___snd__h586275 : - _theResult___snd__h586285 ; - assign _theResult___snd__h586275 = { _theResult____h578015[54:0], 2'd0 } ; - assign _theResult___snd__h586285 = - (!_theResult____h578015[56] && !_theResult____h578015[55] && - !_theResult____h578015[54] && - !_theResult____h578015[53] && - !_theResult____h578015[52] && - !_theResult____h578015[51] && - !_theResult____h578015[50] && - !_theResult____h578015[49] && - !_theResult____h578015[48] && - !_theResult____h578015[47] && - !_theResult____h578015[46] && - !_theResult____h578015[45] && - !_theResult____h578015[44] && - !_theResult____h578015[43] && - !_theResult____h578015[42] && - !_theResult____h578015[41] && - !_theResult____h578015[40] && - !_theResult____h578015[39] && - !_theResult____h578015[38] && - !_theResult____h578015[37] && - !_theResult____h578015[36] && - !_theResult____h578015[35] && - !_theResult____h578015[34] && - !_theResult____h578015[33] && - !_theResult____h578015[32] && - !_theResult____h578015[31] && - !_theResult____h578015[30] && - !_theResult____h578015[29] && - !_theResult____h578015[28] && - !_theResult____h578015[27] && - !_theResult____h578015[26] && - !_theResult____h578015[25] && - !_theResult____h578015[24] && - !_theResult____h578015[23] && - !_theResult____h578015[22] && - !_theResult____h578015[21] && - !_theResult____h578015[20] && - !_theResult____h578015[19] && - !_theResult____h578015[18] && - !_theResult____h578015[17] && - !_theResult____h578015[16] && - !_theResult____h578015[15] && - !_theResult____h578015[14] && - !_theResult____h578015[13] && - !_theResult____h578015[12] && - !_theResult____h578015[11] && - !_theResult____h578015[10] && - !_theResult____h578015[9] && - !_theResult____h578015[8] && - !_theResult____h578015[7] && - !_theResult____h578015[6] && - !_theResult____h578015[5] && - !_theResult____h578015[4] && - !_theResult____h578015[3] && - !_theResult____h578015[2] && - !_theResult____h578015[1] && - !_theResult____h578015[0]) ? - _theResult____h578015 : - _theResult___snd__h586291 ; - assign _theResult___snd__h586291 = + assign _theResult___snd__h586266 = { _theResult____h578019[55:0], 1'd0 } ; + assign _theResult___snd__h586277 = + (!_theResult____h578019[56] && _theResult____h578019[55]) ? + _theResult___snd__h586279 : + _theResult___snd__h586289 ; + assign _theResult___snd__h586279 = { _theResult____h578019[54:0], 2'd0 } ; + assign _theResult___snd__h586289 = + (!_theResult____h578019[56] && !_theResult____h578019[55] && + !_theResult____h578019[54] && + !_theResult____h578019[53] && + !_theResult____h578019[52] && + !_theResult____h578019[51] && + !_theResult____h578019[50] && + !_theResult____h578019[49] && + !_theResult____h578019[48] && + !_theResult____h578019[47] && + !_theResult____h578019[46] && + !_theResult____h578019[45] && + !_theResult____h578019[44] && + !_theResult____h578019[43] && + !_theResult____h578019[42] && + !_theResult____h578019[41] && + !_theResult____h578019[40] && + !_theResult____h578019[39] && + !_theResult____h578019[38] && + !_theResult____h578019[37] && + !_theResult____h578019[36] && + !_theResult____h578019[35] && + !_theResult____h578019[34] && + !_theResult____h578019[33] && + !_theResult____h578019[32] && + !_theResult____h578019[31] && + !_theResult____h578019[30] && + !_theResult____h578019[29] && + !_theResult____h578019[28] && + !_theResult____h578019[27] && + !_theResult____h578019[26] && + !_theResult____h578019[25] && + !_theResult____h578019[24] && + !_theResult____h578019[23] && + !_theResult____h578019[22] && + !_theResult____h578019[21] && + !_theResult____h578019[20] && + !_theResult____h578019[19] && + !_theResult____h578019[18] && + !_theResult____h578019[17] && + !_theResult____h578019[16] && + !_theResult____h578019[15] && + !_theResult____h578019[14] && + !_theResult____h578019[13] && + !_theResult____h578019[12] && + !_theResult____h578019[11] && + !_theResult____h578019[10] && + !_theResult____h578019[9] && + !_theResult____h578019[8] && + !_theResult____h578019[7] && + !_theResult____h578019[6] && + !_theResult____h578019[5] && + !_theResult____h578019[4] && + !_theResult____h578019[3] && + !_theResult____h578019[2] && + !_theResult____h578019[1] && + !_theResult____h578019[0]) ? + _theResult____h578019 : + _theResult___snd__h586295 ; + assign _theResult___snd__h586295 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h586314 = - _theResult____h578015 << + assign _theResult___snd__h586318 = + _theResult____h578019 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 ; - assign _theResult___snd__h595030 = + assign _theResult___snd__h595034 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h595044 : - _theResult___snd__h576627 ; - assign _theResult___snd__h595044 = + _theResult___snd__h595048 : + _theResult___snd__h576631 ; + assign _theResult___snd__h595048 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557814 : - _theResult___snd__h595050 ; - assign _theResult___snd__h595050 = + sfd__h557818 : + _theResult___snd__h595054 ; + assign _theResult___snd__h595054 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h595068 = - sfd__h557814 << + assign _theResult___snd__h595072 = + sfd__h557818 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 ; - assign _theResult___snd__h600258 = - b__h599836[63] ? b___1__h600307 : b__h599836 ; - assign _theResult___snd_fst_exp__h360592 = + assign _theResult___snd__h600262 = + b__h599840[63] ? b___1__h600311 : b__h599840 ; + assign _theResult___snd_fst_exp__h360595 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352007 : - _theResult___fst_exp__h360589 ; - assign _theResult___snd_fst_exp__h378412 = + _theResult___fst_exp__h352010 : + _theResult___fst_exp__h360592 ; + assign _theResult___snd_fst_exp__h378415 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h369773 : - _theResult___fst_exp__h378409 ; - assign _theResult___snd_fst_exp__h406282 = + _theResult___fst_exp__h369776 : + _theResult___fst_exp__h378412 ; + assign _theResult___snd_fst_exp__h406285 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h397697 : - _theResult___fst_exp__h406279 ; - assign _theResult___snd_fst_exp__h424102 = + _theResult___fst_exp__h397700 : + _theResult___fst_exp__h406282 ; + assign _theResult___snd_fst_exp__h424105 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h415463 : - _theResult___fst_exp__h424099 ; - assign _theResult___snd_fst_exp__h451970 = + _theResult___fst_exp__h415466 : + _theResult___fst_exp__h424102 ; + assign _theResult___snd_fst_exp__h451973 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h443385 : - _theResult___fst_exp__h451967 ; - assign _theResult___snd_fst_exp__h469790 = + _theResult___fst_exp__h443388 : + _theResult___fst_exp__h451970 ; + assign _theResult___snd_fst_exp__h469793 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461151 : - _theResult___fst_exp__h469787 ; - assign _theResult___snd_fst_exp__h499433 = + _theResult___fst_exp__h461154 : + _theResult___fst_exp__h469790 ; + assign _theResult___snd_fst_exp__h499437 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 11'd0 : - _theResult___fst_exp__h499430 ; - assign _theResult___snd_fst_exp__h517868 = + _theResult___fst_exp__h499434 ; + assign _theResult___snd_fst_exp__h517872 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_exp__h509081 : - _theResult___fst_exp__h517865 ; - assign _theResult___snd_fst_exp__h538234 = + _theResult___fst_exp__h509085 : + _theResult___fst_exp__h517869 ; + assign _theResult___snd_fst_exp__h538238 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 11'd0 : - _theResult___fst_exp__h538231 ; - assign _theResult___snd_fst_exp__h556669 = + _theResult___fst_exp__h538235 ; + assign _theResult___snd_fst_exp__h556673 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_exp__h547882 : - _theResult___fst_exp__h556666 ; - assign _theResult___snd_fst_exp__h577435 = + _theResult___fst_exp__h547886 : + _theResult___fst_exp__h556670 ; + assign _theResult___snd_fst_exp__h577439 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 11'd0 : - _theResult___fst_exp__h577432 ; - assign _theResult___snd_fst_exp__h595870 = + _theResult___fst_exp__h577436 ; + assign _theResult___snd_fst_exp__h595874 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_exp__h587083 : - _theResult___fst_exp__h595867 ; - assign _theResult___snd_fst_sfd__h335644 = + _theResult___fst_exp__h587087 : + _theResult___fst_exp__h595871 ; + assign _theResult___snd_fst_sfd__h335647 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h360593 = + assign _theResult___snd_fst_sfd__h360596 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352008 : - _theResult___fst_sfd__h360590 ; - assign _theResult___snd_fst_sfd__h378413 = + _theResult___fst_sfd__h352011 : + _theResult___fst_sfd__h360593 ; + assign _theResult___snd_fst_sfd__h378416 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h369774 : - _theResult___fst_sfd__h378410 ; - assign _theResult___snd_fst_sfd__h381339 = + _theResult___fst_sfd__h369777 : + _theResult___fst_sfd__h378413 ; + assign _theResult___snd_fst_sfd__h381342 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406283 = + assign _theResult___snd_fst_sfd__h406286 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h397698 : - _theResult___fst_sfd__h406280 ; - assign _theResult___snd_fst_sfd__h424103 = + _theResult___fst_sfd__h397701 : + _theResult___fst_sfd__h406283 ; + assign _theResult___snd_fst_sfd__h424106 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h415464 : - _theResult___fst_sfd__h424100 ; - assign _theResult___snd_fst_sfd__h427027 = + _theResult___fst_sfd__h415467 : + _theResult___fst_sfd__h424103 ; + assign _theResult___snd_fst_sfd__h427030 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h451971 = + assign _theResult___snd_fst_sfd__h451974 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h443386 : - _theResult___fst_sfd__h451968 ; - assign _theResult___snd_fst_sfd__h469791 = + _theResult___fst_sfd__h443389 : + _theResult___fst_sfd__h451971 ; + assign _theResult___snd_fst_sfd__h469794 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461152 : - _theResult___fst_sfd__h469788 ; - assign _theResult___snd_fst_sfd__h479625 = + _theResult___fst_sfd__h461155 : + _theResult___fst_sfd__h469791 ; + assign _theResult___snd_fst_sfd__h479629 = (coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h479374 ; - assign _theResult___snd_fst_sfd__h499434 = + out___1_sfd__h479378 ; + assign _theResult___snd_fst_sfd__h499438 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 52'd0 : - _theResult___fst_sfd__h499431 ; - assign _theResult___snd_fst_sfd__h517869 = + _theResult___fst_sfd__h499435 ; + assign _theResult___snd_fst_sfd__h517873 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_sfd__h509082 : - _theResult___fst_sfd__h517866 ; - assign _theResult___snd_fst_sfd__h518567 = + _theResult___fst_sfd__h509086 : + _theResult___fst_sfd__h517870 ; + assign _theResult___snd_fst_sfd__h518571 = (coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h518316 ; - assign _theResult___snd_fst_sfd__h538235 = + out___1_sfd__h518320 ; + assign _theResult___snd_fst_sfd__h538239 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 52'd0 : - _theResult___fst_sfd__h538232 ; - assign _theResult___snd_fst_sfd__h556670 = + _theResult___fst_sfd__h538236 ; + assign _theResult___snd_fst_sfd__h556674 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_sfd__h547883 : - _theResult___fst_sfd__h556667 ; - assign _theResult___snd_fst_sfd__h557768 = + _theResult___fst_sfd__h547887 : + _theResult___fst_sfd__h556671 ; + assign _theResult___snd_fst_sfd__h557772 = (coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h557517 ; - assign _theResult___snd_fst_sfd__h577436 = + out___1_sfd__h557521 ; + assign _theResult___snd_fst_sfd__h577440 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 52'd0 : - _theResult___fst_sfd__h577433 ; - assign _theResult___snd_fst_sfd__h595871 = + _theResult___fst_sfd__h577437 ; + assign _theResult___snd_fst_sfd__h595875 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_sfd__h587084 : - _theResult___fst_sfd__h595868 ; - assign a___1__h599976 = + _theResult___fst_sfd__h587088 : + _theResult___fst_sfd__h595872 ; + assign a___1__h599980 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ; - assign a___1__h600262 = 64'd0 - a__h599835 ; - assign a__h599835 = + assign a___1__h600266 = 64'd0 - a__h599839 ; + assign a__h599839 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h599976 : + a___1__h599980 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h599977 = + assign b___1__h599981 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h600307 = 64'd0 - b__h599836 ; - assign b__h599836 = + assign b___1__h600311 = 64'd0 - b__h599840 ; + assign b__h599840 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h599977 : + b___1__h599981 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h694782 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h694985 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h692180 = - commitStage_commitTrap[4] ? i__h692355 : i__h692195 ; + assign base__h694791 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h694994 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h692189 = + commitStage_commitTrap[4] ? i__h692364 : i__h692204 ; assign coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27353,7 +27353,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252023 ; + y__h252026 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || @@ -27707,44 +27707,44 @@ module mkCore(CLK, assign csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871 = csrf_prv_reg < IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[9:8] ; - assign data72478_BITS_31_TO_0__q5 = data__h472478[31:0] ; - assign data___1__h472204 = + assign data72481_BITS_31_TO_0__q5 = data__h472481[31:0] ; + assign data___1__h472207 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ; - assign data___1__h473012 = - { {32{data72478_BITS_31_TO_0__q5[31]}}, - data72478_BITS_31_TO_0__q5 } ; - assign data__h472478 = + assign data___1__h473015 = + { {32{data72481_BITS_31_TO_0__q5[31]}}, + data72481_BITS_31_TO_0__q5 } ; + assign data__h472481 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h472392 : - x_remainder__h472393 ; - assign din_inc___2_exp__h378443 = _theResult___fst_exp__h351410 + 8'd1 ; - assign din_inc___2_exp__h378467 = _theResult___fst_exp__h360066 + 8'd1 ; - assign din_inc___2_exp__h378497 = _theResult___fst_exp__h369176 + 8'd1 ; - assign din_inc___2_exp__h378521 = _theResult___fst_exp__h377861 + 8'd1 ; - assign din_inc___2_exp__h424133 = _theResult___fst_exp__h397100 + 8'd1 ; - assign din_inc___2_exp__h424157 = _theResult___fst_exp__h405756 + 8'd1 ; - assign din_inc___2_exp__h424187 = _theResult___fst_exp__h414866 + 8'd1 ; - assign din_inc___2_exp__h424211 = _theResult___fst_exp__h423551 + 8'd1 ; - assign din_inc___2_exp__h469821 = _theResult___fst_exp__h442788 + 8'd1 ; - assign din_inc___2_exp__h469845 = _theResult___fst_exp__h451444 + 8'd1 ; - assign din_inc___2_exp__h469875 = _theResult___fst_exp__h460554 + 8'd1 ; - assign din_inc___2_exp__h469899 = _theResult___fst_exp__h469239 + 8'd1 ; - assign din_inc___2_exp__h517922 = _theResult___fst_exp__h498672 + 11'd1 ; - assign din_inc___2_exp__h517957 = _theResult___fst_exp__h508249 + 11'd1 ; - assign din_inc___2_exp__h517983 = _theResult___fst_exp__h517082 + 11'd1 ; - assign din_inc___2_exp__h556723 = _theResult___fst_exp__h537473 + 11'd1 ; - assign din_inc___2_exp__h556758 = _theResult___fst_exp__h547050 + 11'd1 ; - assign din_inc___2_exp__h556784 = _theResult___fst_exp__h555883 + 11'd1 ; - assign din_inc___2_exp__h595924 = _theResult___fst_exp__h576674 + 11'd1 ; - assign din_inc___2_exp__h595959 = _theResult___fst_exp__h586251 + 11'd1 ; - assign din_inc___2_exp__h595985 = _theResult___fst_exp__h595084 + 11'd1 ; - assign enabled_ints___1__h645886 = pend_ints__h645387 & y__h645898 ; - assign enabled_ints__h645933 = - pend_ints__h645387 & - { r1__read_BITS_12_TO_0___h645909, csrf_mideleg_1_0_reg } ; - assign fcsr_csr__read__h606143 = { 56'd0, x__h608817 } ; + x_quotient__h472395 : + x_remainder__h472396 ; + assign din_inc___2_exp__h378446 = _theResult___fst_exp__h351413 + 8'd1 ; + assign din_inc___2_exp__h378470 = _theResult___fst_exp__h360069 + 8'd1 ; + assign din_inc___2_exp__h378500 = _theResult___fst_exp__h369179 + 8'd1 ; + assign din_inc___2_exp__h378524 = _theResult___fst_exp__h377864 + 8'd1 ; + assign din_inc___2_exp__h424136 = _theResult___fst_exp__h397103 + 8'd1 ; + assign din_inc___2_exp__h424160 = _theResult___fst_exp__h405759 + 8'd1 ; + assign din_inc___2_exp__h424190 = _theResult___fst_exp__h414869 + 8'd1 ; + assign din_inc___2_exp__h424214 = _theResult___fst_exp__h423554 + 8'd1 ; + assign din_inc___2_exp__h469824 = _theResult___fst_exp__h442791 + 8'd1 ; + assign din_inc___2_exp__h469848 = _theResult___fst_exp__h451447 + 8'd1 ; + assign din_inc___2_exp__h469878 = _theResult___fst_exp__h460557 + 8'd1 ; + assign din_inc___2_exp__h469902 = _theResult___fst_exp__h469242 + 8'd1 ; + assign din_inc___2_exp__h517926 = _theResult___fst_exp__h498676 + 11'd1 ; + assign din_inc___2_exp__h517961 = _theResult___fst_exp__h508253 + 11'd1 ; + assign din_inc___2_exp__h517987 = _theResult___fst_exp__h517086 + 11'd1 ; + assign din_inc___2_exp__h556727 = _theResult___fst_exp__h537477 + 11'd1 ; + assign din_inc___2_exp__h556762 = _theResult___fst_exp__h547054 + 11'd1 ; + assign din_inc___2_exp__h556788 = _theResult___fst_exp__h555887 + 11'd1 ; + assign din_inc___2_exp__h595928 = _theResult___fst_exp__h576678 + 11'd1 ; + assign din_inc___2_exp__h595963 = _theResult___fst_exp__h586255 + 11'd1 ; + assign din_inc___2_exp__h595989 = _theResult___fst_exp__h595088 + 11'd1 ; + assign enabled_ints___1__h645895 = pend_ints__h645396 & y__h645907 ; + assign enabled_ints__h645942 = + pend_ints__h645396 & + { r1__read_BITS_12_TO_0___h645918, csrf_mideleg_1_0_reg } ; + assign fcsr_csr__read__h606148 = { 56'd0, x__h608822 } ; assign fetchStage_RDY_pipelines_0_first__2602_AND_NOT_ETC___d13210 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -27841,8 +27841,8 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d12869 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h649444 != 5'd0 || - imm__h649445 != 32'd0) && + rs1__h649453 != 5'd0 || + imm__h649454 != 32'd0) && IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 = @@ -27969,82 +27969,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 ; - assign fflags__h705618 = + assign fflags__h705627 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_fst__h705678 : + y_avValue_snd_fst__h705687 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 ; - assign fflags_csr__read__h606118 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h606129 = { 61'd0, csrf_frm_reg } ; - assign guard__h343309 = - { IF_sfdin51404_BIT_33_THEN_2_ELSE_0__q21[1], - { sfdin__h351404[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352018 = - { IF_theResult___snd60017_BIT_33_THEN_2_ELSE_0__q23[1], - { _theResult___snd__h360017[32:0], 23'd0 } != 56'd0 } ; - assign guard__h360948 = - { IF_sfdin69170_BIT_33_THEN_2_ELSE_0__q31[1], - { sfdin__h369170[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361546 = x__h361648 != 57'd0 ; - assign guard__h369784 = - { IF_theResult___snd77807_BIT_33_THEN_2_ELSE_0__q36[1], - { _theResult___snd__h377807[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389001 = - { IF_sfdin97094_BIT_33_THEN_2_ELSE_0__q56[1], - { sfdin__h397094[32:0], 23'd0 } != 56'd0 } ; - assign guard__h397708 = - { IF_theResult___snd05707_BIT_33_THEN_2_ELSE_0__q58[1], - { _theResult___snd__h405707[32:0], 23'd0 } != 56'd0 } ; - assign guard__h406638 = - { IF_sfdin14860_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h414860[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407236 = x__h407338 != 57'd0 ; - assign guard__h415474 = - { IF_theResult___snd23497_BIT_33_THEN_2_ELSE_0__q71[1], - { _theResult___snd__h423497[32:0], 23'd0 } != 56'd0 } ; - assign guard__h434689 = - { IF_sfdin42782_BIT_33_THEN_2_ELSE_0__q91[1], - { sfdin__h442782[32:0], 23'd0 } != 56'd0 } ; - assign guard__h443396 = - { IF_theResult___snd51395_BIT_33_THEN_2_ELSE_0__q93[1], - { _theResult___snd__h451395[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452326 = - { IF_sfdin60548_BIT_33_THEN_2_ELSE_0__q101[1], - { sfdin__h460548[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452924 = x__h453026 != 57'd0 ; - assign guard__h461162 = - { IF_theResult___snd69185_BIT_33_THEN_2_ELSE_0__q106[1], - { _theResult___snd__h469185[32:0], 23'd0 } != 56'd0 } ; - assign guard__h490711 = - { IF_theResult___snd98623_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h498623[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500023 = - { IF_sfdin08243_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h508243[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500621 = x__h500721 != 57'd0 ; - assign guard__h509092 = - { IF_theResult___snd17028_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h517028[3:0], 52'd0 } != 56'd0 } ; - assign guard__h529512 = - { IF_theResult___snd37424_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h537424[3:0], 52'd0 } != 56'd0 } ; - assign guard__h538824 = - { IF_sfdin47044_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h547044[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539422 = x__h539522 != 57'd0 ; - assign guard__h547893 = - { IF_theResult___snd55829_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h555829[3:0], 52'd0 } != 56'd0 } ; - assign guard__h568713 = - { IF_theResult___snd76625_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h576625[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578025 = - { IF_sfdin86245_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h586245[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578623 = x__h578723 != 57'd0 ; - assign guard__h587094 = - { IF_theResult___snd95030_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h595030[3:0], 52'd0 } != 56'd0 } ; - assign idx__h675470 = + assign fflags_csr__read__h606123 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h606134 = { 61'd0, csrf_frm_reg } ; + assign guard__h343312 = + { IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21[1], + { sfdin__h351407[32:0], 23'd0 } != 56'd0 } ; + assign guard__h352021 = + { IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23[1], + { _theResult___snd__h360020[32:0], 23'd0 } != 56'd0 } ; + assign guard__h360951 = + { IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31[1], + { sfdin__h369173[32:0], 23'd0 } != 56'd0 } ; + assign guard__h361549 = x__h361651 != 57'd0 ; + assign guard__h369787 = + { IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36[1], + { _theResult___snd__h377810[32:0], 23'd0 } != 56'd0 } ; + assign guard__h389004 = + { IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56[1], + { sfdin__h397097[32:0], 23'd0 } != 56'd0 } ; + assign guard__h397711 = + { IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58[1], + { _theResult___snd__h405710[32:0], 23'd0 } != 56'd0 } ; + assign guard__h406641 = + { IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66[1], + { sfdin__h414863[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407239 = x__h407341 != 57'd0 ; + assign guard__h415477 = + { IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71[1], + { _theResult___snd__h423500[32:0], 23'd0 } != 56'd0 } ; + assign guard__h434692 = + { IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91[1], + { sfdin__h442785[32:0], 23'd0 } != 56'd0 } ; + assign guard__h443399 = + { IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93[1], + { _theResult___snd__h451398[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452329 = + { IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101[1], + { sfdin__h460551[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452927 = x__h453029 != 57'd0 ; + assign guard__h461165 = + { IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106[1], + { _theResult___snd__h469188[32:0], 23'd0 } != 56'd0 } ; + assign guard__h490715 = + { IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h498627[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500027 = + { IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h508247[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500625 = x__h500725 != 57'd0 ; + assign guard__h509096 = + { IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h517032[3:0], 52'd0 } != 56'd0 } ; + assign guard__h529516 = + { IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h537428[3:0], 52'd0 } != 56'd0 } ; + assign guard__h538828 = + { IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h547048[3:0], 52'd0 } != 56'd0 } ; + assign guard__h539426 = x__h539526 != 57'd0 ; + assign guard__h547897 = + { IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h555833[3:0], 52'd0 } != 56'd0 } ; + assign guard__h568717 = + { IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h576629[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578029 = + { IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h586249[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578627 = x__h578727 != 57'd0 ; + assign guard__h587098 = + { IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h595034[3:0], 52'd0 } != 56'd0 } ; + assign idx__h675479 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28052,26 +28052,26 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13523) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign imm__h649445 = + assign imm__h649454 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h661036 = + assign k__h661045 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign mcause_csr__read__h607790 = - { r1__read__h610357, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h607535 = - { r1__read__h610344, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h607135 = - { r1__read__h610180, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h607230 = - { r1__read__h610197, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h607361 = - { r1__read__h610221, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h608030 = - { r1__read__h610363, csrf_software_int_pend_vec_0 } ; + assign mcause_csr__read__h607795 = + { r1__read__h610362, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h607540 = + { r1__read__h610349, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h607140 = + { r1__read__h610185, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h607235 = + { r1__read__h610202, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h607366 = + { r1__read__h610226, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h608035 = + { r1__read__h610368, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28148,40 +28148,40 @@ module mkCore(CLK, !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; assign msip__h75409 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h606987 = { r1__read__h610043, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h607443 = - { r1__read__h610339, csrf_mtvec_mode_low_reg } ; - assign n___1__h195749 = + assign mstatus_csr__read__h606992 = { r1__read__h610048, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h607448 = + { r1__read__h610344, csrf_mtvec_mode_low_reg } ; + assign n___1__h195752 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h194346[63:56], + x__h194349[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h194346[55:48], + x__h194349[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h194346[47:40], + x__h194349[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h194346[39:32], + x__h194349[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h194346[31:24], + x__h194349[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h194346[23:16], + x__h194349[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h194346[15:8], + x__h194349[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h194346[7:0] } ; - assign n__read__h608134 = + x__h194349[7:0] } ; + assign n__read__h608139 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h608325 = + assign n__read__h608330 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -28192,250 +28192,250 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h703190 = + assign n__read__h703199 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h294020 = + assign next_deqP___1__h294022 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302016 = + assign next_deqP___1__h302018 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308297 = + assign next_deqP___1__h308299 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316151 = + assign next_deqP___1__h316153 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326208 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h329433 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h702533 = + assign next_deqP___1__h326210 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h329435 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h702542 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h479374 = + assign out___1_sfd__h479378 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ; - assign out___1_sfd__h518316 = + assign out___1_sfd__h518320 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ; - assign out___1_sfd__h557517 = + assign out___1_sfd__h557521 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ; - assign out_exp__h351929 = - sfdin__h351404[34] ? - _theResult___exp__h351926 : - _theResult___fst_exp__h351410 ; - assign out_exp__h360511 = - _theResult___snd__h360017[34] ? - _theResult___exp__h360508 : - _theResult___fst_exp__h360066 ; - assign out_exp__h369695 = - sfdin__h369170[34] ? - _theResult___exp__h369692 : - _theResult___fst_exp__h369176 ; - assign out_exp__h378331 = - _theResult___snd__h377807[34] ? - _theResult___exp__h378328 : - _theResult___fst_exp__h377861 ; - assign out_exp__h397619 = - sfdin__h397094[34] ? - _theResult___exp__h397616 : - _theResult___fst_exp__h397100 ; - assign out_exp__h406201 = - _theResult___snd__h405707[34] ? - _theResult___exp__h406198 : - _theResult___fst_exp__h405756 ; - assign out_exp__h415385 = - sfdin__h414860[34] ? - _theResult___exp__h415382 : - _theResult___fst_exp__h414866 ; - assign out_exp__h424021 = - _theResult___snd__h423497[34] ? - _theResult___exp__h424018 : - _theResult___fst_exp__h423551 ; - assign out_exp__h443307 = - sfdin__h442782[34] ? - _theResult___exp__h443304 : - _theResult___fst_exp__h442788 ; - assign out_exp__h451889 = - _theResult___snd__h451395[34] ? - _theResult___exp__h451886 : - _theResult___fst_exp__h451444 ; - assign out_exp__h461073 = - sfdin__h460548[34] ? - _theResult___exp__h461070 : - _theResult___fst_exp__h460554 ; - assign out_exp__h469709 = - _theResult___snd__h469185[34] ? - _theResult___exp__h469706 : - _theResult___fst_exp__h469239 ; - assign out_exp__h499330 = - _theResult___snd__h498623[5] ? - _theResult___exp__h499327 : - _theResult___fst_exp__h498672 ; - assign out_exp__h508981 = - sfdin__h508243[5] ? - _theResult___exp__h508978 : - _theResult___fst_exp__h508249 ; - assign out_exp__h517765 = - _theResult___snd__h517028[5] ? - _theResult___exp__h517762 : - _theResult___fst_exp__h517082 ; - assign out_exp__h538131 = - _theResult___snd__h537424[5] ? - _theResult___exp__h538128 : - _theResult___fst_exp__h537473 ; - assign out_exp__h547782 = - sfdin__h547044[5] ? - _theResult___exp__h547779 : - _theResult___fst_exp__h547050 ; - assign out_exp__h556566 = - _theResult___snd__h555829[5] ? - _theResult___exp__h556563 : - _theResult___fst_exp__h555883 ; - assign out_exp__h577332 = - _theResult___snd__h576625[5] ? - _theResult___exp__h577329 : - _theResult___fst_exp__h576674 ; - assign out_exp__h586983 = - sfdin__h586245[5] ? - _theResult___exp__h586980 : - _theResult___fst_exp__h586251 ; - assign out_exp__h595767 = - _theResult___snd__h595030[5] ? - _theResult___exp__h595764 : - _theResult___fst_exp__h595084 ; - assign out_f_exp__h378707 = - (_theResult___exp__h378430 == 8'd255 && - _theResult___sfd__h378431 != 23'd0 || + assign out_exp__h351932 = + sfdin__h351407[34] ? + _theResult___exp__h351929 : + _theResult___fst_exp__h351413 ; + assign out_exp__h360514 = + _theResult___snd__h360020[34] ? + _theResult___exp__h360511 : + _theResult___fst_exp__h360069 ; + assign out_exp__h369698 = + sfdin__h369173[34] ? + _theResult___exp__h369695 : + _theResult___fst_exp__h369179 ; + assign out_exp__h378334 = + _theResult___snd__h377810[34] ? + _theResult___exp__h378331 : + _theResult___fst_exp__h377864 ; + assign out_exp__h397622 = + sfdin__h397097[34] ? + _theResult___exp__h397619 : + _theResult___fst_exp__h397103 ; + assign out_exp__h406204 = + _theResult___snd__h405710[34] ? + _theResult___exp__h406201 : + _theResult___fst_exp__h405759 ; + assign out_exp__h415388 = + sfdin__h414863[34] ? + _theResult___exp__h415385 : + _theResult___fst_exp__h414869 ; + assign out_exp__h424024 = + _theResult___snd__h423500[34] ? + _theResult___exp__h424021 : + _theResult___fst_exp__h423554 ; + assign out_exp__h443310 = + sfdin__h442785[34] ? + _theResult___exp__h443307 : + _theResult___fst_exp__h442791 ; + assign out_exp__h451892 = + _theResult___snd__h451398[34] ? + _theResult___exp__h451889 : + _theResult___fst_exp__h451447 ; + assign out_exp__h461076 = + sfdin__h460551[34] ? + _theResult___exp__h461073 : + _theResult___fst_exp__h460557 ; + assign out_exp__h469712 = + _theResult___snd__h469188[34] ? + _theResult___exp__h469709 : + _theResult___fst_exp__h469242 ; + assign out_exp__h499334 = + _theResult___snd__h498627[5] ? + _theResult___exp__h499331 : + _theResult___fst_exp__h498676 ; + assign out_exp__h508985 = + sfdin__h508247[5] ? + _theResult___exp__h508982 : + _theResult___fst_exp__h508253 ; + assign out_exp__h517769 = + _theResult___snd__h517032[5] ? + _theResult___exp__h517766 : + _theResult___fst_exp__h517086 ; + assign out_exp__h538135 = + _theResult___snd__h537428[5] ? + _theResult___exp__h538132 : + _theResult___fst_exp__h537477 ; + assign out_exp__h547786 = + sfdin__h547048[5] ? + _theResult___exp__h547783 : + _theResult___fst_exp__h547054 ; + assign out_exp__h556570 = + _theResult___snd__h555833[5] ? + _theResult___exp__h556567 : + _theResult___fst_exp__h555887 ; + assign out_exp__h577336 = + _theResult___snd__h576629[5] ? + _theResult___exp__h577333 : + _theResult___fst_exp__h576678 ; + assign out_exp__h586987 = + sfdin__h586249[5] ? + _theResult___exp__h586984 : + _theResult___fst_exp__h586255 ; + assign out_exp__h595771 = + _theResult___snd__h595034[5] ? + _theResult___exp__h595768 : + _theResult___fst_exp__h595088 ; + assign out_f_exp__h378710 = + (_theResult___exp__h378433 == 8'd255 && + _theResult___sfd__h378434 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378421 ; - assign out_f_exp__h424397 = - (_theResult___exp__h424120 == 8'd255 && - _theResult___sfd__h424121 != 23'd0 || + _theResult___fst_exp__h378424 ; + assign out_f_exp__h424400 = + (_theResult___exp__h424123 == 8'd255 && + _theResult___sfd__h424124 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424111 ; - assign out_f_exp__h470085 = - (_theResult___exp__h469808 == 8'd255 && - _theResult___sfd__h469809 != 23'd0 || + _theResult___fst_exp__h424114 ; + assign out_f_exp__h470088 = + (_theResult___exp__h469811 == 8'd255 && + _theResult___sfd__h469812 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469799 ; - assign out_f_sfd__h378708 = - (_theResult___exp__h378430 == 8'd255 && - _theResult___sfd__h378431 != 23'd0) ? + _theResult___fst_exp__h469802 ; + assign out_f_sfd__h378711 = + (_theResult___exp__h378433 == 8'd255 && + _theResult___sfd__h378434 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h378431 ; - assign out_f_sfd__h424398 = - (_theResult___exp__h424120 == 8'd255 && - _theResult___sfd__h424121 != 23'd0) ? + _theResult___sfd__h378434 ; + assign out_f_sfd__h424401 = + (_theResult___exp__h424123 == 8'd255 && + _theResult___sfd__h424124 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424121 ; - assign out_f_sfd__h470086 = - (_theResult___exp__h469808 == 8'd255 && - _theResult___sfd__h469809 != 23'd0) ? + _theResult___sfd__h424124 ; + assign out_f_sfd__h470089 = + (_theResult___exp__h469811 == 8'd255 && + _theResult___sfd__h469812 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h469809 ; - assign out_sfd__h351930 = - sfdin__h351404[34] ? - _theResult___sfd__h351927 : - sfdin__h351404[56:34] ; - assign out_sfd__h360512 = - _theResult___snd__h360017[34] ? - _theResult___sfd__h360509 : - _theResult___snd__h360017[56:34] ; - assign out_sfd__h369696 = - sfdin__h369170[34] ? - _theResult___sfd__h369693 : - sfdin__h369170[56:34] ; - assign out_sfd__h378332 = - _theResult___snd__h377807[34] ? - _theResult___sfd__h378329 : - _theResult___snd__h377807[56:34] ; - assign out_sfd__h397620 = - sfdin__h397094[34] ? - _theResult___sfd__h397617 : - sfdin__h397094[56:34] ; - assign out_sfd__h406202 = - _theResult___snd__h405707[34] ? - _theResult___sfd__h406199 : - _theResult___snd__h405707[56:34] ; - assign out_sfd__h415386 = - sfdin__h414860[34] ? - _theResult___sfd__h415383 : - sfdin__h414860[56:34] ; - assign out_sfd__h424022 = - _theResult___snd__h423497[34] ? - _theResult___sfd__h424019 : - _theResult___snd__h423497[56:34] ; - assign out_sfd__h443308 = - sfdin__h442782[34] ? - _theResult___sfd__h443305 : - sfdin__h442782[56:34] ; - assign out_sfd__h451890 = - _theResult___snd__h451395[34] ? - _theResult___sfd__h451887 : - _theResult___snd__h451395[56:34] ; - assign out_sfd__h461074 = - sfdin__h460548[34] ? - _theResult___sfd__h461071 : - sfdin__h460548[56:34] ; - assign out_sfd__h469710 = - _theResult___snd__h469185[34] ? - _theResult___sfd__h469707 : - _theResult___snd__h469185[56:34] ; - assign out_sfd__h499331 = - _theResult___snd__h498623[5] ? - _theResult___sfd__h499328 : - _theResult___snd__h498623[56:5] ; - assign out_sfd__h508982 = - sfdin__h508243[5] ? - _theResult___sfd__h508979 : - sfdin__h508243[56:5] ; - assign out_sfd__h517766 = - _theResult___snd__h517028[5] ? - _theResult___sfd__h517763 : - _theResult___snd__h517028[56:5] ; - assign out_sfd__h538132 = - _theResult___snd__h537424[5] ? - _theResult___sfd__h538129 : - _theResult___snd__h537424[56:5] ; - assign out_sfd__h547783 = - sfdin__h547044[5] ? - _theResult___sfd__h547780 : - sfdin__h547044[56:5] ; - assign out_sfd__h556567 = - _theResult___snd__h555829[5] ? - _theResult___sfd__h556564 : - _theResult___snd__h555829[56:5] ; - assign out_sfd__h577333 = - _theResult___snd__h576625[5] ? - _theResult___sfd__h577330 : - _theResult___snd__h576625[56:5] ; - assign out_sfd__h586984 = - sfdin__h586245[5] ? - _theResult___sfd__h586981 : - sfdin__h586245[56:5] ; - assign out_sfd__h595768 = - _theResult___snd__h595030[5] ? - _theResult___sfd__h595765 : - _theResult___snd__h595030[56:5] ; - assign pend_ints__h645387 = + _theResult___sfd__h469812 ; + assign out_sfd__h351933 = + sfdin__h351407[34] ? + _theResult___sfd__h351930 : + sfdin__h351407[56:34] ; + assign out_sfd__h360515 = + _theResult___snd__h360020[34] ? + _theResult___sfd__h360512 : + _theResult___snd__h360020[56:34] ; + assign out_sfd__h369699 = + sfdin__h369173[34] ? + _theResult___sfd__h369696 : + sfdin__h369173[56:34] ; + assign out_sfd__h378335 = + _theResult___snd__h377810[34] ? + _theResult___sfd__h378332 : + _theResult___snd__h377810[56:34] ; + assign out_sfd__h397623 = + sfdin__h397097[34] ? + _theResult___sfd__h397620 : + sfdin__h397097[56:34] ; + assign out_sfd__h406205 = + _theResult___snd__h405710[34] ? + _theResult___sfd__h406202 : + _theResult___snd__h405710[56:34] ; + assign out_sfd__h415389 = + sfdin__h414863[34] ? + _theResult___sfd__h415386 : + sfdin__h414863[56:34] ; + assign out_sfd__h424025 = + _theResult___snd__h423500[34] ? + _theResult___sfd__h424022 : + _theResult___snd__h423500[56:34] ; + assign out_sfd__h443311 = + sfdin__h442785[34] ? + _theResult___sfd__h443308 : + sfdin__h442785[56:34] ; + assign out_sfd__h451893 = + _theResult___snd__h451398[34] ? + _theResult___sfd__h451890 : + _theResult___snd__h451398[56:34] ; + assign out_sfd__h461077 = + sfdin__h460551[34] ? + _theResult___sfd__h461074 : + sfdin__h460551[56:34] ; + assign out_sfd__h469713 = + _theResult___snd__h469188[34] ? + _theResult___sfd__h469710 : + _theResult___snd__h469188[56:34] ; + assign out_sfd__h499335 = + _theResult___snd__h498627[5] ? + _theResult___sfd__h499332 : + _theResult___snd__h498627[56:5] ; + assign out_sfd__h508986 = + sfdin__h508247[5] ? + _theResult___sfd__h508983 : + sfdin__h508247[56:5] ; + assign out_sfd__h517770 = + _theResult___snd__h517032[5] ? + _theResult___sfd__h517767 : + _theResult___snd__h517032[56:5] ; + assign out_sfd__h538136 = + _theResult___snd__h537428[5] ? + _theResult___sfd__h538133 : + _theResult___snd__h537428[56:5] ; + assign out_sfd__h547787 = + sfdin__h547048[5] ? + _theResult___sfd__h547784 : + sfdin__h547048[56:5] ; + assign out_sfd__h556571 = + _theResult___snd__h555833[5] ? + _theResult___sfd__h556568 : + _theResult___snd__h555833[56:5] ; + assign out_sfd__h577337 = + _theResult___snd__h576629[5] ? + _theResult___sfd__h577334 : + _theResult___snd__h576629[56:5] ; + assign out_sfd__h586988 = + sfdin__h586249[5] ? + _theResult___sfd__h586985 : + sfdin__h586249[56:5] ; + assign out_sfd__h595772 = + _theResult___snd__h595034[5] ? + _theResult___sfd__h595769 : + _theResult___snd__h595034[56:5] ; + assign pend_ints__h645396 = { csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h707133 = csrf_prv_reg ; - assign prv__h707177 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473077 = + assign prv__h707142 = csrf_prv_reg ; + assign prv__h707186 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h473080 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_12_TO_0___h645909 = + assign r1__read_BITS_12_TO_0___h645918 = { 3'd0, csrf_mideleg_11_reg, 1'b0, @@ -28443,126 +28443,126 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h649313 = csrf_fs_reg ; - assign r1__read_BIT_20___h649941 = csrf_tw_reg ; - assign r1__read__h608832 = { r1__read__h608834, csrf_ie_vec_1 } ; - assign r1__read__h608834 = { r1__read__h608836, 2'b0 } ; - assign r1__read__h608836 = { r1__read__h608838, csrf_prev_ie_vec_0 } ; - assign r1__read__h608838 = { r1__read__h608840, csrf_prev_ie_vec_1 } ; - assign r1__read__h608840 = { r1__read__h608842, 2'b0 } ; - assign r1__read__h608842 = { r1__read__h608844, csrf_spp_reg } ; - assign r1__read__h608844 = { r1__read__h608846, 4'b0 } ; - assign r1__read__h608846 = { r1__read__h608848, csrf_fs_reg } ; - assign r1__read__h608848 = { r1__read__h608850, 2'd0 } ; - assign r1__read__h608850 = { r1__read__h608852, 1'b0 } ; - assign r1__read__h608852 = { r1__read__h608854, csrf_sum_reg } ; - assign r1__read__h608854 = { r1__read__h608856, csrf_mxr_reg } ; - assign r1__read__h608856 = { r1__read__h608858, 12'b0 } ; - assign r1__read__h608858 = { r1__read__h608860, 2'b10 } ; - assign r1__read__h608860 = { r__h608864, 29'b0 } ; - assign r1__read__h609236 = - { r1__read__h609238, csrf_software_int_en_vec_1 } ; - assign r1__read__h609238 = { r1__read__h609240, 2'b0 } ; - assign r1__read__h609240 = { r1__read__h609242, csrf_timer_int_en_vec_0 } ; - assign r1__read__h609242 = { r1__read__h609244, csrf_timer_int_en_vec_1 } ; - assign r1__read__h609244 = { r1__read__h609246, 2'b0 } ; - assign r1__read__h609246 = - { r1__read__h609248, csrf_external_int_en_vec_0 } ; - assign r1__read__h609248 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h609766 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h609771 = { r1__read__h609773, csrf_scounteren_tm_reg } ; - assign r1__read__h609773 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h609784 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h609790 = - { r1__read__h609792, csrf_software_int_pend_vec_1 } ; - assign r1__read__h609792 = { r1__read__h609794, 2'b0 } ; - assign r1__read__h609794 = - { r1__read__h609796, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h609796 = - { r1__read__h609798, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h609798 = { r1__read__h609800, 2'b0 } ; - assign r1__read__h609800 = - { r1__read__h609802, csrf_external_int_pend_vec_0 } ; - assign r1__read__h609802 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610020 = { vm_mode_reg__read__h610026, 16'd0 } ; - assign r1__read__h610043 = { r1__read__h610045, csrf_ie_vec_1 } ; - assign r1__read__h610045 = { r1__read__h610047, 1'b0 } ; - assign r1__read__h610047 = { r1__read__h610049, csrf_ie_vec_3 } ; - assign r1__read__h610049 = { r1__read__h610051, csrf_prev_ie_vec_0 } ; - assign r1__read__h610051 = { r1__read__h610053, csrf_prev_ie_vec_1 } ; - assign r1__read__h610053 = { r1__read__h610055, 1'b0 } ; - assign r1__read__h610055 = { r1__read__h610057, csrf_prev_ie_vec_3 } ; - assign r1__read__h610057 = { r1__read__h610059, csrf_spp_reg } ; - assign r1__read__h610059 = { r1__read__h610061, 2'b0 } ; - assign r1__read__h610061 = { r1__read__h610063, csrf_mpp_reg } ; - assign r1__read__h610063 = { r1__read__h610065, csrf_fs_reg } ; - assign r1__read__h610065 = { r1__read__h610067, 2'd0 } ; - assign r1__read__h610067 = { r1__read__h610069, csrf_mprv_reg } ; - assign r1__read__h610069 = { r1__read__h610071, csrf_sum_reg } ; - assign r1__read__h610071 = { r1__read__h610073, csrf_mxr_reg } ; - assign r1__read__h610073 = { r1__read__h610075, csrf_tvm_reg } ; - assign r1__read__h610075 = { r1__read__h610077, csrf_tw_reg } ; - assign r1__read__h610077 = { r1__read__h610079, csrf_tsr_reg } ; - assign r1__read__h610079 = { r1__read__h610081, 9'b0 } ; - assign r1__read__h610081 = { r1__read__h610083, 2'b10 } ; - assign r1__read__h610083 = { r1__read__h610085, 2'b10 } ; - assign r1__read__h610085 = { r__h608864, 27'b0 } ; - assign r1__read__h610180 = { r1__read__h610182, 1'b0 } ; - assign r1__read__h610182 = { r1__read__h610184, csrf_medeleg_13_11_reg } ; - assign r1__read__h610184 = { r1__read__h610186, 1'b0 } ; - assign r1__read__h610186 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h610197 = { r1__read__h610199, 1'b0 } ; - assign r1__read__h610199 = { r1__read__h610201, csrf_mideleg_5_3_reg } ; - assign r1__read__h610201 = { r1__read__h610203, 1'b0 } ; - assign r1__read__h610203 = { r1__read__h610205, csrf_mideleg_9_7_reg } ; - assign r1__read__h610205 = { r1__read__h610207, 1'b0 } ; - assign r1__read__h610207 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h610221 = - { r1__read__h610223, csrf_software_int_en_vec_1 } ; - assign r1__read__h610223 = { r1__read__h610225, 1'b0 } ; - assign r1__read__h610225 = - { r1__read__h610227, csrf_software_int_en_vec_3 } ; - assign r1__read__h610227 = { r1__read__h610229, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610229 = { r1__read__h610231, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610231 = { r1__read__h610233, 1'b0 } ; - assign r1__read__h610233 = { r1__read__h610235, csrf_timer_int_en_vec_3 } ; - assign r1__read__h610235 = - { r1__read__h610237, csrf_external_int_en_vec_0 } ; - assign r1__read__h610237 = - { r1__read__h610239, csrf_external_int_en_vec_1 } ; - assign r1__read__h610239 = { r1__read__h610241, 1'b0 } ; - assign r1__read__h610241 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h610339 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h610344 = { r1__read__h610346, csrf_mcounteren_tm_reg } ; - assign r1__read__h610346 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h610357 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h610363 = - { r1__read__h610365, csrf_software_int_pend_vec_1 } ; - assign r1__read__h610365 = { r1__read__h610367, 1'b0 } ; - assign r1__read__h610367 = - { r1__read__h610369, csrf_software_int_pend_vec_3 } ; - assign r1__read__h610369 = - { r1__read__h610371, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h610371 = - { r1__read__h610373, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h610373 = { r1__read__h610375, 1'b0 } ; - assign r1__read__h610375 = - { r1__read__h610377, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h610377 = - { r1__read__h610379, csrf_external_int_pend_vec_0 } ; - assign r1__read__h610379 = - { r1__read__h610381, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610381 = { r1__read__h610383, 1'b0 } ; - assign r1__read__h610383 = - { r1__read__h610385, csrf_external_int_pend_vec_3 } ; - assign r1__read__h610385 = { r1__read__h610387, 2'b0 } ; - assign r1__read__h610387 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h478957 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h478958 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473103 = + assign r1__read_BITS_13_TO_12___h649322 = csrf_fs_reg ; + assign r1__read_BIT_20___h649950 = csrf_tw_reg ; + assign r1__read__h608837 = { r1__read__h608839, csrf_ie_vec_1 } ; + assign r1__read__h608839 = { r1__read__h608841, 2'b0 } ; + assign r1__read__h608841 = { r1__read__h608843, csrf_prev_ie_vec_0 } ; + assign r1__read__h608843 = { r1__read__h608845, csrf_prev_ie_vec_1 } ; + assign r1__read__h608845 = { r1__read__h608847, 2'b0 } ; + assign r1__read__h608847 = { r1__read__h608849, csrf_spp_reg } ; + assign r1__read__h608849 = { r1__read__h608851, 4'b0 } ; + assign r1__read__h608851 = { r1__read__h608853, csrf_fs_reg } ; + assign r1__read__h608853 = { r1__read__h608855, 2'd0 } ; + assign r1__read__h608855 = { r1__read__h608857, 1'b0 } ; + assign r1__read__h608857 = { r1__read__h608859, csrf_sum_reg } ; + assign r1__read__h608859 = { r1__read__h608861, csrf_mxr_reg } ; + assign r1__read__h608861 = { r1__read__h608863, 12'b0 } ; + assign r1__read__h608863 = { r1__read__h608865, 2'b10 } ; + assign r1__read__h608865 = { r__h608869, 29'b0 } ; + assign r1__read__h609241 = + { r1__read__h609243, csrf_software_int_en_vec_1 } ; + assign r1__read__h609243 = { r1__read__h609245, 2'b0 } ; + assign r1__read__h609245 = { r1__read__h609247, csrf_timer_int_en_vec_0 } ; + assign r1__read__h609247 = { r1__read__h609249, csrf_timer_int_en_vec_1 } ; + assign r1__read__h609249 = { r1__read__h609251, 2'b0 } ; + assign r1__read__h609251 = + { r1__read__h609253, csrf_external_int_en_vec_0 } ; + assign r1__read__h609253 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h609771 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h609776 = { r1__read__h609778, csrf_scounteren_tm_reg } ; + assign r1__read__h609778 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h609789 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h609795 = + { r1__read__h609797, csrf_software_int_pend_vec_1 } ; + assign r1__read__h609797 = { r1__read__h609799, 2'b0 } ; + assign r1__read__h609799 = + { r1__read__h609801, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h609801 = + { r1__read__h609803, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h609803 = { r1__read__h609805, 2'b0 } ; + assign r1__read__h609805 = + { r1__read__h609807, csrf_external_int_pend_vec_0 } ; + assign r1__read__h609807 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610025 = { vm_mode_reg__read__h610031, 16'd0 } ; + assign r1__read__h610048 = { r1__read__h610050, csrf_ie_vec_1 } ; + assign r1__read__h610050 = { r1__read__h610052, 1'b0 } ; + assign r1__read__h610052 = { r1__read__h610054, csrf_ie_vec_3 } ; + assign r1__read__h610054 = { r1__read__h610056, csrf_prev_ie_vec_0 } ; + assign r1__read__h610056 = { r1__read__h610058, csrf_prev_ie_vec_1 } ; + assign r1__read__h610058 = { r1__read__h610060, 1'b0 } ; + assign r1__read__h610060 = { r1__read__h610062, csrf_prev_ie_vec_3 } ; + assign r1__read__h610062 = { r1__read__h610064, csrf_spp_reg } ; + assign r1__read__h610064 = { r1__read__h610066, 2'b0 } ; + assign r1__read__h610066 = { r1__read__h610068, csrf_mpp_reg } ; + assign r1__read__h610068 = { r1__read__h610070, csrf_fs_reg } ; + assign r1__read__h610070 = { r1__read__h610072, 2'd0 } ; + assign r1__read__h610072 = { r1__read__h610074, csrf_mprv_reg } ; + assign r1__read__h610074 = { r1__read__h610076, csrf_sum_reg } ; + assign r1__read__h610076 = { r1__read__h610078, csrf_mxr_reg } ; + assign r1__read__h610078 = { r1__read__h610080, csrf_tvm_reg } ; + assign r1__read__h610080 = { r1__read__h610082, csrf_tw_reg } ; + assign r1__read__h610082 = { r1__read__h610084, csrf_tsr_reg } ; + assign r1__read__h610084 = { r1__read__h610086, 9'b0 } ; + assign r1__read__h610086 = { r1__read__h610088, 2'b10 } ; + assign r1__read__h610088 = { r1__read__h610090, 2'b10 } ; + assign r1__read__h610090 = { r__h608869, 27'b0 } ; + assign r1__read__h610185 = { r1__read__h610187, 1'b0 } ; + assign r1__read__h610187 = { r1__read__h610189, csrf_medeleg_13_11_reg } ; + assign r1__read__h610189 = { r1__read__h610191, 1'b0 } ; + assign r1__read__h610191 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h610202 = { r1__read__h610204, 1'b0 } ; + assign r1__read__h610204 = { r1__read__h610206, csrf_mideleg_5_3_reg } ; + assign r1__read__h610206 = { r1__read__h610208, 1'b0 } ; + assign r1__read__h610208 = { r1__read__h610210, csrf_mideleg_9_7_reg } ; + assign r1__read__h610210 = { r1__read__h610212, 1'b0 } ; + assign r1__read__h610212 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h610226 = + { r1__read__h610228, csrf_software_int_en_vec_1 } ; + assign r1__read__h610228 = { r1__read__h610230, 1'b0 } ; + assign r1__read__h610230 = + { r1__read__h610232, csrf_software_int_en_vec_3 } ; + assign r1__read__h610232 = { r1__read__h610234, csrf_timer_int_en_vec_0 } ; + assign r1__read__h610234 = { r1__read__h610236, csrf_timer_int_en_vec_1 } ; + assign r1__read__h610236 = { r1__read__h610238, 1'b0 } ; + assign r1__read__h610238 = { r1__read__h610240, csrf_timer_int_en_vec_3 } ; + assign r1__read__h610240 = + { r1__read__h610242, csrf_external_int_en_vec_0 } ; + assign r1__read__h610242 = + { r1__read__h610244, csrf_external_int_en_vec_1 } ; + assign r1__read__h610244 = { r1__read__h610246, 1'b0 } ; + assign r1__read__h610246 = { 52'd4, csrf_external_int_en_vec_3 } ; + assign r1__read__h610344 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h610349 = { r1__read__h610351, csrf_mcounteren_tm_reg } ; + assign r1__read__h610351 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h610362 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h610368 = + { r1__read__h610370, csrf_software_int_pend_vec_1 } ; + assign r1__read__h610370 = { r1__read__h610372, 1'b0 } ; + assign r1__read__h610372 = + { r1__read__h610374, csrf_software_int_pend_vec_3 } ; + assign r1__read__h610374 = + { r1__read__h610376, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h610376 = + { r1__read__h610378, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h610378 = { r1__read__h610380, 1'b0 } ; + assign r1__read__h610380 = + { r1__read__h610382, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h610382 = + { r1__read__h610384, csrf_external_int_pend_vec_0 } ; + assign r1__read__h610384 = + { r1__read__h610386, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610386 = { r1__read__h610388, 1'b0 } ; + assign r1__read__h610388 = + { r1__read__h610390, csrf_external_int_pend_vec_3 } ; + assign r1__read__h610390 = { r1__read__h610392, 2'b0 } ; + assign r1__read__h610392 = { 49'b0, csrf_debug_int_pend } ; + assign rVal1__h478961 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h478962 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h473106 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h608864 = csrf_fs_reg == 2'b11 ; + assign r__h608869 = csrf_fs_reg == 2'b11 ; assign regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && @@ -28662,12 +28662,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renaming_spec_bits__h675339 = + assign renaming_spec_bits__h675348 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h672105 : + y_avValue_snd_fst__h672114 : specTagManager$currentSpecBits ; - assign res_data__h335086 = { 32'd0, x__h335098 } ; - assign res_data__h335091 = + assign res_data__h335089 = { 32'd0, x__h335101 } ; + assign res_data__h335094 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28680,8 +28680,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h380781 = { 32'd0, x__h380793 } ; - assign res_data__h380786 = + assign res_data__h380784 = { 32'd0, x__h380796 } ; + assign res_data__h380789 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28694,8 +28694,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h426469 = { 32'd0, x__h426481 } ; - assign res_data__h426474 = + assign res_data__h426472 = { 32'd0, x__h426484 } ; + assign res_data__h426477 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28708,7 +28708,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335087 = + assign res_fflags__h335090 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -28776,7 +28776,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h380782 = + assign res_fflags__h380785 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -28844,7 +28844,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h426470 = + assign res_fflags__h426473 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -28912,35 +28912,35 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289190 = + assign resp_addr__h289193 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h361551 = + assign result__h361554 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h361546 } ; - assign result__h407241 = + guard__h361549 } ; + assign result__h407244 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407236 } ; - assign result__h452929 = + guard__h407239 } ; + assign result__h452932 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h452924 } ; - assign result__h500626 = + guard__h452927 } ; + assign result__h500630 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[0] | - guard__h500621 } ; - assign result__h539427 = + guard__h500625 } ; + assign result__h539431 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[0] | - guard__h539422 } ; - assign result__h578628 = + guard__h539426 } ; + assign result__h578632 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[0] | - guard__h578623 } ; - assign result__h641096 = w__h641091 & y__h641125 ; - assign result__h641147 = ~x__h641146 ; + guard__h578627 } ; + assign result__h641105 = w__h641100 & y__h641134 ; + assign result__h641156 = ~x__h641155 ; assign rob_RDY_enqPort_0_enq__2627_AND_regRenamingTab_ETC___d13095 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && @@ -28972,12 +28972,12 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q261 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h649444 = + assign rs1__h649453 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h606844 = { r1__read__h610020, csrf_ppn_reg } ; + assign satp_csr__read__h606849 = { r1__read__h610025, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && @@ -28997,298 +28997,298 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 && IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ; - assign sbIdx__h156309 = + assign sbIdx__h156310 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h606642 = - { r1__read__h609784, csrf_scause_code_reg } ; - assign scounteren_csr__read__h606504 = - { r1__read__h609771, csrf_scounteren_cy_reg } ; - assign sfd__h335694 = { value__h343921, 3'd0 } ; - assign sfd__h351502 = + assign scause_csr__read__h606647 = + { r1__read__h609789, csrf_scause_code_reg } ; + assign scounteren_csr__read__h606509 = + { r1__read__h609776, csrf_scounteren_cy_reg } ; + assign sfd__h335697 = { value__h343924, 3'd0 } ; + assign sfd__h351505 = { 1'b0, - _theResult___fst_exp__h351410 != 8'd0, - sfdin__h351404[56:34] } + + _theResult___fst_exp__h351413 != 8'd0, + sfdin__h351407[56:34] } + 25'd1 ; - assign sfd__h360084 = + assign sfd__h360087 = { 1'b0, - _theResult___fst_exp__h360066 != 8'd0, - _theResult___snd__h360017[56:34] } + + _theResult___fst_exp__h360069 != 8'd0, + _theResult___snd__h360020[56:34] } + 25'd1 ; - assign sfd__h369268 = + assign sfd__h369271 = { 1'b0, - _theResult___fst_exp__h369176 != 8'd0, - sfdin__h369170[56:34] } + + _theResult___fst_exp__h369179 != 8'd0, + sfdin__h369173[56:34] } + 25'd1 ; - assign sfd__h377880 = + assign sfd__h377883 = { 1'b0, - _theResult___fst_exp__h377861 != 8'd0, - _theResult___snd__h377807[56:34] } + + _theResult___fst_exp__h377864 != 8'd0, + _theResult___snd__h377810[56:34] } + 25'd1 ; - assign sfd__h381389 = { value__h389611, 3'd0 } ; - assign sfd__h397192 = + assign sfd__h381392 = { value__h389614, 3'd0 } ; + assign sfd__h397195 = { 1'b0, - _theResult___fst_exp__h397100 != 8'd0, - sfdin__h397094[56:34] } + + _theResult___fst_exp__h397103 != 8'd0, + sfdin__h397097[56:34] } + 25'd1 ; - assign sfd__h405774 = + assign sfd__h405777 = { 1'b0, - _theResult___fst_exp__h405756 != 8'd0, - _theResult___snd__h405707[56:34] } + + _theResult___fst_exp__h405759 != 8'd0, + _theResult___snd__h405710[56:34] } + 25'd1 ; - assign sfd__h414958 = + assign sfd__h414961 = { 1'b0, - _theResult___fst_exp__h414866 != 8'd0, - sfdin__h414860[56:34] } + + _theResult___fst_exp__h414869 != 8'd0, + sfdin__h414863[56:34] } + 25'd1 ; - assign sfd__h423570 = + assign sfd__h423573 = { 1'b0, - _theResult___fst_exp__h423551 != 8'd0, - _theResult___snd__h423497[56:34] } + + _theResult___fst_exp__h423554 != 8'd0, + _theResult___snd__h423500[56:34] } + 25'd1 ; - assign sfd__h427077 = { value__h435299, 3'd0 } ; - assign sfd__h442880 = + assign sfd__h427080 = { value__h435302, 3'd0 } ; + assign sfd__h442883 = { 1'b0, - _theResult___fst_exp__h442788 != 8'd0, - sfdin__h442782[56:34] } + + _theResult___fst_exp__h442791 != 8'd0, + sfdin__h442785[56:34] } + 25'd1 ; - assign sfd__h451462 = + assign sfd__h451465 = { 1'b0, - _theResult___fst_exp__h451444 != 8'd0, - _theResult___snd__h451395[56:34] } + + _theResult___fst_exp__h451447 != 8'd0, + _theResult___snd__h451398[56:34] } + 25'd1 ; - assign sfd__h460646 = + assign sfd__h460649 = { 1'b0, - _theResult___fst_exp__h460554 != 8'd0, - sfdin__h460548[56:34] } + + _theResult___fst_exp__h460557 != 8'd0, + sfdin__h460551[56:34] } + 25'd1 ; - assign sfd__h469258 = + assign sfd__h469261 = { 1'b0, - _theResult___fst_exp__h469239 != 8'd0, - _theResult___snd__h469185[56:34] } + + _theResult___fst_exp__h469242 != 8'd0, + _theResult___snd__h469188[56:34] } + 25'd1 ; - assign sfd__h479671 = { value__h484229, 32'd0 } ; - assign sfd__h498690 = + assign sfd__h479675 = { value__h484233, 32'd0 } ; + assign sfd__h498694 = { 1'b0, - _theResult___fst_exp__h498672 != 11'd0, - _theResult___snd__h498623[56:5] } + + _theResult___fst_exp__h498676 != 11'd0, + _theResult___snd__h498627[56:5] } + 54'd1 ; - assign sfd__h508341 = + assign sfd__h508345 = { 1'b0, - _theResult___fst_exp__h508249 != 11'd0, - sfdin__h508243[56:5] } + + _theResult___fst_exp__h508253 != 11'd0, + sfdin__h508247[56:5] } + 54'd1 ; - assign sfd__h517101 = + assign sfd__h517105 = { 1'b0, - _theResult___fst_exp__h517082 != 11'd0, - _theResult___snd__h517028[56:5] } + + _theResult___fst_exp__h517086 != 11'd0, + _theResult___snd__h517032[56:5] } + 54'd1 ; - assign sfd__h518613 = { value__h523030, 32'd0 } ; - assign sfd__h537491 = + assign sfd__h518617 = { value__h523034, 32'd0 } ; + assign sfd__h537495 = { 1'b0, - _theResult___fst_exp__h537473 != 11'd0, - _theResult___snd__h537424[56:5] } + + _theResult___fst_exp__h537477 != 11'd0, + _theResult___snd__h537428[56:5] } + 54'd1 ; - assign sfd__h547142 = + assign sfd__h547146 = { 1'b0, - _theResult___fst_exp__h547050 != 11'd0, - sfdin__h547044[56:5] } + + _theResult___fst_exp__h547054 != 11'd0, + sfdin__h547048[56:5] } + 54'd1 ; - assign sfd__h555902 = + assign sfd__h555906 = { 1'b0, - _theResult___fst_exp__h555883 != 11'd0, - _theResult___snd__h555829[56:5] } + + _theResult___fst_exp__h555887 != 11'd0, + _theResult___snd__h555833[56:5] } + 54'd1 ; - assign sfd__h557814 = { value__h562231, 32'd0 } ; - assign sfd__h576692 = + assign sfd__h557818 = { value__h562235, 32'd0 } ; + assign sfd__h576696 = { 1'b0, - _theResult___fst_exp__h576674 != 11'd0, - _theResult___snd__h576625[56:5] } + + _theResult___fst_exp__h576678 != 11'd0, + _theResult___snd__h576629[56:5] } + 54'd1 ; - assign sfd__h586343 = + assign sfd__h586347 = { 1'b0, - _theResult___fst_exp__h586251 != 11'd0, - sfdin__h586245[56:5] } + + _theResult___fst_exp__h586255 != 11'd0, + sfdin__h586249[56:5] } + 54'd1 ; - assign sfd__h595103 = + assign sfd__h595107 = { 1'b0, - _theResult___fst_exp__h595084 != 11'd0, - _theResult___snd__h595030[56:5] } + + _theResult___fst_exp__h595088 != 11'd0, + _theResult___snd__h595034[56:5] } + 54'd1 ; - assign sfdin__h351404 = - _theResult____h343299[56] ? - _theResult___snd__h351421 : - _theResult___snd__h351432 ; - assign sfdin__h369170 = - _theResult____h360938[56] ? - _theResult___snd__h369187 : - _theResult___snd__h369198 ; - assign sfdin__h397094 = - _theResult____h388991[56] ? - _theResult___snd__h397111 : - _theResult___snd__h397122 ; - assign sfdin__h414860 = - _theResult____h406628[56] ? - _theResult___snd__h414877 : - _theResult___snd__h414888 ; - assign sfdin__h442782 = - _theResult____h434679[56] ? - _theResult___snd__h442799 : - _theResult___snd__h442810 ; - assign sfdin__h460548 = - _theResult____h452316[56] ? - _theResult___snd__h460565 : - _theResult___snd__h460576 ; - assign sfdin__h508243 = - _theResult____h500013[56] ? - _theResult___snd__h508260 : - _theResult___snd__h508271 ; - assign sfdin__h547044 = - _theResult____h538814[56] ? - _theResult___snd__h547061 : - _theResult___snd__h547072 ; - assign sfdin__h586245 = - _theResult____h578015[56] ? - _theResult___snd__h586262 : - _theResult___snd__h586273 ; - assign shiftData__h180513 = - coreFix_memExe_regToExeQ$first[75:12] << x__h180645 ; - assign sie_csr__read__h606408 = - { r1__read__h609236, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h606781 = - { r1__read__h609790, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h678434 = specTagManager$currentSpecBits | y__h678447 ; - assign sstatus_csr__read__h606339 = { r1__read__h608832, csrf_ie_vec_0 } ; - assign stvec_csr__read__h606451 = - { r1__read__h609766, csrf_stvec_mode_low_reg } ; + assign sfdin__h351407 = + _theResult____h343302[56] ? + _theResult___snd__h351424 : + _theResult___snd__h351435 ; + assign sfdin__h369173 = + _theResult____h360941[56] ? + _theResult___snd__h369190 : + _theResult___snd__h369201 ; + assign sfdin__h397097 = + _theResult____h388994[56] ? + _theResult___snd__h397114 : + _theResult___snd__h397125 ; + assign sfdin__h414863 = + _theResult____h406631[56] ? + _theResult___snd__h414880 : + _theResult___snd__h414891 ; + assign sfdin__h442785 = + _theResult____h434682[56] ? + _theResult___snd__h442802 : + _theResult___snd__h442813 ; + assign sfdin__h460551 = + _theResult____h452319[56] ? + _theResult___snd__h460568 : + _theResult___snd__h460579 ; + assign sfdin__h508247 = + _theResult____h500017[56] ? + _theResult___snd__h508264 : + _theResult___snd__h508275 ; + assign sfdin__h547048 = + _theResult____h538818[56] ? + _theResult___snd__h547065 : + _theResult___snd__h547076 ; + assign sfdin__h586249 = + _theResult____h578019[56] ? + _theResult___snd__h586266 : + _theResult___snd__h586277 ; + assign shiftData__h180516 = + coreFix_memExe_regToExeQ$first[75:12] << x__h180648 ; + assign sie_csr__read__h606413 = + { r1__read__h609241, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h606786 = + { r1__read__h609795, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h678443 = specTagManager$currentSpecBits | y__h678456 ; + assign sstatus_csr__read__h606344 = { r1__read__h608837, csrf_ie_vec_0 } ; + assign stvec_csr__read__h606456 = + { r1__read__h609771, csrf_stvec_mode_low_reg } ; assign upd__h3639 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; assign upd__h4956 = n__read__h6134 + 64'd1 ; - assign v__h293161 = + assign v__h293163 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h293392 : + v__h293394 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h293392 = + assign v__h293394 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h296506 = + assign v__h296508 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297024 : + v__h297026 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297024 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307020 = + assign v__h297026 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h307022 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307251 : + v__h307253 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307251 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h310896 = + assign v__h307253 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h310898 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311127 : + v__h311129 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311127 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h325497 = + assign v__h311129 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h325499 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h325728 : + v__h325730 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h325728 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h328722 = + assign v__h325730 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h328724 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h328953 : + v__h328955 : coreFix_memExe_forwardQ_enqP ; - assign v__h328953 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h600770 = + assign v__h328955 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h600774 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h600780 : + v__h600784 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h600780 = + assign v__h600784 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h601415 = v__h600770 - 2'd1 ; - assign v__h604750 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605655 ; - assign v__h628436 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629189 ; - assign vaddr__h180508 = + assign v__h601419 = v__h600774 - 2'd1 ; + assign v__h604754 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605660 ; + assign v__h628444 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629197 ; + assign vaddr__h180511 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ; - assign value__h343921 = + assign value__h343924 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h389611 = + assign value__h389614 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435299 = + assign value__h435302 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484229 = + assign value__h484233 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ; - assign value__h523030 = + assign value__h523034 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ; - assign value__h562231 = + assign value__h562235 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ; - assign vm_mode_reg__read__h610026 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h641091 = + assign vm_mode_reg__read__h610031 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h641100 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h641147 : + result__h641156 : 12'd4095 ; - assign x__h152883 = + assign x__h152884 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h152889 = + assign x__h152890 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h156430 = { 3'd0, sbIdx__h156309 } ; - assign x__h156436 = + assign x__h156431 = { 3'd0, sbIdx__h156310 } ; + assign x__h156437 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h159246 = + assign x__h159247 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h159250 = + assign x__h159251 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161098 = + assign x__h161099 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : @@ -29298,130 +29298,130 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h180422 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179510 ; - assign x__h180423 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180116 ; - assign x__h180645 = { vaddr__h180508[2:0], 3'b0 } ; - assign x__h190899 = + assign x__h180425 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179513 ; + assign x__h180426 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180119 ; + assign x__h180648 = { vaddr__h180511[2:0], 3'b0 } ; + assign x__h190902 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190136[63:32] : - curData__h190136[31:0] ; + curData__h190139[63:32] : + curData__h190139[31:0] ; assign x__h20210 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h284498 = + assign x__h284501 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h284510 = + assign x__h284513 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h286364 = + assign x__h286367 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h299371 = + assign x__h299373 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335098 = - { (_theResult___exp__h378430 != 8'd255 || - _theResult___sfd__h378431 == 23'd0) && + assign x__h335101 = + { (_theResult___exp__h378433 != 8'd255 || + _theResult___sfd__h378434 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h378707, - out_f_sfd__h378708 } ; - assign x__h361648 = - sfd__h335694 << (x__h361681[11] ? 12'hAAA : x__h361681) ; - assign x__h361681 = + out_f_exp__h378710, + out_f_sfd__h378711 } ; + assign x__h361651 = + sfd__h335697 << (x__h361684[11] ? 12'hAAA : x__h361684) ; + assign x__h361684 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h380793 = - { (_theResult___exp__h424120 != 8'd255 || - _theResult___sfd__h424121 == 23'd0) && + assign x__h380796 = + { (_theResult___exp__h424123 != 8'd255 || + _theResult___sfd__h424124 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h424397, - out_f_sfd__h424398 } ; - assign x__h407338 = - sfd__h381389 << (x__h407371[11] ? 12'hAAA : x__h407371) ; - assign x__h407371 = + out_f_exp__h424400, + out_f_sfd__h424401 } ; + assign x__h407341 = + sfd__h381392 << (x__h407374[11] ? 12'hAAA : x__h407374) ; + assign x__h407374 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h426481 = - { (_theResult___exp__h469808 != 8'd255 || - _theResult___sfd__h469809 == 23'd0) && + assign x__h426484 = + { (_theResult___exp__h469811 != 8'd255 || + _theResult___sfd__h469812 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470085, - out_f_sfd__h470086 } ; - assign x__h453026 = - sfd__h427077 << (x__h453059[11] ? 12'hAAA : x__h453059) ; - assign x__h453059 = + out_f_exp__h470088, + out_f_sfd__h470089 } ; + assign x__h453029 = + sfd__h427080 << (x__h453062[11] ? 12'hAAA : x__h453062) ; + assign x__h453062 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; assign x__h45579 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h478866 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476002 ; - assign x__h478867 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476610 ; - assign x__h478868 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477212 ; + assign x__h478870 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476006 ; + assign x__h478871 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476614 ; + assign x__h478872 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477216 ; assign x__h48115 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h500721 = sfd__h479671 << x__h500754 ; - assign x__h500754 = + assign x__h500725 = sfd__h479675 << x__h500758 ; + assign x__h500758 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; - assign x__h539522 = sfd__h518613 << x__h539555 ; - assign x__h539555 = + assign x__h539526 = sfd__h518617 << x__h539559 ; + assign x__h539559 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; - assign x__h578723 = sfd__h557814 << x__h578756 ; - assign x__h578756 = + assign x__h578727 = sfd__h557818 << x__h578760 ; + assign x__h578760 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; - assign x__h600271 = a__h599835[63] ^ b__h599836[63] ; - assign x__h608817 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h613028 = + assign x__h600275 = a__h599839[63] ^ b__h599840[63] ; + assign x__h608822 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h613033 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h605865 : - v__h604750 ; - assign x__h613029 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610917 ; - assign x__h634247 = + rVal1__h605870 : + v__h604754 ; + assign x__h613034 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610922 ; + assign x__h634256 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h629397 : - v__h628436 ; - assign x__h634248 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632146 ; - assign x__h641095 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h641146 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h688716 = + rVal1__h629405 : + v__h628444 ; + assign x__h634257 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632155 ; + assign x__h641104 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h641155 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h688725 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h694797 = { cause_code__h692180, 2'b0 } ; - assign x__h702593 = { 1'b0, csrf_spp_reg } ; - assign x__h705866 = + assign x__h694806 = { cause_code__h692189, 2'b0 } ; + assign x__h702602 = { 1'b0, csrf_spp_reg } ; + assign x__h705875 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_fst__h705688 : + y_avValue_snd_snd_snd_fst__h705697 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 ; assign x__h75524 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311294 = + assign x_addr__h311296 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; @@ -29429,29 +29429,29 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h667940 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h682683 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h649128 = csrf_frm_reg ; - assign x_quotient__h472392 = + assign x_data_imm__h667949 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h682692 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h649137 = csrf_frm_reg ; + assign x_quotient__h472395 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473077 : + q___1__h473080 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h606248 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h472393 = + assign x_reg_ifc__read__h606253 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h472396 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473103 : + r___1__h473106 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252023 = + assign y__h252026 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h641125 = ~x__h641095 ; - assign y__h645898 = + assign y__h641134 = ~x__h641104 ; + assign y__h645907 = { 3'd7, ~csrf_mideleg_11_reg, 1'd1, @@ -29460,71 +29460,71 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h678447 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h705641 = + assign y__h678456 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h705650 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_snd_snd__h705694 : + y_avValue_snd_snd_snd_snd_snd__h705703 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 ; - assign y_avValue__h179510 = + assign y_avValue__h179513 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180116 = + assign y_avValue__h180119 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476002 = + assign y_avValue__h476006 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h476610 = + assign y_avValue__h476614 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477212 = + assign y_avValue__h477216 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h605655 = + assign y_avValue__h605660 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708 ; - assign y_avValue__h610917 = + assign y_avValue__h610922 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720 ; - assign y_avValue__h629189 = + assign y_avValue__h629197 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317 ; - assign y_avValue__h632146 = + assign y_avValue__h632155 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329 ; - assign y_avValue__h693058 = + assign y_avValue__h693067 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694782 + { 58'd0, x__h694797 } : - base__h694782 ; - assign y_avValue__h694819 = + base__h694791 + { 58'd0, x__h694806 } : + base__h694791 ; + assign y_avValue__h694828 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694985 + { 58'd0, x__h694797 } : - base__h694985 ; - assign y_avValue_fst__h671831 = + base__h694994 + { 58'd0, x__h694806 } : + base__h694994 ; + assign y_avValue_fst__h671840 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h678434 : + spec_bits__h678443 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672105 = + assign y_avValue_snd_fst__h672114 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207) ? - y_avValue_snd_fst__h672140 : + y_avValue_snd_fst__h672149 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672140 = + assign y_avValue_snd_fst__h672149 = IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ? - y_avValue_fst__h671831 : + y_avValue_fst__h671840 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h705125 = + assign y_avValue_snd_fst__h705134 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29538,7 +29538,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h705678 = + assign y_avValue_snd_fst__h705687 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29551,11 +29551,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 : - y_avValue_snd_fst__h705707 ; - assign y_avValue_snd_fst__h705707 = + y_avValue_snd_fst__h705716 ; + assign y_avValue_snd_fst__h705716 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_snd_snd_fst__h705135 = + assign y_avValue_snd_snd_snd_fst__h705144 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29569,7 +29569,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h705688 = + assign y_avValue_snd_snd_snd_fst__h705697 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29582,11 +29582,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 : - y_avValue_snd_snd_snd_fst__h705717 ; - assign y_avValue_snd_snd_snd_fst__h705717 = + y_avValue_snd_snd_snd_fst__h705726 ; + assign y_avValue_snd_snd_snd_fst__h705726 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705141 = + assign y_avValue_snd_snd_snd_snd_snd__h705150 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29600,7 +29600,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705694 = + assign y_avValue_snd_snd_snd_snd_snd__h705703 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29613,8 +29613,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 : - y_avValue_snd_snd_snd_snd_snd__h705723 ; - assign y_avValue_snd_snd_snd_snd_snd__h705723 = + y_avValue_snd_snd_snd_snd_snd__h705732 ; + assign y_avValue_snd_snd_snd_snd_snd__h705732 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -29633,28 +29633,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -29670,28 +29670,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -29701,10 +29701,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287286 = + addr__h287289 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h287286 = + addr__h287289 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -29713,36 +29713,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h693211 = commitStage_commitTrap[132:69]; - default: trap_val__h693211 = + 4'd0, 4'd3: trap_val__h693220 = commitStage_commitTrap[132:69]; + default: trap_val__h693220 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -29757,247 +29757,247 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h288835 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h288835 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h606118 or - frm_csr__read__h606129 or - fcsr_csr__read__h606143 or - sstatus_csr__read__h606339 or - sie_csr__read__h606408 or - stvec_csr__read__h606451 or - scounteren_csr__read__h606504 or + fflags_csr__read__h606123 or + frm_csr__read__h606134 or + fcsr_csr__read__h606148 or + sstatus_csr__read__h606344 or + sie_csr__read__h606413 or + stvec_csr__read__h606456 or + scounteren_csr__read__h606509 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606642 or + scause_csr__read__h606647 or csrf_stval_csr or - sip_csr__read__h606781 or - satp_csr__read__h606844 or - mstatus_csr__read__h606987 or - medeleg_csr__read__h607135 or - mideleg_csr__read__h607230 or - mie_csr__read__h607361 or - mtvec_csr__read__h607443 or - mcounteren_csr__read__h607535 or + sip_csr__read__h606786 or + satp_csr__read__h606849 or + mstatus_csr__read__h606992 or + medeleg_csr__read__h607140 or + mideleg_csr__read__h607235 or + mie_csr__read__h607366 or + mtvec_csr__read__h607448 or + mcounteren_csr__read__h607540 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607790 or + mcause_csr__read__h607795 or csrf_mtval_csr or - mip_csr__read__h608030 or - x_reg_ifc__read__h606248 or - n__read__h608134 or n__read__h608325 or csrf_time_reg) + mip_csr__read__h608035 or + x_reg_ifc__read__h606253 or + n__read__h608139 or n__read__h608330 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h605865 = fflags_csr__read__h606118; - 12'd2: rVal1__h605865 = frm_csr__read__h606129; - 12'd3: rVal1__h605865 = fcsr_csr__read__h606143; - 12'd256: rVal1__h605865 = sstatus_csr__read__h606339; - 12'd260: rVal1__h605865 = sie_csr__read__h606408; - 12'd261: rVal1__h605865 = stvec_csr__read__h606451; - 12'd262: rVal1__h605865 = scounteren_csr__read__h606504; - 12'd320: rVal1__h605865 = csrf_sscratch_csr; - 12'd321: rVal1__h605865 = csrf_sepc_csr; - 12'd322: rVal1__h605865 = scause_csr__read__h606642; - 12'd323: rVal1__h605865 = csrf_stval_csr; - 12'd324: rVal1__h605865 = sip_csr__read__h606781; - 12'd384: rVal1__h605865 = satp_csr__read__h606844; - 12'd768: rVal1__h605865 = mstatus_csr__read__h606987; - 12'd769: rVal1__h605865 = 64'h8000000000141129; - 12'd770: rVal1__h605865 = medeleg_csr__read__h607135; - 12'd771: rVal1__h605865 = mideleg_csr__read__h607230; - 12'd772: rVal1__h605865 = mie_csr__read__h607361; - 12'd773: rVal1__h605865 = mtvec_csr__read__h607443; - 12'd774: rVal1__h605865 = mcounteren_csr__read__h607535; - 12'd832: rVal1__h605865 = csrf_mscratch_csr; - 12'd833: rVal1__h605865 = csrf_mepc_csr; - 12'd834: rVal1__h605865 = mcause_csr__read__h607790; - 12'd835: rVal1__h605865 = csrf_mtval_csr; - 12'd836: rVal1__h605865 = mip_csr__read__h608030; - 12'd2048: rVal1__h605865 = 64'd0; - 12'd2049: rVal1__h605865 = x_reg_ifc__read__h606248; - 12'd2816, 12'd3072: rVal1__h605865 = n__read__h608134; - 12'd2818, 12'd3074: rVal1__h605865 = n__read__h608325; - 12'd3073: rVal1__h605865 = csrf_time_reg; - default: rVal1__h605865 = 64'd0; + 12'd1: rVal1__h605870 = fflags_csr__read__h606123; + 12'd2: rVal1__h605870 = frm_csr__read__h606134; + 12'd3: rVal1__h605870 = fcsr_csr__read__h606148; + 12'd256: rVal1__h605870 = sstatus_csr__read__h606344; + 12'd260: rVal1__h605870 = sie_csr__read__h606413; + 12'd261: rVal1__h605870 = stvec_csr__read__h606456; + 12'd262: rVal1__h605870 = scounteren_csr__read__h606509; + 12'd320: rVal1__h605870 = csrf_sscratch_csr; + 12'd321: rVal1__h605870 = csrf_sepc_csr; + 12'd322: rVal1__h605870 = scause_csr__read__h606647; + 12'd323: rVal1__h605870 = csrf_stval_csr; + 12'd324: rVal1__h605870 = sip_csr__read__h606786; + 12'd384: rVal1__h605870 = satp_csr__read__h606849; + 12'd768: rVal1__h605870 = mstatus_csr__read__h606992; + 12'd769: rVal1__h605870 = 64'h8000000000141129; + 12'd770: rVal1__h605870 = medeleg_csr__read__h607140; + 12'd771: rVal1__h605870 = mideleg_csr__read__h607235; + 12'd772: rVal1__h605870 = mie_csr__read__h607366; + 12'd773: rVal1__h605870 = mtvec_csr__read__h607448; + 12'd774: rVal1__h605870 = mcounteren_csr__read__h607540; + 12'd832: rVal1__h605870 = csrf_mscratch_csr; + 12'd833: rVal1__h605870 = csrf_mepc_csr; + 12'd834: rVal1__h605870 = mcause_csr__read__h607795; + 12'd835: rVal1__h605870 = csrf_mtval_csr; + 12'd836: rVal1__h605870 = mip_csr__read__h608035; + 12'd2048: rVal1__h605870 = 64'd0; + 12'd2049: rVal1__h605870 = x_reg_ifc__read__h606253; + 12'd2816, 12'd3072: rVal1__h605870 = n__read__h608139; + 12'd2818, 12'd3074: rVal1__h605870 = n__read__h608330; + 12'd3073: rVal1__h605870 = csrf_time_reg; + default: rVal1__h605870 = 64'd0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h606118 or - frm_csr__read__h606129 or - fcsr_csr__read__h606143 or - sstatus_csr__read__h606339 or - sie_csr__read__h606408 or - stvec_csr__read__h606451 or - scounteren_csr__read__h606504 or + fflags_csr__read__h606123 or + frm_csr__read__h606134 or + fcsr_csr__read__h606148 or + sstatus_csr__read__h606344 or + sie_csr__read__h606413 or + stvec_csr__read__h606456 or + scounteren_csr__read__h606509 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606642 or + scause_csr__read__h606647 or csrf_stval_csr or - sip_csr__read__h606781 or - satp_csr__read__h606844 or - mstatus_csr__read__h606987 or - medeleg_csr__read__h607135 or - mideleg_csr__read__h607230 or - mie_csr__read__h607361 or - mtvec_csr__read__h607443 or - mcounteren_csr__read__h607535 or + sip_csr__read__h606786 or + satp_csr__read__h606849 or + mstatus_csr__read__h606992 or + medeleg_csr__read__h607140 or + mideleg_csr__read__h607235 or + mie_csr__read__h607366 or + mtvec_csr__read__h607448 or + mcounteren_csr__read__h607540 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607790 or + mcause_csr__read__h607795 or csrf_mtval_csr or - mip_csr__read__h608030 or - x_reg_ifc__read__h606248 or - n__read__h608134 or n__read__h608325 or csrf_time_reg) + mip_csr__read__h608035 or + x_reg_ifc__read__h606253 or + n__read__h608139 or n__read__h608330 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h629397 = fflags_csr__read__h606118; - 12'd2: rVal1__h629397 = frm_csr__read__h606129; - 12'd3: rVal1__h629397 = fcsr_csr__read__h606143; - 12'd256: rVal1__h629397 = sstatus_csr__read__h606339; - 12'd260: rVal1__h629397 = sie_csr__read__h606408; - 12'd261: rVal1__h629397 = stvec_csr__read__h606451; - 12'd262: rVal1__h629397 = scounteren_csr__read__h606504; - 12'd320: rVal1__h629397 = csrf_sscratch_csr; - 12'd321: rVal1__h629397 = csrf_sepc_csr; - 12'd322: rVal1__h629397 = scause_csr__read__h606642; - 12'd323: rVal1__h629397 = csrf_stval_csr; - 12'd324: rVal1__h629397 = sip_csr__read__h606781; - 12'd384: rVal1__h629397 = satp_csr__read__h606844; - 12'd768: rVal1__h629397 = mstatus_csr__read__h606987; - 12'd769: rVal1__h629397 = 64'h8000000000141129; - 12'd770: rVal1__h629397 = medeleg_csr__read__h607135; - 12'd771: rVal1__h629397 = mideleg_csr__read__h607230; - 12'd772: rVal1__h629397 = mie_csr__read__h607361; - 12'd773: rVal1__h629397 = mtvec_csr__read__h607443; - 12'd774: rVal1__h629397 = mcounteren_csr__read__h607535; - 12'd832: rVal1__h629397 = csrf_mscratch_csr; - 12'd833: rVal1__h629397 = csrf_mepc_csr; - 12'd834: rVal1__h629397 = mcause_csr__read__h607790; - 12'd835: rVal1__h629397 = csrf_mtval_csr; - 12'd836: rVal1__h629397 = mip_csr__read__h608030; - 12'd2048: rVal1__h629397 = 64'd0; - 12'd2049: rVal1__h629397 = x_reg_ifc__read__h606248; - 12'd2816, 12'd3072: rVal1__h629397 = n__read__h608134; - 12'd2818, 12'd3074: rVal1__h629397 = n__read__h608325; - 12'd3073: rVal1__h629397 = csrf_time_reg; - default: rVal1__h629397 = 64'd0; + 12'd1: rVal1__h629405 = fflags_csr__read__h606123; + 12'd2: rVal1__h629405 = frm_csr__read__h606134; + 12'd3: rVal1__h629405 = fcsr_csr__read__h606148; + 12'd256: rVal1__h629405 = sstatus_csr__read__h606344; + 12'd260: rVal1__h629405 = sie_csr__read__h606413; + 12'd261: rVal1__h629405 = stvec_csr__read__h606456; + 12'd262: rVal1__h629405 = scounteren_csr__read__h606509; + 12'd320: rVal1__h629405 = csrf_sscratch_csr; + 12'd321: rVal1__h629405 = csrf_sepc_csr; + 12'd322: rVal1__h629405 = scause_csr__read__h606647; + 12'd323: rVal1__h629405 = csrf_stval_csr; + 12'd324: rVal1__h629405 = sip_csr__read__h606786; + 12'd384: rVal1__h629405 = satp_csr__read__h606849; + 12'd768: rVal1__h629405 = mstatus_csr__read__h606992; + 12'd769: rVal1__h629405 = 64'h8000000000141129; + 12'd770: rVal1__h629405 = medeleg_csr__read__h607140; + 12'd771: rVal1__h629405 = mideleg_csr__read__h607235; + 12'd772: rVal1__h629405 = mie_csr__read__h607366; + 12'd773: rVal1__h629405 = mtvec_csr__read__h607448; + 12'd774: rVal1__h629405 = mcounteren_csr__read__h607540; + 12'd832: rVal1__h629405 = csrf_mscratch_csr; + 12'd833: rVal1__h629405 = csrf_mepc_csr; + 12'd834: rVal1__h629405 = mcause_csr__read__h607795; + 12'd835: rVal1__h629405 = csrf_mtval_csr; + 12'd836: rVal1__h629405 = mip_csr__read__h608035; + 12'd2048: rVal1__h629405 = 64'd0; + 12'd2049: rVal1__h629405 = x_reg_ifc__read__h606253; + 12'd2816, 12'd3072: rVal1__h629405 = n__read__h608139; + 12'd2818, 12'd3074: rVal1__h629405 = n__read__h608330; + 12'd3073: rVal1__h629405 = csrf_time_reg; + default: rVal1__h629405 = 64'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h388973 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h388976 = 8'd255; 3'd2: - _theResult___fst_exp__h388973 = + _theResult___fst_exp__h388976 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h388973 = + _theResult___fst_exp__h388976 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h388973 = 8'd254; - default: _theResult___fst_exp__h388973 = 8'd0; + 3'd4: _theResult___fst_exp__h388976 = 8'd254; + default: _theResult___fst_exp__h388976 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343281 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h343284 = 8'd255; 3'd2: - _theResult___fst_exp__h343281 = + _theResult___fst_exp__h343284 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h343281 = + _theResult___fst_exp__h343284 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h343281 = 8'd254; - default: _theResult___fst_exp__h343281 = 8'd0; + 3'd4: _theResult___fst_exp__h343284 = 8'd254; + default: _theResult___fst_exp__h343284 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343282 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h343285 = 23'd0; 3'd2: - _theResult___fst_sfd__h343282 = + _theResult___fst_sfd__h343285 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h343282 = + _theResult___fst_sfd__h343285 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h343282 = 23'd8388607; - default: _theResult___fst_sfd__h343282 = 23'd0; + 3'd4: _theResult___fst_sfd__h343285 = 23'd8388607; + default: _theResult___fst_sfd__h343285 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h388974 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h388977 = 23'd0; 3'd2: - _theResult___fst_sfd__h388974 = + _theResult___fst_sfd__h388977 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h388974 = + _theResult___fst_sfd__h388977 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h388974 = 23'd8388607; - default: _theResult___fst_sfd__h388974 = 23'd0; + 3'd4: _theResult___fst_sfd__h388977 = 23'd8388607; + default: _theResult___fst_sfd__h388977 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h434661 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h434664 = 8'd255; 3'd2: - _theResult___fst_exp__h434661 = + _theResult___fst_exp__h434664 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h434661 = + _theResult___fst_exp__h434664 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h434661 = 8'd254; - default: _theResult___fst_exp__h434661 = 8'd0; + 3'd4: _theResult___fst_exp__h434664 = 8'd254; + default: _theResult___fst_exp__h434664 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h434662 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h434665 = 23'd0; 3'd2: - _theResult___fst_sfd__h434662 = + _theResult___fst_sfd__h434665 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h434662 = + _theResult___fst_sfd__h434665 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h434662 = 23'd8388607; - default: _theResult___fst_sfd__h434662 = 23'd0; + 3'd4: _theResult___fst_sfd__h434665 = 23'd8388607; + default: _theResult___fst_sfd__h434665 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30124,16 +30124,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h692195 = commitStage_commitTrap[3:0]; - default: i__h692195 = 4'd15; + i__h692204 = commitStage_commitTrap[3:0]; + default: i__h692204 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - i__h692355 = commitStage_commitTrap[3:0]; - default: i__h692355 = 4'd14; + i__h692364 = commitStage_commitTrap[3:0]; + default: i__h692364 = 4'd14; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -30374,446 +30374,446 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352018 or - _theResult___fst_exp__h360066 or - out_exp__h360511 or _theResult___exp__h360508) + always@(guard__h352021 or + _theResult___fst_exp__h360069 or + out_exp__h360514 or _theResult___exp__h360511) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 = - _theResult___fst_exp__h360066; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = + _theResult___fst_exp__h360069; 2'b10: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 = - out_exp__h360511; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = + out_exp__h360514; 2'b11: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 = - _theResult___exp__h360508; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = + _theResult___exp__h360511; endcase end - always@(guard__h352018 or - _theResult___fst_exp__h360066 or _theResult___exp__h360508) + always@(guard__h352021 or + _theResult___fst_exp__h360069 or _theResult___exp__h360511) begin - case (guard__h352018) + case (guard__h352021) 2'b0: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25 = - _theResult___fst_exp__h360066; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = + _theResult___fst_exp__h360069; 2'b01, 2'b10, 2'b11: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25 = - _theResult___exp__h360508; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = + _theResult___exp__h360511; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 or - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25 or + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 or + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360066) + _theResult___fst_exp__h360069) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h360586 = - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24; + _theResult___fst_exp__h360589 = + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24; 3'd1: - _theResult___fst_exp__h360586 = - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25; + _theResult___fst_exp__h360589 = + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25; 3'd2: - _theResult___fst_exp__h360586 = + _theResult___fst_exp__h360589 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; 3'd3: - _theResult___fst_exp__h360586 = + _theResult___fst_exp__h360589 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h360586 = _theResult___fst_exp__h360066; - default: _theResult___fst_exp__h360586 = 8'd0; + 3'd4: _theResult___fst_exp__h360589 = _theResult___fst_exp__h360069; + default: _theResult___fst_exp__h360589 = 8'd0; endcase end - always@(guard__h343309 or - _theResult___fst_exp__h351410 or - out_exp__h351929 or _theResult___exp__h351926) + always@(guard__h343312 or + _theResult___fst_exp__h351413 or + out_exp__h351932 or _theResult___exp__h351929) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 = - _theResult___fst_exp__h351410; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = + _theResult___fst_exp__h351413; 2'b10: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 = - out_exp__h351929; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = + out_exp__h351932; 2'b11: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 = - _theResult___exp__h351926; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = + _theResult___exp__h351929; endcase end - always@(guard__h343309 or - _theResult___fst_exp__h351410 or _theResult___exp__h351926) + always@(guard__h343312 or + _theResult___fst_exp__h351413 or _theResult___exp__h351929) begin - case (guard__h343309) + case (guard__h343312) 2'b0: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27 = - _theResult___fst_exp__h351410; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = + _theResult___fst_exp__h351413; 2'b01, 2'b10, 2'b11: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27 = - _theResult___exp__h351926; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = + _theResult___exp__h351929; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 or - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27 or + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 or + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h351410) + _theResult___fst_exp__h351413) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h352004 = - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26; + _theResult___fst_exp__h352007 = + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26; 3'd1: - _theResult___fst_exp__h352004 = - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27; + _theResult___fst_exp__h352007 = + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27; 3'd2: - _theResult___fst_exp__h352004 = + _theResult___fst_exp__h352007 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; 3'd3: - _theResult___fst_exp__h352004 = + _theResult___fst_exp__h352007 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352004 = _theResult___fst_exp__h351410; - default: _theResult___fst_exp__h352004 = 8'd0; + 3'd4: _theResult___fst_exp__h352007 = _theResult___fst_exp__h351413; + default: _theResult___fst_exp__h352007 = 8'd0; endcase end - always@(guard__h360948 or - _theResult___fst_exp__h369176 or - out_exp__h369695 or _theResult___exp__h369692) + always@(guard__h360951 or + _theResult___fst_exp__h369179 or + out_exp__h369698 or _theResult___exp__h369695) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 = - _theResult___fst_exp__h369176; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = + _theResult___fst_exp__h369179; 2'b10: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 = - out_exp__h369695; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = + out_exp__h369698; 2'b11: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 = - _theResult___exp__h369692; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = + _theResult___exp__h369695; endcase end - always@(guard__h360948 or - _theResult___fst_exp__h369176 or _theResult___exp__h369692) + always@(guard__h360951 or + _theResult___fst_exp__h369179 or _theResult___exp__h369695) begin - case (guard__h360948) + case (guard__h360951) 2'b0: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33 = - _theResult___fst_exp__h369176; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = + _theResult___fst_exp__h369179; 2'b01, 2'b10, 2'b11: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33 = - _theResult___exp__h369692; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = + _theResult___exp__h369695; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 or - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33 or + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 or + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369176) + _theResult___fst_exp__h369179) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h369770 = - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32; + _theResult___fst_exp__h369773 = + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32; 3'd1: - _theResult___fst_exp__h369770 = - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33; + _theResult___fst_exp__h369773 = + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33; 3'd2: - _theResult___fst_exp__h369770 = + _theResult___fst_exp__h369773 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; 3'd3: - _theResult___fst_exp__h369770 = + _theResult___fst_exp__h369773 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h369770 = _theResult___fst_exp__h369176; - default: _theResult___fst_exp__h369770 = 8'd0; + 3'd4: _theResult___fst_exp__h369773 = _theResult___fst_exp__h369179; + default: _theResult___fst_exp__h369773 = 8'd0; endcase end - always@(guard__h369784 or - _theResult___fst_exp__h377861 or - out_exp__h378331 or _theResult___exp__h378328) + always@(guard__h369787 or + _theResult___fst_exp__h377864 or + out_exp__h378334 or _theResult___exp__h378331) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 = - _theResult___fst_exp__h377861; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = + _theResult___fst_exp__h377864; 2'b10: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 = - out_exp__h378331; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = + out_exp__h378334; 2'b11: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 = - _theResult___exp__h378328; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = + _theResult___exp__h378331; endcase end - always@(guard__h369784 or - _theResult___fst_exp__h377861 or _theResult___exp__h378328) + always@(guard__h369787 or + _theResult___fst_exp__h377864 or _theResult___exp__h378331) begin - case (guard__h369784) + case (guard__h369787) 2'b0: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38 = - _theResult___fst_exp__h377861; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = + _theResult___fst_exp__h377864; 2'b01, 2'b10, 2'b11: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38 = - _theResult___exp__h378328; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = + _theResult___exp__h378331; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 or - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38 or + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 or + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h377861) + _theResult___fst_exp__h377864) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h378406 = - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37; + _theResult___fst_exp__h378409 = + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37; 3'd1: - _theResult___fst_exp__h378406 = - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38; + _theResult___fst_exp__h378409 = + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38; 3'd2: - _theResult___fst_exp__h378406 = + _theResult___fst_exp__h378409 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; 3'd3: - _theResult___fst_exp__h378406 = + _theResult___fst_exp__h378409 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h378406 = _theResult___fst_exp__h377861; - default: _theResult___fst_exp__h378406 = 8'd0; + 3'd4: _theResult___fst_exp__h378409 = _theResult___fst_exp__h377864; + default: _theResult___fst_exp__h378409 = 8'd0; endcase end - always@(guard__h352018 or - _theResult___snd__h360017 or - out_sfd__h360512 or _theResult___sfd__h360509) + always@(guard__h352021 or + _theResult___snd__h360020 or + out_sfd__h360515 or _theResult___sfd__h360512) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 = - _theResult___snd__h360017[56:34]; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = + _theResult___snd__h360020[56:34]; 2'b10: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 = - out_sfd__h360512; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = + out_sfd__h360515; 2'b11: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 = - _theResult___sfd__h360509; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = + _theResult___sfd__h360512; endcase end - always@(guard__h352018 or - _theResult___snd__h360017 or _theResult___sfd__h360509) + always@(guard__h352021 or + _theResult___snd__h360020 or _theResult___sfd__h360512) begin - case (guard__h352018) + case (guard__h352021) 2'b0: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40 = - _theResult___snd__h360017[56:34]; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = + _theResult___snd__h360020[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40 = - _theResult___sfd__h360509; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = + _theResult___sfd__h360512; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 or - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40 or + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 or + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360017) + _theResult___snd__h360020) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h360587 = - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39; + _theResult___fst_sfd__h360590 = + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39; 3'd1: - _theResult___fst_sfd__h360587 = - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40; + _theResult___fst_sfd__h360590 = + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40; 3'd2: - _theResult___fst_sfd__h360587 = + _theResult___fst_sfd__h360590 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; 3'd3: - _theResult___fst_sfd__h360587 = + _theResult___fst_sfd__h360590 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h360587 = _theResult___snd__h360017[56:34]; - default: _theResult___fst_sfd__h360587 = 23'd0; + 3'd4: _theResult___fst_sfd__h360590 = _theResult___snd__h360020[56:34]; + default: _theResult___fst_sfd__h360590 = 23'd0; endcase end - always@(guard__h343309 or - sfdin__h351404 or out_sfd__h351930 or _theResult___sfd__h351927) + always@(guard__h343312 or + sfdin__h351407 or out_sfd__h351933 or _theResult___sfd__h351930) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 = - sfdin__h351404[56:34]; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = + sfdin__h351407[56:34]; 2'b10: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 = - out_sfd__h351930; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = + out_sfd__h351933; 2'b11: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h351927; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = + _theResult___sfd__h351930; endcase end - always@(guard__h343309 or sfdin__h351404 or _theResult___sfd__h351927) + always@(guard__h343312 or sfdin__h351407 or _theResult___sfd__h351930) begin - case (guard__h343309) + case (guard__h343312) 2'b0: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42 = - sfdin__h351404[56:34]; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = + sfdin__h351407[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h351927; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h351930; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 or - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42 or + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 or + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h351404) + sfdin__h351407) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h352005 = - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41; + _theResult___fst_sfd__h352008 = + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41; 3'd1: - _theResult___fst_sfd__h352005 = - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h352008 = + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42; 3'd2: - _theResult___fst_sfd__h352005 = + _theResult___fst_sfd__h352008 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; 3'd3: - _theResult___fst_sfd__h352005 = + _theResult___fst_sfd__h352008 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352005 = sfdin__h351404[56:34]; - default: _theResult___fst_sfd__h352005 = 23'd0; + 3'd4: _theResult___fst_sfd__h352008 = sfdin__h351407[56:34]; + default: _theResult___fst_sfd__h352008 = 23'd0; endcase end - always@(guard__h360948 or - sfdin__h369170 or out_sfd__h369696 or _theResult___sfd__h369693) + always@(guard__h360951 or + sfdin__h369173 or out_sfd__h369699 or _theResult___sfd__h369696) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 = - sfdin__h369170[56:34]; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = + sfdin__h369173[56:34]; 2'b10: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 = - out_sfd__h369696; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = + out_sfd__h369699; 2'b11: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h369693; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h369696; endcase end - always@(guard__h360948 or sfdin__h369170 or _theResult___sfd__h369693) + always@(guard__h360951 or sfdin__h369173 or _theResult___sfd__h369696) begin - case (guard__h360948) + case (guard__h360951) 2'b0: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44 = - sfdin__h369170[56:34]; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = + sfdin__h369173[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h369693; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h369696; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 or - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44 or + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 or + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369170) + sfdin__h369173) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h369771 = - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h369774 = + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43; 3'd1: - _theResult___fst_sfd__h369771 = - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h369774 = + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44; 3'd2: - _theResult___fst_sfd__h369771 = + _theResult___fst_sfd__h369774 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; 3'd3: - _theResult___fst_sfd__h369771 = + _theResult___fst_sfd__h369774 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h369771 = sfdin__h369170[56:34]; - default: _theResult___fst_sfd__h369771 = 23'd0; + 3'd4: _theResult___fst_sfd__h369774 = sfdin__h369173[56:34]; + default: _theResult___fst_sfd__h369774 = 23'd0; endcase end - always@(guard__h369784 or - _theResult___snd__h377807 or - out_sfd__h378332 or _theResult___sfd__h378329) + always@(guard__h369787 or + _theResult___snd__h377810 or + out_sfd__h378335 or _theResult___sfd__h378332) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 = - _theResult___snd__h377807[56:34]; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = + _theResult___snd__h377810[56:34]; 2'b10: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 = - out_sfd__h378332; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = + out_sfd__h378335; 2'b11: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 = - _theResult___sfd__h378329; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = + _theResult___sfd__h378332; endcase end - always@(guard__h369784 or - _theResult___snd__h377807 or _theResult___sfd__h378329) + always@(guard__h369787 or + _theResult___snd__h377810 or _theResult___sfd__h378332) begin - case (guard__h369784) + case (guard__h369787) 2'b0: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46 = - _theResult___snd__h377807[56:34]; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = + _theResult___snd__h377810[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46 = - _theResult___sfd__h378329; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = + _theResult___sfd__h378332; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 or - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46 or + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 or + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h377807) + _theResult___snd__h377810) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h378407 = - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45; + _theResult___fst_sfd__h378410 = + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45; 3'd1: - _theResult___fst_sfd__h378407 = - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46; + _theResult___fst_sfd__h378410 = + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46; 3'd2: - _theResult___fst_sfd__h378407 = + _theResult___fst_sfd__h378410 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; 3'd3: - _theResult___fst_sfd__h378407 = + _theResult___fst_sfd__h378410 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h378407 = _theResult___snd__h377807[56:34]; - default: _theResult___fst_sfd__h378407 = 23'd0; + 3'd4: _theResult___fst_sfd__h378410 = _theResult___snd__h377810[56:34]; + default: _theResult___fst_sfd__h378410 = 23'd0; endcase end - always@(guard__h343309 or + always@(guard__h343312 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01, 2'b10: - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = - guard__h343309 == 2'b11 && + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + guard__h343312 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or - guard__h343309) + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or + guard__h343312) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343309 == 2'b0) ? + (guard__h343312 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343309 == 2'b01 || guard__h343309 == 2'b10 || - guard__h343309 == 2'b11) && + (guard__h343312 == 2'b01 || guard__h343312 == 2'b10 || + guard__h343312 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = @@ -30824,34 +30824,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352018 or + always@(guard__h352021 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01, 2'b10: - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h352018 == 2'b11 && + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h352021 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h352018) + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h352021) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352018 == 2'b0) ? + (guard__h352021 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352018 == 2'b01 || guard__h352018 == 2'b10 || - guard__h352018 == 2'b11) && + (guard__h352021 == 2'b01 || guard__h352021 == 2'b10 || + guard__h352021 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = @@ -30862,34 +30862,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h343309 or + always@(guard__h343312 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01, 2'b10: - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h343309 != 2'b11 || + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h343312 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h343309) + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h343312) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343309 == 2'b0) ? + (guard__h343312 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343309 != 2'b01 && guard__h343309 != 2'b10 && - guard__h343309 != 2'b11 || + guard__h343312 != 2'b01 && guard__h343312 != 2'b10 && + guard__h343312 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = @@ -30900,34 +30900,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352018 or + always@(guard__h352021 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01, 2'b10: - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = - guard__h352018 != 2'b11 || + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + guard__h352021 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or - guard__h352018) + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or + guard__h352021) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352018 == 2'b0) ? + (guard__h352021 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352018 != 2'b01 && guard__h352018 != 2'b10 && - guard__h352018 != 2'b11 || + guard__h352021 != 2'b01 && guard__h352021 != 2'b10 && + guard__h352021 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = @@ -30938,34 +30938,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360948 or + always@(guard__h360951 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01, 2'b10: - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = - guard__h360948 == 2'b11 && + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + guard__h360951 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or - guard__h360948) + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or + guard__h360951) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h360948 == 2'b0) ? + (guard__h360951 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h360948 == 2'b01 || guard__h360948 == 2'b10 || - guard__h360948 == 2'b11) && + (guard__h360951 == 2'b01 || guard__h360951 == 2'b10 || + guard__h360951 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = @@ -30976,34 +30976,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369784 or + always@(guard__h369787 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01, 2'b10: - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h369784 == 2'b11 && + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h369787 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h369784) + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h369787) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h369784 == 2'b0) ? + (guard__h369787 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h369784 == 2'b01 || guard__h369784 == 2'b10 || - guard__h369784 == 2'b11) && + (guard__h369787 == 2'b01 || guard__h369787 == 2'b10 || + guard__h369787 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = @@ -31014,34 +31014,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360948 or + always@(guard__h360951 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01, 2'b10: - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h360948 != 2'b11 || + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h360951 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h360948) + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h360951) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h360948 == 2'b0) ? + (guard__h360951 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h360948 != 2'b01 && guard__h360948 != 2'b10 && - guard__h360948 != 2'b11 || + guard__h360951 != 2'b01 && guard__h360951 != 2'b10 && + guard__h360951 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = @@ -31052,34 +31052,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369784 or + always@(guard__h369787 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01, 2'b10: - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = - guard__h369784 != 2'b11 || + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + guard__h369787 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or - guard__h369784) + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or + guard__h369787) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h369784 == 2'b0) ? + (guard__h369787 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h369784 != 2'b01 && guard__h369784 != 2'b10 && - guard__h369784 != 2'b11 || + guard__h369787 != 2'b01 && guard__h369787 != 2'b10 && + guard__h369787 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = @@ -31103,446 +31103,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h397708 or - _theResult___fst_exp__h405756 or - out_exp__h406201 or _theResult___exp__h406198) + always@(guard__h397711 or + _theResult___fst_exp__h405759 or + out_exp__h406204 or _theResult___exp__h406201) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 = - _theResult___fst_exp__h405756; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = + _theResult___fst_exp__h405759; 2'b10: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 = - out_exp__h406201; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = + out_exp__h406204; 2'b11: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 = - _theResult___exp__h406198; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = + _theResult___exp__h406201; endcase end - always@(guard__h397708 or - _theResult___fst_exp__h405756 or _theResult___exp__h406198) + always@(guard__h397711 or + _theResult___fst_exp__h405759 or _theResult___exp__h406201) begin - case (guard__h397708) + case (guard__h397711) 2'b0: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60 = - _theResult___fst_exp__h405756; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = + _theResult___fst_exp__h405759; 2'b01, 2'b10, 2'b11: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60 = - _theResult___exp__h406198; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = + _theResult___exp__h406201; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 or - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60 or + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 or + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h405756) + _theResult___fst_exp__h405759) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406276 = - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59; + _theResult___fst_exp__h406279 = + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59; 3'd1: - _theResult___fst_exp__h406276 = - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60; + _theResult___fst_exp__h406279 = + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60; 3'd2: - _theResult___fst_exp__h406276 = + _theResult___fst_exp__h406279 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; 3'd3: - _theResult___fst_exp__h406276 = + _theResult___fst_exp__h406279 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406276 = _theResult___fst_exp__h405756; - default: _theResult___fst_exp__h406276 = 8'd0; + 3'd4: _theResult___fst_exp__h406279 = _theResult___fst_exp__h405759; + default: _theResult___fst_exp__h406279 = 8'd0; endcase end - always@(guard__h389001 or - _theResult___fst_exp__h397100 or - out_exp__h397619 or _theResult___exp__h397616) + always@(guard__h389004 or + _theResult___fst_exp__h397103 or + out_exp__h397622 or _theResult___exp__h397619) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 = - _theResult___fst_exp__h397100; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = + _theResult___fst_exp__h397103; 2'b10: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 = - out_exp__h397619; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = + out_exp__h397622; 2'b11: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 = - _theResult___exp__h397616; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = + _theResult___exp__h397619; endcase end - always@(guard__h389001 or - _theResult___fst_exp__h397100 or _theResult___exp__h397616) + always@(guard__h389004 or + _theResult___fst_exp__h397103 or _theResult___exp__h397619) begin - case (guard__h389001) + case (guard__h389004) 2'b0: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62 = - _theResult___fst_exp__h397100; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = + _theResult___fst_exp__h397103; 2'b01, 2'b10, 2'b11: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62 = - _theResult___exp__h397616; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = + _theResult___exp__h397619; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 or - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62 or + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 or + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397100) + _theResult___fst_exp__h397103) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h397694 = - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61; + _theResult___fst_exp__h397697 = + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61; 3'd1: - _theResult___fst_exp__h397694 = - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62; + _theResult___fst_exp__h397697 = + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62; 3'd2: - _theResult___fst_exp__h397694 = + _theResult___fst_exp__h397697 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; 3'd3: - _theResult___fst_exp__h397694 = + _theResult___fst_exp__h397697 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h397694 = _theResult___fst_exp__h397100; - default: _theResult___fst_exp__h397694 = 8'd0; + 3'd4: _theResult___fst_exp__h397697 = _theResult___fst_exp__h397103; + default: _theResult___fst_exp__h397697 = 8'd0; endcase end - always@(guard__h406638 or - _theResult___fst_exp__h414866 or - out_exp__h415385 or _theResult___exp__h415382) + always@(guard__h406641 or + _theResult___fst_exp__h414869 or + out_exp__h415388 or _theResult___exp__h415385) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 = - _theResult___fst_exp__h414866; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = + _theResult___fst_exp__h414869; 2'b10: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 = - out_exp__h415385; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = + out_exp__h415388; 2'b11: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 = - _theResult___exp__h415382; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = + _theResult___exp__h415385; endcase end - always@(guard__h406638 or - _theResult___fst_exp__h414866 or _theResult___exp__h415382) + always@(guard__h406641 or + _theResult___fst_exp__h414869 or _theResult___exp__h415385) begin - case (guard__h406638) + case (guard__h406641) 2'b0: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68 = - _theResult___fst_exp__h414866; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = + _theResult___fst_exp__h414869; 2'b01, 2'b10, 2'b11: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68 = - _theResult___exp__h415382; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = + _theResult___exp__h415385; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 or - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68 or + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 or + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h414866) + _theResult___fst_exp__h414869) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h415460 = - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67; + _theResult___fst_exp__h415463 = + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67; 3'd1: - _theResult___fst_exp__h415460 = - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68; + _theResult___fst_exp__h415463 = + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68; 3'd2: - _theResult___fst_exp__h415460 = + _theResult___fst_exp__h415463 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; 3'd3: - _theResult___fst_exp__h415460 = + _theResult___fst_exp__h415463 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h415460 = _theResult___fst_exp__h414866; - default: _theResult___fst_exp__h415460 = 8'd0; + 3'd4: _theResult___fst_exp__h415463 = _theResult___fst_exp__h414869; + default: _theResult___fst_exp__h415463 = 8'd0; endcase end - always@(guard__h415474 or - _theResult___fst_exp__h423551 or - out_exp__h424021 or _theResult___exp__h424018) + always@(guard__h415477 or + _theResult___fst_exp__h423554 or + out_exp__h424024 or _theResult___exp__h424021) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 = - _theResult___fst_exp__h423551; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = + _theResult___fst_exp__h423554; 2'b10: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 = - out_exp__h424021; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = + out_exp__h424024; 2'b11: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 = - _theResult___exp__h424018; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = + _theResult___exp__h424021; endcase end - always@(guard__h415474 or - _theResult___fst_exp__h423551 or _theResult___exp__h424018) + always@(guard__h415477 or + _theResult___fst_exp__h423554 or _theResult___exp__h424021) begin - case (guard__h415474) + case (guard__h415477) 2'b0: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73 = - _theResult___fst_exp__h423551; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = + _theResult___fst_exp__h423554; 2'b01, 2'b10, 2'b11: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73 = - _theResult___exp__h424018; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = + _theResult___exp__h424021; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 or - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73 or + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 or + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h423551) + _theResult___fst_exp__h423554) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424096 = - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72; + _theResult___fst_exp__h424099 = + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72; 3'd1: - _theResult___fst_exp__h424096 = - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73; + _theResult___fst_exp__h424099 = + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73; 3'd2: - _theResult___fst_exp__h424096 = + _theResult___fst_exp__h424099 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; 3'd3: - _theResult___fst_exp__h424096 = + _theResult___fst_exp__h424099 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424096 = _theResult___fst_exp__h423551; - default: _theResult___fst_exp__h424096 = 8'd0; + 3'd4: _theResult___fst_exp__h424099 = _theResult___fst_exp__h423554; + default: _theResult___fst_exp__h424099 = 8'd0; endcase end - always@(guard__h397708 or - _theResult___snd__h405707 or - out_sfd__h406202 or _theResult___sfd__h406199) + always@(guard__h397711 or + _theResult___snd__h405710 or + out_sfd__h406205 or _theResult___sfd__h406202) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 = - _theResult___snd__h405707[56:34]; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = + _theResult___snd__h405710[56:34]; 2'b10: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 = - out_sfd__h406202; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = + out_sfd__h406205; 2'b11: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 = - _theResult___sfd__h406199; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = + _theResult___sfd__h406202; endcase end - always@(guard__h397708 or - _theResult___snd__h405707 or _theResult___sfd__h406199) + always@(guard__h397711 or + _theResult___snd__h405710 or _theResult___sfd__h406202) begin - case (guard__h397708) + case (guard__h397711) 2'b0: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75 = - _theResult___snd__h405707[56:34]; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = + _theResult___snd__h405710[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75 = - _theResult___sfd__h406199; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = + _theResult___sfd__h406202; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 or - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75 or + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 or + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h405707) + _theResult___snd__h405710) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406277 = - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74; + _theResult___fst_sfd__h406280 = + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74; 3'd1: - _theResult___fst_sfd__h406277 = - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75; + _theResult___fst_sfd__h406280 = + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75; 3'd2: - _theResult___fst_sfd__h406277 = + _theResult___fst_sfd__h406280 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; 3'd3: - _theResult___fst_sfd__h406277 = + _theResult___fst_sfd__h406280 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406277 = _theResult___snd__h405707[56:34]; - default: _theResult___fst_sfd__h406277 = 23'd0; + 3'd4: _theResult___fst_sfd__h406280 = _theResult___snd__h405710[56:34]; + default: _theResult___fst_sfd__h406280 = 23'd0; endcase end - always@(guard__h389001 or - sfdin__h397094 or out_sfd__h397620 or _theResult___sfd__h397617) + always@(guard__h389004 or + sfdin__h397097 or out_sfd__h397623 or _theResult___sfd__h397620) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 = - sfdin__h397094[56:34]; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = + sfdin__h397097[56:34]; 2'b10: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 = - out_sfd__h397620; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = + out_sfd__h397623; 2'b11: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h397617; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = + _theResult___sfd__h397620; endcase end - always@(guard__h389001 or sfdin__h397094 or _theResult___sfd__h397617) + always@(guard__h389004 or sfdin__h397097 or _theResult___sfd__h397620) begin - case (guard__h389001) + case (guard__h389004) 2'b0: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77 = - sfdin__h397094[56:34]; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = + sfdin__h397097[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h397617; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h397620; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 or - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77 or + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 or + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397094) + sfdin__h397097) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h397695 = - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76; + _theResult___fst_sfd__h397698 = + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76; 3'd1: - _theResult___fst_sfd__h397695 = - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h397698 = + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77; 3'd2: - _theResult___fst_sfd__h397695 = + _theResult___fst_sfd__h397698 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; 3'd3: - _theResult___fst_sfd__h397695 = + _theResult___fst_sfd__h397698 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h397695 = sfdin__h397094[56:34]; - default: _theResult___fst_sfd__h397695 = 23'd0; + 3'd4: _theResult___fst_sfd__h397698 = sfdin__h397097[56:34]; + default: _theResult___fst_sfd__h397698 = 23'd0; endcase end - always@(guard__h406638 or - sfdin__h414860 or out_sfd__h415386 or _theResult___sfd__h415383) + always@(guard__h406641 or + sfdin__h414863 or out_sfd__h415389 or _theResult___sfd__h415386) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 = - sfdin__h414860[56:34]; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = + sfdin__h414863[56:34]; 2'b10: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 = - out_sfd__h415386; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = + out_sfd__h415389; 2'b11: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h415383; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h415386; endcase end - always@(guard__h406638 or sfdin__h414860 or _theResult___sfd__h415383) + always@(guard__h406641 or sfdin__h414863 or _theResult___sfd__h415386) begin - case (guard__h406638) + case (guard__h406641) 2'b0: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79 = - sfdin__h414860[56:34]; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = + sfdin__h414863[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h415383; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h415386; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 or - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79 or + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 or + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h414860) + sfdin__h414863) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h415461 = - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h415464 = + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78; 3'd1: - _theResult___fst_sfd__h415461 = - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h415464 = + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79; 3'd2: - _theResult___fst_sfd__h415461 = + _theResult___fst_sfd__h415464 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; 3'd3: - _theResult___fst_sfd__h415461 = + _theResult___fst_sfd__h415464 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h415461 = sfdin__h414860[56:34]; - default: _theResult___fst_sfd__h415461 = 23'd0; + 3'd4: _theResult___fst_sfd__h415464 = sfdin__h414863[56:34]; + default: _theResult___fst_sfd__h415464 = 23'd0; endcase end - always@(guard__h415474 or - _theResult___snd__h423497 or - out_sfd__h424022 or _theResult___sfd__h424019) + always@(guard__h415477 or + _theResult___snd__h423500 or + out_sfd__h424025 or _theResult___sfd__h424022) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 = - _theResult___snd__h423497[56:34]; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = + _theResult___snd__h423500[56:34]; 2'b10: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 = - out_sfd__h424022; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = + out_sfd__h424025; 2'b11: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 = - _theResult___sfd__h424019; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = + _theResult___sfd__h424022; endcase end - always@(guard__h415474 or - _theResult___snd__h423497 or _theResult___sfd__h424019) + always@(guard__h415477 or + _theResult___snd__h423500 or _theResult___sfd__h424022) begin - case (guard__h415474) + case (guard__h415477) 2'b0: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81 = - _theResult___snd__h423497[56:34]; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = + _theResult___snd__h423500[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81 = - _theResult___sfd__h424019; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = + _theResult___sfd__h424022; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 or - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81 or + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 or + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h423497) + _theResult___snd__h423500) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424097 = - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80; + _theResult___fst_sfd__h424100 = + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80; 3'd1: - _theResult___fst_sfd__h424097 = - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81; + _theResult___fst_sfd__h424100 = + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81; 3'd2: - _theResult___fst_sfd__h424097 = + _theResult___fst_sfd__h424100 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; 3'd3: - _theResult___fst_sfd__h424097 = + _theResult___fst_sfd__h424100 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424097 = _theResult___snd__h423497[56:34]; - default: _theResult___fst_sfd__h424097 = 23'd0; + 3'd4: _theResult___fst_sfd__h424100 = _theResult___snd__h423500[56:34]; + default: _theResult___fst_sfd__h424100 = 23'd0; endcase end - always@(guard__h389001 or + always@(guard__h389004 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01, 2'b10: - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = - guard__h389001 == 2'b11 && + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + guard__h389004 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or - guard__h389001) + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or + guard__h389004) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389001 == 2'b0) ? + (guard__h389004 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389001 == 2'b01 || guard__h389001 == 2'b10 || - guard__h389001 == 2'b11) && + (guard__h389004 == 2'b01 || guard__h389004 == 2'b10 || + guard__h389004 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = @@ -31553,34 +31553,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h389001 or + always@(guard__h389004 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01, 2'b10: - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = - guard__h389001 != 2'b11 || + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + guard__h389004 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or - guard__h389001) + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or + guard__h389004) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389001 == 2'b0) ? + (guard__h389004 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389001 != 2'b01 && guard__h389001 != 2'b10 && - guard__h389001 != 2'b11 || + guard__h389004 != 2'b01 && guard__h389004 != 2'b10 && + guard__h389004 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = @@ -31591,34 +31591,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397708 or + always@(guard__h397711 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01, 2'b10: - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - guard__h397708 == 2'b11 && + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + guard__h397711 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or - guard__h397708) + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or + guard__h397711) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h397708 == 2'b0) ? + (guard__h397711 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h397708 == 2'b01 || guard__h397708 == 2'b10 || - guard__h397708 == 2'b11) && + (guard__h397711 == 2'b01 || guard__h397711 == 2'b10 || + guard__h397711 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = @@ -31629,34 +31629,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397708 or + always@(guard__h397711 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01, 2'b10: - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = - guard__h397708 != 2'b11 || + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + guard__h397711 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or - guard__h397708) + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or + guard__h397711) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h397708 == 2'b0) ? + (guard__h397711 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h397708 != 2'b01 && guard__h397708 != 2'b10 && - guard__h397708 != 2'b11 || + guard__h397711 != 2'b01 && guard__h397711 != 2'b10 && + guard__h397711 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = @@ -31667,34 +31667,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406638 or + always@(guard__h406641 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01, 2'b10: - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = - guard__h406638 == 2'b11 && + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + guard__h406641 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or - guard__h406638) + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or + guard__h406641) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h406638 == 2'b0) ? + (guard__h406641 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h406638 == 2'b01 || guard__h406638 == 2'b10 || - guard__h406638 == 2'b11) && + (guard__h406641 == 2'b01 || guard__h406641 == 2'b10 || + guard__h406641 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = @@ -31705,34 +31705,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406638 or + always@(guard__h406641 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01, 2'b10: - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = - guard__h406638 != 2'b11 || + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + guard__h406641 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or - guard__h406638) + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or + guard__h406641) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h406638 == 2'b0) ? + (guard__h406641 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h406638 != 2'b01 && guard__h406638 != 2'b10 && - guard__h406638 != 2'b11 || + guard__h406641 != 2'b01 && guard__h406641 != 2'b10 && + guard__h406641 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = @@ -31743,34 +31743,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415474 or + always@(guard__h415477 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01, 2'b10: - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = - guard__h415474 == 2'b11 && + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + guard__h415477 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or - guard__h415474) + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + guard__h415477) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h415474 == 2'b0) ? + (guard__h415477 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h415474 == 2'b01 || guard__h415474 == 2'b10 || - guard__h415474 == 2'b11) && + (guard__h415477 == 2'b01 || guard__h415477 == 2'b10 || + guard__h415477 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = @@ -31781,34 +31781,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415474 or + always@(guard__h415477 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01, 2'b10: - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = - guard__h415474 != 2'b11 || + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + guard__h415477 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or - guard__h415474) + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or + guard__h415477) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h415474 == 2'b0) ? + (guard__h415477 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h415474 != 2'b01 && guard__h415474 != 2'b10 && - guard__h415474 != 2'b11 || + guard__h415477 != 2'b01 && guard__h415477 != 2'b10 && + guard__h415477 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = @@ -31845,446 +31845,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h443396 or - _theResult___fst_exp__h451444 or - out_exp__h451889 or _theResult___exp__h451886) + always@(guard__h443399 or + _theResult___fst_exp__h451447 or + out_exp__h451892 or _theResult___exp__h451889) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 = - _theResult___fst_exp__h451444; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = + _theResult___fst_exp__h451447; 2'b10: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 = - out_exp__h451889; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = + out_exp__h451892; 2'b11: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 = - _theResult___exp__h451886; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = + _theResult___exp__h451889; endcase end - always@(guard__h443396 or - _theResult___fst_exp__h451444 or _theResult___exp__h451886) + always@(guard__h443399 or + _theResult___fst_exp__h451447 or _theResult___exp__h451889) begin - case (guard__h443396) + case (guard__h443399) 2'b0: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95 = - _theResult___fst_exp__h451444; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = + _theResult___fst_exp__h451447; 2'b01, 2'b10, 2'b11: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95 = - _theResult___exp__h451886; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = + _theResult___exp__h451889; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 or - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95 or + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 or + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h451444) + _theResult___fst_exp__h451447) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h451964 = - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94; + _theResult___fst_exp__h451967 = + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94; 3'd1: - _theResult___fst_exp__h451964 = - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95; + _theResult___fst_exp__h451967 = + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95; 3'd2: - _theResult___fst_exp__h451964 = + _theResult___fst_exp__h451967 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; 3'd3: - _theResult___fst_exp__h451964 = + _theResult___fst_exp__h451967 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h451964 = _theResult___fst_exp__h451444; - default: _theResult___fst_exp__h451964 = 8'd0; + 3'd4: _theResult___fst_exp__h451967 = _theResult___fst_exp__h451447; + default: _theResult___fst_exp__h451967 = 8'd0; endcase end - always@(guard__h434689 or - _theResult___fst_exp__h442788 or - out_exp__h443307 or _theResult___exp__h443304) + always@(guard__h434692 or + _theResult___fst_exp__h442791 or + out_exp__h443310 or _theResult___exp__h443307) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 = - _theResult___fst_exp__h442788; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = + _theResult___fst_exp__h442791; 2'b10: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 = - out_exp__h443307; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = + out_exp__h443310; 2'b11: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 = - _theResult___exp__h443304; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = + _theResult___exp__h443307; endcase end - always@(guard__h434689 or - _theResult___fst_exp__h442788 or _theResult___exp__h443304) + always@(guard__h434692 or + _theResult___fst_exp__h442791 or _theResult___exp__h443307) begin - case (guard__h434689) + case (guard__h434692) 2'b0: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97 = - _theResult___fst_exp__h442788; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = + _theResult___fst_exp__h442791; 2'b01, 2'b10, 2'b11: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97 = - _theResult___exp__h443304; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = + _theResult___exp__h443307; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 or - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97 or + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 or + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h442788) + _theResult___fst_exp__h442791) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h443382 = - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96; + _theResult___fst_exp__h443385 = + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96; 3'd1: - _theResult___fst_exp__h443382 = - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97; + _theResult___fst_exp__h443385 = + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97; 3'd2: - _theResult___fst_exp__h443382 = + _theResult___fst_exp__h443385 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; 3'd3: - _theResult___fst_exp__h443382 = + _theResult___fst_exp__h443385 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h443382 = _theResult___fst_exp__h442788; - default: _theResult___fst_exp__h443382 = 8'd0; + 3'd4: _theResult___fst_exp__h443385 = _theResult___fst_exp__h442791; + default: _theResult___fst_exp__h443385 = 8'd0; endcase end - always@(guard__h452326 or - _theResult___fst_exp__h460554 or - out_exp__h461073 or _theResult___exp__h461070) + always@(guard__h452329 or + _theResult___fst_exp__h460557 or + out_exp__h461076 or _theResult___exp__h461073) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 = - _theResult___fst_exp__h460554; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = + _theResult___fst_exp__h460557; 2'b10: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 = - out_exp__h461073; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = + out_exp__h461076; 2'b11: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 = - _theResult___exp__h461070; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = + _theResult___exp__h461073; endcase end - always@(guard__h452326 or - _theResult___fst_exp__h460554 or _theResult___exp__h461070) + always@(guard__h452329 or + _theResult___fst_exp__h460557 or _theResult___exp__h461073) begin - case (guard__h452326) + case (guard__h452329) 2'b0: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103 = - _theResult___fst_exp__h460554; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = + _theResult___fst_exp__h460557; 2'b01, 2'b10, 2'b11: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103 = - _theResult___exp__h461070; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = + _theResult___exp__h461073; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 or - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103 or + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 or + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h460554) + _theResult___fst_exp__h460557) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461148 = - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102; + _theResult___fst_exp__h461151 = + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102; 3'd1: - _theResult___fst_exp__h461148 = - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103; + _theResult___fst_exp__h461151 = + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103; 3'd2: - _theResult___fst_exp__h461148 = + _theResult___fst_exp__h461151 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; 3'd3: - _theResult___fst_exp__h461148 = + _theResult___fst_exp__h461151 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461148 = _theResult___fst_exp__h460554; - default: _theResult___fst_exp__h461148 = 8'd0; + 3'd4: _theResult___fst_exp__h461151 = _theResult___fst_exp__h460557; + default: _theResult___fst_exp__h461151 = 8'd0; endcase end - always@(guard__h461162 or - _theResult___fst_exp__h469239 or - out_exp__h469709 or _theResult___exp__h469706) + always@(guard__h461165 or + _theResult___fst_exp__h469242 or + out_exp__h469712 or _theResult___exp__h469709) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 = - _theResult___fst_exp__h469239; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = + _theResult___fst_exp__h469242; 2'b10: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 = - out_exp__h469709; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = + out_exp__h469712; 2'b11: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 = - _theResult___exp__h469706; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = + _theResult___exp__h469709; endcase end - always@(guard__h461162 or - _theResult___fst_exp__h469239 or _theResult___exp__h469706) + always@(guard__h461165 or + _theResult___fst_exp__h469242 or _theResult___exp__h469709) begin - case (guard__h461162) + case (guard__h461165) 2'b0: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108 = - _theResult___fst_exp__h469239; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = + _theResult___fst_exp__h469242; 2'b01, 2'b10, 2'b11: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108 = - _theResult___exp__h469706; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = + _theResult___exp__h469709; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 or - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108 or + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 or + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469239) + _theResult___fst_exp__h469242) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h469784 = - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107; + _theResult___fst_exp__h469787 = + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107; 3'd1: - _theResult___fst_exp__h469784 = - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108; + _theResult___fst_exp__h469787 = + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108; 3'd2: - _theResult___fst_exp__h469784 = + _theResult___fst_exp__h469787 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; 3'd3: - _theResult___fst_exp__h469784 = + _theResult___fst_exp__h469787 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h469784 = _theResult___fst_exp__h469239; - default: _theResult___fst_exp__h469784 = 8'd0; + 3'd4: _theResult___fst_exp__h469787 = _theResult___fst_exp__h469242; + default: _theResult___fst_exp__h469787 = 8'd0; endcase end - always@(guard__h443396 or - _theResult___snd__h451395 or - out_sfd__h451890 or _theResult___sfd__h451887) + always@(guard__h443399 or + _theResult___snd__h451398 or + out_sfd__h451893 or _theResult___sfd__h451890) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 = - _theResult___snd__h451395[56:34]; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = + _theResult___snd__h451398[56:34]; 2'b10: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 = - out_sfd__h451890; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = + out_sfd__h451893; 2'b11: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 = - _theResult___sfd__h451887; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = + _theResult___sfd__h451890; endcase end - always@(guard__h443396 or - _theResult___snd__h451395 or _theResult___sfd__h451887) + always@(guard__h443399 or + _theResult___snd__h451398 or _theResult___sfd__h451890) begin - case (guard__h443396) + case (guard__h443399) 2'b0: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110 = - _theResult___snd__h451395[56:34]; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = + _theResult___snd__h451398[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110 = - _theResult___sfd__h451887; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = + _theResult___sfd__h451890; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 or - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110 or + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 or + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h451395) + _theResult___snd__h451398) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h451965 = - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109; + _theResult___fst_sfd__h451968 = + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109; 3'd1: - _theResult___fst_sfd__h451965 = - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110; + _theResult___fst_sfd__h451968 = + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110; 3'd2: - _theResult___fst_sfd__h451965 = + _theResult___fst_sfd__h451968 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; 3'd3: - _theResult___fst_sfd__h451965 = + _theResult___fst_sfd__h451968 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h451965 = _theResult___snd__h451395[56:34]; - default: _theResult___fst_sfd__h451965 = 23'd0; + 3'd4: _theResult___fst_sfd__h451968 = _theResult___snd__h451398[56:34]; + default: _theResult___fst_sfd__h451968 = 23'd0; endcase end - always@(guard__h434689 or - sfdin__h442782 or out_sfd__h443308 or _theResult___sfd__h443305) + always@(guard__h434692 or + sfdin__h442785 or out_sfd__h443311 or _theResult___sfd__h443308) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 = - sfdin__h442782[56:34]; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = + sfdin__h442785[56:34]; 2'b10: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 = - out_sfd__h443308; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = + out_sfd__h443311; 2'b11: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 = - _theResult___sfd__h443305; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = + _theResult___sfd__h443308; endcase end - always@(guard__h434689 or sfdin__h442782 or _theResult___sfd__h443305) + always@(guard__h434692 or sfdin__h442785 or _theResult___sfd__h443308) begin - case (guard__h434689) + case (guard__h434692) 2'b0: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112 = - sfdin__h442782[56:34]; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = + sfdin__h442785[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h443305; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h443308; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 or - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112 or + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 or + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h442782) + sfdin__h442785) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h443383 = - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111; + _theResult___fst_sfd__h443386 = + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111; 3'd1: - _theResult___fst_sfd__h443383 = - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h443386 = + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112; 3'd2: - _theResult___fst_sfd__h443383 = + _theResult___fst_sfd__h443386 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; 3'd3: - _theResult___fst_sfd__h443383 = + _theResult___fst_sfd__h443386 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h443383 = sfdin__h442782[56:34]; - default: _theResult___fst_sfd__h443383 = 23'd0; + 3'd4: _theResult___fst_sfd__h443386 = sfdin__h442785[56:34]; + default: _theResult___fst_sfd__h443386 = 23'd0; endcase end - always@(guard__h452326 or - sfdin__h460548 or out_sfd__h461074 or _theResult___sfd__h461071) + always@(guard__h452329 or + sfdin__h460551 or out_sfd__h461077 or _theResult___sfd__h461074) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 = - sfdin__h460548[56:34]; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = + sfdin__h460551[56:34]; 2'b10: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 = - out_sfd__h461074; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = + out_sfd__h461077; 2'b11: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h461071; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h461074; endcase end - always@(guard__h452326 or sfdin__h460548 or _theResult___sfd__h461071) + always@(guard__h452329 or sfdin__h460551 or _theResult___sfd__h461074) begin - case (guard__h452326) + case (guard__h452329) 2'b0: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114 = - sfdin__h460548[56:34]; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = + sfdin__h460551[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h461071; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h461074; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 or - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114 or + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 or + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h460548) + sfdin__h460551) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461149 = - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h461152 = + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113; 3'd1: - _theResult___fst_sfd__h461149 = - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h461152 = + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114; 3'd2: - _theResult___fst_sfd__h461149 = + _theResult___fst_sfd__h461152 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; 3'd3: - _theResult___fst_sfd__h461149 = + _theResult___fst_sfd__h461152 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461149 = sfdin__h460548[56:34]; - default: _theResult___fst_sfd__h461149 = 23'd0; + 3'd4: _theResult___fst_sfd__h461152 = sfdin__h460551[56:34]; + default: _theResult___fst_sfd__h461152 = 23'd0; endcase end - always@(guard__h461162 or - _theResult___snd__h469185 or - out_sfd__h469710 or _theResult___sfd__h469707) + always@(guard__h461165 or + _theResult___snd__h469188 or + out_sfd__h469713 or _theResult___sfd__h469710) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 = - _theResult___snd__h469185[56:34]; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = + _theResult___snd__h469188[56:34]; 2'b10: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 = - out_sfd__h469710; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = + out_sfd__h469713; 2'b11: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 = - _theResult___sfd__h469707; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = + _theResult___sfd__h469710; endcase end - always@(guard__h461162 or - _theResult___snd__h469185 or _theResult___sfd__h469707) + always@(guard__h461165 or + _theResult___snd__h469188 or _theResult___sfd__h469710) begin - case (guard__h461162) + case (guard__h461165) 2'b0: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116 = - _theResult___snd__h469185[56:34]; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = + _theResult___snd__h469188[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116 = - _theResult___sfd__h469707; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = + _theResult___sfd__h469710; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 or - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116 or + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 or + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469185) + _theResult___snd__h469188) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h469785 = - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115; + _theResult___fst_sfd__h469788 = + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115; 3'd1: - _theResult___fst_sfd__h469785 = - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116; + _theResult___fst_sfd__h469788 = + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116; 3'd2: - _theResult___fst_sfd__h469785 = + _theResult___fst_sfd__h469788 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; 3'd3: - _theResult___fst_sfd__h469785 = + _theResult___fst_sfd__h469788 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h469785 = _theResult___snd__h469185[56:34]; - default: _theResult___fst_sfd__h469785 = 23'd0; + 3'd4: _theResult___fst_sfd__h469788 = _theResult___snd__h469188[56:34]; + default: _theResult___fst_sfd__h469788 = 23'd0; endcase end - always@(guard__h434689 or + always@(guard__h434692 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01, 2'b10: - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = - guard__h434689 == 2'b11 && + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + guard__h434692 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or - guard__h434689) + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or + guard__h434692) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h434689 == 2'b0) ? + (guard__h434692 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h434689 == 2'b01 || guard__h434689 == 2'b10 || - guard__h434689 == 2'b11) && + (guard__h434692 == 2'b01 || guard__h434692 == 2'b10 || + guard__h434692 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = @@ -32295,34 +32295,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h434689 or + always@(guard__h434692 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01, 2'b10: - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = - guard__h434689 != 2'b11 || + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h434692 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or - guard__h434689) + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h434692) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h434689 == 2'b0) ? + (guard__h434692 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h434689 != 2'b01 && guard__h434689 != 2'b10 && - guard__h434689 != 2'b11 || + guard__h434692 != 2'b01 && guard__h434692 != 2'b10 && + guard__h434692 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = @@ -32333,34 +32333,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443396 or + always@(guard__h443399 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01, 2'b10: - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = - guard__h443396 == 2'b11 && + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h443399 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or - guard__h443396) + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h443399) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h443396 == 2'b0) ? + (guard__h443399 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h443396 == 2'b01 || guard__h443396 == 2'b10 || - guard__h443396 == 2'b11) && + (guard__h443399 == 2'b01 || guard__h443399 == 2'b10 || + guard__h443399 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = @@ -32371,34 +32371,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443396 or + always@(guard__h443399 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01, 2'b10: - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h443396 != 2'b11 || + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h443399 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h443396) + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h443399) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h443396 == 2'b0) ? + (guard__h443399 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h443396 != 2'b01 && guard__h443396 != 2'b10 && - guard__h443396 != 2'b11 || + guard__h443399 != 2'b01 && guard__h443399 != 2'b10 && + guard__h443399 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = @@ -32409,34 +32409,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452326 or + always@(guard__h452329 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01, 2'b10: - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = - guard__h452326 == 2'b11 && + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + guard__h452329 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or - guard__h452326) + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or + guard__h452329) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h452326 == 2'b0) ? + (guard__h452329 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h452326 == 2'b01 || guard__h452326 == 2'b10 || - guard__h452326 == 2'b11) && + (guard__h452329 == 2'b01 || guard__h452329 == 2'b10 || + guard__h452329 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = @@ -32447,34 +32447,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452326 or + always@(guard__h452329 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01, 2'b10: - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = - guard__h452326 != 2'b11 || + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + guard__h452329 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or - guard__h452326) + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or + guard__h452329) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h452326 == 2'b0) ? + (guard__h452329 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h452326 != 2'b01 && guard__h452326 != 2'b10 && - guard__h452326 != 2'b11 || + guard__h452329 != 2'b01 && guard__h452329 != 2'b10 && + guard__h452329 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = @@ -32485,34 +32485,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461162 or + always@(guard__h461165 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01, 2'b10: - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h461162 == 2'b11 && + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + guard__h461165 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h461162) + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or + guard__h461165) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461162 == 2'b0) ? + (guard__h461165 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461162 == 2'b01 || guard__h461162 == 2'b10 || - guard__h461162 == 2'b11) && + (guard__h461165 == 2'b01 || guard__h461165 == 2'b10 || + guard__h461165 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = @@ -32523,34 +32523,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461162 or + always@(guard__h461165 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01, 2'b10: - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = - guard__h461162 != 2'b11 || + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + guard__h461165 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or - guard__h461162) + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or + guard__h461165) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461162 == 2'b0) ? + (guard__h461165 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461162 != 2'b01 && guard__h461162 != 2'b10 && - guard__h461162 != 2'b11 || + guard__h461165 != 2'b01 && guard__h461165 != 2'b10 && + guard__h461165 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = @@ -32607,28 +32607,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h490711 or - _theResult___fst_exp__h498672 or _theResult___exp__h499327) + always@(guard__h490715 or + _theResult___fst_exp__h498676 or _theResult___exp__h499331) begin - case (guard__h490711) + case (guard__h490715) 2'b0: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135 = - _theResult___fst_exp__h498672; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = + _theResult___fst_exp__h498676; 2'b01, 2'b10, 2'b11: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135 = - _theResult___exp__h499327; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = + _theResult___exp__h499331; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h498672 or + _theResult___fst_exp__h498676 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 or - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135) + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - _theResult___fst_exp__h498672; + _theResult___fst_exp__h498676; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007; @@ -32637,40 +32637,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = 11'd0; endcase end - always@(guard__h490711 or - _theResult___fst_exp__h498672 or - out_exp__h499330 or _theResult___exp__h499327) + always@(guard__h490715 or + _theResult___fst_exp__h498676 or + out_exp__h499334 or _theResult___exp__h499331) begin - case (guard__h490711) + case (guard__h490715) 2'b0, 2'b01: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 = - _theResult___fst_exp__h498672; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = + _theResult___fst_exp__h498676; 2'b10: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 = - out_exp__h499330; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = + out_exp__h499334; 2'b11: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 = - _theResult___exp__h499327; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = + _theResult___exp__h499331; endcase end - always@(guard__h490711 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h490715 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h490711) + case (guard__h490715) 2'b0, 2'b01, 2'b10: - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h490711 == 2'b11 && + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h490715 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490711) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490715) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32678,29 +32678,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h490711 == 2'b0) ? + (guard__h490715 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h490711 == 2'b01 || guard__h490711 == 2'b10 || - guard__h490711 == 2'b11) && + (guard__h490715 == 2'b01 || guard__h490715 == 2'b10 || + guard__h490715 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h500023 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h500027 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h500023) + case (guard__h500027) 2'b0, 2'b01, 2'b10: - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h500023 == 2'b11 && + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h500027 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500023) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500027) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32708,29 +32708,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h500023 == 2'b0) ? + (guard__h500027 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500023 == 2'b01 || guard__h500023 == 2'b10 || - guard__h500023 == 2'b11) && + (guard__h500027 == 2'b01 || guard__h500027 == 2'b10 || + guard__h500027 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h509092 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h509096 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h509092) + case (guard__h509096) 2'b0, 2'b01, 2'b10: - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h509092 == 2'b11 && + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h509096 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509092) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509096) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32738,38 +32738,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h509092 == 2'b0) ? + (guard__h509096 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509092 == 2'b01 || guard__h509092 == 2'b10 || - guard__h509092 == 2'b11) && + (guard__h509096 == 2'b01 || guard__h509096 == 2'b10 || + guard__h509096 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h568713 or - _theResult___fst_exp__h576674 or _theResult___exp__h577329) + always@(guard__h568717 or + _theResult___fst_exp__h576678 or _theResult___exp__h577333) begin - case (guard__h568713) + case (guard__h568717) 2'b0: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152 = - _theResult___fst_exp__h576674; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = + _theResult___fst_exp__h576678; 2'b01, 2'b10, 2'b11: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152 = - _theResult___exp__h577329; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = + _theResult___exp__h577333; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h576674 or + _theResult___fst_exp__h576678 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 or - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152) + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - _theResult___fst_exp__h576674; + _theResult___fst_exp__h576678; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717; @@ -32778,40 +32778,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = 11'd0; endcase end - always@(guard__h568713 or - _theResult___fst_exp__h576674 or - out_exp__h577332 or _theResult___exp__h577329) + always@(guard__h568717 or + _theResult___fst_exp__h576678 or + out_exp__h577336 or _theResult___exp__h577333) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 = - _theResult___fst_exp__h576674; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = + _theResult___fst_exp__h576678; 2'b10: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 = - out_exp__h577332; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = + out_exp__h577336; 2'b11: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 = - _theResult___exp__h577329; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = + _theResult___exp__h577333; endcase end - always@(guard__h568713 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01, 2'b10: - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h568713 == 2'b11 && + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h568717 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568713) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32819,29 +32819,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h568713 == 2'b0) ? + (guard__h568717 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h568713 == 2'b01 || guard__h568713 == 2'b10 || - guard__h568713 == 2'b11) && + (guard__h568717 == 2'b01 || guard__h568717 == 2'b10 || + guard__h568717 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578025 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01, 2'b10: - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h578025 == 2'b11 && + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h578029 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578025) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32849,29 +32849,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h578025 == 2'b0) ? + (guard__h578029 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578025 == 2'b01 || guard__h578025 == 2'b10 || - guard__h578025 == 2'b11) && + (guard__h578029 == 2'b01 || guard__h578029 == 2'b10 || + guard__h578029 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587094 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01, 2'b10: - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h587094 == 2'b11 && + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h587098 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587094) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32879,29 +32879,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h587094 == 2'b0) ? + (guard__h587098 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587094 == 2'b01 || guard__h587094 == 2'b10 || - guard__h587094 == 2'b11) && + (guard__h587098 == 2'b01 || guard__h587098 == 2'b10 || + guard__h587098 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578025 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01, 2'b10: - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h578025 != 2'b11 || + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h578029 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578025) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32909,29 +32909,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h578025 == 2'b0) ? + (guard__h578029 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578025 != 2'b01 && guard__h578025 != 2'b10 && - guard__h578025 != 2'b11 || + guard__h578029 != 2'b01 && guard__h578029 != 2'b10 && + guard__h578029 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587094 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01, 2'b10: - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h587094 != 2'b11 || + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h587098 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587094) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32939,29 +32939,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h587094 == 2'b0) ? + (guard__h587098 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587094 != 2'b01 && guard__h587094 != 2'b10 && - guard__h587094 != 2'b11 || + guard__h587098 != 2'b01 && guard__h587098 != 2'b10 && + guard__h587098 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h568713 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01, 2'b10: - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h568713 != 2'b11 || + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h568717 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568713) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32969,38 +32969,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h568713 == 2'b0) ? + (guard__h568717 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h568713 != 2'b01 && guard__h568713 != 2'b10 && - guard__h568713 != 2'b11 || + guard__h568717 != 2'b01 && guard__h568717 != 2'b10 && + guard__h568717 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h529512 or - _theResult___fst_exp__h537473 or _theResult___exp__h538128) + always@(guard__h529516 or + _theResult___fst_exp__h537477 or _theResult___exp__h538132) begin - case (guard__h529512) + case (guard__h529516) 2'b0: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175 = - _theResult___fst_exp__h537473; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = + _theResult___fst_exp__h537477; 2'b01, 2'b10, 2'b11: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175 = - _theResult___exp__h538128; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = + _theResult___exp__h538132; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h537473 or + _theResult___fst_exp__h537477 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 or - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175) + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - _theResult___fst_exp__h537473; + _theResult___fst_exp__h537477; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480; @@ -33009,49 +33009,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = 11'd0; endcase end - always@(guard__h529512 or - _theResult___fst_exp__h537473 or - out_exp__h538131 or _theResult___exp__h538128) + always@(guard__h529516 or + _theResult___fst_exp__h537477 or + out_exp__h538135 or _theResult___exp__h538132) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 = - _theResult___fst_exp__h537473; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = + _theResult___fst_exp__h537477; 2'b10: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 = - out_exp__h538131; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = + out_exp__h538135; 2'b11: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 = - _theResult___exp__h538128; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = + _theResult___exp__h538132; endcase end - always@(guard__h538824 or - _theResult___fst_exp__h547050 or _theResult___exp__h547779) + always@(guard__h538828 or + _theResult___fst_exp__h547054 or _theResult___exp__h547783) begin - case (guard__h538824) + case (guard__h538828) 2'b0: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177 = - _theResult___fst_exp__h547050; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = + _theResult___fst_exp__h547054; 2'b01, 2'b10, 2'b11: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177 = - _theResult___exp__h547779; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = + _theResult___exp__h547783; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547050 or + _theResult___fst_exp__h547054 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 or - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177) + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - _theResult___fst_exp__h547050; + _theResult___fst_exp__h547054; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518; @@ -33060,49 +33060,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = 11'd0; endcase end - always@(guard__h538824 or - _theResult___fst_exp__h547050 or - out_exp__h547782 or _theResult___exp__h547779) + always@(guard__h538828 or + _theResult___fst_exp__h547054 or + out_exp__h547786 or _theResult___exp__h547783) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 = - _theResult___fst_exp__h547050; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = + _theResult___fst_exp__h547054; 2'b10: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 = - out_exp__h547782; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = + out_exp__h547786; 2'b11: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 = - _theResult___exp__h547779; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = + _theResult___exp__h547783; endcase end - always@(guard__h547893 or - _theResult___fst_exp__h555883 or _theResult___exp__h556563) + always@(guard__h547897 or + _theResult___fst_exp__h555887 or _theResult___exp__h556567) begin - case (guard__h547893) + case (guard__h547897) 2'b0: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179 = - _theResult___fst_exp__h555883; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = + _theResult___fst_exp__h555887; 2'b01, 2'b10, 2'b11: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179 = - _theResult___exp__h556563; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = + _theResult___exp__h556567; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555883 or + _theResult___fst_exp__h555887 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 or - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179) + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - _theResult___fst_exp__h555883; + _theResult___fst_exp__h555887; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549; @@ -33111,49 +33111,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = 11'd0; endcase end - always@(guard__h547893 or - _theResult___fst_exp__h555883 or - out_exp__h556566 or _theResult___exp__h556563) + always@(guard__h547897 or + _theResult___fst_exp__h555887 or + out_exp__h556570 or _theResult___exp__h556567) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 = - _theResult___fst_exp__h555883; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = + _theResult___fst_exp__h555887; 2'b10: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 = - out_exp__h556566; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = + out_exp__h556570; 2'b11: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 = - _theResult___exp__h556563; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = + _theResult___exp__h556567; endcase end - always@(guard__h587094 or - _theResult___fst_exp__h595084 or _theResult___exp__h595764) + always@(guard__h587098 or + _theResult___fst_exp__h595088 or _theResult___exp__h595768) begin - case (guard__h587094) + case (guard__h587098) 2'b0: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181 = - _theResult___fst_exp__h595084; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = + _theResult___fst_exp__h595088; 2'b01, 2'b10, 2'b11: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181 = - _theResult___exp__h595764; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = + _theResult___exp__h595768; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595084 or + _theResult___fst_exp__h595088 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 or - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181) + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - _theResult___fst_exp__h595084; + _theResult___fst_exp__h595088; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786; @@ -33162,49 +33162,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = 11'd0; endcase end - always@(guard__h587094 or - _theResult___fst_exp__h595084 or - out_exp__h595767 or _theResult___exp__h595764) + always@(guard__h587098 or + _theResult___fst_exp__h595088 or + out_exp__h595771 or _theResult___exp__h595768) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 = - _theResult___fst_exp__h595084; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = + _theResult___fst_exp__h595088; 2'b10: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 = - out_exp__h595767; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = + out_exp__h595771; 2'b11: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 = - _theResult___exp__h595764; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = + _theResult___exp__h595768; endcase end - always@(guard__h578025 or - _theResult___fst_exp__h586251 or _theResult___exp__h586980) + always@(guard__h578029 or + _theResult___fst_exp__h586255 or _theResult___exp__h586984) begin - case (guard__h578025) + case (guard__h578029) 2'b0: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183 = - _theResult___fst_exp__h586251; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = + _theResult___fst_exp__h586255; 2'b01, 2'b10, 2'b11: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183 = - _theResult___exp__h586980; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = + _theResult___exp__h586984; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h586251 or + _theResult___fst_exp__h586255 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 or - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183) + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - _theResult___fst_exp__h586251; + _theResult___fst_exp__h586255; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755; @@ -33213,40 +33213,40 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = 11'd0; endcase end - always@(guard__h578025 or - _theResult___fst_exp__h586251 or - out_exp__h586983 or _theResult___exp__h586980) + always@(guard__h578029 or + _theResult___fst_exp__h586255 or + out_exp__h586987 or _theResult___exp__h586984) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 = - _theResult___fst_exp__h586251; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = + _theResult___fst_exp__h586255; 2'b10: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 = - out_exp__h586983; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = + out_exp__h586987; 2'b11: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 = - _theResult___exp__h586980; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = + _theResult___exp__h586984; endcase end - always@(guard__h529512 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01, 2'b10: - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h529512 == 2'b11 && + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h529516 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529512) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33254,29 +33254,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h529512 == 2'b0) ? + (guard__h529516 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h529512 == 2'b01 || guard__h529512 == 2'b10 || - guard__h529512 == 2'b11) && + (guard__h529516 == 2'b01 || guard__h529516 == 2'b10 || + guard__h529516 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538824 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01, 2'b10: - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h538824 == 2'b11 && + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h538828 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538824) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33284,29 +33284,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h538824 == 2'b0) ? + (guard__h538828 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h538824 == 2'b01 || guard__h538824 == 2'b10 || - guard__h538824 == 2'b11) && + (guard__h538828 == 2'b01 || guard__h538828 == 2'b10 || + guard__h538828 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547893 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01, 2'b10: - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h547893 == 2'b11 && + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h547897 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547893) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33314,29 +33314,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h547893 == 2'b0) ? + (guard__h547897 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547893 == 2'b01 || guard__h547893 == 2'b10 || - guard__h547893 == 2'b11) && + (guard__h547897 == 2'b01 || guard__h547897 == 2'b10 || + guard__h547897 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538824 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01, 2'b10: - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h538824 != 2'b11 || + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h538828 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538824) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33344,29 +33344,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h538824 == 2'b0) ? + (guard__h538828 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h538824 != 2'b01 && guard__h538824 != 2'b10 && - guard__h538824 != 2'b11 || + guard__h538828 != 2'b01 && guard__h538828 != 2'b10 && + guard__h538828 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547893 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01, 2'b10: - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h547893 != 2'b11 || + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h547897 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547893) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33374,29 +33374,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h547893 == 2'b0) ? + (guard__h547897 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547893 != 2'b01 && guard__h547893 != 2'b10 && - guard__h547893 != 2'b11 || + guard__h547897 != 2'b01 && guard__h547897 != 2'b10 && + guard__h547897 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529512 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01, 2'b10: - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h529512 != 2'b11 || + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h529516 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529512) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33404,38 +33404,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h529512 == 2'b0) ? + (guard__h529516 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h529512 != 2'b01 && guard__h529512 != 2'b10 && - guard__h529512 != 2'b11 || + guard__h529516 != 2'b01 && guard__h529516 != 2'b10 && + guard__h529516 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529512 or - _theResult___snd__h537424 or _theResult___sfd__h538129) + always@(guard__h529516 or + _theResult___snd__h537428 or _theResult___sfd__h538133) begin - case (guard__h529512) + case (guard__h529516) 2'b0: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197 = - _theResult___snd__h537424[56:5]; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = + _theResult___snd__h537428[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197 = - _theResult___sfd__h538129; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = + _theResult___sfd__h538133; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h537424 or + _theResult___snd__h537428 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 or - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197) + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - _theResult___snd__h537424[56:5]; + _theResult___snd__h537428[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575; @@ -33444,48 +33444,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = 52'd0; endcase end - always@(guard__h529512 or - _theResult___snd__h537424 or - out_sfd__h538132 or _theResult___sfd__h538129) + always@(guard__h529516 or + _theResult___snd__h537428 or + out_sfd__h538136 or _theResult___sfd__h538133) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 = - _theResult___snd__h537424[56:5]; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = + _theResult___snd__h537428[56:5]; 2'b10: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 = - out_sfd__h538132; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = + out_sfd__h538136; 2'b11: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 = - _theResult___sfd__h538129; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = + _theResult___sfd__h538133; endcase end - always@(guard__h538824 or sfdin__h547044 or _theResult___sfd__h547780) + always@(guard__h538828 or sfdin__h547048 or _theResult___sfd__h547784) begin - case (guard__h538824) + case (guard__h538828) 2'b0: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h547044[56:5]; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h547048[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h547780; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h547784; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547044 or + sfdin__h547048 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 or - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199) + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - sfdin__h547044[56:5]; + sfdin__h547048[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601; @@ -33494,48 +33494,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = 52'd0; endcase end - always@(guard__h538824 or - sfdin__h547044 or out_sfd__h547783 or _theResult___sfd__h547780) + always@(guard__h538828 or + sfdin__h547048 or out_sfd__h547787 or _theResult___sfd__h547784) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h547044[56:5]; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h547048[56:5]; 2'b10: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h547783; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h547787; 2'b11: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h547780; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h547784; endcase end - always@(guard__h547893 or - _theResult___snd__h555829 or _theResult___sfd__h556564) + always@(guard__h547897 or + _theResult___snd__h555833 or _theResult___sfd__h556568) begin - case (guard__h547893) + case (guard__h547897) 2'b0: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201 = - _theResult___snd__h555829[56:5]; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = + _theResult___snd__h555833[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201 = - _theResult___sfd__h556564; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = + _theResult___sfd__h556568; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h555829 or + _theResult___snd__h555833 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 or - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201) + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - _theResult___snd__h555829[56:5]; + _theResult___snd__h555833[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620; @@ -33544,49 +33544,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = 52'd0; endcase end - always@(guard__h547893 or - _theResult___snd__h555829 or - out_sfd__h556567 or _theResult___sfd__h556564) + always@(guard__h547897 or + _theResult___snd__h555833 or + out_sfd__h556571 or _theResult___sfd__h556568) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 = - _theResult___snd__h555829[56:5]; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = + _theResult___snd__h555833[56:5]; 2'b10: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 = - out_sfd__h556567; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = + out_sfd__h556571; 2'b11: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 = - _theResult___sfd__h556564; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = + _theResult___sfd__h556568; endcase end - always@(guard__h500023 or - _theResult___fst_exp__h508249 or _theResult___exp__h508978) + always@(guard__h500027 or + _theResult___fst_exp__h508253 or _theResult___exp__h508982) begin - case (guard__h500023) + case (guard__h500027) 2'b0: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203 = - _theResult___fst_exp__h508249; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = + _theResult___fst_exp__h508253; 2'b01, 2'b10, 2'b11: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203 = - _theResult___exp__h508978; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = + _theResult___exp__h508982; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508249 or + _theResult___fst_exp__h508253 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 or - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203) + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - _theResult___fst_exp__h508249; + _theResult___fst_exp__h508253; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050; @@ -33595,49 +33595,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = 11'd0; endcase end - always@(guard__h500023 or - _theResult___fst_exp__h508249 or - out_exp__h508981 or _theResult___exp__h508978) + always@(guard__h500027 or + _theResult___fst_exp__h508253 or + out_exp__h508985 or _theResult___exp__h508982) begin - case (guard__h500023) + case (guard__h500027) 2'b0, 2'b01: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 = - _theResult___fst_exp__h508249; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = + _theResult___fst_exp__h508253; 2'b10: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 = - out_exp__h508981; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = + out_exp__h508985; 2'b11: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 = - _theResult___exp__h508978; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = + _theResult___exp__h508982; endcase end - always@(guard__h509092 or - _theResult___fst_exp__h517082 or _theResult___exp__h517762) + always@(guard__h509096 or + _theResult___fst_exp__h517086 or _theResult___exp__h517766) begin - case (guard__h509092) + case (guard__h509096) 2'b0: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205 = - _theResult___fst_exp__h517082; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = + _theResult___fst_exp__h517086; 2'b01, 2'b10, 2'b11: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205 = - _theResult___exp__h517762; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = + _theResult___exp__h517766; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517082 or + _theResult___fst_exp__h517086 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 or - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205) + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - _theResult___fst_exp__h517082; + _theResult___fst_exp__h517086; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081; @@ -33646,49 +33646,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = 11'd0; endcase end - always@(guard__h509092 or - _theResult___fst_exp__h517082 or - out_exp__h517765 or _theResult___exp__h517762) + always@(guard__h509096 or + _theResult___fst_exp__h517086 or + out_exp__h517769 or _theResult___exp__h517766) begin - case (guard__h509092) + case (guard__h509096) 2'b0, 2'b01: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 = - _theResult___fst_exp__h517082; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = + _theResult___fst_exp__h517086; 2'b10: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 = - out_exp__h517765; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = + out_exp__h517769; 2'b11: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 = - _theResult___exp__h517762; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = + _theResult___exp__h517766; endcase end - always@(guard__h490711 or - _theResult___snd__h498623 or _theResult___sfd__h499328) + always@(guard__h490715 or + _theResult___snd__h498627 or _theResult___sfd__h499332) begin - case (guard__h490711) + case (guard__h490715) 2'b0: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207 = - _theResult___snd__h498623[56:5]; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = + _theResult___snd__h498627[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207 = - _theResult___sfd__h499328; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = + _theResult___sfd__h499332; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h498623 or + _theResult___snd__h498627 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 or - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207) + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - _theResult___snd__h498623[56:5]; + _theResult___snd__h498627[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107; @@ -33697,49 +33697,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = 52'd0; endcase end - always@(guard__h490711 or - _theResult___snd__h498623 or - out_sfd__h499331 or _theResult___sfd__h499328) + always@(guard__h490715 or + _theResult___snd__h498627 or + out_sfd__h499335 or _theResult___sfd__h499332) begin - case (guard__h490711) + case (guard__h490715) 2'b0, 2'b01: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 = - _theResult___snd__h498623[56:5]; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = + _theResult___snd__h498627[56:5]; 2'b10: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 = - out_sfd__h499331; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = + out_sfd__h499335; 2'b11: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 = - _theResult___sfd__h499328; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = + _theResult___sfd__h499332; endcase end - always@(guard__h509092 or - _theResult___snd__h517028 or _theResult___sfd__h517763) + always@(guard__h509096 or + _theResult___snd__h517032 or _theResult___sfd__h517767) begin - case (guard__h509092) + case (guard__h509096) 2'b0: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209 = - _theResult___snd__h517028[56:5]; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = + _theResult___snd__h517032[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209 = - _theResult___sfd__h517763; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = + _theResult___sfd__h517767; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517028 or + _theResult___snd__h517032 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 or - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209) + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - _theResult___snd__h517028[56:5]; + _theResult___snd__h517032[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153; @@ -33748,48 +33748,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = 52'd0; endcase end - always@(guard__h509092 or - _theResult___snd__h517028 or - out_sfd__h517766 or _theResult___sfd__h517763) + always@(guard__h509096 or + _theResult___snd__h517032 or + out_sfd__h517770 or _theResult___sfd__h517767) begin - case (guard__h509092) + case (guard__h509096) 2'b0, 2'b01: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 = - _theResult___snd__h517028[56:5]; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = + _theResult___snd__h517032[56:5]; 2'b10: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 = - out_sfd__h517766; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = + out_sfd__h517770; 2'b11: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 = - _theResult___sfd__h517763; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = + _theResult___sfd__h517767; endcase end - always@(guard__h500023 or sfdin__h508243 or _theResult___sfd__h508979) + always@(guard__h500027 or sfdin__h508247 or _theResult___sfd__h508983) begin - case (guard__h500023) + case (guard__h500027) 2'b0: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211 = - sfdin__h508243[56:5]; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = + sfdin__h508247[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211 = - _theResult___sfd__h508979; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = + _theResult___sfd__h508983; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508243 or + sfdin__h508247 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 or - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211) + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - sfdin__h508243[56:5]; + sfdin__h508247[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134; @@ -33798,48 +33798,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = 52'd0; endcase end - always@(guard__h500023 or - sfdin__h508243 or out_sfd__h508982 or _theResult___sfd__h508979) + always@(guard__h500027 or + sfdin__h508247 or out_sfd__h508986 or _theResult___sfd__h508983) begin - case (guard__h500023) + case (guard__h500027) 2'b0, 2'b01: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 = - sfdin__h508243[56:5]; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = + sfdin__h508247[56:5]; 2'b10: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 = - out_sfd__h508982; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = + out_sfd__h508986; 2'b11: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 = - _theResult___sfd__h508979; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = + _theResult___sfd__h508983; endcase end - always@(guard__h568713 or - _theResult___snd__h576625 or _theResult___sfd__h577330) + always@(guard__h568717 or + _theResult___snd__h576629 or _theResult___sfd__h577334) begin - case (guard__h568713) + case (guard__h568717) 2'b0: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213 = - _theResult___snd__h576625[56:5]; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = + _theResult___snd__h576629[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213 = - _theResult___sfd__h577330; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = + _theResult___sfd__h577334; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h576625 or + _theResult___snd__h576629 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 or - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213) + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - _theResult___snd__h576625[56:5]; + _theResult___snd__h576629[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812; @@ -33848,48 +33848,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = 52'd0; endcase end - always@(guard__h568713 or - _theResult___snd__h576625 or - out_sfd__h577333 or _theResult___sfd__h577330) + always@(guard__h568717 or + _theResult___snd__h576629 or + out_sfd__h577337 or _theResult___sfd__h577334) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 = - _theResult___snd__h576625[56:5]; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = + _theResult___snd__h576629[56:5]; 2'b10: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 = - out_sfd__h577333; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = + out_sfd__h577337; 2'b11: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 = - _theResult___sfd__h577330; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = + _theResult___sfd__h577334; endcase end - always@(guard__h578025 or sfdin__h586245 or _theResult___sfd__h586981) + always@(guard__h578029 or sfdin__h586249 or _theResult___sfd__h586985) begin - case (guard__h578025) + case (guard__h578029) 2'b0: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h586245[56:5]; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h586249[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h586981; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h586985; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h586245 or + sfdin__h586249 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 or - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215) + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - sfdin__h586245[56:5]; + sfdin__h586249[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838; @@ -33898,24 +33898,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = 52'd0; endcase end - always@(guard__h578025 or - sfdin__h586245 or out_sfd__h586984 or _theResult___sfd__h586981) + always@(guard__h578029 or + sfdin__h586249 or out_sfd__h586988 or _theResult___sfd__h586985) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h586245[56:5]; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h586249[56:5]; 2'b10: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h586984; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h586988; 2'b11: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h586981; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h586985; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -33950,28 +33950,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830; endcase end - always@(guard__h587094 or - _theResult___snd__h595030 or _theResult___sfd__h595765) + always@(guard__h587098 or + _theResult___snd__h595034 or _theResult___sfd__h595769) begin - case (guard__h587094) + case (guard__h587098) 2'b0: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217 = - _theResult___snd__h595030[56:5]; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = + _theResult___snd__h595034[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217 = - _theResult___sfd__h595765; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = + _theResult___sfd__h595769; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595030 or + _theResult___snd__h595034 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 or - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217) + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - _theResult___snd__h595030[56:5]; + _theResult___snd__h595034[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857; @@ -33980,25 +33980,25 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = 52'd0; endcase end - always@(guard__h587094 or - _theResult___snd__h595030 or - out_sfd__h595768 or _theResult___sfd__h595765) + always@(guard__h587098 or + _theResult___snd__h595034 or + out_sfd__h595772 or _theResult___sfd__h595769) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 = - _theResult___snd__h595030[56:5]; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = + _theResult___snd__h595034[56:5]; 2'b10: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 = - out_sfd__h595768; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = + out_sfd__h595772; 2'b11: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 = - _theResult___sfd__h595765; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = + _theResult___sfd__h595769; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34311,10 +34311,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h661036 or + always@(k__h661045 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661036) + case (k__h661045) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 = coreFix_aluExe_0_rsAlu$canEnq; @@ -34353,10 +34353,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(k__h661036 or + always@(k__h661045 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661036) + case (k__h661045) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -34498,14 +34498,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h675470 or + always@(idx__h675479 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675470) + case (idx__h675479) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 = fetchStage$pipelines_0_canDeq && @@ -34641,15 +34641,15 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494; endcase end - always@(k__h661036 or + always@(k__h661045 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h661036) + case (k__h661045) 1'd0: - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -34752,14 +34752,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(idx__h675470 or + always@(idx__h675479 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675470) + case (idx__h675479) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 = (!fetchStage$pipelines_0_canDeq || @@ -35668,28 +35668,6 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -35706,9 +35684,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = 4'd15; endcase end @@ -37751,7 +37751,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h600770 == 2'd0) + v__h600774 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 1035e97..8a98286 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -1530,10 +1530,10 @@ module mkCoreW(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5048; + reg [31 : 0] v__h5014; reg [31 : 0] v__h4855; reg [31 : 0] v__h4849; - reg [31 : 0] v__h5042; + reg [31 : 0] v__h5008; // synopsys translate_on // action method set_verbosity @@ -2580,9 +2580,9 @@ module mkCoreW(CLK, // rule RL_rl_hart0_server_reset assign CAN_FIRE_RL_rl_hart0_server_reset = - proc$RDY_hart0_server_reset_response_get ; + proc$RDY_start && proc$RDY_hart0_server_reset_response_get ; assign WILL_FIRE_RL_rl_hart0_server_reset = - proc$RDY_hart0_server_reset_response_get ; + CAN_FIRE_RL_rl_hart0_server_reset ; // rule RL_rl_hart0_server_run_halt assign CAN_FIRE_RL_rl_hart0_server_run_halt = 1'd1 ; @@ -2600,20 +2600,20 @@ module mkCoreW(CLK, // rule RL_rl_gpr assign CAN_FIRE_RL_rl_gpr = - debug_module$RDY_hart0_gpr_mem_client_request_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + debug_module$RDY_hart0_gpr_mem_client_request_get ; assign WILL_FIRE_RL_rl_gpr = CAN_FIRE_RL_rl_gpr ; // rule RL_rl_fpr assign CAN_FIRE_RL_rl_fpr = - debug_module$RDY_hart0_fpr_mem_client_request_get && - debug_module$RDY_hart0_fpr_mem_client_response_put ; + debug_module$RDY_hart0_fpr_mem_client_response_put && + debug_module$RDY_hart0_fpr_mem_client_request_get ; assign WILL_FIRE_RL_rl_fpr = CAN_FIRE_RL_rl_fpr ; // rule RL_rl_csr assign CAN_FIRE_RL_rl_csr = - debug_module$RDY_hart0_csr_mem_client_request_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + debug_module$RDY_hart0_csr_mem_client_request_get ; assign WILL_FIRE_RL_rl_csr = CAN_FIRE_RL_rl_csr ; // rule RL_rl_cpu_hart0_reset_from_dm_complete @@ -2743,8 +2743,7 @@ module mkCoreW(CLK, // rule RL_rl_cpu_hart0_reset_complete assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && proc$RDY_start && - f_reset_rsps$FULL_N && + plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N && !cpu_reset$ASSERT_OUT ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; @@ -2904,8 +2903,7 @@ module mkCoreW(CLK, // submodule f_reset_rsps assign f_reset_rsps$ENQ = - plic$RDY_server_reset_response_get && proc$RDY_start && - f_reset_rsps$FULL_N && + plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N && !cpu_reset$ASSERT_OUT ; assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -3131,8 +3129,8 @@ module mkCoreW(CLK, assign proc$start_tohostAddr = rg_tohost_addr ; assign proc$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_once ; assign proc$EN_hart0_server_reset_response_get = - proc$RDY_hart0_server_reset_response_get ; - assign proc$EN_start = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + CAN_FIRE_RL_rl_hart0_server_reset ; + assign proc$EN_start = CAN_FIRE_RL_rl_hart0_server_reset ; assign proc$EN_set_verbosity = EN_set_verbosity ; assign proc$EN_trace_data_out_get = CAN_FIRE_RL_merge_cpu_trace_data ; assign proc$EN_hart0_server_run_halt_request_put = 1'b0 ; @@ -3205,18 +3203,16 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (cpu_reset_either$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h5048 = $stime; - #0; - end - v__h5042 = v__h5048 / 32'd10; + if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) + begin + v__h5014 = $stime; + #0; + end + v__h5008 = v__h5014 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (cpu_reset_either$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h5042); + if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) + $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", + v__h5008); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin diff --git a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v index 681bff9..1a41e81 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v index 62280a6..935f2d7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v index 659476b..f6ead5f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v index 16f6afa..2843207 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v index b30df25..9f748f7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v index 0d6421c..32b8295 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v index 7eb91a4..1a3ba20 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v index d7ed640..8f7dfb4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v index 053bf66..e885e7d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -7,15 +7,16 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 -// RDY_response_get O 1 +// response_get O 69 reg +// RDY_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// request_put I 131 +// request_put I 131 reg // EN_request_put I 1 // EN_response_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// EN_response_get -> RDY_request_put // // @@ -59,44 +60,4031 @@ module mkDoubleDiv(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu - wire [130 : 0] fpu$request_put; - wire [68 : 0] fpu$response_get; - wire fpu$EN_request_put, - fpu$EN_response_get, - fpu$RDY_request_put, - fpu$RDY_response_get; + // ports of submodule fpu_fOperands_S0 + wire [130 : 0] fpu_fOperands_S0$D_IN, fpu_fOperands_S0$D_OUT; + wire fpu_fOperands_S0$CLR, + fpu_fOperands_S0$DEQ, + fpu_fOperands_S0$EMPTY_N, + fpu_fOperands_S0$ENQ, + fpu_fOperands_S0$FULL_N; + + // ports of submodule fpu_fResult_S5 + wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; + wire fpu_fResult_S5$CLR, + fpu_fResult_S5$DEQ, + fpu_fResult_S5$EMPTY_N, + fpu_fResult_S5$ENQ, + fpu_fResult_S5$FULL_N; + + // ports of submodule fpu_fState_S1 + wire [318 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; + wire fpu_fState_S1$CLR, + fpu_fState_S1$DEQ, + fpu_fState_S1$EMPTY_N, + fpu_fState_S1$ENQ, + fpu_fState_S1$FULL_N; + + // ports of submodule fpu_fState_S2 + wire [147 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; + wire fpu_fState_S2$CLR, + fpu_fState_S2$DEQ, + fpu_fState_S2$EMPTY_N, + fpu_fState_S2$ENQ, + fpu_fState_S2$FULL_N; + + // ports of submodule fpu_fState_S3 + wire [194 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; + wire fpu_fState_S3$CLR, + fpu_fState_S3$DEQ, + fpu_fState_S3$EMPTY_N, + fpu_fState_S3$ENQ, + fpu_fState_S3$FULL_N; + + // ports of submodule fpu_fState_S4 + wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; + wire fpu_fState_S4$CLR, + fpu_fState_S4$DEQ, + fpu_fState_S4$EMPTY_N, + fpu_fState_S4$ENQ, + fpu_fState_S4$FULL_N; + + // ports of submodule int_div_fFirst + wire [231 : 0] int_div_fFirst$D_IN, int_div_fFirst$D_OUT; + wire int_div_fFirst$CLR, + int_div_fFirst$DEQ, + int_div_fFirst$EMPTY_N, + int_div_fFirst$ENQ, + int_div_fFirst$FULL_N; + + // ports of submodule int_div_fNext_0 + wire [231 : 0] int_div_fNext_0$D_IN, int_div_fNext_0$D_OUT; + wire int_div_fNext_0$CLR, + int_div_fNext_0$DEQ, + int_div_fNext_0$EMPTY_N, + int_div_fNext_0$ENQ, + int_div_fNext_0$FULL_N; + + // ports of submodule int_div_fNext_1 + wire [231 : 0] int_div_fNext_1$D_IN, int_div_fNext_1$D_OUT; + wire int_div_fNext_1$CLR, + int_div_fNext_1$DEQ, + int_div_fNext_1$EMPTY_N, + int_div_fNext_1$ENQ, + int_div_fNext_1$FULL_N; + + // ports of submodule int_div_fNext_10 + wire [231 : 0] int_div_fNext_10$D_IN, int_div_fNext_10$D_OUT; + wire int_div_fNext_10$CLR, + int_div_fNext_10$DEQ, + int_div_fNext_10$EMPTY_N, + int_div_fNext_10$ENQ, + int_div_fNext_10$FULL_N; + + // ports of submodule int_div_fNext_11 + wire [231 : 0] int_div_fNext_11$D_IN, int_div_fNext_11$D_OUT; + wire int_div_fNext_11$CLR, + int_div_fNext_11$DEQ, + int_div_fNext_11$EMPTY_N, + int_div_fNext_11$ENQ, + int_div_fNext_11$FULL_N; + + // ports of submodule int_div_fNext_12 + wire [231 : 0] int_div_fNext_12$D_IN, int_div_fNext_12$D_OUT; + wire int_div_fNext_12$CLR, + int_div_fNext_12$DEQ, + int_div_fNext_12$EMPTY_N, + int_div_fNext_12$ENQ, + int_div_fNext_12$FULL_N; + + // ports of submodule int_div_fNext_13 + wire [231 : 0] int_div_fNext_13$D_IN, int_div_fNext_13$D_OUT; + wire int_div_fNext_13$CLR, + int_div_fNext_13$DEQ, + int_div_fNext_13$EMPTY_N, + int_div_fNext_13$ENQ, + int_div_fNext_13$FULL_N; + + // ports of submodule int_div_fNext_14 + wire [231 : 0] int_div_fNext_14$D_IN, int_div_fNext_14$D_OUT; + wire int_div_fNext_14$CLR, + int_div_fNext_14$DEQ, + int_div_fNext_14$EMPTY_N, + int_div_fNext_14$ENQ, + int_div_fNext_14$FULL_N; + + // ports of submodule int_div_fNext_15 + wire [231 : 0] int_div_fNext_15$D_IN, int_div_fNext_15$D_OUT; + wire int_div_fNext_15$CLR, + int_div_fNext_15$DEQ, + int_div_fNext_15$EMPTY_N, + int_div_fNext_15$ENQ, + int_div_fNext_15$FULL_N; + + // ports of submodule int_div_fNext_16 + wire [231 : 0] int_div_fNext_16$D_IN, int_div_fNext_16$D_OUT; + wire int_div_fNext_16$CLR, + int_div_fNext_16$DEQ, + int_div_fNext_16$EMPTY_N, + int_div_fNext_16$ENQ, + int_div_fNext_16$FULL_N; + + // ports of submodule int_div_fNext_17 + wire [231 : 0] int_div_fNext_17$D_IN, int_div_fNext_17$D_OUT; + wire int_div_fNext_17$CLR, + int_div_fNext_17$DEQ, + int_div_fNext_17$EMPTY_N, + int_div_fNext_17$ENQ, + int_div_fNext_17$FULL_N; + + // ports of submodule int_div_fNext_18 + wire [231 : 0] int_div_fNext_18$D_IN, int_div_fNext_18$D_OUT; + wire int_div_fNext_18$CLR, + int_div_fNext_18$DEQ, + int_div_fNext_18$EMPTY_N, + int_div_fNext_18$ENQ, + int_div_fNext_18$FULL_N; + + // ports of submodule int_div_fNext_19 + wire [231 : 0] int_div_fNext_19$D_IN, int_div_fNext_19$D_OUT; + wire int_div_fNext_19$CLR, + int_div_fNext_19$DEQ, + int_div_fNext_19$EMPTY_N, + int_div_fNext_19$ENQ, + int_div_fNext_19$FULL_N; + + // ports of submodule int_div_fNext_2 + wire [231 : 0] int_div_fNext_2$D_IN, int_div_fNext_2$D_OUT; + wire int_div_fNext_2$CLR, + int_div_fNext_2$DEQ, + int_div_fNext_2$EMPTY_N, + int_div_fNext_2$ENQ, + int_div_fNext_2$FULL_N; + + // ports of submodule int_div_fNext_20 + wire [231 : 0] int_div_fNext_20$D_IN, int_div_fNext_20$D_OUT; + wire int_div_fNext_20$CLR, + int_div_fNext_20$DEQ, + int_div_fNext_20$EMPTY_N, + int_div_fNext_20$ENQ, + int_div_fNext_20$FULL_N; + + // ports of submodule int_div_fNext_21 + wire [231 : 0] int_div_fNext_21$D_IN, int_div_fNext_21$D_OUT; + wire int_div_fNext_21$CLR, + int_div_fNext_21$DEQ, + int_div_fNext_21$EMPTY_N, + int_div_fNext_21$ENQ, + int_div_fNext_21$FULL_N; + + // ports of submodule int_div_fNext_22 + wire [231 : 0] int_div_fNext_22$D_IN, int_div_fNext_22$D_OUT; + wire int_div_fNext_22$CLR, + int_div_fNext_22$DEQ, + int_div_fNext_22$EMPTY_N, + int_div_fNext_22$ENQ, + int_div_fNext_22$FULL_N; + + // ports of submodule int_div_fNext_23 + wire [231 : 0] int_div_fNext_23$D_IN, int_div_fNext_23$D_OUT; + wire int_div_fNext_23$CLR, + int_div_fNext_23$DEQ, + int_div_fNext_23$EMPTY_N, + int_div_fNext_23$ENQ, + int_div_fNext_23$FULL_N; + + // ports of submodule int_div_fNext_24 + wire [231 : 0] int_div_fNext_24$D_IN, int_div_fNext_24$D_OUT; + wire int_div_fNext_24$CLR, + int_div_fNext_24$DEQ, + int_div_fNext_24$EMPTY_N, + int_div_fNext_24$ENQ, + int_div_fNext_24$FULL_N; + + // ports of submodule int_div_fNext_25 + wire [231 : 0] int_div_fNext_25$D_IN, int_div_fNext_25$D_OUT; + wire int_div_fNext_25$CLR, + int_div_fNext_25$DEQ, + int_div_fNext_25$EMPTY_N, + int_div_fNext_25$ENQ, + int_div_fNext_25$FULL_N; + + // ports of submodule int_div_fNext_26 + wire [231 : 0] int_div_fNext_26$D_IN, int_div_fNext_26$D_OUT; + wire int_div_fNext_26$CLR, + int_div_fNext_26$DEQ, + int_div_fNext_26$EMPTY_N, + int_div_fNext_26$ENQ, + int_div_fNext_26$FULL_N; + + // ports of submodule int_div_fNext_27 + wire [231 : 0] int_div_fNext_27$D_IN, int_div_fNext_27$D_OUT; + wire int_div_fNext_27$CLR, + int_div_fNext_27$DEQ, + int_div_fNext_27$EMPTY_N, + int_div_fNext_27$ENQ, + int_div_fNext_27$FULL_N; + + // ports of submodule int_div_fNext_28 + wire [231 : 0] int_div_fNext_28$D_IN, int_div_fNext_28$D_OUT; + wire int_div_fNext_28$CLR, + int_div_fNext_28$DEQ, + int_div_fNext_28$EMPTY_N, + int_div_fNext_28$ENQ, + int_div_fNext_28$FULL_N; + + // ports of submodule int_div_fNext_29 + wire [231 : 0] int_div_fNext_29$D_IN, int_div_fNext_29$D_OUT; + wire int_div_fNext_29$CLR, + int_div_fNext_29$DEQ, + int_div_fNext_29$EMPTY_N, + int_div_fNext_29$ENQ, + int_div_fNext_29$FULL_N; + + // ports of submodule int_div_fNext_3 + wire [231 : 0] int_div_fNext_3$D_IN, int_div_fNext_3$D_OUT; + wire int_div_fNext_3$CLR, + int_div_fNext_3$DEQ, + int_div_fNext_3$EMPTY_N, + int_div_fNext_3$ENQ, + int_div_fNext_3$FULL_N; + + // ports of submodule int_div_fNext_30 + wire [231 : 0] int_div_fNext_30$D_IN, int_div_fNext_30$D_OUT; + wire int_div_fNext_30$CLR, + int_div_fNext_30$DEQ, + int_div_fNext_30$EMPTY_N, + int_div_fNext_30$ENQ, + int_div_fNext_30$FULL_N; + + // ports of submodule int_div_fNext_31 + wire [231 : 0] int_div_fNext_31$D_IN, int_div_fNext_31$D_OUT; + wire int_div_fNext_31$CLR, + int_div_fNext_31$DEQ, + int_div_fNext_31$EMPTY_N, + int_div_fNext_31$ENQ, + int_div_fNext_31$FULL_N; + + // ports of submodule int_div_fNext_32 + wire [231 : 0] int_div_fNext_32$D_IN, int_div_fNext_32$D_OUT; + wire int_div_fNext_32$CLR, + int_div_fNext_32$DEQ, + int_div_fNext_32$EMPTY_N, + int_div_fNext_32$ENQ, + int_div_fNext_32$FULL_N; + + // ports of submodule int_div_fNext_33 + wire [231 : 0] int_div_fNext_33$D_IN, int_div_fNext_33$D_OUT; + wire int_div_fNext_33$CLR, + int_div_fNext_33$DEQ, + int_div_fNext_33$EMPTY_N, + int_div_fNext_33$ENQ, + int_div_fNext_33$FULL_N; + + // ports of submodule int_div_fNext_34 + wire [231 : 0] int_div_fNext_34$D_IN, int_div_fNext_34$D_OUT; + wire int_div_fNext_34$CLR, + int_div_fNext_34$DEQ, + int_div_fNext_34$EMPTY_N, + int_div_fNext_34$ENQ, + int_div_fNext_34$FULL_N; + + // ports of submodule int_div_fNext_35 + wire [231 : 0] int_div_fNext_35$D_IN, int_div_fNext_35$D_OUT; + wire int_div_fNext_35$CLR, + int_div_fNext_35$DEQ, + int_div_fNext_35$EMPTY_N, + int_div_fNext_35$ENQ, + int_div_fNext_35$FULL_N; + + // ports of submodule int_div_fNext_36 + wire [231 : 0] int_div_fNext_36$D_IN, int_div_fNext_36$D_OUT; + wire int_div_fNext_36$CLR, + int_div_fNext_36$DEQ, + int_div_fNext_36$EMPTY_N, + int_div_fNext_36$ENQ, + int_div_fNext_36$FULL_N; + + // ports of submodule int_div_fNext_37 + wire [231 : 0] int_div_fNext_37$D_IN, int_div_fNext_37$D_OUT; + wire int_div_fNext_37$CLR, + int_div_fNext_37$DEQ, + int_div_fNext_37$EMPTY_N, + int_div_fNext_37$ENQ, + int_div_fNext_37$FULL_N; + + // ports of submodule int_div_fNext_38 + wire [231 : 0] int_div_fNext_38$D_IN, int_div_fNext_38$D_OUT; + wire int_div_fNext_38$CLR, + int_div_fNext_38$DEQ, + int_div_fNext_38$EMPTY_N, + int_div_fNext_38$ENQ, + int_div_fNext_38$FULL_N; + + // ports of submodule int_div_fNext_39 + wire [231 : 0] int_div_fNext_39$D_IN, int_div_fNext_39$D_OUT; + wire int_div_fNext_39$CLR, + int_div_fNext_39$DEQ, + int_div_fNext_39$EMPTY_N, + int_div_fNext_39$ENQ, + int_div_fNext_39$FULL_N; + + // ports of submodule int_div_fNext_4 + wire [231 : 0] int_div_fNext_4$D_IN, int_div_fNext_4$D_OUT; + wire int_div_fNext_4$CLR, + int_div_fNext_4$DEQ, + int_div_fNext_4$EMPTY_N, + int_div_fNext_4$ENQ, + int_div_fNext_4$FULL_N; + + // ports of submodule int_div_fNext_40 + wire [231 : 0] int_div_fNext_40$D_IN, int_div_fNext_40$D_OUT; + wire int_div_fNext_40$CLR, + int_div_fNext_40$DEQ, + int_div_fNext_40$EMPTY_N, + int_div_fNext_40$ENQ, + int_div_fNext_40$FULL_N; + + // ports of submodule int_div_fNext_41 + wire [231 : 0] int_div_fNext_41$D_IN, int_div_fNext_41$D_OUT; + wire int_div_fNext_41$CLR, + int_div_fNext_41$DEQ, + int_div_fNext_41$EMPTY_N, + int_div_fNext_41$ENQ, + int_div_fNext_41$FULL_N; + + // ports of submodule int_div_fNext_42 + wire [231 : 0] int_div_fNext_42$D_IN, int_div_fNext_42$D_OUT; + wire int_div_fNext_42$CLR, + int_div_fNext_42$DEQ, + int_div_fNext_42$EMPTY_N, + int_div_fNext_42$ENQ, + int_div_fNext_42$FULL_N; + + // ports of submodule int_div_fNext_43 + wire [231 : 0] int_div_fNext_43$D_IN, int_div_fNext_43$D_OUT; + wire int_div_fNext_43$CLR, + int_div_fNext_43$DEQ, + int_div_fNext_43$EMPTY_N, + int_div_fNext_43$ENQ, + int_div_fNext_43$FULL_N; + + // ports of submodule int_div_fNext_44 + wire [231 : 0] int_div_fNext_44$D_IN, int_div_fNext_44$D_OUT; + wire int_div_fNext_44$CLR, + int_div_fNext_44$DEQ, + int_div_fNext_44$EMPTY_N, + int_div_fNext_44$ENQ, + int_div_fNext_44$FULL_N; + + // ports of submodule int_div_fNext_45 + wire [231 : 0] int_div_fNext_45$D_IN, int_div_fNext_45$D_OUT; + wire int_div_fNext_45$CLR, + int_div_fNext_45$DEQ, + int_div_fNext_45$EMPTY_N, + int_div_fNext_45$ENQ, + int_div_fNext_45$FULL_N; + + // ports of submodule int_div_fNext_46 + wire [231 : 0] int_div_fNext_46$D_IN, int_div_fNext_46$D_OUT; + wire int_div_fNext_46$CLR, + int_div_fNext_46$DEQ, + int_div_fNext_46$EMPTY_N, + int_div_fNext_46$ENQ, + int_div_fNext_46$FULL_N; + + // ports of submodule int_div_fNext_47 + wire [231 : 0] int_div_fNext_47$D_IN, int_div_fNext_47$D_OUT; + wire int_div_fNext_47$CLR, + int_div_fNext_47$DEQ, + int_div_fNext_47$EMPTY_N, + int_div_fNext_47$ENQ, + int_div_fNext_47$FULL_N; + + // ports of submodule int_div_fNext_48 + wire [231 : 0] int_div_fNext_48$D_IN, int_div_fNext_48$D_OUT; + wire int_div_fNext_48$CLR, + int_div_fNext_48$DEQ, + int_div_fNext_48$EMPTY_N, + int_div_fNext_48$ENQ, + int_div_fNext_48$FULL_N; + + // ports of submodule int_div_fNext_49 + wire [231 : 0] int_div_fNext_49$D_IN, int_div_fNext_49$D_OUT; + wire int_div_fNext_49$CLR, + int_div_fNext_49$DEQ, + int_div_fNext_49$EMPTY_N, + int_div_fNext_49$ENQ, + int_div_fNext_49$FULL_N; + + // ports of submodule int_div_fNext_5 + wire [231 : 0] int_div_fNext_5$D_IN, int_div_fNext_5$D_OUT; + wire int_div_fNext_5$CLR, + int_div_fNext_5$DEQ, + int_div_fNext_5$EMPTY_N, + int_div_fNext_5$ENQ, + int_div_fNext_5$FULL_N; + + // ports of submodule int_div_fNext_50 + wire [231 : 0] int_div_fNext_50$D_IN, int_div_fNext_50$D_OUT; + wire int_div_fNext_50$CLR, + int_div_fNext_50$DEQ, + int_div_fNext_50$EMPTY_N, + int_div_fNext_50$ENQ, + int_div_fNext_50$FULL_N; + + // ports of submodule int_div_fNext_51 + wire [231 : 0] int_div_fNext_51$D_IN, int_div_fNext_51$D_OUT; + wire int_div_fNext_51$CLR, + int_div_fNext_51$DEQ, + int_div_fNext_51$EMPTY_N, + int_div_fNext_51$ENQ, + int_div_fNext_51$FULL_N; + + // ports of submodule int_div_fNext_52 + wire [231 : 0] int_div_fNext_52$D_IN, int_div_fNext_52$D_OUT; + wire int_div_fNext_52$CLR, + int_div_fNext_52$DEQ, + int_div_fNext_52$EMPTY_N, + int_div_fNext_52$ENQ, + int_div_fNext_52$FULL_N; + + // ports of submodule int_div_fNext_53 + wire [231 : 0] int_div_fNext_53$D_IN, int_div_fNext_53$D_OUT; + wire int_div_fNext_53$CLR, + int_div_fNext_53$DEQ, + int_div_fNext_53$EMPTY_N, + int_div_fNext_53$ENQ, + int_div_fNext_53$FULL_N; + + // ports of submodule int_div_fNext_54 + wire [231 : 0] int_div_fNext_54$D_IN, int_div_fNext_54$D_OUT; + wire int_div_fNext_54$CLR, + int_div_fNext_54$DEQ, + int_div_fNext_54$EMPTY_N, + int_div_fNext_54$ENQ, + int_div_fNext_54$FULL_N; + + // ports of submodule int_div_fNext_55 + wire [231 : 0] int_div_fNext_55$D_IN, int_div_fNext_55$D_OUT; + wire int_div_fNext_55$CLR, + int_div_fNext_55$DEQ, + int_div_fNext_55$EMPTY_N, + int_div_fNext_55$ENQ, + int_div_fNext_55$FULL_N; + + // ports of submodule int_div_fNext_56 + wire [231 : 0] int_div_fNext_56$D_IN, int_div_fNext_56$D_OUT; + wire int_div_fNext_56$CLR, + int_div_fNext_56$DEQ, + int_div_fNext_56$EMPTY_N, + int_div_fNext_56$ENQ, + int_div_fNext_56$FULL_N; + + // ports of submodule int_div_fNext_57 + wire [231 : 0] int_div_fNext_57$D_IN, int_div_fNext_57$D_OUT; + wire int_div_fNext_57$CLR, + int_div_fNext_57$DEQ, + int_div_fNext_57$EMPTY_N, + int_div_fNext_57$ENQ, + int_div_fNext_57$FULL_N; + + // ports of submodule int_div_fNext_6 + wire [231 : 0] int_div_fNext_6$D_IN, int_div_fNext_6$D_OUT; + wire int_div_fNext_6$CLR, + int_div_fNext_6$DEQ, + int_div_fNext_6$EMPTY_N, + int_div_fNext_6$ENQ, + int_div_fNext_6$FULL_N; + + // ports of submodule int_div_fNext_7 + wire [231 : 0] int_div_fNext_7$D_IN, int_div_fNext_7$D_OUT; + wire int_div_fNext_7$CLR, + int_div_fNext_7$DEQ, + int_div_fNext_7$EMPTY_N, + int_div_fNext_7$ENQ, + int_div_fNext_7$FULL_N; + + // ports of submodule int_div_fNext_8 + wire [231 : 0] int_div_fNext_8$D_IN, int_div_fNext_8$D_OUT; + wire int_div_fNext_8$CLR, + int_div_fNext_8$DEQ, + int_div_fNext_8$EMPTY_N, + int_div_fNext_8$ENQ, + int_div_fNext_8$FULL_N; + + // ports of submodule int_div_fNext_9 + wire [231 : 0] int_div_fNext_9$D_IN, int_div_fNext_9$D_OUT; + wire int_div_fNext_9$CLR, + int_div_fNext_9$DEQ, + int_div_fNext_9$EMPTY_N, + int_div_fNext_9$ENQ, + int_div_fNext_9$FULL_N; + + // ports of submodule int_div_fRequest + wire [170 : 0] int_div_fRequest$D_IN, int_div_fRequest$D_OUT; + wire int_div_fRequest$CLR, + int_div_fRequest$DEQ, + int_div_fRequest$EMPTY_N, + int_div_fRequest$ENQ, + int_div_fRequest$FULL_N; + + // ports of submodule int_div_fResponse + wire [113 : 0] int_div_fResponse$D_IN, int_div_fResponse$D_OUT; + wire int_div_fResponse$CLR, + int_div_fResponse$DEQ, + int_div_fResponse$EMPTY_N, + int_div_fResponse$ENQ, + int_div_fResponse$FULL_N; // rule scheduling signals - wire CAN_FIRE_request_put, + wire CAN_FIRE_RL_fpu_s1_stage, + CAN_FIRE_RL_fpu_s2_stage, + CAN_FIRE_RL_fpu_s3_stage, + CAN_FIRE_RL_fpu_s4_stage, + CAN_FIRE_RL_fpu_s5_stage, + CAN_FIRE_RL_int_div_finish, + CAN_FIRE_RL_int_div_start, + CAN_FIRE_RL_int_div_work, + CAN_FIRE_RL_int_div_work_1, + CAN_FIRE_RL_int_div_work_10, + CAN_FIRE_RL_int_div_work_11, + CAN_FIRE_RL_int_div_work_12, + CAN_FIRE_RL_int_div_work_13, + CAN_FIRE_RL_int_div_work_14, + CAN_FIRE_RL_int_div_work_15, + CAN_FIRE_RL_int_div_work_16, + CAN_FIRE_RL_int_div_work_17, + CAN_FIRE_RL_int_div_work_18, + CAN_FIRE_RL_int_div_work_19, + CAN_FIRE_RL_int_div_work_2, + CAN_FIRE_RL_int_div_work_20, + CAN_FIRE_RL_int_div_work_21, + CAN_FIRE_RL_int_div_work_22, + CAN_FIRE_RL_int_div_work_23, + CAN_FIRE_RL_int_div_work_24, + CAN_FIRE_RL_int_div_work_25, + CAN_FIRE_RL_int_div_work_26, + CAN_FIRE_RL_int_div_work_27, + CAN_FIRE_RL_int_div_work_28, + CAN_FIRE_RL_int_div_work_29, + CAN_FIRE_RL_int_div_work_3, + CAN_FIRE_RL_int_div_work_30, + CAN_FIRE_RL_int_div_work_31, + CAN_FIRE_RL_int_div_work_32, + CAN_FIRE_RL_int_div_work_33, + CAN_FIRE_RL_int_div_work_34, + CAN_FIRE_RL_int_div_work_35, + CAN_FIRE_RL_int_div_work_36, + CAN_FIRE_RL_int_div_work_37, + CAN_FIRE_RL_int_div_work_38, + CAN_FIRE_RL_int_div_work_39, + CAN_FIRE_RL_int_div_work_4, + CAN_FIRE_RL_int_div_work_40, + CAN_FIRE_RL_int_div_work_41, + CAN_FIRE_RL_int_div_work_42, + CAN_FIRE_RL_int_div_work_43, + CAN_FIRE_RL_int_div_work_44, + CAN_FIRE_RL_int_div_work_45, + CAN_FIRE_RL_int_div_work_46, + CAN_FIRE_RL_int_div_work_47, + CAN_FIRE_RL_int_div_work_48, + CAN_FIRE_RL_int_div_work_49, + CAN_FIRE_RL_int_div_work_5, + CAN_FIRE_RL_int_div_work_50, + CAN_FIRE_RL_int_div_work_51, + CAN_FIRE_RL_int_div_work_52, + CAN_FIRE_RL_int_div_work_53, + CAN_FIRE_RL_int_div_work_54, + CAN_FIRE_RL_int_div_work_55, + CAN_FIRE_RL_int_div_work_56, + CAN_FIRE_RL_int_div_work_57, + CAN_FIRE_RL_int_div_work_6, + CAN_FIRE_RL_int_div_work_7, + CAN_FIRE_RL_int_div_work_8, + CAN_FIRE_RL_int_div_work_9, + CAN_FIRE_request_put, CAN_FIRE_response_get, + WILL_FIRE_RL_fpu_s1_stage, + WILL_FIRE_RL_fpu_s2_stage, + WILL_FIRE_RL_fpu_s3_stage, + WILL_FIRE_RL_fpu_s4_stage, + WILL_FIRE_RL_fpu_s5_stage, + WILL_FIRE_RL_int_div_finish, + WILL_FIRE_RL_int_div_start, + WILL_FIRE_RL_int_div_work, + WILL_FIRE_RL_int_div_work_1, + WILL_FIRE_RL_int_div_work_10, + WILL_FIRE_RL_int_div_work_11, + WILL_FIRE_RL_int_div_work_12, + WILL_FIRE_RL_int_div_work_13, + WILL_FIRE_RL_int_div_work_14, + WILL_FIRE_RL_int_div_work_15, + WILL_FIRE_RL_int_div_work_16, + WILL_FIRE_RL_int_div_work_17, + WILL_FIRE_RL_int_div_work_18, + WILL_FIRE_RL_int_div_work_19, + WILL_FIRE_RL_int_div_work_2, + WILL_FIRE_RL_int_div_work_20, + WILL_FIRE_RL_int_div_work_21, + WILL_FIRE_RL_int_div_work_22, + WILL_FIRE_RL_int_div_work_23, + WILL_FIRE_RL_int_div_work_24, + WILL_FIRE_RL_int_div_work_25, + WILL_FIRE_RL_int_div_work_26, + WILL_FIRE_RL_int_div_work_27, + WILL_FIRE_RL_int_div_work_28, + WILL_FIRE_RL_int_div_work_29, + WILL_FIRE_RL_int_div_work_3, + WILL_FIRE_RL_int_div_work_30, + WILL_FIRE_RL_int_div_work_31, + WILL_FIRE_RL_int_div_work_32, + WILL_FIRE_RL_int_div_work_33, + WILL_FIRE_RL_int_div_work_34, + WILL_FIRE_RL_int_div_work_35, + WILL_FIRE_RL_int_div_work_36, + WILL_FIRE_RL_int_div_work_37, + WILL_FIRE_RL_int_div_work_38, + WILL_FIRE_RL_int_div_work_39, + WILL_FIRE_RL_int_div_work_4, + WILL_FIRE_RL_int_div_work_40, + WILL_FIRE_RL_int_div_work_41, + WILL_FIRE_RL_int_div_work_42, + WILL_FIRE_RL_int_div_work_43, + WILL_FIRE_RL_int_div_work_44, + WILL_FIRE_RL_int_div_work_45, + WILL_FIRE_RL_int_div_work_46, + WILL_FIRE_RL_int_div_work_47, + WILL_FIRE_RL_int_div_work_48, + WILL_FIRE_RL_int_div_work_49, + WILL_FIRE_RL_int_div_work_5, + WILL_FIRE_RL_int_div_work_50, + WILL_FIRE_RL_int_div_work_51, + WILL_FIRE_RL_int_div_work_52, + WILL_FIRE_RL_int_div_work_53, + WILL_FIRE_RL_int_div_work_54, + WILL_FIRE_RL_int_div_work_55, + WILL_FIRE_RL_int_div_work_56, + WILL_FIRE_RL_int_div_work_57, + WILL_FIRE_RL_int_div_work_6, + WILL_FIRE_RL_int_div_work_7, + WILL_FIRE_RL_int_div_work_8, + WILL_FIRE_RL_int_div_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; + // remaining internal signals + reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16; + reg [62 : 0] CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12; + reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, + _theResult___fst_sfd__h37218, + _theResult___fst_sfd__h37707, + _theResult___fst_sfd__h60989; + reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9, + _theResult___fst_exp__h37217, + _theResult___fst_exp__h60988; + reg CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5, + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11; + wire [115 : 0] b__h10163, + b__h10487, + b__h10811, + b__h1091, + b__h11135, + b__h11459, + b__h11783, + b__h12107, + b__h12431, + b__h12755, + b__h13079, + b__h13403, + b__h13727, + b__h14051, + b__h1415, + b__h14375, + b__h14699, + b__h15023, + b__h15347, + b__h15671, + b__h15995, + b__h16319, + b__h16643, + b__h16967, + b__h17291, + b__h1739, + b__h17615, + b__h17939, + b__h18263, + b__h18587, + b__h18911, + b__h19235, + b__h19482, + b__h2063, + b__h2387, + b__h2711, + b__h3035, + b__h3359, + b__h3683, + b__h4007, + b__h4331, + b__h4655, + b__h4979, + b__h5303, + b__h5627, + b__h5951, + b__h6275, + b__h6599, + b__h6923, + b__h7247, + b__h7571, + b__h767, + b__h7895, + b__h8219, + b__h8543, + b__h8867, + b__h9191, + b__h9515, + b__h9839, + value__h19447; + wire [113 : 0] x__h49176; + wire [63 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305, + fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780; + wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773; + wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7, + IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19, + _theResult____h50063, + _theResult___snd__h52150, + _theResult___snd__h59785, + _theResult___snd__h59800, + _theResult___snd__h59802, + _theResult___snd__h59815, + _theResult___snd__h59821, + _theResult___snd__h59839, + _theResult___snd__h59844, + _theResult___snd_snd_snd__h51398, + b__h378, + int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945, + result__h50077, + result__h50108, + result__h50258, + sfdin__h51553, + sfdin__h59762, + x__h50197, + x__h50487; + wire [56 : 0] value__h50121, x__h49237; + wire [53 : 0] sfd__h60417, value__h49179; + wire [52 : 0] sfdA__h19785, sfdA__h19789, sfdB__h19786, sfdB__h19791; + wire [51 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303, + _theResult___fst_sfd__h60992, + _theResult___sfd__h60911, + _theResult___snd_fst_sfd__h49112, + out_sfd__h60914, + sfd__h36684, + sfd__h36687; + wire [12 : 0] IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205, + value__h49124, + value__h49300; + wire [11 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726; + wire [10 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, + IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, + _theResult___exp__h60910, + _theResult___fst__h49072, + _theResult___fst_exp__h59719, + _theResult___fst_exp__h59722, + _theResult___fst_exp__h59725, + _theResult___fst_exp__h59768, + _theResult___fst_exp__h59771, + _theResult___fst_exp__h59791, + _theResult___fst_exp__h59807, + _theResult___fst_exp__h59846, + _theResult___fst_exp__h59852, + _theResult___fst_exp__h59855, + _theResult___fst_exp__h60991, + _theResult___snd_fst_exp__h49084, + _theResult___snd_fst_exp__h49087, + _theResult___snd_fst_exp__h49111, + din_inc___2_exp__h61001, + fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3, + fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4, + out_exp__h60913, + theResult___fst_exp9725_MINUS_1023__q6, + x__h49291, + x__h50204; + wire [5 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724, + b__h21789, + b__h29207; + wire [4 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765; + wire [1 : 0] IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8, + _theResult___snd_fst__h59874, + guard__h51381, + x__h60140; + wire IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208, + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352, + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441, + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253, + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, + _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351, + fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212, + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, + sfdlsb__h50103; + // action method request_put - assign RDY_request_put = fpu$RDY_request_put ; - assign CAN_FIRE_request_put = fpu$RDY_request_put ; + assign RDY_request_put = fpu_fOperands_S0$FULL_N ; + assign CAN_FIRE_request_put = fpu_fOperands_S0$FULL_N ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu$response_get ; - assign RDY_response_get = fpu$RDY_response_get ; - assign CAN_FIRE_response_get = fpu$RDY_response_get ; + assign response_get = fpu_fResult_S5$D_OUT ; + assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; + assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu - mkXilinxFpDiv fpu(.CLK(CLK), - .RST_N(RST_N), - .request_put(fpu$request_put), - .EN_request_put(fpu$EN_request_put), - .EN_response_get(fpu$EN_response_get), - .RDY_request_put(fpu$RDY_request_put), - .response_get(fpu$response_get), - .RDY_response_get(fpu$RDY_response_get)); + // submodule fpu_fOperands_S0 + FIFOL1 #(.width(32'd131)) fpu_fOperands_S0(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fOperands_S0$D_IN), + .ENQ(fpu_fOperands_S0$ENQ), + .DEQ(fpu_fOperands_S0$DEQ), + .CLR(fpu_fOperands_S0$CLR), + .D_OUT(fpu_fOperands_S0$D_OUT), + .FULL_N(fpu_fOperands_S0$FULL_N), + .EMPTY_N(fpu_fOperands_S0$EMPTY_N)); - // submodule fpu - assign fpu$request_put = request_put ; - assign fpu$EN_request_put = EN_request_put ; - assign fpu$EN_response_get = EN_response_get ; + // submodule fpu_fResult_S5 + FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fResult_S5$D_IN), + .ENQ(fpu_fResult_S5$ENQ), + .DEQ(fpu_fResult_S5$DEQ), + .CLR(fpu_fResult_S5$CLR), + .D_OUT(fpu_fResult_S5$D_OUT), + .FULL_N(fpu_fResult_S5$FULL_N), + .EMPTY_N(fpu_fResult_S5$EMPTY_N)); + + // submodule fpu_fState_S1 + FIFOL1 #(.width(32'd319)) fpu_fState_S1(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S1$D_IN), + .ENQ(fpu_fState_S1$ENQ), + .DEQ(fpu_fState_S1$DEQ), + .CLR(fpu_fState_S1$CLR), + .D_OUT(fpu_fState_S1$D_OUT), + .FULL_N(fpu_fState_S1$FULL_N), + .EMPTY_N(fpu_fState_S1$EMPTY_N)); + + // submodule fpu_fState_S2 + FIFOL1 #(.width(32'd148)) fpu_fState_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S2$D_IN), + .ENQ(fpu_fState_S2$ENQ), + .DEQ(fpu_fState_S2$DEQ), + .CLR(fpu_fState_S2$CLR), + .D_OUT(fpu_fState_S2$D_OUT), + .FULL_N(fpu_fState_S2$FULL_N), + .EMPTY_N(fpu_fState_S2$EMPTY_N)); + + // submodule fpu_fState_S3 + FIFOL1 #(.width(32'd195)) fpu_fState_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S3$D_IN), + .ENQ(fpu_fState_S3$ENQ), + .DEQ(fpu_fState_S3$DEQ), + .CLR(fpu_fState_S3$CLR), + .D_OUT(fpu_fState_S3$D_OUT), + .FULL_N(fpu_fState_S3$FULL_N), + .EMPTY_N(fpu_fState_S3$EMPTY_N)); + + // submodule fpu_fState_S4 + FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S4$D_IN), + .ENQ(fpu_fState_S4$ENQ), + .DEQ(fpu_fState_S4$DEQ), + .CLR(fpu_fState_S4$CLR), + .D_OUT(fpu_fState_S4$D_OUT), + .FULL_N(fpu_fState_S4$FULL_N), + .EMPTY_N(fpu_fState_S4$EMPTY_N)); + + // submodule int_div_fFirst + FIFOL1 #(.width(32'd232)) int_div_fFirst(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fFirst$D_IN), + .ENQ(int_div_fFirst$ENQ), + .DEQ(int_div_fFirst$DEQ), + .CLR(int_div_fFirst$CLR), + .D_OUT(int_div_fFirst$D_OUT), + .FULL_N(int_div_fFirst$FULL_N), + .EMPTY_N(int_div_fFirst$EMPTY_N)); + + // submodule int_div_fNext_0 + FIFOL1 #(.width(32'd232)) int_div_fNext_0(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_0$D_IN), + .ENQ(int_div_fNext_0$ENQ), + .DEQ(int_div_fNext_0$DEQ), + .CLR(int_div_fNext_0$CLR), + .D_OUT(int_div_fNext_0$D_OUT), + .FULL_N(int_div_fNext_0$FULL_N), + .EMPTY_N(int_div_fNext_0$EMPTY_N)); + + // submodule int_div_fNext_1 + FIFOL1 #(.width(32'd232)) int_div_fNext_1(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_1$D_IN), + .ENQ(int_div_fNext_1$ENQ), + .DEQ(int_div_fNext_1$DEQ), + .CLR(int_div_fNext_1$CLR), + .D_OUT(int_div_fNext_1$D_OUT), + .FULL_N(int_div_fNext_1$FULL_N), + .EMPTY_N(int_div_fNext_1$EMPTY_N)); + + // submodule int_div_fNext_10 + FIFOL1 #(.width(32'd232)) int_div_fNext_10(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_10$D_IN), + .ENQ(int_div_fNext_10$ENQ), + .DEQ(int_div_fNext_10$DEQ), + .CLR(int_div_fNext_10$CLR), + .D_OUT(int_div_fNext_10$D_OUT), + .FULL_N(int_div_fNext_10$FULL_N), + .EMPTY_N(int_div_fNext_10$EMPTY_N)); + + // submodule int_div_fNext_11 + FIFOL1 #(.width(32'd232)) int_div_fNext_11(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_11$D_IN), + .ENQ(int_div_fNext_11$ENQ), + .DEQ(int_div_fNext_11$DEQ), + .CLR(int_div_fNext_11$CLR), + .D_OUT(int_div_fNext_11$D_OUT), + .FULL_N(int_div_fNext_11$FULL_N), + .EMPTY_N(int_div_fNext_11$EMPTY_N)); + + // submodule int_div_fNext_12 + FIFOL1 #(.width(32'd232)) int_div_fNext_12(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_12$D_IN), + .ENQ(int_div_fNext_12$ENQ), + .DEQ(int_div_fNext_12$DEQ), + .CLR(int_div_fNext_12$CLR), + .D_OUT(int_div_fNext_12$D_OUT), + .FULL_N(int_div_fNext_12$FULL_N), + .EMPTY_N(int_div_fNext_12$EMPTY_N)); + + // submodule int_div_fNext_13 + FIFOL1 #(.width(32'd232)) int_div_fNext_13(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_13$D_IN), + .ENQ(int_div_fNext_13$ENQ), + .DEQ(int_div_fNext_13$DEQ), + .CLR(int_div_fNext_13$CLR), + .D_OUT(int_div_fNext_13$D_OUT), + .FULL_N(int_div_fNext_13$FULL_N), + .EMPTY_N(int_div_fNext_13$EMPTY_N)); + + // submodule int_div_fNext_14 + FIFOL1 #(.width(32'd232)) int_div_fNext_14(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_14$D_IN), + .ENQ(int_div_fNext_14$ENQ), + .DEQ(int_div_fNext_14$DEQ), + .CLR(int_div_fNext_14$CLR), + .D_OUT(int_div_fNext_14$D_OUT), + .FULL_N(int_div_fNext_14$FULL_N), + .EMPTY_N(int_div_fNext_14$EMPTY_N)); + + // submodule int_div_fNext_15 + FIFOL1 #(.width(32'd232)) int_div_fNext_15(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_15$D_IN), + .ENQ(int_div_fNext_15$ENQ), + .DEQ(int_div_fNext_15$DEQ), + .CLR(int_div_fNext_15$CLR), + .D_OUT(int_div_fNext_15$D_OUT), + .FULL_N(int_div_fNext_15$FULL_N), + .EMPTY_N(int_div_fNext_15$EMPTY_N)); + + // submodule int_div_fNext_16 + FIFOL1 #(.width(32'd232)) int_div_fNext_16(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_16$D_IN), + .ENQ(int_div_fNext_16$ENQ), + .DEQ(int_div_fNext_16$DEQ), + .CLR(int_div_fNext_16$CLR), + .D_OUT(int_div_fNext_16$D_OUT), + .FULL_N(int_div_fNext_16$FULL_N), + .EMPTY_N(int_div_fNext_16$EMPTY_N)); + + // submodule int_div_fNext_17 + FIFOL1 #(.width(32'd232)) int_div_fNext_17(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_17$D_IN), + .ENQ(int_div_fNext_17$ENQ), + .DEQ(int_div_fNext_17$DEQ), + .CLR(int_div_fNext_17$CLR), + .D_OUT(int_div_fNext_17$D_OUT), + .FULL_N(int_div_fNext_17$FULL_N), + .EMPTY_N(int_div_fNext_17$EMPTY_N)); + + // submodule int_div_fNext_18 + FIFOL1 #(.width(32'd232)) int_div_fNext_18(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_18$D_IN), + .ENQ(int_div_fNext_18$ENQ), + .DEQ(int_div_fNext_18$DEQ), + .CLR(int_div_fNext_18$CLR), + .D_OUT(int_div_fNext_18$D_OUT), + .FULL_N(int_div_fNext_18$FULL_N), + .EMPTY_N(int_div_fNext_18$EMPTY_N)); + + // submodule int_div_fNext_19 + FIFOL1 #(.width(32'd232)) int_div_fNext_19(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_19$D_IN), + .ENQ(int_div_fNext_19$ENQ), + .DEQ(int_div_fNext_19$DEQ), + .CLR(int_div_fNext_19$CLR), + .D_OUT(int_div_fNext_19$D_OUT), + .FULL_N(int_div_fNext_19$FULL_N), + .EMPTY_N(int_div_fNext_19$EMPTY_N)); + + // submodule int_div_fNext_2 + FIFOL1 #(.width(32'd232)) int_div_fNext_2(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_2$D_IN), + .ENQ(int_div_fNext_2$ENQ), + .DEQ(int_div_fNext_2$DEQ), + .CLR(int_div_fNext_2$CLR), + .D_OUT(int_div_fNext_2$D_OUT), + .FULL_N(int_div_fNext_2$FULL_N), + .EMPTY_N(int_div_fNext_2$EMPTY_N)); + + // submodule int_div_fNext_20 + FIFOL1 #(.width(32'd232)) int_div_fNext_20(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_20$D_IN), + .ENQ(int_div_fNext_20$ENQ), + .DEQ(int_div_fNext_20$DEQ), + .CLR(int_div_fNext_20$CLR), + .D_OUT(int_div_fNext_20$D_OUT), + .FULL_N(int_div_fNext_20$FULL_N), + .EMPTY_N(int_div_fNext_20$EMPTY_N)); + + // submodule int_div_fNext_21 + FIFOL1 #(.width(32'd232)) int_div_fNext_21(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_21$D_IN), + .ENQ(int_div_fNext_21$ENQ), + .DEQ(int_div_fNext_21$DEQ), + .CLR(int_div_fNext_21$CLR), + .D_OUT(int_div_fNext_21$D_OUT), + .FULL_N(int_div_fNext_21$FULL_N), + .EMPTY_N(int_div_fNext_21$EMPTY_N)); + + // submodule int_div_fNext_22 + FIFOL1 #(.width(32'd232)) int_div_fNext_22(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_22$D_IN), + .ENQ(int_div_fNext_22$ENQ), + .DEQ(int_div_fNext_22$DEQ), + .CLR(int_div_fNext_22$CLR), + .D_OUT(int_div_fNext_22$D_OUT), + .FULL_N(int_div_fNext_22$FULL_N), + .EMPTY_N(int_div_fNext_22$EMPTY_N)); + + // submodule int_div_fNext_23 + FIFOL1 #(.width(32'd232)) int_div_fNext_23(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_23$D_IN), + .ENQ(int_div_fNext_23$ENQ), + .DEQ(int_div_fNext_23$DEQ), + .CLR(int_div_fNext_23$CLR), + .D_OUT(int_div_fNext_23$D_OUT), + .FULL_N(int_div_fNext_23$FULL_N), + .EMPTY_N(int_div_fNext_23$EMPTY_N)); + + // submodule int_div_fNext_24 + FIFOL1 #(.width(32'd232)) int_div_fNext_24(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_24$D_IN), + .ENQ(int_div_fNext_24$ENQ), + .DEQ(int_div_fNext_24$DEQ), + .CLR(int_div_fNext_24$CLR), + .D_OUT(int_div_fNext_24$D_OUT), + .FULL_N(int_div_fNext_24$FULL_N), + .EMPTY_N(int_div_fNext_24$EMPTY_N)); + + // submodule int_div_fNext_25 + FIFOL1 #(.width(32'd232)) int_div_fNext_25(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_25$D_IN), + .ENQ(int_div_fNext_25$ENQ), + .DEQ(int_div_fNext_25$DEQ), + .CLR(int_div_fNext_25$CLR), + .D_OUT(int_div_fNext_25$D_OUT), + .FULL_N(int_div_fNext_25$FULL_N), + .EMPTY_N(int_div_fNext_25$EMPTY_N)); + + // submodule int_div_fNext_26 + FIFOL1 #(.width(32'd232)) int_div_fNext_26(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_26$D_IN), + .ENQ(int_div_fNext_26$ENQ), + .DEQ(int_div_fNext_26$DEQ), + .CLR(int_div_fNext_26$CLR), + .D_OUT(int_div_fNext_26$D_OUT), + .FULL_N(int_div_fNext_26$FULL_N), + .EMPTY_N(int_div_fNext_26$EMPTY_N)); + + // submodule int_div_fNext_27 + FIFOL1 #(.width(32'd232)) int_div_fNext_27(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_27$D_IN), + .ENQ(int_div_fNext_27$ENQ), + .DEQ(int_div_fNext_27$DEQ), + .CLR(int_div_fNext_27$CLR), + .D_OUT(int_div_fNext_27$D_OUT), + .FULL_N(int_div_fNext_27$FULL_N), + .EMPTY_N(int_div_fNext_27$EMPTY_N)); + + // submodule int_div_fNext_28 + FIFOL1 #(.width(32'd232)) int_div_fNext_28(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_28$D_IN), + .ENQ(int_div_fNext_28$ENQ), + .DEQ(int_div_fNext_28$DEQ), + .CLR(int_div_fNext_28$CLR), + .D_OUT(int_div_fNext_28$D_OUT), + .FULL_N(int_div_fNext_28$FULL_N), + .EMPTY_N(int_div_fNext_28$EMPTY_N)); + + // submodule int_div_fNext_29 + FIFOL1 #(.width(32'd232)) int_div_fNext_29(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_29$D_IN), + .ENQ(int_div_fNext_29$ENQ), + .DEQ(int_div_fNext_29$DEQ), + .CLR(int_div_fNext_29$CLR), + .D_OUT(int_div_fNext_29$D_OUT), + .FULL_N(int_div_fNext_29$FULL_N), + .EMPTY_N(int_div_fNext_29$EMPTY_N)); + + // submodule int_div_fNext_3 + FIFOL1 #(.width(32'd232)) int_div_fNext_3(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_3$D_IN), + .ENQ(int_div_fNext_3$ENQ), + .DEQ(int_div_fNext_3$DEQ), + .CLR(int_div_fNext_3$CLR), + .D_OUT(int_div_fNext_3$D_OUT), + .FULL_N(int_div_fNext_3$FULL_N), + .EMPTY_N(int_div_fNext_3$EMPTY_N)); + + // submodule int_div_fNext_30 + FIFOL1 #(.width(32'd232)) int_div_fNext_30(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_30$D_IN), + .ENQ(int_div_fNext_30$ENQ), + .DEQ(int_div_fNext_30$DEQ), + .CLR(int_div_fNext_30$CLR), + .D_OUT(int_div_fNext_30$D_OUT), + .FULL_N(int_div_fNext_30$FULL_N), + .EMPTY_N(int_div_fNext_30$EMPTY_N)); + + // submodule int_div_fNext_31 + FIFOL1 #(.width(32'd232)) int_div_fNext_31(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_31$D_IN), + .ENQ(int_div_fNext_31$ENQ), + .DEQ(int_div_fNext_31$DEQ), + .CLR(int_div_fNext_31$CLR), + .D_OUT(int_div_fNext_31$D_OUT), + .FULL_N(int_div_fNext_31$FULL_N), + .EMPTY_N(int_div_fNext_31$EMPTY_N)); + + // submodule int_div_fNext_32 + FIFOL1 #(.width(32'd232)) int_div_fNext_32(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_32$D_IN), + .ENQ(int_div_fNext_32$ENQ), + .DEQ(int_div_fNext_32$DEQ), + .CLR(int_div_fNext_32$CLR), + .D_OUT(int_div_fNext_32$D_OUT), + .FULL_N(int_div_fNext_32$FULL_N), + .EMPTY_N(int_div_fNext_32$EMPTY_N)); + + // submodule int_div_fNext_33 + FIFOL1 #(.width(32'd232)) int_div_fNext_33(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_33$D_IN), + .ENQ(int_div_fNext_33$ENQ), + .DEQ(int_div_fNext_33$DEQ), + .CLR(int_div_fNext_33$CLR), + .D_OUT(int_div_fNext_33$D_OUT), + .FULL_N(int_div_fNext_33$FULL_N), + .EMPTY_N(int_div_fNext_33$EMPTY_N)); + + // submodule int_div_fNext_34 + FIFOL1 #(.width(32'd232)) int_div_fNext_34(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_34$D_IN), + .ENQ(int_div_fNext_34$ENQ), + .DEQ(int_div_fNext_34$DEQ), + .CLR(int_div_fNext_34$CLR), + .D_OUT(int_div_fNext_34$D_OUT), + .FULL_N(int_div_fNext_34$FULL_N), + .EMPTY_N(int_div_fNext_34$EMPTY_N)); + + // submodule int_div_fNext_35 + FIFOL1 #(.width(32'd232)) int_div_fNext_35(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_35$D_IN), + .ENQ(int_div_fNext_35$ENQ), + .DEQ(int_div_fNext_35$DEQ), + .CLR(int_div_fNext_35$CLR), + .D_OUT(int_div_fNext_35$D_OUT), + .FULL_N(int_div_fNext_35$FULL_N), + .EMPTY_N(int_div_fNext_35$EMPTY_N)); + + // submodule int_div_fNext_36 + FIFOL1 #(.width(32'd232)) int_div_fNext_36(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_36$D_IN), + .ENQ(int_div_fNext_36$ENQ), + .DEQ(int_div_fNext_36$DEQ), + .CLR(int_div_fNext_36$CLR), + .D_OUT(int_div_fNext_36$D_OUT), + .FULL_N(int_div_fNext_36$FULL_N), + .EMPTY_N(int_div_fNext_36$EMPTY_N)); + + // submodule int_div_fNext_37 + FIFOL1 #(.width(32'd232)) int_div_fNext_37(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_37$D_IN), + .ENQ(int_div_fNext_37$ENQ), + .DEQ(int_div_fNext_37$DEQ), + .CLR(int_div_fNext_37$CLR), + .D_OUT(int_div_fNext_37$D_OUT), + .FULL_N(int_div_fNext_37$FULL_N), + .EMPTY_N(int_div_fNext_37$EMPTY_N)); + + // submodule int_div_fNext_38 + FIFOL1 #(.width(32'd232)) int_div_fNext_38(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_38$D_IN), + .ENQ(int_div_fNext_38$ENQ), + .DEQ(int_div_fNext_38$DEQ), + .CLR(int_div_fNext_38$CLR), + .D_OUT(int_div_fNext_38$D_OUT), + .FULL_N(int_div_fNext_38$FULL_N), + .EMPTY_N(int_div_fNext_38$EMPTY_N)); + + // submodule int_div_fNext_39 + FIFOL1 #(.width(32'd232)) int_div_fNext_39(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_39$D_IN), + .ENQ(int_div_fNext_39$ENQ), + .DEQ(int_div_fNext_39$DEQ), + .CLR(int_div_fNext_39$CLR), + .D_OUT(int_div_fNext_39$D_OUT), + .FULL_N(int_div_fNext_39$FULL_N), + .EMPTY_N(int_div_fNext_39$EMPTY_N)); + + // submodule int_div_fNext_4 + FIFOL1 #(.width(32'd232)) int_div_fNext_4(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_4$D_IN), + .ENQ(int_div_fNext_4$ENQ), + .DEQ(int_div_fNext_4$DEQ), + .CLR(int_div_fNext_4$CLR), + .D_OUT(int_div_fNext_4$D_OUT), + .FULL_N(int_div_fNext_4$FULL_N), + .EMPTY_N(int_div_fNext_4$EMPTY_N)); + + // submodule int_div_fNext_40 + FIFOL1 #(.width(32'd232)) int_div_fNext_40(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_40$D_IN), + .ENQ(int_div_fNext_40$ENQ), + .DEQ(int_div_fNext_40$DEQ), + .CLR(int_div_fNext_40$CLR), + .D_OUT(int_div_fNext_40$D_OUT), + .FULL_N(int_div_fNext_40$FULL_N), + .EMPTY_N(int_div_fNext_40$EMPTY_N)); + + // submodule int_div_fNext_41 + FIFOL1 #(.width(32'd232)) int_div_fNext_41(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_41$D_IN), + .ENQ(int_div_fNext_41$ENQ), + .DEQ(int_div_fNext_41$DEQ), + .CLR(int_div_fNext_41$CLR), + .D_OUT(int_div_fNext_41$D_OUT), + .FULL_N(int_div_fNext_41$FULL_N), + .EMPTY_N(int_div_fNext_41$EMPTY_N)); + + // submodule int_div_fNext_42 + FIFOL1 #(.width(32'd232)) int_div_fNext_42(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_42$D_IN), + .ENQ(int_div_fNext_42$ENQ), + .DEQ(int_div_fNext_42$DEQ), + .CLR(int_div_fNext_42$CLR), + .D_OUT(int_div_fNext_42$D_OUT), + .FULL_N(int_div_fNext_42$FULL_N), + .EMPTY_N(int_div_fNext_42$EMPTY_N)); + + // submodule int_div_fNext_43 + FIFOL1 #(.width(32'd232)) int_div_fNext_43(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_43$D_IN), + .ENQ(int_div_fNext_43$ENQ), + .DEQ(int_div_fNext_43$DEQ), + .CLR(int_div_fNext_43$CLR), + .D_OUT(int_div_fNext_43$D_OUT), + .FULL_N(int_div_fNext_43$FULL_N), + .EMPTY_N(int_div_fNext_43$EMPTY_N)); + + // submodule int_div_fNext_44 + FIFOL1 #(.width(32'd232)) int_div_fNext_44(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_44$D_IN), + .ENQ(int_div_fNext_44$ENQ), + .DEQ(int_div_fNext_44$DEQ), + .CLR(int_div_fNext_44$CLR), + .D_OUT(int_div_fNext_44$D_OUT), + .FULL_N(int_div_fNext_44$FULL_N), + .EMPTY_N(int_div_fNext_44$EMPTY_N)); + + // submodule int_div_fNext_45 + FIFOL1 #(.width(32'd232)) int_div_fNext_45(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_45$D_IN), + .ENQ(int_div_fNext_45$ENQ), + .DEQ(int_div_fNext_45$DEQ), + .CLR(int_div_fNext_45$CLR), + .D_OUT(int_div_fNext_45$D_OUT), + .FULL_N(int_div_fNext_45$FULL_N), + .EMPTY_N(int_div_fNext_45$EMPTY_N)); + + // submodule int_div_fNext_46 + FIFOL1 #(.width(32'd232)) int_div_fNext_46(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_46$D_IN), + .ENQ(int_div_fNext_46$ENQ), + .DEQ(int_div_fNext_46$DEQ), + .CLR(int_div_fNext_46$CLR), + .D_OUT(int_div_fNext_46$D_OUT), + .FULL_N(int_div_fNext_46$FULL_N), + .EMPTY_N(int_div_fNext_46$EMPTY_N)); + + // submodule int_div_fNext_47 + FIFOL1 #(.width(32'd232)) int_div_fNext_47(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_47$D_IN), + .ENQ(int_div_fNext_47$ENQ), + .DEQ(int_div_fNext_47$DEQ), + .CLR(int_div_fNext_47$CLR), + .D_OUT(int_div_fNext_47$D_OUT), + .FULL_N(int_div_fNext_47$FULL_N), + .EMPTY_N(int_div_fNext_47$EMPTY_N)); + + // submodule int_div_fNext_48 + FIFOL1 #(.width(32'd232)) int_div_fNext_48(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_48$D_IN), + .ENQ(int_div_fNext_48$ENQ), + .DEQ(int_div_fNext_48$DEQ), + .CLR(int_div_fNext_48$CLR), + .D_OUT(int_div_fNext_48$D_OUT), + .FULL_N(int_div_fNext_48$FULL_N), + .EMPTY_N(int_div_fNext_48$EMPTY_N)); + + // submodule int_div_fNext_49 + FIFOL1 #(.width(32'd232)) int_div_fNext_49(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_49$D_IN), + .ENQ(int_div_fNext_49$ENQ), + .DEQ(int_div_fNext_49$DEQ), + .CLR(int_div_fNext_49$CLR), + .D_OUT(int_div_fNext_49$D_OUT), + .FULL_N(int_div_fNext_49$FULL_N), + .EMPTY_N(int_div_fNext_49$EMPTY_N)); + + // submodule int_div_fNext_5 + FIFOL1 #(.width(32'd232)) int_div_fNext_5(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_5$D_IN), + .ENQ(int_div_fNext_5$ENQ), + .DEQ(int_div_fNext_5$DEQ), + .CLR(int_div_fNext_5$CLR), + .D_OUT(int_div_fNext_5$D_OUT), + .FULL_N(int_div_fNext_5$FULL_N), + .EMPTY_N(int_div_fNext_5$EMPTY_N)); + + // submodule int_div_fNext_50 + FIFOL1 #(.width(32'd232)) int_div_fNext_50(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_50$D_IN), + .ENQ(int_div_fNext_50$ENQ), + .DEQ(int_div_fNext_50$DEQ), + .CLR(int_div_fNext_50$CLR), + .D_OUT(int_div_fNext_50$D_OUT), + .FULL_N(int_div_fNext_50$FULL_N), + .EMPTY_N(int_div_fNext_50$EMPTY_N)); + + // submodule int_div_fNext_51 + FIFOL1 #(.width(32'd232)) int_div_fNext_51(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_51$D_IN), + .ENQ(int_div_fNext_51$ENQ), + .DEQ(int_div_fNext_51$DEQ), + .CLR(int_div_fNext_51$CLR), + .D_OUT(int_div_fNext_51$D_OUT), + .FULL_N(int_div_fNext_51$FULL_N), + .EMPTY_N(int_div_fNext_51$EMPTY_N)); + + // submodule int_div_fNext_52 + FIFOL1 #(.width(32'd232)) int_div_fNext_52(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_52$D_IN), + .ENQ(int_div_fNext_52$ENQ), + .DEQ(int_div_fNext_52$DEQ), + .CLR(int_div_fNext_52$CLR), + .D_OUT(int_div_fNext_52$D_OUT), + .FULL_N(int_div_fNext_52$FULL_N), + .EMPTY_N(int_div_fNext_52$EMPTY_N)); + + // submodule int_div_fNext_53 + FIFOL1 #(.width(32'd232)) int_div_fNext_53(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_53$D_IN), + .ENQ(int_div_fNext_53$ENQ), + .DEQ(int_div_fNext_53$DEQ), + .CLR(int_div_fNext_53$CLR), + .D_OUT(int_div_fNext_53$D_OUT), + .FULL_N(int_div_fNext_53$FULL_N), + .EMPTY_N(int_div_fNext_53$EMPTY_N)); + + // submodule int_div_fNext_54 + FIFOL1 #(.width(32'd232)) int_div_fNext_54(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_54$D_IN), + .ENQ(int_div_fNext_54$ENQ), + .DEQ(int_div_fNext_54$DEQ), + .CLR(int_div_fNext_54$CLR), + .D_OUT(int_div_fNext_54$D_OUT), + .FULL_N(int_div_fNext_54$FULL_N), + .EMPTY_N(int_div_fNext_54$EMPTY_N)); + + // submodule int_div_fNext_55 + FIFOL1 #(.width(32'd232)) int_div_fNext_55(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_55$D_IN), + .ENQ(int_div_fNext_55$ENQ), + .DEQ(int_div_fNext_55$DEQ), + .CLR(int_div_fNext_55$CLR), + .D_OUT(int_div_fNext_55$D_OUT), + .FULL_N(int_div_fNext_55$FULL_N), + .EMPTY_N(int_div_fNext_55$EMPTY_N)); + + // submodule int_div_fNext_56 + FIFOL1 #(.width(32'd232)) int_div_fNext_56(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_56$D_IN), + .ENQ(int_div_fNext_56$ENQ), + .DEQ(int_div_fNext_56$DEQ), + .CLR(int_div_fNext_56$CLR), + .D_OUT(int_div_fNext_56$D_OUT), + .FULL_N(int_div_fNext_56$FULL_N), + .EMPTY_N(int_div_fNext_56$EMPTY_N)); + + // submodule int_div_fNext_57 + FIFOL1 #(.width(32'd232)) int_div_fNext_57(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_57$D_IN), + .ENQ(int_div_fNext_57$ENQ), + .DEQ(int_div_fNext_57$DEQ), + .CLR(int_div_fNext_57$CLR), + .D_OUT(int_div_fNext_57$D_OUT), + .FULL_N(int_div_fNext_57$FULL_N), + .EMPTY_N(int_div_fNext_57$EMPTY_N)); + + // submodule int_div_fNext_6 + FIFOL1 #(.width(32'd232)) int_div_fNext_6(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_6$D_IN), + .ENQ(int_div_fNext_6$ENQ), + .DEQ(int_div_fNext_6$DEQ), + .CLR(int_div_fNext_6$CLR), + .D_OUT(int_div_fNext_6$D_OUT), + .FULL_N(int_div_fNext_6$FULL_N), + .EMPTY_N(int_div_fNext_6$EMPTY_N)); + + // submodule int_div_fNext_7 + FIFOL1 #(.width(32'd232)) int_div_fNext_7(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_7$D_IN), + .ENQ(int_div_fNext_7$ENQ), + .DEQ(int_div_fNext_7$DEQ), + .CLR(int_div_fNext_7$CLR), + .D_OUT(int_div_fNext_7$D_OUT), + .FULL_N(int_div_fNext_7$FULL_N), + .EMPTY_N(int_div_fNext_7$EMPTY_N)); + + // submodule int_div_fNext_8 + FIFOL1 #(.width(32'd232)) int_div_fNext_8(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_8$D_IN), + .ENQ(int_div_fNext_8$ENQ), + .DEQ(int_div_fNext_8$DEQ), + .CLR(int_div_fNext_8$CLR), + .D_OUT(int_div_fNext_8$D_OUT), + .FULL_N(int_div_fNext_8$FULL_N), + .EMPTY_N(int_div_fNext_8$EMPTY_N)); + + // submodule int_div_fNext_9 + FIFOL1 #(.width(32'd232)) int_div_fNext_9(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_9$D_IN), + .ENQ(int_div_fNext_9$ENQ), + .DEQ(int_div_fNext_9$DEQ), + .CLR(int_div_fNext_9$CLR), + .D_OUT(int_div_fNext_9$D_OUT), + .FULL_N(int_div_fNext_9$FULL_N), + .EMPTY_N(int_div_fNext_9$EMPTY_N)); + + // submodule int_div_fRequest + FIFOL1 #(.width(32'd171)) int_div_fRequest(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fRequest$D_IN), + .ENQ(int_div_fRequest$ENQ), + .DEQ(int_div_fRequest$DEQ), + .CLR(int_div_fRequest$CLR), + .D_OUT(int_div_fRequest$D_OUT), + .FULL_N(int_div_fRequest$FULL_N), + .EMPTY_N(int_div_fRequest$EMPTY_N)); + + // submodule int_div_fResponse + FIFOL1 #(.width(32'd114)) int_div_fResponse(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fResponse$D_IN), + .ENQ(int_div_fResponse$ENQ), + .DEQ(int_div_fResponse$DEQ), + .CLR(int_div_fResponse$CLR), + .D_OUT(int_div_fResponse$D_OUT), + .FULL_N(int_div_fResponse$FULL_N), + .EMPTY_N(int_div_fResponse$EMPTY_N)); + + // rule RL_fpu_s5_stage + assign CAN_FIRE_RL_fpu_s5_stage = + fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; + assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; + + // rule RL_fpu_s4_stage + assign CAN_FIRE_RL_fpu_s4_stage = + fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; + assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; + + // rule RL_fpu_s3_stage + assign CAN_FIRE_RL_fpu_s3_stage = + fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && + (fpu_fState_S2$D_OUT[147] || int_div_fResponse$EMPTY_N) ; + assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; + + // rule RL_int_div_finish + assign CAN_FIRE_RL_int_div_finish = + int_div_fNext_57$EMPTY_N && int_div_fResponse$FULL_N ; + assign WILL_FIRE_RL_int_div_finish = CAN_FIRE_RL_int_div_finish ; + + // rule RL_int_div_work_57 + assign CAN_FIRE_RL_int_div_work_57 = + int_div_fNext_56$EMPTY_N && int_div_fNext_57$FULL_N ; + assign WILL_FIRE_RL_int_div_work_57 = CAN_FIRE_RL_int_div_work_57 ; + + // rule RL_int_div_work_56 + assign CAN_FIRE_RL_int_div_work_56 = + int_div_fNext_55$EMPTY_N && int_div_fNext_56$FULL_N ; + assign WILL_FIRE_RL_int_div_work_56 = CAN_FIRE_RL_int_div_work_56 ; + + // rule RL_int_div_work_55 + assign CAN_FIRE_RL_int_div_work_55 = + int_div_fNext_54$EMPTY_N && int_div_fNext_55$FULL_N ; + assign WILL_FIRE_RL_int_div_work_55 = CAN_FIRE_RL_int_div_work_55 ; + + // rule RL_int_div_work_54 + assign CAN_FIRE_RL_int_div_work_54 = + int_div_fNext_53$EMPTY_N && int_div_fNext_54$FULL_N ; + assign WILL_FIRE_RL_int_div_work_54 = CAN_FIRE_RL_int_div_work_54 ; + + // rule RL_int_div_work_53 + assign CAN_FIRE_RL_int_div_work_53 = + int_div_fNext_52$EMPTY_N && int_div_fNext_53$FULL_N ; + assign WILL_FIRE_RL_int_div_work_53 = CAN_FIRE_RL_int_div_work_53 ; + + // rule RL_int_div_work_52 + assign CAN_FIRE_RL_int_div_work_52 = + int_div_fNext_51$EMPTY_N && int_div_fNext_52$FULL_N ; + assign WILL_FIRE_RL_int_div_work_52 = CAN_FIRE_RL_int_div_work_52 ; + + // rule RL_int_div_work_51 + assign CAN_FIRE_RL_int_div_work_51 = + int_div_fNext_50$EMPTY_N && int_div_fNext_51$FULL_N ; + assign WILL_FIRE_RL_int_div_work_51 = CAN_FIRE_RL_int_div_work_51 ; + + // rule RL_int_div_work_50 + assign CAN_FIRE_RL_int_div_work_50 = + int_div_fNext_49$EMPTY_N && int_div_fNext_50$FULL_N ; + assign WILL_FIRE_RL_int_div_work_50 = CAN_FIRE_RL_int_div_work_50 ; + + // rule RL_int_div_work_49 + assign CAN_FIRE_RL_int_div_work_49 = + int_div_fNext_48$EMPTY_N && int_div_fNext_49$FULL_N ; + assign WILL_FIRE_RL_int_div_work_49 = CAN_FIRE_RL_int_div_work_49 ; + + // rule RL_int_div_work_48 + assign CAN_FIRE_RL_int_div_work_48 = + int_div_fNext_47$EMPTY_N && int_div_fNext_48$FULL_N ; + assign WILL_FIRE_RL_int_div_work_48 = CAN_FIRE_RL_int_div_work_48 ; + + // rule RL_int_div_work_47 + assign CAN_FIRE_RL_int_div_work_47 = + int_div_fNext_46$EMPTY_N && int_div_fNext_47$FULL_N ; + assign WILL_FIRE_RL_int_div_work_47 = CAN_FIRE_RL_int_div_work_47 ; + + // rule RL_int_div_work_46 + assign CAN_FIRE_RL_int_div_work_46 = + int_div_fNext_45$EMPTY_N && int_div_fNext_46$FULL_N ; + assign WILL_FIRE_RL_int_div_work_46 = CAN_FIRE_RL_int_div_work_46 ; + + // rule RL_int_div_work_45 + assign CAN_FIRE_RL_int_div_work_45 = + int_div_fNext_44$EMPTY_N && int_div_fNext_45$FULL_N ; + assign WILL_FIRE_RL_int_div_work_45 = CAN_FIRE_RL_int_div_work_45 ; + + // rule RL_int_div_work_44 + assign CAN_FIRE_RL_int_div_work_44 = + int_div_fNext_43$EMPTY_N && int_div_fNext_44$FULL_N ; + assign WILL_FIRE_RL_int_div_work_44 = CAN_FIRE_RL_int_div_work_44 ; + + // rule RL_int_div_work_43 + assign CAN_FIRE_RL_int_div_work_43 = + int_div_fNext_42$EMPTY_N && int_div_fNext_43$FULL_N ; + assign WILL_FIRE_RL_int_div_work_43 = CAN_FIRE_RL_int_div_work_43 ; + + // rule RL_int_div_work_42 + assign CAN_FIRE_RL_int_div_work_42 = + int_div_fNext_41$EMPTY_N && int_div_fNext_42$FULL_N ; + assign WILL_FIRE_RL_int_div_work_42 = CAN_FIRE_RL_int_div_work_42 ; + + // rule RL_int_div_work_41 + assign CAN_FIRE_RL_int_div_work_41 = + int_div_fNext_40$EMPTY_N && int_div_fNext_41$FULL_N ; + assign WILL_FIRE_RL_int_div_work_41 = CAN_FIRE_RL_int_div_work_41 ; + + // rule RL_int_div_work_40 + assign CAN_FIRE_RL_int_div_work_40 = + int_div_fNext_39$EMPTY_N && int_div_fNext_40$FULL_N ; + assign WILL_FIRE_RL_int_div_work_40 = CAN_FIRE_RL_int_div_work_40 ; + + // rule RL_int_div_work_39 + assign CAN_FIRE_RL_int_div_work_39 = + int_div_fNext_38$EMPTY_N && int_div_fNext_39$FULL_N ; + assign WILL_FIRE_RL_int_div_work_39 = CAN_FIRE_RL_int_div_work_39 ; + + // rule RL_int_div_work_38 + assign CAN_FIRE_RL_int_div_work_38 = + int_div_fNext_37$EMPTY_N && int_div_fNext_38$FULL_N ; + assign WILL_FIRE_RL_int_div_work_38 = CAN_FIRE_RL_int_div_work_38 ; + + // rule RL_int_div_work_37 + assign CAN_FIRE_RL_int_div_work_37 = + int_div_fNext_36$EMPTY_N && int_div_fNext_37$FULL_N ; + assign WILL_FIRE_RL_int_div_work_37 = CAN_FIRE_RL_int_div_work_37 ; + + // rule RL_int_div_work_36 + assign CAN_FIRE_RL_int_div_work_36 = + int_div_fNext_35$EMPTY_N && int_div_fNext_36$FULL_N ; + assign WILL_FIRE_RL_int_div_work_36 = CAN_FIRE_RL_int_div_work_36 ; + + // rule RL_int_div_work_35 + assign CAN_FIRE_RL_int_div_work_35 = + int_div_fNext_34$EMPTY_N && int_div_fNext_35$FULL_N ; + assign WILL_FIRE_RL_int_div_work_35 = CAN_FIRE_RL_int_div_work_35 ; + + // rule RL_int_div_work_34 + assign CAN_FIRE_RL_int_div_work_34 = + int_div_fNext_33$EMPTY_N && int_div_fNext_34$FULL_N ; + assign WILL_FIRE_RL_int_div_work_34 = CAN_FIRE_RL_int_div_work_34 ; + + // rule RL_int_div_work_33 + assign CAN_FIRE_RL_int_div_work_33 = + int_div_fNext_32$EMPTY_N && int_div_fNext_33$FULL_N ; + assign WILL_FIRE_RL_int_div_work_33 = CAN_FIRE_RL_int_div_work_33 ; + + // rule RL_int_div_work_32 + assign CAN_FIRE_RL_int_div_work_32 = + int_div_fNext_31$EMPTY_N && int_div_fNext_32$FULL_N ; + assign WILL_FIRE_RL_int_div_work_32 = CAN_FIRE_RL_int_div_work_32 ; + + // rule RL_int_div_work_31 + assign CAN_FIRE_RL_int_div_work_31 = + int_div_fNext_30$EMPTY_N && int_div_fNext_31$FULL_N ; + assign WILL_FIRE_RL_int_div_work_31 = CAN_FIRE_RL_int_div_work_31 ; + + // rule RL_int_div_work_30 + assign CAN_FIRE_RL_int_div_work_30 = + int_div_fNext_29$EMPTY_N && int_div_fNext_30$FULL_N ; + assign WILL_FIRE_RL_int_div_work_30 = CAN_FIRE_RL_int_div_work_30 ; + + // rule RL_int_div_work_29 + assign CAN_FIRE_RL_int_div_work_29 = + int_div_fNext_28$EMPTY_N && int_div_fNext_29$FULL_N ; + assign WILL_FIRE_RL_int_div_work_29 = CAN_FIRE_RL_int_div_work_29 ; + + // rule RL_int_div_work_28 + assign CAN_FIRE_RL_int_div_work_28 = + int_div_fNext_27$EMPTY_N && int_div_fNext_28$FULL_N ; + assign WILL_FIRE_RL_int_div_work_28 = CAN_FIRE_RL_int_div_work_28 ; + + // rule RL_int_div_work_27 + assign CAN_FIRE_RL_int_div_work_27 = + int_div_fNext_26$EMPTY_N && int_div_fNext_27$FULL_N ; + assign WILL_FIRE_RL_int_div_work_27 = CAN_FIRE_RL_int_div_work_27 ; + + // rule RL_int_div_work_26 + assign CAN_FIRE_RL_int_div_work_26 = + int_div_fNext_25$EMPTY_N && int_div_fNext_26$FULL_N ; + assign WILL_FIRE_RL_int_div_work_26 = CAN_FIRE_RL_int_div_work_26 ; + + // rule RL_int_div_work_25 + assign CAN_FIRE_RL_int_div_work_25 = + int_div_fNext_24$EMPTY_N && int_div_fNext_25$FULL_N ; + assign WILL_FIRE_RL_int_div_work_25 = CAN_FIRE_RL_int_div_work_25 ; + + // rule RL_int_div_work_24 + assign CAN_FIRE_RL_int_div_work_24 = + int_div_fNext_23$EMPTY_N && int_div_fNext_24$FULL_N ; + assign WILL_FIRE_RL_int_div_work_24 = CAN_FIRE_RL_int_div_work_24 ; + + // rule RL_int_div_work_23 + assign CAN_FIRE_RL_int_div_work_23 = + int_div_fNext_22$EMPTY_N && int_div_fNext_23$FULL_N ; + assign WILL_FIRE_RL_int_div_work_23 = CAN_FIRE_RL_int_div_work_23 ; + + // rule RL_int_div_work_22 + assign CAN_FIRE_RL_int_div_work_22 = + int_div_fNext_21$EMPTY_N && int_div_fNext_22$FULL_N ; + assign WILL_FIRE_RL_int_div_work_22 = CAN_FIRE_RL_int_div_work_22 ; + + // rule RL_int_div_work_21 + assign CAN_FIRE_RL_int_div_work_21 = + int_div_fNext_20$EMPTY_N && int_div_fNext_21$FULL_N ; + assign WILL_FIRE_RL_int_div_work_21 = CAN_FIRE_RL_int_div_work_21 ; + + // rule RL_int_div_work_20 + assign CAN_FIRE_RL_int_div_work_20 = + int_div_fNext_19$EMPTY_N && int_div_fNext_20$FULL_N ; + assign WILL_FIRE_RL_int_div_work_20 = CAN_FIRE_RL_int_div_work_20 ; + + // rule RL_int_div_work_19 + assign CAN_FIRE_RL_int_div_work_19 = + int_div_fNext_18$EMPTY_N && int_div_fNext_19$FULL_N ; + assign WILL_FIRE_RL_int_div_work_19 = CAN_FIRE_RL_int_div_work_19 ; + + // rule RL_int_div_work_18 + assign CAN_FIRE_RL_int_div_work_18 = + int_div_fNext_17$EMPTY_N && int_div_fNext_18$FULL_N ; + assign WILL_FIRE_RL_int_div_work_18 = CAN_FIRE_RL_int_div_work_18 ; + + // rule RL_int_div_work_17 + assign CAN_FIRE_RL_int_div_work_17 = + int_div_fNext_16$EMPTY_N && int_div_fNext_17$FULL_N ; + assign WILL_FIRE_RL_int_div_work_17 = CAN_FIRE_RL_int_div_work_17 ; + + // rule RL_int_div_work_16 + assign CAN_FIRE_RL_int_div_work_16 = + int_div_fNext_15$EMPTY_N && int_div_fNext_16$FULL_N ; + assign WILL_FIRE_RL_int_div_work_16 = CAN_FIRE_RL_int_div_work_16 ; + + // rule RL_int_div_work_15 + assign CAN_FIRE_RL_int_div_work_15 = + int_div_fNext_14$EMPTY_N && int_div_fNext_15$FULL_N ; + assign WILL_FIRE_RL_int_div_work_15 = CAN_FIRE_RL_int_div_work_15 ; + + // rule RL_int_div_work_14 + assign CAN_FIRE_RL_int_div_work_14 = + int_div_fNext_13$EMPTY_N && int_div_fNext_14$FULL_N ; + assign WILL_FIRE_RL_int_div_work_14 = CAN_FIRE_RL_int_div_work_14 ; + + // rule RL_int_div_work_13 + assign CAN_FIRE_RL_int_div_work_13 = + int_div_fNext_12$EMPTY_N && int_div_fNext_13$FULL_N ; + assign WILL_FIRE_RL_int_div_work_13 = CAN_FIRE_RL_int_div_work_13 ; + + // rule RL_int_div_work_12 + assign CAN_FIRE_RL_int_div_work_12 = + int_div_fNext_11$EMPTY_N && int_div_fNext_12$FULL_N ; + assign WILL_FIRE_RL_int_div_work_12 = CAN_FIRE_RL_int_div_work_12 ; + + // rule RL_int_div_work_11 + assign CAN_FIRE_RL_int_div_work_11 = + int_div_fNext_10$EMPTY_N && int_div_fNext_11$FULL_N ; + assign WILL_FIRE_RL_int_div_work_11 = CAN_FIRE_RL_int_div_work_11 ; + + // rule RL_int_div_work_10 + assign CAN_FIRE_RL_int_div_work_10 = + int_div_fNext_9$EMPTY_N && int_div_fNext_10$FULL_N ; + assign WILL_FIRE_RL_int_div_work_10 = CAN_FIRE_RL_int_div_work_10 ; + + // rule RL_int_div_work_9 + assign CAN_FIRE_RL_int_div_work_9 = + int_div_fNext_8$EMPTY_N && int_div_fNext_9$FULL_N ; + assign WILL_FIRE_RL_int_div_work_9 = CAN_FIRE_RL_int_div_work_9 ; + + // rule RL_int_div_work_8 + assign CAN_FIRE_RL_int_div_work_8 = + int_div_fNext_7$EMPTY_N && int_div_fNext_8$FULL_N ; + assign WILL_FIRE_RL_int_div_work_8 = CAN_FIRE_RL_int_div_work_8 ; + + // rule RL_int_div_work_7 + assign CAN_FIRE_RL_int_div_work_7 = + int_div_fNext_6$EMPTY_N && int_div_fNext_7$FULL_N ; + assign WILL_FIRE_RL_int_div_work_7 = CAN_FIRE_RL_int_div_work_7 ; + + // rule RL_int_div_work_6 + assign CAN_FIRE_RL_int_div_work_6 = + int_div_fNext_5$EMPTY_N && int_div_fNext_6$FULL_N ; + assign WILL_FIRE_RL_int_div_work_6 = CAN_FIRE_RL_int_div_work_6 ; + + // rule RL_int_div_work_5 + assign CAN_FIRE_RL_int_div_work_5 = + int_div_fNext_4$EMPTY_N && int_div_fNext_5$FULL_N ; + assign WILL_FIRE_RL_int_div_work_5 = CAN_FIRE_RL_int_div_work_5 ; + + // rule RL_int_div_work_4 + assign CAN_FIRE_RL_int_div_work_4 = + int_div_fNext_3$EMPTY_N && int_div_fNext_4$FULL_N ; + assign WILL_FIRE_RL_int_div_work_4 = CAN_FIRE_RL_int_div_work_4 ; + + // rule RL_int_div_work_3 + assign CAN_FIRE_RL_int_div_work_3 = + int_div_fNext_2$EMPTY_N && int_div_fNext_3$FULL_N ; + assign WILL_FIRE_RL_int_div_work_3 = CAN_FIRE_RL_int_div_work_3 ; + + // rule RL_int_div_work_2 + assign CAN_FIRE_RL_int_div_work_2 = + int_div_fNext_1$EMPTY_N && int_div_fNext_2$FULL_N ; + assign WILL_FIRE_RL_int_div_work_2 = CAN_FIRE_RL_int_div_work_2 ; + + // rule RL_int_div_work_1 + assign CAN_FIRE_RL_int_div_work_1 = + int_div_fNext_0$EMPTY_N && int_div_fNext_1$FULL_N ; + assign WILL_FIRE_RL_int_div_work_1 = CAN_FIRE_RL_int_div_work_1 ; + + // rule RL_int_div_work + assign CAN_FIRE_RL_int_div_work = + int_div_fFirst$EMPTY_N && int_div_fNext_0$FULL_N ; + assign WILL_FIRE_RL_int_div_work = CAN_FIRE_RL_int_div_work ; + + // rule RL_int_div_start + assign CAN_FIRE_RL_int_div_start = + int_div_fRequest$EMPTY_N && int_div_fFirst$FULL_N ; + assign WILL_FIRE_RL_int_div_start = CAN_FIRE_RL_int_div_start ; + + // rule RL_fpu_s2_stage + assign CAN_FIRE_RL_fpu_s2_stage = + fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && + (fpu_fState_S1$D_OUT[318] || int_div_fRequest$FULL_N) ; + assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; + + // rule RL_fpu_s1_stage + assign CAN_FIRE_RL_fpu_s1_stage = + fpu_fOperands_S0$EMPTY_N && fpu_fState_S1$FULL_N ; + assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; + + // submodule fpu_fOperands_S0 + assign fpu_fOperands_S0$D_IN = request_put ; + assign fpu_fOperands_S0$ENQ = EN_request_put ; + assign fpu_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fOperands_S0$CLR = 1'b0 ; + + // submodule fpu_fResult_S5 + assign fpu_fResult_S5$D_IN = + fpu_fState_S4$D_OUT[138] ? + fpu_fState_S4$D_OUT[137:69] : + { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[65:2] : + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16, + fpu_fState_S4$D_OUT[73:69] | + { 2'd0, + _theResult___fst_exp__h60991 == 11'd2047 && + _theResult___fst_sfd__h60992 == 52'd0, + 1'd0, + fpu_fState_S4$D_OUT[64:54] != 11'd2047 && + fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; + assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fResult_S5$DEQ = EN_response_get ; + assign fpu_fResult_S5$CLR = 1'b0 ; + + // submodule fpu_fState_S1 + assign fpu_fState_S1$D_IN = + { fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, + (fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118]) ? + { fpu_fOperands_S0$D_OUT[130:119], sfd__h36684 } : + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54] || + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0), + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, + fpu_fOperands_S0$D_OUT[2:0], + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, + _theResult___snd_fst_exp__h49111, + _theResult___snd_fst_sfd__h49112, + x__h49176, + x__h49237, + x__h49291 } ; + assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S1$CLR = 1'b0 ; + + // submodule fpu_fState_S2 + assign fpu_fState_S2$D_IN = + { fpu_fState_S1$D_OUT[318:182], fpu_fState_S1$D_OUT[10:0] } ; + assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S2$CLR = 1'b0 ; + + // submodule fpu_fState_S3 + assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT[147:11], x__h50487 } ; + assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S3$CLR = 1'b0 ; + + // submodule fpu_fState_S4 + assign fpu_fState_S4$D_IN = + { (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[194] : + fpu_fState_S3$D_OUT[194], + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + fpu_fState_S3$D_OUT[193:130] : + { CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 }) : + fpu_fState_S3$D_OUT[193:130], + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, + fpu_fState_S3$D_OUT[124:122], + fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780, + x__h60140 } ; + assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S4$CLR = 1'b0 ; + + // submodule int_div_fFirst + assign int_div_fFirst$D_IN = + { b__h378, 60'd0, int_div_fRequest$D_OUT[170:57] } ; + assign int_div_fFirst$ENQ = CAN_FIRE_RL_int_div_start ; + assign int_div_fFirst$DEQ = CAN_FIRE_RL_int_div_work ; + assign int_div_fFirst$CLR = 1'b0 ; + + // submodule int_div_fNext_0 + assign int_div_fNext_0$D_IN = + { int_div_fFirst$D_OUT[231:174], + int_div_fFirst$D_OUT[172:116], + !int_div_fFirst$D_OUT[115], + int_div_fFirst$D_OUT[115] ? + { int_div_fFirst$D_OUT[114:0], 1'd0 } + b__h767 : + { int_div_fFirst$D_OUT[114:0], 1'd0 } - b__h767 } ; + assign int_div_fNext_0$ENQ = CAN_FIRE_RL_int_div_work ; + assign int_div_fNext_0$DEQ = CAN_FIRE_RL_int_div_work_1 ; + assign int_div_fNext_0$CLR = 1'b0 ; + + // submodule int_div_fNext_1 + assign int_div_fNext_1$D_IN = + { int_div_fNext_0$D_OUT[231:174], + int_div_fNext_0$D_OUT[172:116], + !int_div_fNext_0$D_OUT[115], + int_div_fNext_0$D_OUT[115] ? + { int_div_fNext_0$D_OUT[114:0], 1'd0 } + b__h1091 : + { int_div_fNext_0$D_OUT[114:0], 1'd0 } - b__h1091 } ; + assign int_div_fNext_1$ENQ = CAN_FIRE_RL_int_div_work_1 ; + assign int_div_fNext_1$DEQ = CAN_FIRE_RL_int_div_work_2 ; + assign int_div_fNext_1$CLR = 1'b0 ; + + // submodule int_div_fNext_10 + assign int_div_fNext_10$D_IN = + { int_div_fNext_9$D_OUT[231:174], + int_div_fNext_9$D_OUT[172:116], + !int_div_fNext_9$D_OUT[115], + int_div_fNext_9$D_OUT[115] ? + { int_div_fNext_9$D_OUT[114:0], 1'd0 } + b__h4007 : + { int_div_fNext_9$D_OUT[114:0], 1'd0 } - b__h4007 } ; + assign int_div_fNext_10$ENQ = CAN_FIRE_RL_int_div_work_10 ; + assign int_div_fNext_10$DEQ = CAN_FIRE_RL_int_div_work_11 ; + assign int_div_fNext_10$CLR = 1'b0 ; + + // submodule int_div_fNext_11 + assign int_div_fNext_11$D_IN = + { int_div_fNext_10$D_OUT[231:174], + int_div_fNext_10$D_OUT[172:116], + !int_div_fNext_10$D_OUT[115], + int_div_fNext_10$D_OUT[115] ? + { int_div_fNext_10$D_OUT[114:0], 1'd0 } + b__h4331 : + { int_div_fNext_10$D_OUT[114:0], 1'd0 } - b__h4331 } ; + assign int_div_fNext_11$ENQ = CAN_FIRE_RL_int_div_work_11 ; + assign int_div_fNext_11$DEQ = CAN_FIRE_RL_int_div_work_12 ; + assign int_div_fNext_11$CLR = 1'b0 ; + + // submodule int_div_fNext_12 + assign int_div_fNext_12$D_IN = + { int_div_fNext_11$D_OUT[231:174], + int_div_fNext_11$D_OUT[172:116], + !int_div_fNext_11$D_OUT[115], + int_div_fNext_11$D_OUT[115] ? + { int_div_fNext_11$D_OUT[114:0], 1'd0 } + b__h4655 : + { int_div_fNext_11$D_OUT[114:0], 1'd0 } - b__h4655 } ; + assign int_div_fNext_12$ENQ = CAN_FIRE_RL_int_div_work_12 ; + assign int_div_fNext_12$DEQ = CAN_FIRE_RL_int_div_work_13 ; + assign int_div_fNext_12$CLR = 1'b0 ; + + // submodule int_div_fNext_13 + assign int_div_fNext_13$D_IN = + { int_div_fNext_12$D_OUT[231:174], + int_div_fNext_12$D_OUT[172:116], + !int_div_fNext_12$D_OUT[115], + int_div_fNext_12$D_OUT[115] ? + { int_div_fNext_12$D_OUT[114:0], 1'd0 } + b__h4979 : + { int_div_fNext_12$D_OUT[114:0], 1'd0 } - b__h4979 } ; + assign int_div_fNext_13$ENQ = CAN_FIRE_RL_int_div_work_13 ; + assign int_div_fNext_13$DEQ = CAN_FIRE_RL_int_div_work_14 ; + assign int_div_fNext_13$CLR = 1'b0 ; + + // submodule int_div_fNext_14 + assign int_div_fNext_14$D_IN = + { int_div_fNext_13$D_OUT[231:174], + int_div_fNext_13$D_OUT[172:116], + !int_div_fNext_13$D_OUT[115], + int_div_fNext_13$D_OUT[115] ? + { int_div_fNext_13$D_OUT[114:0], 1'd0 } + b__h5303 : + { int_div_fNext_13$D_OUT[114:0], 1'd0 } - b__h5303 } ; + assign int_div_fNext_14$ENQ = CAN_FIRE_RL_int_div_work_14 ; + assign int_div_fNext_14$DEQ = CAN_FIRE_RL_int_div_work_15 ; + assign int_div_fNext_14$CLR = 1'b0 ; + + // submodule int_div_fNext_15 + assign int_div_fNext_15$D_IN = + { int_div_fNext_14$D_OUT[231:174], + int_div_fNext_14$D_OUT[172:116], + !int_div_fNext_14$D_OUT[115], + int_div_fNext_14$D_OUT[115] ? + { int_div_fNext_14$D_OUT[114:0], 1'd0 } + b__h5627 : + { int_div_fNext_14$D_OUT[114:0], 1'd0 } - b__h5627 } ; + assign int_div_fNext_15$ENQ = CAN_FIRE_RL_int_div_work_15 ; + assign int_div_fNext_15$DEQ = CAN_FIRE_RL_int_div_work_16 ; + assign int_div_fNext_15$CLR = 1'b0 ; + + // submodule int_div_fNext_16 + assign int_div_fNext_16$D_IN = + { int_div_fNext_15$D_OUT[231:174], + int_div_fNext_15$D_OUT[172:116], + !int_div_fNext_15$D_OUT[115], + int_div_fNext_15$D_OUT[115] ? + { int_div_fNext_15$D_OUT[114:0], 1'd0 } + b__h5951 : + { int_div_fNext_15$D_OUT[114:0], 1'd0 } - b__h5951 } ; + assign int_div_fNext_16$ENQ = CAN_FIRE_RL_int_div_work_16 ; + assign int_div_fNext_16$DEQ = CAN_FIRE_RL_int_div_work_17 ; + assign int_div_fNext_16$CLR = 1'b0 ; + + // submodule int_div_fNext_17 + assign int_div_fNext_17$D_IN = + { int_div_fNext_16$D_OUT[231:174], + int_div_fNext_16$D_OUT[172:116], + !int_div_fNext_16$D_OUT[115], + int_div_fNext_16$D_OUT[115] ? + { int_div_fNext_16$D_OUT[114:0], 1'd0 } + b__h6275 : + { int_div_fNext_16$D_OUT[114:0], 1'd0 } - b__h6275 } ; + assign int_div_fNext_17$ENQ = CAN_FIRE_RL_int_div_work_17 ; + assign int_div_fNext_17$DEQ = CAN_FIRE_RL_int_div_work_18 ; + assign int_div_fNext_17$CLR = 1'b0 ; + + // submodule int_div_fNext_18 + assign int_div_fNext_18$D_IN = + { int_div_fNext_17$D_OUT[231:174], + int_div_fNext_17$D_OUT[172:116], + !int_div_fNext_17$D_OUT[115], + int_div_fNext_17$D_OUT[115] ? + { int_div_fNext_17$D_OUT[114:0], 1'd0 } + b__h6599 : + { int_div_fNext_17$D_OUT[114:0], 1'd0 } - b__h6599 } ; + assign int_div_fNext_18$ENQ = CAN_FIRE_RL_int_div_work_18 ; + assign int_div_fNext_18$DEQ = CAN_FIRE_RL_int_div_work_19 ; + assign int_div_fNext_18$CLR = 1'b0 ; + + // submodule int_div_fNext_19 + assign int_div_fNext_19$D_IN = + { int_div_fNext_18$D_OUT[231:174], + int_div_fNext_18$D_OUT[172:116], + !int_div_fNext_18$D_OUT[115], + int_div_fNext_18$D_OUT[115] ? + { int_div_fNext_18$D_OUT[114:0], 1'd0 } + b__h6923 : + { int_div_fNext_18$D_OUT[114:0], 1'd0 } - b__h6923 } ; + assign int_div_fNext_19$ENQ = CAN_FIRE_RL_int_div_work_19 ; + assign int_div_fNext_19$DEQ = CAN_FIRE_RL_int_div_work_20 ; + assign int_div_fNext_19$CLR = 1'b0 ; + + // submodule int_div_fNext_2 + assign int_div_fNext_2$D_IN = + { int_div_fNext_1$D_OUT[231:174], + int_div_fNext_1$D_OUT[172:116], + !int_div_fNext_1$D_OUT[115], + int_div_fNext_1$D_OUT[115] ? + { int_div_fNext_1$D_OUT[114:0], 1'd0 } + b__h1415 : + { int_div_fNext_1$D_OUT[114:0], 1'd0 } - b__h1415 } ; + assign int_div_fNext_2$ENQ = CAN_FIRE_RL_int_div_work_2 ; + assign int_div_fNext_2$DEQ = CAN_FIRE_RL_int_div_work_3 ; + assign int_div_fNext_2$CLR = 1'b0 ; + + // submodule int_div_fNext_20 + assign int_div_fNext_20$D_IN = + { int_div_fNext_19$D_OUT[231:174], + int_div_fNext_19$D_OUT[172:116], + !int_div_fNext_19$D_OUT[115], + int_div_fNext_19$D_OUT[115] ? + { int_div_fNext_19$D_OUT[114:0], 1'd0 } + b__h7247 : + { int_div_fNext_19$D_OUT[114:0], 1'd0 } - b__h7247 } ; + assign int_div_fNext_20$ENQ = CAN_FIRE_RL_int_div_work_20 ; + assign int_div_fNext_20$DEQ = CAN_FIRE_RL_int_div_work_21 ; + assign int_div_fNext_20$CLR = 1'b0 ; + + // submodule int_div_fNext_21 + assign int_div_fNext_21$D_IN = + { int_div_fNext_20$D_OUT[231:174], + int_div_fNext_20$D_OUT[172:116], + !int_div_fNext_20$D_OUT[115], + int_div_fNext_20$D_OUT[115] ? + { int_div_fNext_20$D_OUT[114:0], 1'd0 } + b__h7571 : + { int_div_fNext_20$D_OUT[114:0], 1'd0 } - b__h7571 } ; + assign int_div_fNext_21$ENQ = CAN_FIRE_RL_int_div_work_21 ; + assign int_div_fNext_21$DEQ = CAN_FIRE_RL_int_div_work_22 ; + assign int_div_fNext_21$CLR = 1'b0 ; + + // submodule int_div_fNext_22 + assign int_div_fNext_22$D_IN = + { int_div_fNext_21$D_OUT[231:174], + int_div_fNext_21$D_OUT[172:116], + !int_div_fNext_21$D_OUT[115], + int_div_fNext_21$D_OUT[115] ? + { int_div_fNext_21$D_OUT[114:0], 1'd0 } + b__h7895 : + { int_div_fNext_21$D_OUT[114:0], 1'd0 } - b__h7895 } ; + assign int_div_fNext_22$ENQ = CAN_FIRE_RL_int_div_work_22 ; + assign int_div_fNext_22$DEQ = CAN_FIRE_RL_int_div_work_23 ; + assign int_div_fNext_22$CLR = 1'b0 ; + + // submodule int_div_fNext_23 + assign int_div_fNext_23$D_IN = + { int_div_fNext_22$D_OUT[231:174], + int_div_fNext_22$D_OUT[172:116], + !int_div_fNext_22$D_OUT[115], + int_div_fNext_22$D_OUT[115] ? + { int_div_fNext_22$D_OUT[114:0], 1'd0 } + b__h8219 : + { int_div_fNext_22$D_OUT[114:0], 1'd0 } - b__h8219 } ; + assign int_div_fNext_23$ENQ = CAN_FIRE_RL_int_div_work_23 ; + assign int_div_fNext_23$DEQ = CAN_FIRE_RL_int_div_work_24 ; + assign int_div_fNext_23$CLR = 1'b0 ; + + // submodule int_div_fNext_24 + assign int_div_fNext_24$D_IN = + { int_div_fNext_23$D_OUT[231:174], + int_div_fNext_23$D_OUT[172:116], + !int_div_fNext_23$D_OUT[115], + int_div_fNext_23$D_OUT[115] ? + { int_div_fNext_23$D_OUT[114:0], 1'd0 } + b__h8543 : + { int_div_fNext_23$D_OUT[114:0], 1'd0 } - b__h8543 } ; + assign int_div_fNext_24$ENQ = CAN_FIRE_RL_int_div_work_24 ; + assign int_div_fNext_24$DEQ = CAN_FIRE_RL_int_div_work_25 ; + assign int_div_fNext_24$CLR = 1'b0 ; + + // submodule int_div_fNext_25 + assign int_div_fNext_25$D_IN = + { int_div_fNext_24$D_OUT[231:174], + int_div_fNext_24$D_OUT[172:116], + !int_div_fNext_24$D_OUT[115], + int_div_fNext_24$D_OUT[115] ? + { int_div_fNext_24$D_OUT[114:0], 1'd0 } + b__h8867 : + { int_div_fNext_24$D_OUT[114:0], 1'd0 } - b__h8867 } ; + assign int_div_fNext_25$ENQ = CAN_FIRE_RL_int_div_work_25 ; + assign int_div_fNext_25$DEQ = CAN_FIRE_RL_int_div_work_26 ; + assign int_div_fNext_25$CLR = 1'b0 ; + + // submodule int_div_fNext_26 + assign int_div_fNext_26$D_IN = + { int_div_fNext_25$D_OUT[231:174], + int_div_fNext_25$D_OUT[172:116], + !int_div_fNext_25$D_OUT[115], + int_div_fNext_25$D_OUT[115] ? + { int_div_fNext_25$D_OUT[114:0], 1'd0 } + b__h9191 : + { int_div_fNext_25$D_OUT[114:0], 1'd0 } - b__h9191 } ; + assign int_div_fNext_26$ENQ = CAN_FIRE_RL_int_div_work_26 ; + assign int_div_fNext_26$DEQ = CAN_FIRE_RL_int_div_work_27 ; + assign int_div_fNext_26$CLR = 1'b0 ; + + // submodule int_div_fNext_27 + assign int_div_fNext_27$D_IN = + { int_div_fNext_26$D_OUT[231:174], + int_div_fNext_26$D_OUT[172:116], + !int_div_fNext_26$D_OUT[115], + int_div_fNext_26$D_OUT[115] ? + { int_div_fNext_26$D_OUT[114:0], 1'd0 } + b__h9515 : + { int_div_fNext_26$D_OUT[114:0], 1'd0 } - b__h9515 } ; + assign int_div_fNext_27$ENQ = CAN_FIRE_RL_int_div_work_27 ; + assign int_div_fNext_27$DEQ = CAN_FIRE_RL_int_div_work_28 ; + assign int_div_fNext_27$CLR = 1'b0 ; + + // submodule int_div_fNext_28 + assign int_div_fNext_28$D_IN = + { int_div_fNext_27$D_OUT[231:174], + int_div_fNext_27$D_OUT[172:116], + !int_div_fNext_27$D_OUT[115], + int_div_fNext_27$D_OUT[115] ? + { int_div_fNext_27$D_OUT[114:0], 1'd0 } + b__h9839 : + { int_div_fNext_27$D_OUT[114:0], 1'd0 } - b__h9839 } ; + assign int_div_fNext_28$ENQ = CAN_FIRE_RL_int_div_work_28 ; + assign int_div_fNext_28$DEQ = CAN_FIRE_RL_int_div_work_29 ; + assign int_div_fNext_28$CLR = 1'b0 ; + + // submodule int_div_fNext_29 + assign int_div_fNext_29$D_IN = + { int_div_fNext_28$D_OUT[231:174], + int_div_fNext_28$D_OUT[172:116], + !int_div_fNext_28$D_OUT[115], + int_div_fNext_28$D_OUT[115] ? + { int_div_fNext_28$D_OUT[114:0], 1'd0 } + b__h10163 : + { int_div_fNext_28$D_OUT[114:0], 1'd0 } - b__h10163 } ; + assign int_div_fNext_29$ENQ = CAN_FIRE_RL_int_div_work_29 ; + assign int_div_fNext_29$DEQ = CAN_FIRE_RL_int_div_work_30 ; + assign int_div_fNext_29$CLR = 1'b0 ; + + // submodule int_div_fNext_3 + assign int_div_fNext_3$D_IN = + { int_div_fNext_2$D_OUT[231:174], + int_div_fNext_2$D_OUT[172:116], + !int_div_fNext_2$D_OUT[115], + int_div_fNext_2$D_OUT[115] ? + { int_div_fNext_2$D_OUT[114:0], 1'd0 } + b__h1739 : + { int_div_fNext_2$D_OUT[114:0], 1'd0 } - b__h1739 } ; + assign int_div_fNext_3$ENQ = CAN_FIRE_RL_int_div_work_3 ; + assign int_div_fNext_3$DEQ = CAN_FIRE_RL_int_div_work_4 ; + assign int_div_fNext_3$CLR = 1'b0 ; + + // submodule int_div_fNext_30 + assign int_div_fNext_30$D_IN = + { int_div_fNext_29$D_OUT[231:174], + int_div_fNext_29$D_OUT[172:116], + !int_div_fNext_29$D_OUT[115], + int_div_fNext_29$D_OUT[115] ? + { int_div_fNext_29$D_OUT[114:0], 1'd0 } + b__h10487 : + { int_div_fNext_29$D_OUT[114:0], 1'd0 } - b__h10487 } ; + assign int_div_fNext_30$ENQ = CAN_FIRE_RL_int_div_work_30 ; + assign int_div_fNext_30$DEQ = CAN_FIRE_RL_int_div_work_31 ; + assign int_div_fNext_30$CLR = 1'b0 ; + + // submodule int_div_fNext_31 + assign int_div_fNext_31$D_IN = + { int_div_fNext_30$D_OUT[231:174], + int_div_fNext_30$D_OUT[172:116], + !int_div_fNext_30$D_OUT[115], + int_div_fNext_30$D_OUT[115] ? + { int_div_fNext_30$D_OUT[114:0], 1'd0 } + b__h10811 : + { int_div_fNext_30$D_OUT[114:0], 1'd0 } - b__h10811 } ; + assign int_div_fNext_31$ENQ = CAN_FIRE_RL_int_div_work_31 ; + assign int_div_fNext_31$DEQ = CAN_FIRE_RL_int_div_work_32 ; + assign int_div_fNext_31$CLR = 1'b0 ; + + // submodule int_div_fNext_32 + assign int_div_fNext_32$D_IN = + { int_div_fNext_31$D_OUT[231:174], + int_div_fNext_31$D_OUT[172:116], + !int_div_fNext_31$D_OUT[115], + int_div_fNext_31$D_OUT[115] ? + { int_div_fNext_31$D_OUT[114:0], 1'd0 } + b__h11135 : + { int_div_fNext_31$D_OUT[114:0], 1'd0 } - b__h11135 } ; + assign int_div_fNext_32$ENQ = CAN_FIRE_RL_int_div_work_32 ; + assign int_div_fNext_32$DEQ = CAN_FIRE_RL_int_div_work_33 ; + assign int_div_fNext_32$CLR = 1'b0 ; + + // submodule int_div_fNext_33 + assign int_div_fNext_33$D_IN = + { int_div_fNext_32$D_OUT[231:174], + int_div_fNext_32$D_OUT[172:116], + !int_div_fNext_32$D_OUT[115], + int_div_fNext_32$D_OUT[115] ? + { int_div_fNext_32$D_OUT[114:0], 1'd0 } + b__h11459 : + { int_div_fNext_32$D_OUT[114:0], 1'd0 } - b__h11459 } ; + assign int_div_fNext_33$ENQ = CAN_FIRE_RL_int_div_work_33 ; + assign int_div_fNext_33$DEQ = CAN_FIRE_RL_int_div_work_34 ; + assign int_div_fNext_33$CLR = 1'b0 ; + + // submodule int_div_fNext_34 + assign int_div_fNext_34$D_IN = + { int_div_fNext_33$D_OUT[231:174], + int_div_fNext_33$D_OUT[172:116], + !int_div_fNext_33$D_OUT[115], + int_div_fNext_33$D_OUT[115] ? + { int_div_fNext_33$D_OUT[114:0], 1'd0 } + b__h11783 : + { int_div_fNext_33$D_OUT[114:0], 1'd0 } - b__h11783 } ; + assign int_div_fNext_34$ENQ = CAN_FIRE_RL_int_div_work_34 ; + assign int_div_fNext_34$DEQ = CAN_FIRE_RL_int_div_work_35 ; + assign int_div_fNext_34$CLR = 1'b0 ; + + // submodule int_div_fNext_35 + assign int_div_fNext_35$D_IN = + { int_div_fNext_34$D_OUT[231:174], + int_div_fNext_34$D_OUT[172:116], + !int_div_fNext_34$D_OUT[115], + int_div_fNext_34$D_OUT[115] ? + { int_div_fNext_34$D_OUT[114:0], 1'd0 } + b__h12107 : + { int_div_fNext_34$D_OUT[114:0], 1'd0 } - b__h12107 } ; + assign int_div_fNext_35$ENQ = CAN_FIRE_RL_int_div_work_35 ; + assign int_div_fNext_35$DEQ = CAN_FIRE_RL_int_div_work_36 ; + assign int_div_fNext_35$CLR = 1'b0 ; + + // submodule int_div_fNext_36 + assign int_div_fNext_36$D_IN = + { int_div_fNext_35$D_OUT[231:174], + int_div_fNext_35$D_OUT[172:116], + !int_div_fNext_35$D_OUT[115], + int_div_fNext_35$D_OUT[115] ? + { int_div_fNext_35$D_OUT[114:0], 1'd0 } + b__h12431 : + { int_div_fNext_35$D_OUT[114:0], 1'd0 } - b__h12431 } ; + assign int_div_fNext_36$ENQ = CAN_FIRE_RL_int_div_work_36 ; + assign int_div_fNext_36$DEQ = CAN_FIRE_RL_int_div_work_37 ; + assign int_div_fNext_36$CLR = 1'b0 ; + + // submodule int_div_fNext_37 + assign int_div_fNext_37$D_IN = + { int_div_fNext_36$D_OUT[231:174], + int_div_fNext_36$D_OUT[172:116], + !int_div_fNext_36$D_OUT[115], + int_div_fNext_36$D_OUT[115] ? + { int_div_fNext_36$D_OUT[114:0], 1'd0 } + b__h12755 : + { int_div_fNext_36$D_OUT[114:0], 1'd0 } - b__h12755 } ; + assign int_div_fNext_37$ENQ = CAN_FIRE_RL_int_div_work_37 ; + assign int_div_fNext_37$DEQ = CAN_FIRE_RL_int_div_work_38 ; + assign int_div_fNext_37$CLR = 1'b0 ; + + // submodule int_div_fNext_38 + assign int_div_fNext_38$D_IN = + { int_div_fNext_37$D_OUT[231:174], + int_div_fNext_37$D_OUT[172:116], + !int_div_fNext_37$D_OUT[115], + int_div_fNext_37$D_OUT[115] ? + { int_div_fNext_37$D_OUT[114:0], 1'd0 } + b__h13079 : + { int_div_fNext_37$D_OUT[114:0], 1'd0 } - b__h13079 } ; + assign int_div_fNext_38$ENQ = CAN_FIRE_RL_int_div_work_38 ; + assign int_div_fNext_38$DEQ = CAN_FIRE_RL_int_div_work_39 ; + assign int_div_fNext_38$CLR = 1'b0 ; + + // submodule int_div_fNext_39 + assign int_div_fNext_39$D_IN = + { int_div_fNext_38$D_OUT[231:174], + int_div_fNext_38$D_OUT[172:116], + !int_div_fNext_38$D_OUT[115], + int_div_fNext_38$D_OUT[115] ? + { int_div_fNext_38$D_OUT[114:0], 1'd0 } + b__h13403 : + { int_div_fNext_38$D_OUT[114:0], 1'd0 } - b__h13403 } ; + assign int_div_fNext_39$ENQ = CAN_FIRE_RL_int_div_work_39 ; + assign int_div_fNext_39$DEQ = CAN_FIRE_RL_int_div_work_40 ; + assign int_div_fNext_39$CLR = 1'b0 ; + + // submodule int_div_fNext_4 + assign int_div_fNext_4$D_IN = + { int_div_fNext_3$D_OUT[231:174], + int_div_fNext_3$D_OUT[172:116], + !int_div_fNext_3$D_OUT[115], + int_div_fNext_3$D_OUT[115] ? + { int_div_fNext_3$D_OUT[114:0], 1'd0 } + b__h2063 : + { int_div_fNext_3$D_OUT[114:0], 1'd0 } - b__h2063 } ; + assign int_div_fNext_4$ENQ = CAN_FIRE_RL_int_div_work_4 ; + assign int_div_fNext_4$DEQ = CAN_FIRE_RL_int_div_work_5 ; + assign int_div_fNext_4$CLR = 1'b0 ; + + // submodule int_div_fNext_40 + assign int_div_fNext_40$D_IN = + { int_div_fNext_39$D_OUT[231:174], + int_div_fNext_39$D_OUT[172:116], + !int_div_fNext_39$D_OUT[115], + int_div_fNext_39$D_OUT[115] ? + { int_div_fNext_39$D_OUT[114:0], 1'd0 } + b__h13727 : + { int_div_fNext_39$D_OUT[114:0], 1'd0 } - b__h13727 } ; + assign int_div_fNext_40$ENQ = CAN_FIRE_RL_int_div_work_40 ; + assign int_div_fNext_40$DEQ = CAN_FIRE_RL_int_div_work_41 ; + assign int_div_fNext_40$CLR = 1'b0 ; + + // submodule int_div_fNext_41 + assign int_div_fNext_41$D_IN = + { int_div_fNext_40$D_OUT[231:174], + int_div_fNext_40$D_OUT[172:116], + !int_div_fNext_40$D_OUT[115], + int_div_fNext_40$D_OUT[115] ? + { int_div_fNext_40$D_OUT[114:0], 1'd0 } + b__h14051 : + { int_div_fNext_40$D_OUT[114:0], 1'd0 } - b__h14051 } ; + assign int_div_fNext_41$ENQ = CAN_FIRE_RL_int_div_work_41 ; + assign int_div_fNext_41$DEQ = CAN_FIRE_RL_int_div_work_42 ; + assign int_div_fNext_41$CLR = 1'b0 ; + + // submodule int_div_fNext_42 + assign int_div_fNext_42$D_IN = + { int_div_fNext_41$D_OUT[231:174], + int_div_fNext_41$D_OUT[172:116], + !int_div_fNext_41$D_OUT[115], + int_div_fNext_41$D_OUT[115] ? + { int_div_fNext_41$D_OUT[114:0], 1'd0 } + b__h14375 : + { int_div_fNext_41$D_OUT[114:0], 1'd0 } - b__h14375 } ; + assign int_div_fNext_42$ENQ = CAN_FIRE_RL_int_div_work_42 ; + assign int_div_fNext_42$DEQ = CAN_FIRE_RL_int_div_work_43 ; + assign int_div_fNext_42$CLR = 1'b0 ; + + // submodule int_div_fNext_43 + assign int_div_fNext_43$D_IN = + { int_div_fNext_42$D_OUT[231:174], + int_div_fNext_42$D_OUT[172:116], + !int_div_fNext_42$D_OUT[115], + int_div_fNext_42$D_OUT[115] ? + { int_div_fNext_42$D_OUT[114:0], 1'd0 } + b__h14699 : + { int_div_fNext_42$D_OUT[114:0], 1'd0 } - b__h14699 } ; + assign int_div_fNext_43$ENQ = CAN_FIRE_RL_int_div_work_43 ; + assign int_div_fNext_43$DEQ = CAN_FIRE_RL_int_div_work_44 ; + assign int_div_fNext_43$CLR = 1'b0 ; + + // submodule int_div_fNext_44 + assign int_div_fNext_44$D_IN = + { int_div_fNext_43$D_OUT[231:174], + int_div_fNext_43$D_OUT[172:116], + !int_div_fNext_43$D_OUT[115], + int_div_fNext_43$D_OUT[115] ? + { int_div_fNext_43$D_OUT[114:0], 1'd0 } + b__h15023 : + { int_div_fNext_43$D_OUT[114:0], 1'd0 } - b__h15023 } ; + assign int_div_fNext_44$ENQ = CAN_FIRE_RL_int_div_work_44 ; + assign int_div_fNext_44$DEQ = CAN_FIRE_RL_int_div_work_45 ; + assign int_div_fNext_44$CLR = 1'b0 ; + + // submodule int_div_fNext_45 + assign int_div_fNext_45$D_IN = + { int_div_fNext_44$D_OUT[231:174], + int_div_fNext_44$D_OUT[172:116], + !int_div_fNext_44$D_OUT[115], + int_div_fNext_44$D_OUT[115] ? + { int_div_fNext_44$D_OUT[114:0], 1'd0 } + b__h15347 : + { int_div_fNext_44$D_OUT[114:0], 1'd0 } - b__h15347 } ; + assign int_div_fNext_45$ENQ = CAN_FIRE_RL_int_div_work_45 ; + assign int_div_fNext_45$DEQ = CAN_FIRE_RL_int_div_work_46 ; + assign int_div_fNext_45$CLR = 1'b0 ; + + // submodule int_div_fNext_46 + assign int_div_fNext_46$D_IN = + { int_div_fNext_45$D_OUT[231:174], + int_div_fNext_45$D_OUT[172:116], + !int_div_fNext_45$D_OUT[115], + int_div_fNext_45$D_OUT[115] ? + { int_div_fNext_45$D_OUT[114:0], 1'd0 } + b__h15671 : + { int_div_fNext_45$D_OUT[114:0], 1'd0 } - b__h15671 } ; + assign int_div_fNext_46$ENQ = CAN_FIRE_RL_int_div_work_46 ; + assign int_div_fNext_46$DEQ = CAN_FIRE_RL_int_div_work_47 ; + assign int_div_fNext_46$CLR = 1'b0 ; + + // submodule int_div_fNext_47 + assign int_div_fNext_47$D_IN = + { int_div_fNext_46$D_OUT[231:174], + int_div_fNext_46$D_OUT[172:116], + !int_div_fNext_46$D_OUT[115], + int_div_fNext_46$D_OUT[115] ? + { int_div_fNext_46$D_OUT[114:0], 1'd0 } + b__h15995 : + { int_div_fNext_46$D_OUT[114:0], 1'd0 } - b__h15995 } ; + assign int_div_fNext_47$ENQ = CAN_FIRE_RL_int_div_work_47 ; + assign int_div_fNext_47$DEQ = CAN_FIRE_RL_int_div_work_48 ; + assign int_div_fNext_47$CLR = 1'b0 ; + + // submodule int_div_fNext_48 + assign int_div_fNext_48$D_IN = + { int_div_fNext_47$D_OUT[231:174], + int_div_fNext_47$D_OUT[172:116], + !int_div_fNext_47$D_OUT[115], + int_div_fNext_47$D_OUT[115] ? + { int_div_fNext_47$D_OUT[114:0], 1'd0 } + b__h16319 : + { int_div_fNext_47$D_OUT[114:0], 1'd0 } - b__h16319 } ; + assign int_div_fNext_48$ENQ = CAN_FIRE_RL_int_div_work_48 ; + assign int_div_fNext_48$DEQ = CAN_FIRE_RL_int_div_work_49 ; + assign int_div_fNext_48$CLR = 1'b0 ; + + // submodule int_div_fNext_49 + assign int_div_fNext_49$D_IN = + { int_div_fNext_48$D_OUT[231:174], + int_div_fNext_48$D_OUT[172:116], + !int_div_fNext_48$D_OUT[115], + int_div_fNext_48$D_OUT[115] ? + { int_div_fNext_48$D_OUT[114:0], 1'd0 } + b__h16643 : + { int_div_fNext_48$D_OUT[114:0], 1'd0 } - b__h16643 } ; + assign int_div_fNext_49$ENQ = CAN_FIRE_RL_int_div_work_49 ; + assign int_div_fNext_49$DEQ = CAN_FIRE_RL_int_div_work_50 ; + assign int_div_fNext_49$CLR = 1'b0 ; + + // submodule int_div_fNext_5 + assign int_div_fNext_5$D_IN = + { int_div_fNext_4$D_OUT[231:174], + int_div_fNext_4$D_OUT[172:116], + !int_div_fNext_4$D_OUT[115], + int_div_fNext_4$D_OUT[115] ? + { int_div_fNext_4$D_OUT[114:0], 1'd0 } + b__h2387 : + { int_div_fNext_4$D_OUT[114:0], 1'd0 } - b__h2387 } ; + assign int_div_fNext_5$ENQ = CAN_FIRE_RL_int_div_work_5 ; + assign int_div_fNext_5$DEQ = CAN_FIRE_RL_int_div_work_6 ; + assign int_div_fNext_5$CLR = 1'b0 ; + + // submodule int_div_fNext_50 + assign int_div_fNext_50$D_IN = + { int_div_fNext_49$D_OUT[231:174], + int_div_fNext_49$D_OUT[172:116], + !int_div_fNext_49$D_OUT[115], + int_div_fNext_49$D_OUT[115] ? + { int_div_fNext_49$D_OUT[114:0], 1'd0 } + b__h16967 : + { int_div_fNext_49$D_OUT[114:0], 1'd0 } - b__h16967 } ; + assign int_div_fNext_50$ENQ = CAN_FIRE_RL_int_div_work_50 ; + assign int_div_fNext_50$DEQ = CAN_FIRE_RL_int_div_work_51 ; + assign int_div_fNext_50$CLR = 1'b0 ; + + // submodule int_div_fNext_51 + assign int_div_fNext_51$D_IN = + { int_div_fNext_50$D_OUT[231:174], + int_div_fNext_50$D_OUT[172:116], + !int_div_fNext_50$D_OUT[115], + int_div_fNext_50$D_OUT[115] ? + { int_div_fNext_50$D_OUT[114:0], 1'd0 } + b__h17291 : + { int_div_fNext_50$D_OUT[114:0], 1'd0 } - b__h17291 } ; + assign int_div_fNext_51$ENQ = CAN_FIRE_RL_int_div_work_51 ; + assign int_div_fNext_51$DEQ = CAN_FIRE_RL_int_div_work_52 ; + assign int_div_fNext_51$CLR = 1'b0 ; + + // submodule int_div_fNext_52 + assign int_div_fNext_52$D_IN = + { int_div_fNext_51$D_OUT[231:174], + int_div_fNext_51$D_OUT[172:116], + !int_div_fNext_51$D_OUT[115], + int_div_fNext_51$D_OUT[115] ? + { int_div_fNext_51$D_OUT[114:0], 1'd0 } + b__h17615 : + { int_div_fNext_51$D_OUT[114:0], 1'd0 } - b__h17615 } ; + assign int_div_fNext_52$ENQ = CAN_FIRE_RL_int_div_work_52 ; + assign int_div_fNext_52$DEQ = CAN_FIRE_RL_int_div_work_53 ; + assign int_div_fNext_52$CLR = 1'b0 ; + + // submodule int_div_fNext_53 + assign int_div_fNext_53$D_IN = + { int_div_fNext_52$D_OUT[231:174], + int_div_fNext_52$D_OUT[172:116], + !int_div_fNext_52$D_OUT[115], + int_div_fNext_52$D_OUT[115] ? + { int_div_fNext_52$D_OUT[114:0], 1'd0 } + b__h17939 : + { int_div_fNext_52$D_OUT[114:0], 1'd0 } - b__h17939 } ; + assign int_div_fNext_53$ENQ = CAN_FIRE_RL_int_div_work_53 ; + assign int_div_fNext_53$DEQ = CAN_FIRE_RL_int_div_work_54 ; + assign int_div_fNext_53$CLR = 1'b0 ; + + // submodule int_div_fNext_54 + assign int_div_fNext_54$D_IN = + { int_div_fNext_53$D_OUT[231:174], + int_div_fNext_53$D_OUT[172:116], + !int_div_fNext_53$D_OUT[115], + int_div_fNext_53$D_OUT[115] ? + { int_div_fNext_53$D_OUT[114:0], 1'd0 } + b__h18263 : + { int_div_fNext_53$D_OUT[114:0], 1'd0 } - b__h18263 } ; + assign int_div_fNext_54$ENQ = CAN_FIRE_RL_int_div_work_54 ; + assign int_div_fNext_54$DEQ = CAN_FIRE_RL_int_div_work_55 ; + assign int_div_fNext_54$CLR = 1'b0 ; + + // submodule int_div_fNext_55 + assign int_div_fNext_55$D_IN = + { int_div_fNext_54$D_OUT[231:174], + int_div_fNext_54$D_OUT[172:116], + !int_div_fNext_54$D_OUT[115], + int_div_fNext_54$D_OUT[115] ? + { int_div_fNext_54$D_OUT[114:0], 1'd0 } + b__h18587 : + { int_div_fNext_54$D_OUT[114:0], 1'd0 } - b__h18587 } ; + assign int_div_fNext_55$ENQ = CAN_FIRE_RL_int_div_work_55 ; + assign int_div_fNext_55$DEQ = CAN_FIRE_RL_int_div_work_56 ; + assign int_div_fNext_55$CLR = 1'b0 ; + + // submodule int_div_fNext_56 + assign int_div_fNext_56$D_IN = + { int_div_fNext_55$D_OUT[231:174], + int_div_fNext_55$D_OUT[172:116], + !int_div_fNext_55$D_OUT[115], + int_div_fNext_55$D_OUT[115] ? + { int_div_fNext_55$D_OUT[114:0], 1'd0 } + b__h18911 : + { int_div_fNext_55$D_OUT[114:0], 1'd0 } - b__h18911 } ; + assign int_div_fNext_56$ENQ = CAN_FIRE_RL_int_div_work_56 ; + assign int_div_fNext_56$DEQ = CAN_FIRE_RL_int_div_work_57 ; + assign int_div_fNext_56$CLR = 1'b0 ; + + // submodule int_div_fNext_57 + assign int_div_fNext_57$D_IN = + { int_div_fNext_56$D_OUT[231:174], + int_div_fNext_56$D_OUT[172:116], + !int_div_fNext_56$D_OUT[115], + int_div_fNext_56$D_OUT[115] ? + { int_div_fNext_56$D_OUT[114:0], 1'd0 } + b__h19235 : + { int_div_fNext_56$D_OUT[114:0], 1'd0 } - b__h19235 } ; + assign int_div_fNext_57$ENQ = CAN_FIRE_RL_int_div_work_57 ; + assign int_div_fNext_57$DEQ = CAN_FIRE_RL_int_div_finish ; + assign int_div_fNext_57$CLR = 1'b0 ; + + // submodule int_div_fNext_6 + assign int_div_fNext_6$D_IN = + { int_div_fNext_5$D_OUT[231:174], + int_div_fNext_5$D_OUT[172:116], + !int_div_fNext_5$D_OUT[115], + int_div_fNext_5$D_OUT[115] ? + { int_div_fNext_5$D_OUT[114:0], 1'd0 } + b__h2711 : + { int_div_fNext_5$D_OUT[114:0], 1'd0 } - b__h2711 } ; + assign int_div_fNext_6$ENQ = CAN_FIRE_RL_int_div_work_6 ; + assign int_div_fNext_6$DEQ = CAN_FIRE_RL_int_div_work_7 ; + assign int_div_fNext_6$CLR = 1'b0 ; + + // submodule int_div_fNext_7 + assign int_div_fNext_7$D_IN = + { int_div_fNext_6$D_OUT[231:174], + int_div_fNext_6$D_OUT[172:116], + !int_div_fNext_6$D_OUT[115], + int_div_fNext_6$D_OUT[115] ? + { int_div_fNext_6$D_OUT[114:0], 1'd0 } + b__h3035 : + { int_div_fNext_6$D_OUT[114:0], 1'd0 } - b__h3035 } ; + assign int_div_fNext_7$ENQ = CAN_FIRE_RL_int_div_work_7 ; + assign int_div_fNext_7$DEQ = CAN_FIRE_RL_int_div_work_8 ; + assign int_div_fNext_7$CLR = 1'b0 ; + + // submodule int_div_fNext_8 + assign int_div_fNext_8$D_IN = + { int_div_fNext_7$D_OUT[231:174], + int_div_fNext_7$D_OUT[172:116], + !int_div_fNext_7$D_OUT[115], + int_div_fNext_7$D_OUT[115] ? + { int_div_fNext_7$D_OUT[114:0], 1'd0 } + b__h3359 : + { int_div_fNext_7$D_OUT[114:0], 1'd0 } - b__h3359 } ; + assign int_div_fNext_8$ENQ = CAN_FIRE_RL_int_div_work_8 ; + assign int_div_fNext_8$DEQ = CAN_FIRE_RL_int_div_work_9 ; + assign int_div_fNext_8$CLR = 1'b0 ; + + // submodule int_div_fNext_9 + assign int_div_fNext_9$D_IN = + { int_div_fNext_8$D_OUT[231:174], + int_div_fNext_8$D_OUT[172:116], + !int_div_fNext_8$D_OUT[115], + int_div_fNext_8$D_OUT[115] ? + { int_div_fNext_8$D_OUT[114:0], 1'd0 } + b__h3683 : + { int_div_fNext_8$D_OUT[114:0], 1'd0 } - b__h3683 } ; + assign int_div_fNext_9$ENQ = CAN_FIRE_RL_int_div_work_9 ; + assign int_div_fNext_9$DEQ = CAN_FIRE_RL_int_div_work_10 ; + assign int_div_fNext_9$CLR = 1'b0 ; + + // submodule int_div_fRequest + assign int_div_fRequest$D_IN = fpu_fState_S1$D_OUT[181:11] ; + assign int_div_fRequest$ENQ = + WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[318] ; + assign int_div_fRequest$DEQ = CAN_FIRE_RL_int_div_start ; + assign int_div_fRequest$CLR = 1'b0 ; + + // submodule int_div_fResponse + assign int_div_fResponse$D_IN = + { IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19[56:0], + value__h19447[114:58] } ; + assign int_div_fResponse$ENQ = CAN_FIRE_RL_int_div_finish ; + assign int_div_fResponse$DEQ = + WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[147] ; + assign int_div_fResponse$CLR = 1'b0 ; + + // remaining internal signals + assign IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7 = + _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 ? + _theResult___snd__h59844 : + _theResult___snd__h59839 ; + assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 = + sfd__h60417[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 63'h7FF0000000000000 : + { din_inc___2_exp__h61001, sfd__h60417[52:1] }) : + { IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, + sfd__h60417[51:0] } ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 = + (_theResult___fst_exp__h59725 == 11'd0) ? + 12'd3074 : + { theResult___fst_exp9725_MINUS_1023__q6[10], + theResult___fst_exp9725_MINUS_1023__q6 } ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 = + (sfdin__h51553[57] ? + 6'd0 : + (sfdin__h51553[56] ? + 6'd1 : + (sfdin__h51553[55] ? + 6'd2 : + (sfdin__h51553[54] ? + 6'd3 : + (sfdin__h51553[53] ? + 6'd4 : + (sfdin__h51553[52] ? + 6'd5 : + (sfdin__h51553[51] ? + 6'd6 : + (sfdin__h51553[50] ? + 6'd7 : + (sfdin__h51553[49] ? + 6'd8 : + (sfdin__h51553[48] ? + 6'd9 : + (sfdin__h51553[47] ? + 6'd10 : + (sfdin__h51553[46] ? + 6'd11 : + (sfdin__h51553[45] ? + 6'd12 : + (sfdin__h51553[44] ? + 6'd13 : + (sfdin__h51553[43] ? + 6'd14 : + (sfdin__h51553[42] ? + 6'd15 : + (sfdin__h51553[41] ? + 6'd16 : + (sfdin__h51553[40] ? + 6'd17 : + (sfdin__h51553[39] ? + 6'd18 : + (sfdin__h51553[38] ? + 6'd19 : + (sfdin__h51553[37] ? + 6'd20 : + (sfdin__h51553[36] ? + 6'd21 : + (sfdin__h51553[35] ? + 6'd22 : + (sfdin__h51553[34] ? + 6'd23 : + (sfdin__h51553[33] ? + 6'd24 : + (sfdin__h51553[32] ? + 6'd25 : + (sfdin__h51553[31] ? + 6'd26 : + (sfdin__h51553[30] ? + 6'd27 : + (sfdin__h51553[29] ? + 6'd28 : + (sfdin__h51553[28] ? + 6'd29 : + (sfdin__h51553[27] ? + 6'd30 : + (sfdin__h51553[26] ? + 6'd31 : + (sfdin__h51553[25] ? + 6'd32 : + (sfdin__h51553[24] ? + 6'd33 : + (sfdin__h51553[23] ? + 6'd34 : + (sfdin__h51553[22] ? + 6'd35 : + (sfdin__h51553[21] ? + 6'd36 : + (sfdin__h51553[20] ? + 6'd37 : + (sfdin__h51553[19] ? + 6'd38 : + (sfdin__h51553[18] ? + 6'd39 : + (sfdin__h51553[17] ? + 6'd40 : + (sfdin__h51553[16] ? + 6'd41 : + (sfdin__h51553[15] ? + 6'd42 : + (sfdin__h51553[14] ? + 6'd43 : + (sfdin__h51553[13] ? + 6'd44 : + (sfdin__h51553[12] ? + 6'd45 : + (sfdin__h51553[11] ? + 6'd46 : + (sfdin__h51553[10] ? + 6'd47 : + (sfdin__h51553[9] ? + 6'd48 : + (sfdin__h51553[8] ? + 6'd49 : + (sfdin__h51553[7] ? + 6'd50 : + (sfdin__h51553[6] ? + 6'd51 : + (sfdin__h51553[5] ? + 6'd52 : + (sfdin__h51553[4] ? + 6'd53 : + (sfdin__h51553[3] ? + 6'd54 : + (sfdin__h51553[2] ? + 6'd55 : + (sfdin__h51553[1] ? + 6'd56 : + (sfdin__h51553[0] ? + 6'd57 : + 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 6'd1 ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 = + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 - + 12'd3074 ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770 = + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 : + { fpu_fState_S3$D_OUT[129:128], + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[127] : + fpu_fState_S3$D_OUT[127], + fpu_fState_S3$D_OUT[126], + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[125] : + fpu_fState_S3$D_OUT[125] } ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 = + (sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h59768, sfdin__h59762[57:6] } ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 = + (((fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3[10]}}, + fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 }) - + { 7'd0, b__h21789 }) - + (((fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4[10]}}, + fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 }) - + { 7'd0, b__h29207 }) ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ + 13'h1000) <= + 13'd5120 ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ + 13'h1000) < + 13'd3020 ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ + 13'h1000) < + 13'd3074 ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 : + CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0) ? + 11'd2047 : + ((fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? + 11'd0 : + _theResult___fst_exp__h37217) ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? + 52'd0 : + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? + _theResult___fst_sfd__h37707 : + _theResult___fst_sfd__h37218) ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54]) ? + { fpu_fOperands_S0$D_OUT[66:55], sfd__h36687 } : + ((fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118]) ? + fpu_fOperands_S0$D_OUT[130:67] : + ((fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54]) ? + fpu_fOperands_S0$D_OUT[66:3] : + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305)) ; + assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 = + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] == 2'b0 && + !fpu_fState_S3$D_OUT[194] : + !fpu_fState_S3$D_OUT[194] ; + assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 = + ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + { fpu_fState_S3$D_OUT[129:128], + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[127], + fpu_fState_S3$D_OUT[126], + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[125] } : + fpu_fState_S3$D_OUT[129:125]) | + { 2'd0, + sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023, + _theResult___fst_exp__h59771 == 11'd0 && guard__h51381 != 2'd0, + sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023 } ; + assign IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 = + (fpu_fState_S4$D_OUT[64:54] == 11'd0 && + sfd__h60417[53:52] == 2'b01) ? + 11'd1 : + fpu_fState_S4$D_OUT[64:54] ; + assign IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19 = + int_div_fNext_57$D_OUT[115] ? + int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 - + 58'd1 : + int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 ; + assign IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8 = + sfdin__h59762[5] ? 2'd2 : 2'd0 ; + assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 = + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) ; + assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305 = + { NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 ? + 52'h8000000000000 : + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 } ; + assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334 = + (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 && + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; + assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341 = + (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208) ; + assign _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 = + ({ 6'd0, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ^ + 12'h800) <= + (IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ^ + 12'h800) ; + assign _theResult____h50063 = + (fpu_fState_S2$D_OUT[10:0] < 11'd58) ? + result__h50108 : + result__h50258 ; + assign _theResult___exp__h60910 = + sfd__h60417[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 11'd2047 : + din_inc___2_exp__h61001) : + IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 ; + assign _theResult___fst__h49072 = + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 ? + value__h49300[10:0] : + 11'd0 ; + assign _theResult___fst_exp__h59719 = fpu_fState_S3$D_OUT[120:110] - 11'd1 ; + assign _theResult___fst_exp__h59722 = + (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + _theResult___fst_exp__h59719 : + 11'd2046 ; + assign _theResult___fst_exp__h59725 = + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + _theResult___fst_exp__h59722 : + fpu_fState_S3$D_OUT[120:110] ; + assign _theResult___fst_exp__h59768 = + sfdin__h51553[57] ? + _theResult___fst_exp__h59791 : + _theResult___fst_exp__h59855 ; + assign _theResult___fst_exp__h59771 = + (sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h59768 ; + assign _theResult___fst_exp__h59791 = + (_theResult___fst_exp__h59725 == 11'd0) ? + 11'd2 : + _theResult___fst_exp__h59725 + 11'd1 ; + assign _theResult___fst_exp__h59807 = + (_theResult___fst_exp__h59725 == 11'd0) ? + 11'd1 : + _theResult___fst_exp__h59725 ; + assign _theResult___fst_exp__h59846 = + _theResult___fst_exp__h59725 - + { 5'd0, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ; + assign _theResult___fst_exp__h59852 = + (!sfdin__h51553[57] && !sfdin__h51553[56] && + !sfdin__h51553[55] && + !sfdin__h51553[54] && + !sfdin__h51553[53] && + !sfdin__h51553[52] && + !sfdin__h51553[51] && + !sfdin__h51553[50] && + !sfdin__h51553[49] && + !sfdin__h51553[48] && + !sfdin__h51553[47] && + !sfdin__h51553[46] && + !sfdin__h51553[45] && + !sfdin__h51553[44] && + !sfdin__h51553[43] && + !sfdin__h51553[42] && + !sfdin__h51553[41] && + !sfdin__h51553[40] && + !sfdin__h51553[39] && + !sfdin__h51553[38] && + !sfdin__h51553[37] && + !sfdin__h51553[36] && + !sfdin__h51553[35] && + !sfdin__h51553[34] && + !sfdin__h51553[33] && + !sfdin__h51553[32] && + !sfdin__h51553[31] && + !sfdin__h51553[30] && + !sfdin__h51553[29] && + !sfdin__h51553[28] && + !sfdin__h51553[27] && + !sfdin__h51553[26] && + !sfdin__h51553[25] && + !sfdin__h51553[24] && + !sfdin__h51553[23] && + !sfdin__h51553[22] && + !sfdin__h51553[21] && + !sfdin__h51553[20] && + !sfdin__h51553[19] && + !sfdin__h51553[18] && + !sfdin__h51553[17] && + !sfdin__h51553[16] && + !sfdin__h51553[15] && + !sfdin__h51553[14] && + !sfdin__h51553[13] && + !sfdin__h51553[12] && + !sfdin__h51553[11] && + !sfdin__h51553[10] && + !sfdin__h51553[9] && + !sfdin__h51553[8] && + !sfdin__h51553[7] && + !sfdin__h51553[6] && + !sfdin__h51553[5] && + !sfdin__h51553[4] && + !sfdin__h51553[3] && + !sfdin__h51553[2] && + !sfdin__h51553[1] && + !sfdin__h51553[0] || + !_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727) ? + 11'd0 : + _theResult___fst_exp__h59846 ; + assign _theResult___fst_exp__h59855 = + (!sfdin__h51553[57] && sfdin__h51553[56]) ? + _theResult___fst_exp__h59807 : + _theResult___fst_exp__h59852 ; + assign _theResult___fst_exp__h60991 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___fst_exp__h60988 ; + assign _theResult___fst_sfd__h60992 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___fst_sfd__h60989 ; + assign _theResult___sfd__h60911 = + sfd__h60417[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 52'd0 : + sfd__h60417[52:1]) : + sfd__h60417[51:0] ; + assign _theResult___snd__h52150 = { fpu_fState_S3$D_OUT[56:0], 1'd0 } ; + assign _theResult___snd__h59785 = { sfdin__h51553[56:0], 1'd0 } ; + assign _theResult___snd__h59800 = + (!sfdin__h51553[57] && sfdin__h51553[56]) ? + _theResult___snd__h59802 : + _theResult___snd__h59815 ; + assign _theResult___snd__h59802 = { sfdin__h51553[55:0], 2'd0 } ; + assign _theResult___snd__h59815 = + (!sfdin__h51553[57] && !sfdin__h51553[56] && + !sfdin__h51553[55] && + !sfdin__h51553[54] && + !sfdin__h51553[53] && + !sfdin__h51553[52] && + !sfdin__h51553[51] && + !sfdin__h51553[50] && + !sfdin__h51553[49] && + !sfdin__h51553[48] && + !sfdin__h51553[47] && + !sfdin__h51553[46] && + !sfdin__h51553[45] && + !sfdin__h51553[44] && + !sfdin__h51553[43] && + !sfdin__h51553[42] && + !sfdin__h51553[41] && + !sfdin__h51553[40] && + !sfdin__h51553[39] && + !sfdin__h51553[38] && + !sfdin__h51553[37] && + !sfdin__h51553[36] && + !sfdin__h51553[35] && + !sfdin__h51553[34] && + !sfdin__h51553[33] && + !sfdin__h51553[32] && + !sfdin__h51553[31] && + !sfdin__h51553[30] && + !sfdin__h51553[29] && + !sfdin__h51553[28] && + !sfdin__h51553[27] && + !sfdin__h51553[26] && + !sfdin__h51553[25] && + !sfdin__h51553[24] && + !sfdin__h51553[23] && + !sfdin__h51553[22] && + !sfdin__h51553[21] && + !sfdin__h51553[20] && + !sfdin__h51553[19] && + !sfdin__h51553[18] && + !sfdin__h51553[17] && + !sfdin__h51553[16] && + !sfdin__h51553[15] && + !sfdin__h51553[14] && + !sfdin__h51553[13] && + !sfdin__h51553[12] && + !sfdin__h51553[11] && + !sfdin__h51553[10] && + !sfdin__h51553[9] && + !sfdin__h51553[8] && + !sfdin__h51553[7] && + !sfdin__h51553[6] && + !sfdin__h51553[5] && + !sfdin__h51553[4] && + !sfdin__h51553[3] && + !sfdin__h51553[2] && + !sfdin__h51553[1] && + !sfdin__h51553[0]) ? + sfdin__h51553 : + _theResult___snd__h59821 ; + assign _theResult___snd__h59821 = + { IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7[55:0], + 2'd0 } ; + assign _theResult___snd__h59839 = + sfdin__h51553 << + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ; + assign _theResult___snd__h59844 = + sfdin__h51553 << + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 ; + assign _theResult___snd_fst__h59874 = + { IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8[1], + { sfdin__h59762[4:0], 52'd0 } != 57'd0 } ; + assign _theResult___snd_fst_exp__h49084 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352) ? + 11'd0 : + value__h49124[10:0] ; + assign _theResult___snd_fst_exp__h49087 = + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? + _theResult___snd_fst_exp__h49084 : + 11'd2046 ; + assign _theResult___snd_fst_exp__h49111 = + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 ? + 11'd0 : + _theResult___snd_fst_exp__h49087 ; + assign _theResult___snd_fst_sfd__h49112 = + (fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? + 52'd0 : + 52'hFFFFFFFFFFFFF ; + assign _theResult___snd_snd_snd__h51398 = + (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + _theResult___snd__h52150 : + fpu_fState_S3$D_OUT[57:0] ; + assign b__h10163 = { int_div_fNext_28$D_OUT[231:174], 58'd0 } ; + assign b__h10487 = { int_div_fNext_29$D_OUT[231:174], 58'd0 } ; + assign b__h10811 = { int_div_fNext_30$D_OUT[231:174], 58'd0 } ; + assign b__h1091 = { int_div_fNext_0$D_OUT[231:174], 58'd0 } ; + assign b__h11135 = { int_div_fNext_31$D_OUT[231:174], 58'd0 } ; + assign b__h11459 = { int_div_fNext_32$D_OUT[231:174], 58'd0 } ; + assign b__h11783 = { int_div_fNext_33$D_OUT[231:174], 58'd0 } ; + assign b__h12107 = { int_div_fNext_34$D_OUT[231:174], 58'd0 } ; + assign b__h12431 = { int_div_fNext_35$D_OUT[231:174], 58'd0 } ; + assign b__h12755 = { int_div_fNext_36$D_OUT[231:174], 58'd0 } ; + assign b__h13079 = { int_div_fNext_37$D_OUT[231:174], 58'd0 } ; + assign b__h13403 = { int_div_fNext_38$D_OUT[231:174], 58'd0 } ; + assign b__h13727 = { int_div_fNext_39$D_OUT[231:174], 58'd0 } ; + assign b__h14051 = { int_div_fNext_40$D_OUT[231:174], 58'd0 } ; + assign b__h1415 = { int_div_fNext_1$D_OUT[231:174], 58'd0 } ; + assign b__h14375 = { int_div_fNext_41$D_OUT[231:174], 58'd0 } ; + assign b__h14699 = { int_div_fNext_42$D_OUT[231:174], 58'd0 } ; + assign b__h15023 = { int_div_fNext_43$D_OUT[231:174], 58'd0 } ; + assign b__h15347 = { int_div_fNext_44$D_OUT[231:174], 58'd0 } ; + assign b__h15671 = { int_div_fNext_45$D_OUT[231:174], 58'd0 } ; + assign b__h15995 = { int_div_fNext_46$D_OUT[231:174], 58'd0 } ; + assign b__h16319 = { int_div_fNext_47$D_OUT[231:174], 58'd0 } ; + assign b__h16643 = { int_div_fNext_48$D_OUT[231:174], 58'd0 } ; + assign b__h16967 = { int_div_fNext_49$D_OUT[231:174], 58'd0 } ; + assign b__h17291 = { int_div_fNext_50$D_OUT[231:174], 58'd0 } ; + assign b__h1739 = { int_div_fNext_2$D_OUT[231:174], 58'd0 } ; + assign b__h17615 = { int_div_fNext_51$D_OUT[231:174], 58'd0 } ; + assign b__h17939 = { int_div_fNext_52$D_OUT[231:174], 58'd0 } ; + assign b__h18263 = { int_div_fNext_53$D_OUT[231:174], 58'd0 } ; + assign b__h18587 = { int_div_fNext_54$D_OUT[231:174], 58'd0 } ; + assign b__h18911 = { int_div_fNext_55$D_OUT[231:174], 58'd0 } ; + assign b__h19235 = { int_div_fNext_56$D_OUT[231:174], 58'd0 } ; + assign b__h19482 = { int_div_fNext_57$D_OUT[231:174], 58'd0 } ; + assign b__h2063 = { int_div_fNext_3$D_OUT[231:174], 58'd0 } ; + assign b__h21789 = + (fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? + (fpu_fOperands_S0$D_OUT[118] ? + 6'd1 : + (fpu_fOperands_S0$D_OUT[117] ? + 6'd2 : + (fpu_fOperands_S0$D_OUT[116] ? + 6'd3 : + (fpu_fOperands_S0$D_OUT[115] ? + 6'd4 : + (fpu_fOperands_S0$D_OUT[114] ? + 6'd5 : + (fpu_fOperands_S0$D_OUT[113] ? + 6'd6 : + (fpu_fOperands_S0$D_OUT[112] ? + 6'd7 : + (fpu_fOperands_S0$D_OUT[111] ? + 6'd8 : + (fpu_fOperands_S0$D_OUT[110] ? + 6'd9 : + (fpu_fOperands_S0$D_OUT[109] ? + 6'd10 : + (fpu_fOperands_S0$D_OUT[108] ? + 6'd11 : + (fpu_fOperands_S0$D_OUT[107] ? + 6'd12 : + (fpu_fOperands_S0$D_OUT[106] ? + 6'd13 : + (fpu_fOperands_S0$D_OUT[105] ? + 6'd14 : + (fpu_fOperands_S0$D_OUT[104] ? + 6'd15 : + (fpu_fOperands_S0$D_OUT[103] ? + 6'd16 : + (fpu_fOperands_S0$D_OUT[102] ? + 6'd17 : + (fpu_fOperands_S0$D_OUT[101] ? + 6'd18 : + (fpu_fOperands_S0$D_OUT[100] ? + 6'd19 : + (fpu_fOperands_S0$D_OUT[99] ? + 6'd20 : + (fpu_fOperands_S0$D_OUT[98] ? + 6'd21 : + (fpu_fOperands_S0$D_OUT[97] ? + 6'd22 : + (fpu_fOperands_S0$D_OUT[96] ? + 6'd23 : + (fpu_fOperands_S0$D_OUT[95] ? + 6'd24 : + (fpu_fOperands_S0$D_OUT[94] ? + 6'd25 : + (fpu_fOperands_S0$D_OUT[93] ? + 6'd26 : + (fpu_fOperands_S0$D_OUT[92] ? + 6'd27 : + (fpu_fOperands_S0$D_OUT[91] ? + 6'd28 : + (fpu_fOperands_S0$D_OUT[90] ? + 6'd29 : + (fpu_fOperands_S0$D_OUT[89] ? + 6'd30 : + (fpu_fOperands_S0$D_OUT[88] ? + 6'd31 : + (fpu_fOperands_S0$D_OUT[87] ? + 6'd32 : + (fpu_fOperands_S0$D_OUT[86] ? + 6'd33 : + (fpu_fOperands_S0$D_OUT[85] ? + 6'd34 : + (fpu_fOperands_S0$D_OUT[84] ? + 6'd35 : + (fpu_fOperands_S0$D_OUT[83] ? + 6'd36 : + (fpu_fOperands_S0$D_OUT[82] ? + 6'd37 : + (fpu_fOperands_S0$D_OUT[81] ? + 6'd38 : + (fpu_fOperands_S0$D_OUT[80] ? + 6'd39 : + (fpu_fOperands_S0$D_OUT[79] ? + 6'd40 : + (fpu_fOperands_S0$D_OUT[78] ? + 6'd41 : + (fpu_fOperands_S0$D_OUT[77] ? + 6'd42 : + (fpu_fOperands_S0$D_OUT[76] ? + 6'd43 : + (fpu_fOperands_S0$D_OUT[75] ? + 6'd44 : + (fpu_fOperands_S0$D_OUT[74] ? + 6'd45 : + (fpu_fOperands_S0$D_OUT[73] ? + 6'd46 : + (fpu_fOperands_S0$D_OUT[72] ? + 6'd47 : + (fpu_fOperands_S0$D_OUT[71] ? + 6'd48 : + (fpu_fOperands_S0$D_OUT[70] ? + 6'd49 : + (fpu_fOperands_S0$D_OUT[69] ? + 6'd50 : + (fpu_fOperands_S0$D_OUT[68] ? + 6'd51 : + (fpu_fOperands_S0$D_OUT[67] ? + 6'd52 : + 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : + 6'd0 ; + assign b__h2387 = { int_div_fNext_4$D_OUT[231:174], 58'd0 } ; + assign b__h2711 = { int_div_fNext_5$D_OUT[231:174], 58'd0 } ; + assign b__h29207 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? + (fpu_fOperands_S0$D_OUT[54] ? + 6'd1 : + (fpu_fOperands_S0$D_OUT[53] ? + 6'd2 : + (fpu_fOperands_S0$D_OUT[52] ? + 6'd3 : + (fpu_fOperands_S0$D_OUT[51] ? + 6'd4 : + (fpu_fOperands_S0$D_OUT[50] ? + 6'd5 : + (fpu_fOperands_S0$D_OUT[49] ? + 6'd6 : + (fpu_fOperands_S0$D_OUT[48] ? + 6'd7 : + (fpu_fOperands_S0$D_OUT[47] ? + 6'd8 : + (fpu_fOperands_S0$D_OUT[46] ? + 6'd9 : + (fpu_fOperands_S0$D_OUT[45] ? + 6'd10 : + (fpu_fOperands_S0$D_OUT[44] ? + 6'd11 : + (fpu_fOperands_S0$D_OUT[43] ? + 6'd12 : + (fpu_fOperands_S0$D_OUT[42] ? + 6'd13 : + (fpu_fOperands_S0$D_OUT[41] ? + 6'd14 : + (fpu_fOperands_S0$D_OUT[40] ? + 6'd15 : + (fpu_fOperands_S0$D_OUT[39] ? + 6'd16 : + (fpu_fOperands_S0$D_OUT[38] ? + 6'd17 : + (fpu_fOperands_S0$D_OUT[37] ? + 6'd18 : + (fpu_fOperands_S0$D_OUT[36] ? + 6'd19 : + (fpu_fOperands_S0$D_OUT[35] ? + 6'd20 : + (fpu_fOperands_S0$D_OUT[34] ? + 6'd21 : + (fpu_fOperands_S0$D_OUT[33] ? + 6'd22 : + (fpu_fOperands_S0$D_OUT[32] ? + 6'd23 : + (fpu_fOperands_S0$D_OUT[31] ? + 6'd24 : + (fpu_fOperands_S0$D_OUT[30] ? + 6'd25 : + (fpu_fOperands_S0$D_OUT[29] ? + 6'd26 : + (fpu_fOperands_S0$D_OUT[28] ? + 6'd27 : + (fpu_fOperands_S0$D_OUT[27] ? + 6'd28 : + (fpu_fOperands_S0$D_OUT[26] ? + 6'd29 : + (fpu_fOperands_S0$D_OUT[25] ? + 6'd30 : + (fpu_fOperands_S0$D_OUT[24] ? + 6'd31 : + (fpu_fOperands_S0$D_OUT[23] ? + 6'd32 : + (fpu_fOperands_S0$D_OUT[22] ? + 6'd33 : + (fpu_fOperands_S0$D_OUT[21] ? + 6'd34 : + (fpu_fOperands_S0$D_OUT[20] ? + 6'd35 : + (fpu_fOperands_S0$D_OUT[19] ? + 6'd36 : + (fpu_fOperands_S0$D_OUT[18] ? + 6'd37 : + (fpu_fOperands_S0$D_OUT[17] ? + 6'd38 : + (fpu_fOperands_S0$D_OUT[16] ? + 6'd39 : + (fpu_fOperands_S0$D_OUT[15] ? + 6'd40 : + (fpu_fOperands_S0$D_OUT[14] ? + 6'd41 : + (fpu_fOperands_S0$D_OUT[13] ? + 6'd42 : + (fpu_fOperands_S0$D_OUT[12] ? + 6'd43 : + (fpu_fOperands_S0$D_OUT[11] ? + 6'd44 : + (fpu_fOperands_S0$D_OUT[10] ? + 6'd45 : + (fpu_fOperands_S0$D_OUT[9] ? + 6'd46 : + (fpu_fOperands_S0$D_OUT[8] ? + 6'd47 : + (fpu_fOperands_S0$D_OUT[7] ? + 6'd48 : + (fpu_fOperands_S0$D_OUT[6] ? + 6'd49 : + (fpu_fOperands_S0$D_OUT[5] ? + 6'd50 : + (fpu_fOperands_S0$D_OUT[4] ? + 6'd51 : + (fpu_fOperands_S0$D_OUT[3] ? + 6'd52 : + 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : + 6'd0 ; + assign b__h3035 = { int_div_fNext_6$D_OUT[231:174], 58'd0 } ; + assign b__h3359 = { int_div_fNext_7$D_OUT[231:174], 58'd0 } ; + assign b__h3683 = { int_div_fNext_8$D_OUT[231:174], 58'd0 } ; + assign b__h378 = { 1'd0, int_div_fRequest$D_OUT[56:0] } ; + assign b__h4007 = { int_div_fNext_9$D_OUT[231:174], 58'd0 } ; + assign b__h4331 = { int_div_fNext_10$D_OUT[231:174], 58'd0 } ; + assign b__h4655 = { int_div_fNext_11$D_OUT[231:174], 58'd0 } ; + assign b__h4979 = { int_div_fNext_12$D_OUT[231:174], 58'd0 } ; + assign b__h5303 = { int_div_fNext_13$D_OUT[231:174], 58'd0 } ; + assign b__h5627 = { int_div_fNext_14$D_OUT[231:174], 58'd0 } ; + assign b__h5951 = { int_div_fNext_15$D_OUT[231:174], 58'd0 } ; + assign b__h6275 = { int_div_fNext_16$D_OUT[231:174], 58'd0 } ; + assign b__h6599 = { int_div_fNext_17$D_OUT[231:174], 58'd0 } ; + assign b__h6923 = { int_div_fNext_18$D_OUT[231:174], 58'd0 } ; + assign b__h7247 = { int_div_fNext_19$D_OUT[231:174], 58'd0 } ; + assign b__h7571 = { int_div_fNext_20$D_OUT[231:174], 58'd0 } ; + assign b__h767 = { int_div_fFirst$D_OUT[231:174], 58'd0 } ; + assign b__h7895 = { int_div_fNext_21$D_OUT[231:174], 58'd0 } ; + assign b__h8219 = { int_div_fNext_22$D_OUT[231:174], 58'd0 } ; + assign b__h8543 = { int_div_fNext_23$D_OUT[231:174], 58'd0 } ; + assign b__h8867 = { int_div_fNext_24$D_OUT[231:174], 58'd0 } ; + assign b__h9191 = { int_div_fNext_25$D_OUT[231:174], 58'd0 } ; + assign b__h9515 = { int_div_fNext_26$D_OUT[231:174], 58'd0 } ; + assign b__h9839 = { int_div_fNext_27$D_OUT[231:174], 58'd0 } ; + assign din_inc___2_exp__h61001 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; + assign fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 = + fpu_fOperands_S0$D_OUT[129:119] - 11'd1023 ; + assign fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 = + fpu_fOperands_S0$D_OUT[65:55] - 11'd1023 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 ; + assign fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 = + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; + assign fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 = + fpu_fOperands_S0$D_OUT[130] == fpu_fOperands_S0$D_OUT[66] ; + assign fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780 = + { fpu_fState_S3$D_OUT[121], + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 : + ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + { _theResult___fst_exp__h59719, + fpu_fState_S3$D_OUT[109:58] } : + 63'h7FEFFFFFFFFFFFFF) : + fpu_fState_S3$D_OUT[120:58]) } ; + assign guard__h51381 = x__h60140 ; + assign int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 = + int_div_fNext_57$D_OUT[173:116] + + -(~int_div_fNext_57$D_OUT[173:116]) ; + assign out_exp__h60913 = + fpu_fState_S4$D_OUT[2] ? + _theResult___exp__h60910 : + fpu_fState_S4$D_OUT[64:54] ; + assign out_sfd__h60914 = + fpu_fState_S4$D_OUT[2] ? + _theResult___sfd__h60911 : + fpu_fState_S4$D_OUT[53:2] ; + assign result__h50077 = { _theResult____h50063[57:1], 1'd1 } ; + assign result__h50108 = + { 1'd0, + value__h50121[56:1], + value__h50121[0] | sfdlsb__h50103 } ; + assign result__h50258 = + (int_div_fResponse$D_OUT[113:57] == 57'd0) ? 58'd0 : 58'd1 ; + assign sfdA__h19785 = + { fpu_fOperands_S0$D_OUT[129:119] != 11'd0, + fpu_fOperands_S0$D_OUT[118:67] } ; + assign sfdA__h19789 = sfdA__h19785 << b__h21789 ; + assign sfdB__h19786 = + { fpu_fOperands_S0$D_OUT[65:55] != 11'd0, + fpu_fOperands_S0$D_OUT[54:3] } ; + assign sfdB__h19791 = sfdB__h19786 << b__h29207 ; + assign sfd__h36684 = { 1'd1, fpu_fOperands_S0$D_OUT[117:67] } ; + assign sfd__h36687 = { 1'd1, fpu_fOperands_S0$D_OUT[53:3] } ; + assign sfd__h60417 = + { 1'b0, + fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:2] } + + 54'd1 ; + assign sfdin__h51553 = + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + _theResult___snd_snd_snd__h51398 : + fpu_fState_S3$D_OUT[57:0] ; + assign sfdin__h59762 = + sfdin__h51553[57] ? + _theResult___snd__h59785 : + _theResult___snd__h59800 ; + assign sfdlsb__h50103 = x__h50197 != 58'd0 ; + assign theResult___fst_exp9725_MINUS_1023__q6 = + _theResult___fst_exp__h59725 - 11'd1023 ; + assign value__h19447 = + int_div_fNext_57$D_OUT[115] ? + int_div_fNext_57$D_OUT[115:0] + b__h19482 : + int_div_fNext_57$D_OUT[115:0] ; + assign value__h49124 = + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 + + 13'd1023 ; + assign value__h49179 = { 1'b0, sfdA__h19789 } ; + assign value__h49300 = + 13'd7170 - + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ; + assign value__h50121 = + int_div_fResponse$D_OUT[113:57] >> fpu_fState_S2$D_OUT[10:0] ; + assign x__h49176 = { value__h49179, 60'd0 } ; + assign x__h49237 = { sfdB__h19791, 4'b0 } ; + assign x__h49291 = + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 ? + 11'd0 : + _theResult___fst__h49072 ; + assign x__h50197 = { 1'd0, int_div_fResponse$D_OUT[113:57] } << x__h50204 ; + assign x__h50204 = 11'd58 - fpu_fState_S2$D_OUT[10:0] ; + assign x__h50487 = + (int_div_fResponse$D_OUT[56:0] == 57'd0) ? + _theResult____h50063 : + result__h50077 ; + assign x__h60140 = + (sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h59874 ; + always@(fpu_fState_S4$D_OUT or out_sfd__h60914 or _theResult___sfd__h60911) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + fpu_fState_S4$D_OUT[53:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + out_sfd__h60914; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + _theResult___sfd__h60911; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___sfd__h60911) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + fpu_fState_S4$D_OUT[53:2]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + _theResult___sfd__h60911; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or + _theResult___sfd__h60911) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_sfd__h60989 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; + 3'd1: + _theResult___fst_sfd__h60989 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; + 3'd2: + _theResult___fst_sfd__h60989 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___sfd__h60911; + 3'd3: + _theResult___fst_sfd__h60989 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[53:2] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___sfd__h60911 : + fpu_fState_S4$D_OUT[53:2]); + 3'd4: _theResult___fst_sfd__h60989 = fpu_fState_S4$D_OUT[53:2]; + default: _theResult___fst_sfd__h60989 = 52'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0, 3'd1: _theResult___fst_exp__h37217 = 11'd2047; + 3'd2: + _theResult___fst_exp__h37217 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 11'd2047 : + 11'd2046; + 3'd3: + _theResult___fst_exp__h37217 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 11'd2046 : + 11'd2047; + 3'd4: _theResult___fst_exp__h37217 = 11'd2046; + default: _theResult___fst_exp__h37217 = 11'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0, 3'd1: _theResult___fst_sfd__h37218 = 52'd0; + 3'd2: + _theResult___fst_sfd__h37218 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'd0 : + 52'hFFFFFFFFFFFFF; + 3'd3: + _theResult___fst_sfd__h37218 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'hFFFFFFFFFFFFF : + 52'd0; + 3'd4: _theResult___fst_sfd__h37218 = 52'hFFFFFFFFFFFFF; + default: _theResult___fst_sfd__h37218 = 52'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0: _theResult___fst_sfd__h37707 = 52'd0; + 3'd1: _theResult___fst_sfd__h37707 = 52'd1; + 3'd2: + _theResult___fst_sfd__h37707 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'd1 : + 52'd0; + 3'd3: + _theResult___fst_sfd__h37707 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'd0 : + 52'd1; + default: _theResult___fst_sfd__h37707 = 52'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; + default: CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = + fpu_fOperands_S0$D_OUT[2:0] == 3'd4 && + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; + endcase + end + always@(fpu_fState_S4$D_OUT or out_exp__h60913 or _theResult___exp__h60910) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = + fpu_fState_S4$D_OUT[64:54]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = + out_exp__h60913; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = + _theResult___exp__h60910; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___exp__h60910) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = + fpu_fState_S4$D_OUT[64:54]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = + _theResult___exp__h60910; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 or + _theResult___exp__h60910) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_exp__h60988 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9; + 3'd1: + _theResult___fst_exp__h60988 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10; + 3'd2: + _theResult___fst_exp__h60988 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___exp__h60910; + 3'd3: + _theResult___fst_exp__h60988 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:54] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___exp__h60910 : + fpu_fState_S4$D_OUT[64:54]); + 3'd4: _theResult___fst_exp__h60988 = fpu_fState_S4$D_OUT[64:54]; + default: _theResult___fst_exp__h60988 = 11'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2, 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = + fpu_fState_S4$D_OUT[65]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = + fpu_fState_S4$D_OUT[68:66] == 3'd4 && + fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:2] : + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; + 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:2] : + (fpu_fState_S4$D_OUT[65] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : + fpu_fState_S4$D_OUT[64:2]); + 3'd4: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = + fpu_fState_S4$D_OUT[64:2]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = 63'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01, 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[65]; + 2'd3: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = + fpu_fState_S4$D_OUT[64:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = + fpu_fState_S4$D_OUT[2] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : + fpu_fState_S4$D_OUT[64:2]; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = 63'd0; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = + { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 }; + 3'd1: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[65:2] : + { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || + fpu_fState_S4$D_OUT[1:0] == 2'b10 || + fpu_fState_S4$D_OUT[1:0] == 2'b11) && + fpu_fState_S4$D_OUT[65], + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 }; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = + { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 }; + endcase + end + always@(fpu_fState_S3$D_OUT) + begin + case (fpu_fState_S3$D_OUT[124:122]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = + fpu_fState_S3$D_OUT[121]; + default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = + fpu_fState_S3$D_OUT[124:122] == 3'd4 && + fpu_fState_S3$D_OUT[121]; + endcase + end + always@(fpu_fState_S3$D_OUT) + begin + case (fpu_fState_S3$D_OUT[124:122]) + 3'd0, 3'd1: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + 63'h7FF0000000000000; + 3'd2: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + fpu_fState_S3$D_OUT[121] ? + 63'h7FEFFFFFFFFFFFFF : + 63'h7FF0000000000000; + 3'd3: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + fpu_fState_S3$D_OUT[121] ? + 63'h7FF0000000000000 : + 63'h7FEFFFFFFFFFFFFF; + 3'd4: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + 63'h7FEFFFFFFFFFFFFF; + default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = 63'd0; + endcase + end endmodule // mkDoubleDiv diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v index a75a034..de193e3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -7,15 +7,16 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 -// RDY_response_get O 1 +// response_get O 69 reg +// RDY_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// request_put I 196 +// request_put I 196 reg // EN_request_put I 1 // EN_response_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// EN_response_get -> RDY_request_put // // @@ -59,44 +60,2035 @@ module mkDoubleFMA(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu - wire [195 : 0] fpu$request_put; - wire [68 : 0] fpu$response_get; - wire fpu$EN_request_put, - fpu$EN_response_get, - fpu$RDY_request_put, - fpu$RDY_response_get; + // ports of submodule fpu_fOperand_S0 + wire [195 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; + wire fpu_fOperand_S0$CLR, + fpu_fOperand_S0$DEQ, + fpu_fOperand_S0$EMPTY_N, + fpu_fOperand_S0$ENQ, + fpu_fOperand_S0$FULL_N; + + // ports of submodule fpu_fProd_S2 + wire [105 : 0] fpu_fProd_S2$D_IN, fpu_fProd_S2$D_OUT; + wire fpu_fProd_S2$CLR, + fpu_fProd_S2$DEQ, + fpu_fProd_S2$EMPTY_N, + fpu_fProd_S2$ENQ, + fpu_fProd_S2$FULL_N; + + // ports of submodule fpu_fProd_S3 + wire [105 : 0] fpu_fProd_S3$D_IN, fpu_fProd_S3$D_OUT; + wire fpu_fProd_S3$CLR, + fpu_fProd_S3$DEQ, + fpu_fProd_S3$EMPTY_N, + fpu_fProd_S3$ENQ, + fpu_fProd_S3$FULL_N; + + // ports of submodule fpu_fResult_S9 + wire [68 : 0] fpu_fResult_S9$D_IN, fpu_fResult_S9$D_OUT; + wire fpu_fResult_S9$CLR, + fpu_fResult_S9$DEQ, + fpu_fResult_S9$EMPTY_N, + fpu_fResult_S9$ENQ, + fpu_fResult_S9$FULL_N; + + // ports of submodule fpu_fState_S1 + wire [257 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; + wire fpu_fState_S1$CLR, + fpu_fState_S1$DEQ, + fpu_fState_S1$EMPTY_N, + fpu_fState_S1$ENQ, + fpu_fState_S1$FULL_N; + + // ports of submodule fpu_fState_S2 + wire [151 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; + wire fpu_fState_S2$CLR, + fpu_fState_S2$DEQ, + fpu_fState_S2$EMPTY_N, + fpu_fState_S2$ENQ, + fpu_fState_S2$FULL_N; + + // ports of submodule fpu_fState_S3 + wire [151 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; + wire fpu_fState_S3$CLR, + fpu_fState_S3$DEQ, + fpu_fState_S3$EMPTY_N, + fpu_fState_S3$ENQ, + fpu_fState_S3$FULL_N; + + // ports of submodule fpu_fState_S4 + wire [203 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; + wire fpu_fState_S4$CLR, + fpu_fState_S4$DEQ, + fpu_fState_S4$EMPTY_N, + fpu_fState_S4$ENQ, + fpu_fState_S4$FULL_N; + + // ports of submodule fpu_fState_S5 + wire [215 : 0] fpu_fState_S5$D_IN, fpu_fState_S5$D_OUT; + wire fpu_fState_S5$CLR, + fpu_fState_S5$DEQ, + fpu_fState_S5$EMPTY_N, + fpu_fState_S5$ENQ, + fpu_fState_S5$FULL_N; + + // ports of submodule fpu_fState_S6 + wire [202 : 0] fpu_fState_S6$D_IN, fpu_fState_S6$D_OUT; + wire fpu_fState_S6$CLR, + fpu_fState_S6$DEQ, + fpu_fState_S6$EMPTY_N, + fpu_fState_S6$ENQ, + fpu_fState_S6$FULL_N; + + // ports of submodule fpu_fState_S7 + wire [202 : 0] fpu_fState_S7$D_IN, fpu_fState_S7$D_OUT; + wire fpu_fState_S7$CLR, + fpu_fState_S7$DEQ, + fpu_fState_S7$EMPTY_N, + fpu_fState_S7$ENQ, + fpu_fState_S7$FULL_N; + + // ports of submodule fpu_fState_S8 + wire [140 : 0] fpu_fState_S8$D_IN, fpu_fState_S8$D_OUT; + wire fpu_fState_S8$CLR, + fpu_fState_S8$DEQ, + fpu_fState_S8$EMPTY_N, + fpu_fState_S8$ENQ, + fpu_fState_S8$FULL_N; // rule scheduling signals - wire CAN_FIRE_request_put, + wire CAN_FIRE_RL_fpu_s1_stage, + CAN_FIRE_RL_fpu_s2_stage, + CAN_FIRE_RL_fpu_s3_stage, + CAN_FIRE_RL_fpu_s4_stage, + CAN_FIRE_RL_fpu_s5_stage, + CAN_FIRE_RL_fpu_s6_stage, + CAN_FIRE_RL_fpu_s7_stage, + CAN_FIRE_RL_fpu_s8_stage, + CAN_FIRE_RL_fpu_s9_stage, + CAN_FIRE_request_put, CAN_FIRE_response_get, + WILL_FIRE_RL_fpu_s1_stage, + WILL_FIRE_RL_fpu_s2_stage, + WILL_FIRE_RL_fpu_s3_stage, + WILL_FIRE_RL_fpu_s4_stage, + WILL_FIRE_RL_fpu_s5_stage, + WILL_FIRE_RL_fpu_s6_stage, + WILL_FIRE_RL_fpu_s7_stage, + WILL_FIRE_RL_fpu_s8_stage, + WILL_FIRE_RL_fpu_s9_stage, WILL_FIRE_request_put, WILL_FIRE_response_get; + // remaining internal signals + reg [62 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17, + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18, + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19; + reg [51 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1, + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2, + _theResult___fst_sfd__h46438; + reg [10 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11, + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12, + _theResult___fst_exp__h46437; + reg CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14; + wire [139 : 0] IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796; + wire [118 : 0] IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160; + wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4, + _theResult___fst__h20642, + _theResult___snd__h34781, + _theResult___snd__h34795, + _theResult___snd__h34797, + _theResult___snd__h34809, + _theResult___snd__h34815, + _theResult___snd__h34833, + _theResult___snd__h34838, + fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213, + sfdBC__h19477, + sfdin__h34758, + x__h20711; + wire [68 : 0] IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282; + wire [63 : 0] IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137, + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139; + wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735, + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132, + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737; + wire [56 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9, + _theResult___snd__h45207, + _theResult___snd__h45221, + _theResult___snd__h45223, + _theResult___snd__h45235, + _theResult___snd__h45241, + _theResult___snd__h45259, + _theResult___snd__h45264, + fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816, + guard__h36182, + result__h36187, + sfdA__h35392, + sfdBC__h35393, + sfd__h36934, + sfdin__h45184, + x__h35755, + x__h35759, + x__h36174, + x__h36686, + x__h36695; + wire [53 : 0] sfd__h45855; + wire [52 : 0] x__h18058, x__h18070; + wire [51 : 0] _theResult___fst_sfd__h396, + _theResult___sfd__h46360, + out_sfd__h46363, + sfd__h3208, + sfd__h3211, + sfd__h3214; + wire [12 : 0] IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208, + value__h34698, + value__h45122, + x__h20744, + x__h36286; + wire [11 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663, + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104, + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869; + wire [10 : 0] IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212, + _theResult___exp__h46359, + _theResult___fst_exp__h34764, + _theResult___fst_exp__h34767, + _theResult___fst_exp__h34786, + _theResult___fst_exp__h34801, + _theResult___fst_exp__h34840, + _theResult___fst_exp__h34846, + _theResult___fst_exp__h34849, + _theResult___fst_exp__h45190, + _theResult___fst_exp__h45193, + _theResult___fst_exp__h45212, + _theResult___fst_exp__h45227, + _theResult___fst_exp__h45266, + _theResult___fst_exp__h45272, + _theResult___fst_exp__h45275, + din_exp4681_MINUS_1023__q3, + din_exp__h34681, + din_inc___2_exp__h46444, + fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16, + fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7, + fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6, + out_exp__h46362, + value5122_BITS_10_TO_0_MINUS_1023__q8, + x__h327; + wire [6 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661; + wire [5 : 0] IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102; + wire [4 : 0] IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702, + fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, + fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244; + wire [2 : 0] NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724; + wire [1 : 0] IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5, + IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10, + _theResult___snd_fst__h34866, + _theResult___snd_fst__h45292, + _theResult___snd_snd__h35186, + _theResult___snd_snd_snd__h35184, + guardBC__h19481, + guard__h36938, + x__h35221, + x__h45575; + wire IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123, + IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, + IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717, + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722, + IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, + NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147, + NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, + NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785, + _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664, + _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105, + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209, + fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127, + fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58, + fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56, + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203, + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205, + sfdlsb__h20640; + // action method request_put - assign RDY_request_put = fpu$RDY_request_put ; - assign CAN_FIRE_request_put = fpu$RDY_request_put ; + assign RDY_request_put = fpu_fOperand_S0$FULL_N ; + assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu$response_get ; - assign RDY_response_get = fpu$RDY_response_get ; - assign CAN_FIRE_response_get = fpu$RDY_response_get ; + assign response_get = fpu_fResult_S9$D_OUT ; + assign RDY_response_get = fpu_fResult_S9$EMPTY_N ; + assign CAN_FIRE_response_get = fpu_fResult_S9$EMPTY_N ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu - mkXilinxFpFma fpu(.CLK(CLK), - .RST_N(RST_N), - .request_put(fpu$request_put), - .EN_request_put(fpu$EN_request_put), - .EN_response_get(fpu$EN_response_get), - .RDY_request_put(fpu$RDY_request_put), - .response_get(fpu$response_get), - .RDY_response_get(fpu$RDY_response_get)); + // submodule fpu_fOperand_S0 + FIFOL1 #(.width(32'd196)) fpu_fOperand_S0(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fOperand_S0$D_IN), + .ENQ(fpu_fOperand_S0$ENQ), + .DEQ(fpu_fOperand_S0$DEQ), + .CLR(fpu_fOperand_S0$CLR), + .D_OUT(fpu_fOperand_S0$D_OUT), + .FULL_N(fpu_fOperand_S0$FULL_N), + .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); - // submodule fpu - assign fpu$request_put = request_put ; - assign fpu$EN_request_put = EN_request_put ; - assign fpu$EN_response_get = EN_response_get ; + // submodule fpu_fProd_S2 + FIFOL1 #(.width(32'd106)) fpu_fProd_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fProd_S2$D_IN), + .ENQ(fpu_fProd_S2$ENQ), + .DEQ(fpu_fProd_S2$DEQ), + .CLR(fpu_fProd_S2$CLR), + .D_OUT(fpu_fProd_S2$D_OUT), + .FULL_N(fpu_fProd_S2$FULL_N), + .EMPTY_N(fpu_fProd_S2$EMPTY_N)); + + // submodule fpu_fProd_S3 + FIFOL1 #(.width(32'd106)) fpu_fProd_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fProd_S3$D_IN), + .ENQ(fpu_fProd_S3$ENQ), + .DEQ(fpu_fProd_S3$DEQ), + .CLR(fpu_fProd_S3$CLR), + .D_OUT(fpu_fProd_S3$D_OUT), + .FULL_N(fpu_fProd_S3$FULL_N), + .EMPTY_N(fpu_fProd_S3$EMPTY_N)); + + // submodule fpu_fResult_S9 + FIFOL1 #(.width(32'd69)) fpu_fResult_S9(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fResult_S9$D_IN), + .ENQ(fpu_fResult_S9$ENQ), + .DEQ(fpu_fResult_S9$DEQ), + .CLR(fpu_fResult_S9$CLR), + .D_OUT(fpu_fResult_S9$D_OUT), + .FULL_N(fpu_fResult_S9$FULL_N), + .EMPTY_N(fpu_fResult_S9$EMPTY_N)); + + // submodule fpu_fState_S1 + FIFOL1 #(.width(32'd258)) fpu_fState_S1(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S1$D_IN), + .ENQ(fpu_fState_S1$ENQ), + .DEQ(fpu_fState_S1$DEQ), + .CLR(fpu_fState_S1$CLR), + .D_OUT(fpu_fState_S1$D_OUT), + .FULL_N(fpu_fState_S1$FULL_N), + .EMPTY_N(fpu_fState_S1$EMPTY_N)); + + // submodule fpu_fState_S2 + FIFOL1 #(.width(32'd152)) fpu_fState_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S2$D_IN), + .ENQ(fpu_fState_S2$ENQ), + .DEQ(fpu_fState_S2$DEQ), + .CLR(fpu_fState_S2$CLR), + .D_OUT(fpu_fState_S2$D_OUT), + .FULL_N(fpu_fState_S2$FULL_N), + .EMPTY_N(fpu_fState_S2$EMPTY_N)); + + // submodule fpu_fState_S3 + FIFOL1 #(.width(32'd152)) fpu_fState_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S3$D_IN), + .ENQ(fpu_fState_S3$ENQ), + .DEQ(fpu_fState_S3$DEQ), + .CLR(fpu_fState_S3$CLR), + .D_OUT(fpu_fState_S3$D_OUT), + .FULL_N(fpu_fState_S3$FULL_N), + .EMPTY_N(fpu_fState_S3$EMPTY_N)); + + // submodule fpu_fState_S4 + FIFOL1 #(.width(32'd204)) fpu_fState_S4(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S4$D_IN), + .ENQ(fpu_fState_S4$ENQ), + .DEQ(fpu_fState_S4$DEQ), + .CLR(fpu_fState_S4$CLR), + .D_OUT(fpu_fState_S4$D_OUT), + .FULL_N(fpu_fState_S4$FULL_N), + .EMPTY_N(fpu_fState_S4$EMPTY_N)); + + // submodule fpu_fState_S5 + FIFOL1 #(.width(32'd216)) fpu_fState_S5(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S5$D_IN), + .ENQ(fpu_fState_S5$ENQ), + .DEQ(fpu_fState_S5$DEQ), + .CLR(fpu_fState_S5$CLR), + .D_OUT(fpu_fState_S5$D_OUT), + .FULL_N(fpu_fState_S5$FULL_N), + .EMPTY_N(fpu_fState_S5$EMPTY_N)); + + // submodule fpu_fState_S6 + FIFOL1 #(.width(32'd203)) fpu_fState_S6(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S6$D_IN), + .ENQ(fpu_fState_S6$ENQ), + .DEQ(fpu_fState_S6$DEQ), + .CLR(fpu_fState_S6$CLR), + .D_OUT(fpu_fState_S6$D_OUT), + .FULL_N(fpu_fState_S6$FULL_N), + .EMPTY_N(fpu_fState_S6$EMPTY_N)); + + // submodule fpu_fState_S7 + FIFOL1 #(.width(32'd203)) fpu_fState_S7(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S7$D_IN), + .ENQ(fpu_fState_S7$ENQ), + .DEQ(fpu_fState_S7$DEQ), + .CLR(fpu_fState_S7$CLR), + .D_OUT(fpu_fState_S7$D_OUT), + .FULL_N(fpu_fState_S7$FULL_N), + .EMPTY_N(fpu_fState_S7$EMPTY_N)); + + // submodule fpu_fState_S8 + FIFOL1 #(.width(32'd141)) fpu_fState_S8(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S8$D_IN), + .ENQ(fpu_fState_S8$ENQ), + .DEQ(fpu_fState_S8$DEQ), + .CLR(fpu_fState_S8$CLR), + .D_OUT(fpu_fState_S8$D_OUT), + .FULL_N(fpu_fState_S8$FULL_N), + .EMPTY_N(fpu_fState_S8$EMPTY_N)); + + // rule RL_fpu_s9_stage + assign CAN_FIRE_RL_fpu_s9_stage = + fpu_fState_S8$EMPTY_N && fpu_fResult_S9$FULL_N ; + assign WILL_FIRE_RL_fpu_s9_stage = CAN_FIRE_RL_fpu_s9_stage ; + + // rule RL_fpu_s8_stage + assign CAN_FIRE_RL_fpu_s8_stage = + fpu_fState_S7$EMPTY_N && fpu_fState_S8$FULL_N ; + assign WILL_FIRE_RL_fpu_s8_stage = CAN_FIRE_RL_fpu_s8_stage ; + + // rule RL_fpu_s7_stage + assign CAN_FIRE_RL_fpu_s7_stage = + fpu_fState_S6$EMPTY_N && fpu_fState_S7$FULL_N ; + assign WILL_FIRE_RL_fpu_s7_stage = CAN_FIRE_RL_fpu_s7_stage ; + + // rule RL_fpu_s6_stage + assign CAN_FIRE_RL_fpu_s6_stage = + fpu_fState_S5$EMPTY_N && fpu_fState_S6$FULL_N ; + assign WILL_FIRE_RL_fpu_s6_stage = CAN_FIRE_RL_fpu_s6_stage ; + + // rule RL_fpu_s5_stage + assign CAN_FIRE_RL_fpu_s5_stage = + fpu_fState_S4$EMPTY_N && fpu_fState_S5$FULL_N ; + assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; + + // rule RL_fpu_s4_stage + assign CAN_FIRE_RL_fpu_s4_stage = + fpu_fState_S3$EMPTY_N && fpu_fProd_S3$EMPTY_N && + fpu_fState_S4$FULL_N ; + assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; + + // rule RL_fpu_s3_stage + assign CAN_FIRE_RL_fpu_s3_stage = + fpu_fState_S2$EMPTY_N && fpu_fProd_S2$EMPTY_N && + fpu_fProd_S3$FULL_N && + fpu_fState_S3$FULL_N ; + assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; + + // rule RL_fpu_s2_stage + assign CAN_FIRE_RL_fpu_s2_stage = + fpu_fState_S1$EMPTY_N && fpu_fProd_S2$FULL_N && + fpu_fState_S2$FULL_N ; + assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; + + // rule RL_fpu_s1_stage + assign CAN_FIRE_RL_fpu_s1_stage = + fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; + assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; + + // submodule fpu_fOperand_S0 + assign fpu_fOperand_S0$D_IN = request_put ; + assign fpu_fOperand_S0$ENQ = EN_request_put ; + assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fOperand_S0$CLR = 1'b0 ; + + // submodule fpu_fProd_S2 + assign fpu_fProd_S2$D_IN = + fpu_fState_S1$D_OUT[105:53] * fpu_fState_S1$D_OUT[52:0] ; + assign fpu_fProd_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fProd_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fProd_S2$CLR = 1'b0 ; + + // submodule fpu_fProd_S3 + assign fpu_fProd_S3$D_IN = fpu_fProd_S2$D_OUT ; + assign fpu_fProd_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fProd_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fProd_S3$CLR = 1'b0 ; + + // submodule fpu_fResult_S9 + assign fpu_fResult_S9$D_IN = + fpu_fState_S8$D_OUT[140] ? + fpu_fState_S8$D_OUT[139:71] : + IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 ; + assign fpu_fResult_S9$ENQ = CAN_FIRE_RL_fpu_s9_stage ; + assign fpu_fResult_S9$DEQ = EN_response_get ; + assign fpu_fResult_S9$CLR = 1'b0 ; + + // submodule fpu_fState_S1 + assign fpu_fState_S1$D_IN = + { x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && + !_theResult___fst_sfd__h396[51] || + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperand_S0$D_OUT[118] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54] || + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, + 4'd0, + fpu_fOperand_S0$D_OUT[2:0], + fpu_fOperand_S0$D_OUT[195], + fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 } ; + assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S1$CLR = 1'b0 ; + + // submodule fpu_fState_S2 + assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[257:106] ; + assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S2$CLR = 1'b0 ; + + // submodule fpu_fState_S3 + assign fpu_fState_S3$D_IN = fpu_fState_S2$D_OUT ; + assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S3$CLR = 1'b0 ; + + // submodule fpu_fState_S4 + assign fpu_fState_S4$D_IN = + { fpu_fState_S3$D_OUT[151:87], + IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, + fpu_fState_S3$D_OUT[81:14], + !fpu_fState_S3$D_OUT[151] && fpu_fState_S3$D_OUT[13], + fpu_fState_S3$D_OUT[151] ? + 63'd0 : + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737, + x__h35221 } ; + assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S4$CLR = 1'b0 ; + + // submodule fpu_fState_S5 + assign fpu_fState_S5$D_IN = + { fpu_fState_S4$D_OUT[203:130], + fpu_fState_S4$D_OUT[129] != fpu_fState_S4$D_OUT[65], + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + fpu_fState_S4$D_OUT[65] : + fpu_fState_S4$D_OUT[129], + IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 } ; + assign fpu_fState_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S5$DEQ = CAN_FIRE_RL_fpu_s6_stage ; + assign fpu_fState_S5$CLR = 1'b0 ; + + // submodule fpu_fState_S6 + assign fpu_fState_S6$D_IN = + { fpu_fState_S5$D_OUT[215:127], + fpu_fState_S5$D_OUT[113:57], + x__h36174 } ; + assign fpu_fState_S6$ENQ = CAN_FIRE_RL_fpu_s6_stage ; + assign fpu_fState_S6$DEQ = CAN_FIRE_RL_fpu_s7_stage ; + assign fpu_fState_S6$CLR = 1'b0 ; + + // submodule fpu_fState_S7 + assign fpu_fState_S7$D_IN = + { fpu_fState_S6$D_OUT[202:114], x__h36686, x__h36695 } ; + assign fpu_fState_S7$ENQ = CAN_FIRE_RL_fpu_s7_stage ; + assign fpu_fState_S7$DEQ = CAN_FIRE_RL_fpu_s8_stage ; + assign fpu_fState_S7$CLR = 1'b0 ; + + // submodule fpu_fState_S8 + assign fpu_fState_S8$D_IN = + { fpu_fState_S7$D_OUT[202:138], + fpu_fState_S7$D_OUT[202] ? + fpu_fState_S7$D_OUT[137:133] : + fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, + fpu_fState_S7$D_OUT[132:129], + !fpu_fState_S7$D_OUT[202] && fpu_fState_S7$D_OUT[127], + fpu_fState_S7$D_OUT[202] ? + 63'd0 : + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, + x__h45575, + fpu_fState_S7$D_OUT[128] } ; + assign fpu_fState_S8$ENQ = CAN_FIRE_RL_fpu_s8_stage ; + assign fpu_fState_S8$DEQ = CAN_FIRE_RL_fpu_s9_stage ; + assign fpu_fState_S8$CLR = 1'b0 ; + + // remaining internal signals + assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4 = + _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 ? + _theResult___snd__h34838 : + _theResult___snd__h34833 ; + assign IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9 = + _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 ? + _theResult___snd__h45264 : + _theResult___snd__h45259 ; + assign IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 = + sfd__h45855[53] ? + ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? + 63'h7FF0000000000000 : + { din_inc___2_exp__h46444, sfd__h45855[52:1] }) : + { IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, + sfd__h45855[51:0] } ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 = + (din_exp__h34681 == 11'd0) ? + 12'd3074 : + { din_exp4681_MINUS_1023__q3[10], + din_exp4681_MINUS_1023__q3 } ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 = + (sfdBC__h19477[105] ? + 7'd0 : + (sfdBC__h19477[104] ? + 7'd1 : + (sfdBC__h19477[103] ? + 7'd2 : + (sfdBC__h19477[102] ? + 7'd3 : + (sfdBC__h19477[101] ? + 7'd4 : + (sfdBC__h19477[100] ? + 7'd5 : + (sfdBC__h19477[99] ? + 7'd6 : + (sfdBC__h19477[98] ? + 7'd7 : + (sfdBC__h19477[97] ? + 7'd8 : + (sfdBC__h19477[96] ? + 7'd9 : + (sfdBC__h19477[95] ? + 7'd10 : + (sfdBC__h19477[94] ? + 7'd11 : + (sfdBC__h19477[93] ? + 7'd12 : + (sfdBC__h19477[92] ? + 7'd13 : + (sfdBC__h19477[91] ? + 7'd14 : + (sfdBC__h19477[90] ? + 7'd15 : + (sfdBC__h19477[89] ? + 7'd16 : + (sfdBC__h19477[88] ? + 7'd17 : + (sfdBC__h19477[87] ? + 7'd18 : + (sfdBC__h19477[86] ? + 7'd19 : + (sfdBC__h19477[85] ? + 7'd20 : + (sfdBC__h19477[84] ? + 7'd21 : + (sfdBC__h19477[83] ? + 7'd22 : + (sfdBC__h19477[82] ? + 7'd23 : + (sfdBC__h19477[81] ? + 7'd24 : + (sfdBC__h19477[80] ? + 7'd25 : + (sfdBC__h19477[79] ? + 7'd26 : + (sfdBC__h19477[78] ? + 7'd27 : + (sfdBC__h19477[77] ? + 7'd28 : + (sfdBC__h19477[76] ? + 7'd29 : + (sfdBC__h19477[75] ? + 7'd30 : + (sfdBC__h19477[74] ? + 7'd31 : + (sfdBC__h19477[73] ? + 7'd32 : + (sfdBC__h19477[72] ? + 7'd33 : + (sfdBC__h19477[71] ? + 7'd34 : + (sfdBC__h19477[70] ? + 7'd35 : + (sfdBC__h19477[69] ? + 7'd36 : + (sfdBC__h19477[68] ? + 7'd37 : + (sfdBC__h19477[67] ? + 7'd38 : + (sfdBC__h19477[66] ? + 7'd39 : + (sfdBC__h19477[65] ? + 7'd40 : + (sfdBC__h19477[64] ? + 7'd41 : + (sfdBC__h19477[63] ? + 7'd42 : + (sfdBC__h19477[62] ? + 7'd43 : + (sfdBC__h19477[61] ? + 7'd44 : + (sfdBC__h19477[60] ? + 7'd45 : + (sfdBC__h19477[59] ? + 7'd46 : + (sfdBC__h19477[58] ? + 7'd47 : + (sfdBC__h19477[57] ? + 7'd48 : + (sfdBC__h19477[56] ? + 7'd49 : + (sfdBC__h19477[55] ? + 7'd50 : + (sfdBC__h19477[54] ? + 7'd51 : + (sfdBC__h19477[53] ? + 7'd52 : + (sfdBC__h19477[52] ? + 7'd53 : + (sfdBC__h19477[51] ? + 7'd54 : + (sfdBC__h19477[50] ? + 7'd55 : + (sfdBC__h19477[49] ? + 7'd56 : + (sfdBC__h19477[48] ? + 7'd57 : + (sfdBC__h19477[47] ? + 7'd58 : + (sfdBC__h19477[46] ? + 7'd59 : + (sfdBC__h19477[45] ? + 7'd60 : + (sfdBC__h19477[44] ? + 7'd61 : + (sfdBC__h19477[43] ? + 7'd62 : + (sfdBC__h19477[42] ? + 7'd63 : + (sfdBC__h19477[41] ? + 7'd64 : + (sfdBC__h19477[40] ? + 7'd65 : + (sfdBC__h19477[39] ? + 7'd66 : + (sfdBC__h19477[38] ? + 7'd67 : + (sfdBC__h19477[37] ? + 7'd68 : + (sfdBC__h19477[36] ? + 7'd69 : + (sfdBC__h19477[35] ? + 7'd70 : + (sfdBC__h19477[34] ? + 7'd71 : + (sfdBC__h19477[33] ? + 7'd72 : + (sfdBC__h19477[32] ? + 7'd73 : + (sfdBC__h19477[31] ? + 7'd74 : + (sfdBC__h19477[30] ? + 7'd75 : + (sfdBC__h19477[29] ? + 7'd76 : + (sfdBC__h19477[28] ? + 7'd77 : + (sfdBC__h19477[27] ? + 7'd78 : + (sfdBC__h19477[26] ? + 7'd79 : + (sfdBC__h19477[25] ? + 7'd80 : + (sfdBC__h19477[24] ? + 7'd81 : + (sfdBC__h19477[23] ? + 7'd82 : + (sfdBC__h19477[22] ? + 7'd83 : + (sfdBC__h19477[21] ? + 7'd84 : + (sfdBC__h19477[20] ? + 7'd85 : + (sfdBC__h19477[19] ? + 7'd86 : + (sfdBC__h19477[18] ? + 7'd87 : + (sfdBC__h19477[17] ? + 7'd88 : + (sfdBC__h19477[16] ? + 7'd89 : + (sfdBC__h19477[15] ? + 7'd90 : + (sfdBC__h19477[14] ? + 7'd91 : + (sfdBC__h19477[13] ? + 7'd92 : + (sfdBC__h19477[12] ? + 7'd93 : + (sfdBC__h19477[11] ? + 7'd94 : + (sfdBC__h19477[10] ? + 7'd95 : + (sfdBC__h19477[9] ? + 7'd96 : + (sfdBC__h19477[8] ? + 7'd97 : + (sfdBC__h19477[7] ? + 7'd98 : + (sfdBC__h19477[6] ? + 7'd99 : + (sfdBC__h19477[5] ? + 7'd100 : + (sfdBC__h19477[4] ? + 7'd101 : + (sfdBC__h19477[3] ? + 7'd102 : + (sfdBC__h19477[2] ? + 7'd103 : + (sfdBC__h19477[1] ? + 7'd104 : + (sfdBC__h19477[0] ? + 7'd105 : + 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 7'd1 ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 = + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 - + 12'd3074 ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735 = + (sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h34764, sfdin__h34758[105:54] } ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? + fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194] : + ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 : + fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 : + ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? + 63'h7FF0000000000000 : + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112) ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51]) ? + { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 } : + ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118]) ? + fpu_fOperand_S0$D_OUT[130:67] : + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54]) ? + fpu_fOperand_S0$D_OUT[66:3] : + { NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 })) ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && + !_theResult___fst_sfd__h396[51]) ? + { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], + x__h327, + sfd__h3208 } : + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 ; + assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 = + (sfd__h36934[56] ? + 6'd0 : + (sfd__h36934[55] ? + 6'd1 : + (sfd__h36934[54] ? + 6'd2 : + (sfd__h36934[53] ? + 6'd3 : + (sfd__h36934[52] ? + 6'd4 : + (sfd__h36934[51] ? + 6'd5 : + (sfd__h36934[50] ? + 6'd6 : + (sfd__h36934[49] ? + 6'd7 : + (sfd__h36934[48] ? + 6'd8 : + (sfd__h36934[47] ? + 6'd9 : + (sfd__h36934[46] ? + 6'd10 : + (sfd__h36934[45] ? + 6'd11 : + (sfd__h36934[44] ? + 6'd12 : + (sfd__h36934[43] ? + 6'd13 : + (sfd__h36934[42] ? + 6'd14 : + (sfd__h36934[41] ? + 6'd15 : + (sfd__h36934[40] ? + 6'd16 : + (sfd__h36934[39] ? + 6'd17 : + (sfd__h36934[38] ? + 6'd18 : + (sfd__h36934[37] ? + 6'd19 : + (sfd__h36934[36] ? + 6'd20 : + (sfd__h36934[35] ? + 6'd21 : + (sfd__h36934[34] ? + 6'd22 : + (sfd__h36934[33] ? + 6'd23 : + (sfd__h36934[32] ? + 6'd24 : + (sfd__h36934[31] ? + 6'd25 : + (sfd__h36934[30] ? + 6'd26 : + (sfd__h36934[29] ? + 6'd27 : + (sfd__h36934[28] ? + 6'd28 : + (sfd__h36934[27] ? + 6'd29 : + (sfd__h36934[26] ? + 6'd30 : + (sfd__h36934[25] ? + 6'd31 : + (sfd__h36934[24] ? + 6'd32 : + (sfd__h36934[23] ? + 6'd33 : + (sfd__h36934[22] ? + 6'd34 : + (sfd__h36934[21] ? + 6'd35 : + (sfd__h36934[20] ? + 6'd36 : + (sfd__h36934[19] ? + 6'd37 : + (sfd__h36934[18] ? + 6'd38 : + (sfd__h36934[17] ? + 6'd39 : + (sfd__h36934[16] ? + 6'd40 : + (sfd__h36934[15] ? + 6'd41 : + (sfd__h36934[14] ? + 6'd42 : + (sfd__h36934[13] ? + 6'd43 : + (sfd__h36934[12] ? + 6'd44 : + (sfd__h36934[11] ? + 6'd45 : + (sfd__h36934[10] ? + 6'd46 : + (sfd__h36934[9] ? + 6'd47 : + (sfd__h36934[8] ? + 6'd48 : + (sfd__h36934[7] ? + 6'd49 : + (sfd__h36934[6] ? + 6'd50 : + (sfd__h36934[5] ? + 6'd51 : + (sfd__h36934[4] ? + 6'd52 : + (sfd__h36934[3] ? + 6'd53 : + (sfd__h36934[2] ? + 6'd54 : + (sfd__h36934[1] ? + 6'd55 : + (sfd__h36934[0] ? + 6'd56 : + 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 6'd1 ; + assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153 = + (sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h45190, sfdin__h45184[56:5] } ; + assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704 = + (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? + fpu_fState_S3$D_OUT[86] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[4] ; + assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707 = + (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? + fpu_fState_S3$D_OUT[85] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[3] ; + assign IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 = + { NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 : + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 - + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 : + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 - + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, + x__h35755, + x__h35759 } ; + assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 = + (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && + !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ? + 63'h7FF8000000000000 : + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 ; + assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 = + (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperand_S0$D_OUT[118]) ? + { fpu_fOperand_S0$D_OUT[130:119], sfd__h3211 } : + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54]) ? + { fpu_fOperand_S0$D_OUT[66:55], sfd__h3214 } : + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137) ; + assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 = + { ((fpu_fOperand_S0$D_OUT[129:119] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15[10]}}, + fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 }) + + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16[10]}}, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 }), + x__h18058, + x__h18070 } ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 = + fpu_fOperand_S0$D_OUT[195] ? + fpu_fOperand_S0$D_OUT[193:131] : + 63'd0 ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 = + x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 && + (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148 = + x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && + !_theResult___fst_sfd__h396[51] || + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperand_S0$D_OUT[118] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54] || + NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62 = + x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51] || + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54] || + x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 || + fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 ; + assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? + (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + 63'd0 : + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735) : + 63'h7FEFFFFFFFFFFFFF ; + assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[83] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[1] ; + assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[82] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[0] ; + assign IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726 = + fpu_fState_S3$D_OUT[151] ? + fpu_fState_S3$D_OUT[86:82] : + { IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, + IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, + NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 } ; + assign IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 = + (fpu_fState_S4$D_OUT[128:118] == 11'd0) ? + 13'd7170 : + { {2{fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7[10]}}, + fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 } ; + assign IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 = + (fpu_fState_S4$D_OUT[64:54] == 11'd0) ? + 13'd7170 : + { {2{fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6[10]}}, + fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 } ; + assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 = + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 - + 12'd3074 ; + assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 = + (value__h45122[10:0] == 11'd0) ? + 12'd3074 : + { value5122_BITS_10_TO_0_MINUS_1023__q8[10], + value5122_BITS_10_TO_0_MINUS_1023__q8 } ; + assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 = + (fpu_fState_S8$D_OUT[65:55] == 11'd0 && + sfd__h45855[53:52] == 2'b01) ? + 11'd1 : + fpu_fState_S8$D_OUT[65:55] ; + assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 = + (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[65:55] : + _theResult___fst_exp__h46437 ; + assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261 = + (fpu_fState_S8$D_OUT[67] && + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == + 11'd0 && + ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[54:3] : + _theResult___fst_sfd__h46438) == + 52'd0 && + !fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244[0] && + fpu_fState_S8$D_OUT[0]) ? + fpu_fState_S8$D_OUT[70:68] == 3'd3 : + ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[66] : + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14) ; + assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 = + { IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, + (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[65:3] : + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19, + fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 } ; + assign IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5 = + sfdin__h34758[53] ? 2'd2 : 2'd0 ; + assign IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10 = + sfdin__h45184[4] ? 2'd2 : 2'd0 ; + assign NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 = + (x__h327 != 11'd2047 || !_theResult___fst_sfd__h396[51]) && + (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperand_S0$D_OUT[118]) && + (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperand_S0$D_OUT[54]) && + (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && + !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ; + assign NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124 = + (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperand_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && + (x__h327 != 11'd2047 || _theResult___fst_sfd__h396 != 52'd0 || + (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperand_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperand_S0$D_OUT[54:3] != 52'd0) || + fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) && + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 ; + assign NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 = + fpu_fOperand_S0$D_OUT[130] != fpu_fOperand_S0$D_OUT[66] ; + assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711 = + !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + fpu_fState_S3$D_OUT[84] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[2]) ; + assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 = + { NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 : + fpu_fState_S3$D_OUT[83], + !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 } ; + assign NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 = + !fpu_fState_S4$D_OUT[130] || + (IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 ^ + 13'h1000) > + (IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 ^ + 13'h1000) || + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 == + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 && + sfdBC__h35393 > sfdA__h35392 ; + assign _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 = + ({ 5'd0, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ^ + 12'h800) <= + (IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ^ + 12'h800) ; + assign _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 = + ({ 6'd0, + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ^ + 12'h800) <= + (IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ^ + 12'h800) ; + assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 = + 13'd7170 - fpu_fState_S3$D_OUT[12:0] ; + assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 = + (_7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ^ + 13'h1000) <= + 13'd4096 ; + assign _theResult___exp__h46359 = + sfd__h45855[53] ? + ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? + 11'd2047 : + din_inc___2_exp__h46444) : + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 ; + assign _theResult___fst__h20642 = + { fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[105:1], + fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[0] | + sfdlsb__h20640 } ; + assign _theResult___fst_exp__h34764 = + sfdBC__h19477[105] ? + _theResult___fst_exp__h34786 : + _theResult___fst_exp__h34849 ; + assign _theResult___fst_exp__h34767 = + (sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h34764 ; + assign _theResult___fst_exp__h34786 = + (din_exp__h34681 == 11'd0) ? 11'd2 : din_exp__h34681 + 11'd1 ; + assign _theResult___fst_exp__h34801 = + (din_exp__h34681 == 11'd0) ? 11'd1 : din_exp__h34681 ; + assign _theResult___fst_exp__h34840 = + din_exp__h34681 - + { 4'd0, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ; + assign _theResult___fst_exp__h34846 = + (!sfdBC__h19477[105] && !sfdBC__h19477[104] && + !sfdBC__h19477[103] && + !sfdBC__h19477[102] && + !sfdBC__h19477[101] && + !sfdBC__h19477[100] && + !sfdBC__h19477[99] && + !sfdBC__h19477[98] && + !sfdBC__h19477[97] && + !sfdBC__h19477[96] && + !sfdBC__h19477[95] && + !sfdBC__h19477[94] && + !sfdBC__h19477[93] && + !sfdBC__h19477[92] && + !sfdBC__h19477[91] && + !sfdBC__h19477[90] && + !sfdBC__h19477[89] && + !sfdBC__h19477[88] && + !sfdBC__h19477[87] && + !sfdBC__h19477[86] && + !sfdBC__h19477[85] && + !sfdBC__h19477[84] && + !sfdBC__h19477[83] && + !sfdBC__h19477[82] && + !sfdBC__h19477[81] && + !sfdBC__h19477[80] && + !sfdBC__h19477[79] && + !sfdBC__h19477[78] && + !sfdBC__h19477[77] && + !sfdBC__h19477[76] && + !sfdBC__h19477[75] && + !sfdBC__h19477[74] && + !sfdBC__h19477[73] && + !sfdBC__h19477[72] && + !sfdBC__h19477[71] && + !sfdBC__h19477[70] && + !sfdBC__h19477[69] && + !sfdBC__h19477[68] && + !sfdBC__h19477[67] && + !sfdBC__h19477[66] && + !sfdBC__h19477[65] && + !sfdBC__h19477[64] && + !sfdBC__h19477[63] && + !sfdBC__h19477[62] && + !sfdBC__h19477[61] && + !sfdBC__h19477[60] && + !sfdBC__h19477[59] && + !sfdBC__h19477[58] && + !sfdBC__h19477[57] && + !sfdBC__h19477[56] && + !sfdBC__h19477[55] && + !sfdBC__h19477[54] && + !sfdBC__h19477[53] && + !sfdBC__h19477[52] && + !sfdBC__h19477[51] && + !sfdBC__h19477[50] && + !sfdBC__h19477[49] && + !sfdBC__h19477[48] && + !sfdBC__h19477[47] && + !sfdBC__h19477[46] && + !sfdBC__h19477[45] && + !sfdBC__h19477[44] && + !sfdBC__h19477[43] && + !sfdBC__h19477[42] && + !sfdBC__h19477[41] && + !sfdBC__h19477[40] && + !sfdBC__h19477[39] && + !sfdBC__h19477[38] && + !sfdBC__h19477[37] && + !sfdBC__h19477[36] && + !sfdBC__h19477[35] && + !sfdBC__h19477[34] && + !sfdBC__h19477[33] && + !sfdBC__h19477[32] && + !sfdBC__h19477[31] && + !sfdBC__h19477[30] && + !sfdBC__h19477[29] && + !sfdBC__h19477[28] && + !sfdBC__h19477[27] && + !sfdBC__h19477[26] && + !sfdBC__h19477[25] && + !sfdBC__h19477[24] && + !sfdBC__h19477[23] && + !sfdBC__h19477[22] && + !sfdBC__h19477[21] && + !sfdBC__h19477[20] && + !sfdBC__h19477[19] && + !sfdBC__h19477[18] && + !sfdBC__h19477[17] && + !sfdBC__h19477[16] && + !sfdBC__h19477[15] && + !sfdBC__h19477[14] && + !sfdBC__h19477[13] && + !sfdBC__h19477[12] && + !sfdBC__h19477[11] && + !sfdBC__h19477[10] && + !sfdBC__h19477[9] && + !sfdBC__h19477[8] && + !sfdBC__h19477[7] && + !sfdBC__h19477[6] && + !sfdBC__h19477[5] && + !sfdBC__h19477[4] && + !sfdBC__h19477[3] && + !sfdBC__h19477[2] && + !sfdBC__h19477[1] && + !sfdBC__h19477[0] || + !_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664) ? + 11'd0 : + _theResult___fst_exp__h34840 ; + assign _theResult___fst_exp__h34849 = + (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? + _theResult___fst_exp__h34801 : + _theResult___fst_exp__h34846 ; + assign _theResult___fst_exp__h45190 = + sfd__h36934[56] ? + _theResult___fst_exp__h45212 : + _theResult___fst_exp__h45275 ; + assign _theResult___fst_exp__h45193 = + (sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h45190 ; + assign _theResult___fst_exp__h45212 = + (value__h45122[10:0] == 11'd0) ? + 11'd2 : + value__h45122[10:0] + 11'd1 ; + assign _theResult___fst_exp__h45227 = + (value__h45122[10:0] == 11'd0) ? 11'd1 : value__h45122[10:0] ; + assign _theResult___fst_exp__h45266 = + value__h45122[10:0] - + { 5'd0, + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ; + assign _theResult___fst_exp__h45272 = + (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && + !sfd__h36934[53] && + !sfd__h36934[52] && + !sfd__h36934[51] && + !sfd__h36934[50] && + !sfd__h36934[49] && + !sfd__h36934[48] && + !sfd__h36934[47] && + !sfd__h36934[46] && + !sfd__h36934[45] && + !sfd__h36934[44] && + !sfd__h36934[43] && + !sfd__h36934[42] && + !sfd__h36934[41] && + !sfd__h36934[40] && + !sfd__h36934[39] && + !sfd__h36934[38] && + !sfd__h36934[37] && + !sfd__h36934[36] && + !sfd__h36934[35] && + !sfd__h36934[34] && + !sfd__h36934[33] && + !sfd__h36934[32] && + !sfd__h36934[31] && + !sfd__h36934[30] && + !sfd__h36934[29] && + !sfd__h36934[28] && + !sfd__h36934[27] && + !sfd__h36934[26] && + !sfd__h36934[25] && + !sfd__h36934[24] && + !sfd__h36934[23] && + !sfd__h36934[22] && + !sfd__h36934[21] && + !sfd__h36934[20] && + !sfd__h36934[19] && + !sfd__h36934[18] && + !sfd__h36934[17] && + !sfd__h36934[16] && + !sfd__h36934[15] && + !sfd__h36934[14] && + !sfd__h36934[13] && + !sfd__h36934[12] && + !sfd__h36934[11] && + !sfd__h36934[10] && + !sfd__h36934[9] && + !sfd__h36934[8] && + !sfd__h36934[7] && + !sfd__h36934[6] && + !sfd__h36934[5] && + !sfd__h36934[4] && + !sfd__h36934[3] && + !sfd__h36934[2] && + !sfd__h36934[1] && + !sfd__h36934[0] || + !_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105) ? + 11'd0 : + _theResult___fst_exp__h45266 ; + assign _theResult___fst_exp__h45275 = + (!sfd__h36934[56] && sfd__h36934[55]) ? + _theResult___fst_exp__h45227 : + _theResult___fst_exp__h45272 ; + assign _theResult___fst_sfd__h396 = + fpu_fOperand_S0$D_OUT[195] ? + fpu_fOperand_S0$D_OUT[182:131] : + 52'd0 ; + assign _theResult___sfd__h46360 = + sfd__h45855[53] ? + ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? + 52'd0 : + sfd__h45855[52:1]) : + sfd__h45855[51:0] ; + assign _theResult___snd__h34781 = { sfdBC__h19477[104:0], 1'd0 } ; + assign _theResult___snd__h34795 = + (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? + _theResult___snd__h34797 : + _theResult___snd__h34809 ; + assign _theResult___snd__h34797 = { sfdBC__h19477[103:0], 2'd0 } ; + assign _theResult___snd__h34809 = + (!sfdBC__h19477[105] && !sfdBC__h19477[104] && + !sfdBC__h19477[103] && + !sfdBC__h19477[102] && + !sfdBC__h19477[101] && + !sfdBC__h19477[100] && + !sfdBC__h19477[99] && + !sfdBC__h19477[98] && + !sfdBC__h19477[97] && + !sfdBC__h19477[96] && + !sfdBC__h19477[95] && + !sfdBC__h19477[94] && + !sfdBC__h19477[93] && + !sfdBC__h19477[92] && + !sfdBC__h19477[91] && + !sfdBC__h19477[90] && + !sfdBC__h19477[89] && + !sfdBC__h19477[88] && + !sfdBC__h19477[87] && + !sfdBC__h19477[86] && + !sfdBC__h19477[85] && + !sfdBC__h19477[84] && + !sfdBC__h19477[83] && + !sfdBC__h19477[82] && + !sfdBC__h19477[81] && + !sfdBC__h19477[80] && + !sfdBC__h19477[79] && + !sfdBC__h19477[78] && + !sfdBC__h19477[77] && + !sfdBC__h19477[76] && + !sfdBC__h19477[75] && + !sfdBC__h19477[74] && + !sfdBC__h19477[73] && + !sfdBC__h19477[72] && + !sfdBC__h19477[71] && + !sfdBC__h19477[70] && + !sfdBC__h19477[69] && + !sfdBC__h19477[68] && + !sfdBC__h19477[67] && + !sfdBC__h19477[66] && + !sfdBC__h19477[65] && + !sfdBC__h19477[64] && + !sfdBC__h19477[63] && + !sfdBC__h19477[62] && + !sfdBC__h19477[61] && + !sfdBC__h19477[60] && + !sfdBC__h19477[59] && + !sfdBC__h19477[58] && + !sfdBC__h19477[57] && + !sfdBC__h19477[56] && + !sfdBC__h19477[55] && + !sfdBC__h19477[54] && + !sfdBC__h19477[53] && + !sfdBC__h19477[52] && + !sfdBC__h19477[51] && + !sfdBC__h19477[50] && + !sfdBC__h19477[49] && + !sfdBC__h19477[48] && + !sfdBC__h19477[47] && + !sfdBC__h19477[46] && + !sfdBC__h19477[45] && + !sfdBC__h19477[44] && + !sfdBC__h19477[43] && + !sfdBC__h19477[42] && + !sfdBC__h19477[41] && + !sfdBC__h19477[40] && + !sfdBC__h19477[39] && + !sfdBC__h19477[38] && + !sfdBC__h19477[37] && + !sfdBC__h19477[36] && + !sfdBC__h19477[35] && + !sfdBC__h19477[34] && + !sfdBC__h19477[33] && + !sfdBC__h19477[32] && + !sfdBC__h19477[31] && + !sfdBC__h19477[30] && + !sfdBC__h19477[29] && + !sfdBC__h19477[28] && + !sfdBC__h19477[27] && + !sfdBC__h19477[26] && + !sfdBC__h19477[25] && + !sfdBC__h19477[24] && + !sfdBC__h19477[23] && + !sfdBC__h19477[22] && + !sfdBC__h19477[21] && + !sfdBC__h19477[20] && + !sfdBC__h19477[19] && + !sfdBC__h19477[18] && + !sfdBC__h19477[17] && + !sfdBC__h19477[16] && + !sfdBC__h19477[15] && + !sfdBC__h19477[14] && + !sfdBC__h19477[13] && + !sfdBC__h19477[12] && + !sfdBC__h19477[11] && + !sfdBC__h19477[10] && + !sfdBC__h19477[9] && + !sfdBC__h19477[8] && + !sfdBC__h19477[7] && + !sfdBC__h19477[6] && + !sfdBC__h19477[5] && + !sfdBC__h19477[4] && + !sfdBC__h19477[3] && + !sfdBC__h19477[2] && + !sfdBC__h19477[1] && + !sfdBC__h19477[0]) ? + sfdBC__h19477 : + _theResult___snd__h34815 ; + assign _theResult___snd__h34815 = + { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4[103:0], + 2'd0 } ; + assign _theResult___snd__h34833 = + sfdBC__h19477 << + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ; + assign _theResult___snd__h34838 = + sfdBC__h19477 << + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 ; + assign _theResult___snd__h45207 = { sfd__h36934[55:0], 1'd0 } ; + assign _theResult___snd__h45221 = + (!sfd__h36934[56] && sfd__h36934[55]) ? + _theResult___snd__h45223 : + _theResult___snd__h45235 ; + assign _theResult___snd__h45223 = { sfd__h36934[54:0], 2'd0 } ; + assign _theResult___snd__h45235 = + (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && + !sfd__h36934[53] && + !sfd__h36934[52] && + !sfd__h36934[51] && + !sfd__h36934[50] && + !sfd__h36934[49] && + !sfd__h36934[48] && + !sfd__h36934[47] && + !sfd__h36934[46] && + !sfd__h36934[45] && + !sfd__h36934[44] && + !sfd__h36934[43] && + !sfd__h36934[42] && + !sfd__h36934[41] && + !sfd__h36934[40] && + !sfd__h36934[39] && + !sfd__h36934[38] && + !sfd__h36934[37] && + !sfd__h36934[36] && + !sfd__h36934[35] && + !sfd__h36934[34] && + !sfd__h36934[33] && + !sfd__h36934[32] && + !sfd__h36934[31] && + !sfd__h36934[30] && + !sfd__h36934[29] && + !sfd__h36934[28] && + !sfd__h36934[27] && + !sfd__h36934[26] && + !sfd__h36934[25] && + !sfd__h36934[24] && + !sfd__h36934[23] && + !sfd__h36934[22] && + !sfd__h36934[21] && + !sfd__h36934[20] && + !sfd__h36934[19] && + !sfd__h36934[18] && + !sfd__h36934[17] && + !sfd__h36934[16] && + !sfd__h36934[15] && + !sfd__h36934[14] && + !sfd__h36934[13] && + !sfd__h36934[12] && + !sfd__h36934[11] && + !sfd__h36934[10] && + !sfd__h36934[9] && + !sfd__h36934[8] && + !sfd__h36934[7] && + !sfd__h36934[6] && + !sfd__h36934[5] && + !sfd__h36934[4] && + !sfd__h36934[3] && + !sfd__h36934[2] && + !sfd__h36934[1] && + !sfd__h36934[0]) ? + sfd__h36934 : + _theResult___snd__h45241 ; + assign _theResult___snd__h45241 = + { IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9[54:0], + 2'd0 } ; + assign _theResult___snd__h45259 = + sfd__h36934 << + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ; + assign _theResult___snd__h45264 = + sfd__h36934 << + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 ; + assign _theResult___snd_fst__h34866 = + { IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5[1], + { sfdin__h34758[52:0], 52'd0 } != 105'd0 } ; + assign _theResult___snd_fst__h45292 = + { IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10[1], + { sfdin__h45184[3:0], 52'd0 } != 56'd0 } ; + assign _theResult___snd_snd__h35186 = + (fpu_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; + assign _theResult___snd_snd_snd__h35184 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + _theResult___snd_snd__h35186 : + guardBC__h19481 ; + assign din_exp4681_MINUS_1023__q3 = din_exp__h34681 - 11'd1023 ; + assign din_exp__h34681 = + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? + value__h34698[10:0] : + 11'd0 ; + assign din_inc___2_exp__h46444 = fpu_fState_S8$D_OUT[65:55] + 11'd1 ; + assign fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 = + fpu_fOperand_S0$D_OUT[129:119] - 11'd1023 ; + assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 = + fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; + assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 = + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ; + assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 = + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || + x__h327 == 11'd0 && _theResult___fst_sfd__h396 == 52'd0 && + (fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) && + fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 ; + assign fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 = + (fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) == + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 ; + assign fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213 = + fpu_fProd_S3$D_OUT >> + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; + assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 = + (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; + assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 = + (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; + assign fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702 = + fpu_fState_S3$D_OUT[86:82] | + { 2'd0, + sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023, + _theResult___fst_exp__h34767 == 11'd0 && + guardBC__h19481 != 2'd0, + sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023 } ; + assign fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 = + fpu_fState_S4$D_OUT[128:118] - 11'd1023 ; + assign fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 = + fpu_fState_S4$D_OUT[64:54] - 11'd1023 ; + assign fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816 = + fpu_fState_S5$D_OUT[56:0] >> fpu_fState_S5$D_OUT[126:114] ; + assign fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143 = + fpu_fState_S7$D_OUT[137:133] | + { 2'd0, + sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023, + _theResult___fst_exp__h45193 == 11'd0 && guard__h36938 != 2'd0, + sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023 } ; + assign fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 = + fpu_fState_S8$D_OUT[75:71] | + { 2'd0, + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == + 11'd2047 && + ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[54:3] : + _theResult___fst_sfd__h46438) == + 52'd0, + 1'd0, + fpu_fState_S8$D_OUT[65:55] != 11'd2047 && + fpu_fState_S8$D_OUT[2:1] != 2'b0 } ; + assign guardBC__h19481 = + (sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h34866 ; + assign guard__h36182 = fpu_fState_S5$D_OUT[56:0] << x__h36286 ; + assign guard__h36938 = + (sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h45292 ; + assign out_exp__h46362 = + fpu_fState_S8$D_OUT[3] ? + _theResult___exp__h46359 : + fpu_fState_S8$D_OUT[65:55] ; + assign out_sfd__h46363 = + fpu_fState_S8$D_OUT[3] ? + _theResult___sfd__h46360 : + fpu_fState_S8$D_OUT[54:3] ; + assign result__h36187 = + { fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[56:1], + fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[0] | + guard__h36182 != 57'd0 } ; + assign sfdA__h35392 = + { 1'b0, + fpu_fState_S4$D_OUT[128:118] != 11'd0, + fpu_fState_S4$D_OUT[117:66], + 3'b0 } ; + assign sfdBC__h19477 = + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? + fpu_fProd_S3$D_OUT : + _theResult___fst__h20642 ; + assign sfdBC__h35393 = + { 1'b0, + fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:0], + 1'b0 } ; + assign sfd__h3208 = { 1'd1, _theResult___fst_sfd__h396[50:0] } ; + assign sfd__h3211 = { 1'd1, fpu_fOperand_S0$D_OUT[117:67] } ; + assign sfd__h3214 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; + assign sfd__h36934 = + fpu_fState_S7$D_OUT[128] ? + fpu_fState_S7$D_OUT[56:0] : + fpu_fState_S7$D_OUT[113:57] ; + assign sfd__h45855 = + { 1'b0, + fpu_fState_S8$D_OUT[65:55] != 11'd0, + fpu_fState_S8$D_OUT[54:3] } + + 54'd1 ; + assign sfdin__h34758 = + sfdBC__h19477[105] ? + _theResult___snd__h34781 : + _theResult___snd__h34795 ; + assign sfdin__h45184 = + sfd__h36934[56] ? + _theResult___snd__h45207 : + _theResult___snd__h45221 ; + assign sfdlsb__h20640 = x__h20711 != 106'd0 ; + assign value5122_BITS_10_TO_0_MINUS_1023__q8 = + value__h45122[10:0] - 11'd1023 ; + assign value__h34698 = fpu_fState_S3$D_OUT[12:0] + 13'd1023 ; + assign value__h45122 = fpu_fState_S7$D_OUT[126:114] + 13'd1023 ; + assign x__h18058 = + { fpu_fOperand_S0$D_OUT[129:119] != 11'd0, + fpu_fOperand_S0$D_OUT[118:67] } ; + assign x__h18070 = + { fpu_fOperand_S0$D_OUT[65:55] != 11'd0, + fpu_fOperand_S0$D_OUT[54:3] } ; + assign x__h20711 = fpu_fProd_S3$D_OUT << x__h20744 ; + assign x__h20744 = + 13'd106 - + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; + assign x__h327 = + fpu_fOperand_S0$D_OUT[195] ? + fpu_fOperand_S0$D_OUT[193:183] : + 11'd0 ; + assign x__h35221 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? + _theResult___snd_snd_snd__h35184 : + 2'd3 ; + assign x__h35755 = + { 1'b0, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + { fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:0], + 1'b0 } : + { fpu_fState_S4$D_OUT[128:118] != 11'd0, + fpu_fState_S4$D_OUT[117:66], + 3'b0 } } ; + assign x__h35759 = + { 1'b0, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + { fpu_fState_S4$D_OUT[128:118] != 11'd0, + fpu_fState_S4$D_OUT[117:66], + 3'b0 } : + { fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:0], + 1'b0 } } ; + assign x__h36174 = + fpu_fState_S5$D_OUT[215] ? + fpu_fState_S5$D_OUT[56:0] : + (((fpu_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? + result__h36187 : + ((fpu_fState_S5$D_OUT[56:0] == 57'd0) ? + fpu_fState_S5$D_OUT[56:0] : + 57'd1)) ; + assign x__h36286 = 13'd57 - fpu_fState_S5$D_OUT[126:114] ; + assign x__h36686 = fpu_fState_S6$D_OUT[113:57] + fpu_fState_S6$D_OUT[56:0] ; + assign x__h36695 = fpu_fState_S6$D_OUT[113:57] - fpu_fState_S6$D_OUT[56:0] ; + assign x__h45575 = fpu_fState_S7$D_OUT[202] ? 2'd0 : guard__h36938 ; + always@(fpu_fState_S8$D_OUT or out_sfd__h46363 or _theResult___sfd__h46360) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = + fpu_fState_S8$D_OUT[54:3]; + 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = + out_sfd__h46363; + 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = + _theResult___sfd__h46360; + endcase + end + always@(fpu_fState_S8$D_OUT or _theResult___sfd__h46360) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = + fpu_fState_S8$D_OUT[54:3]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = + _theResult___sfd__h46360; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 or + _theResult___sfd__h46360) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + _theResult___fst_sfd__h46438 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1; + 3'd1: + _theResult___fst_sfd__h46438 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2; + 3'd2: + _theResult___fst_sfd__h46438 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? + fpu_fState_S8$D_OUT[54:3] : + _theResult___sfd__h46360; + 3'd3: + _theResult___fst_sfd__h46438 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[54:3] : + (fpu_fState_S8$D_OUT[66] ? + _theResult___sfd__h46360 : + fpu_fState_S8$D_OUT[54:3]); + 3'd4: _theResult___fst_sfd__h46438 = fpu_fState_S8$D_OUT[54:3]; + default: _theResult___fst_sfd__h46438 = 52'd0; + endcase + end + always@(fpu_fState_S8$D_OUT or out_exp__h46362 or _theResult___exp__h46359) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = + fpu_fState_S8$D_OUT[65:55]; + 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = + out_exp__h46362; + 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = + _theResult___exp__h46359; + endcase + end + always@(fpu_fState_S8$D_OUT or _theResult___exp__h46359) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = + fpu_fState_S8$D_OUT[65:55]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = + _theResult___exp__h46359; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 or + _theResult___exp__h46359) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + _theResult___fst_exp__h46437 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11; + 3'd1: + _theResult___fst_exp__h46437 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12; + 3'd2: + _theResult___fst_exp__h46437 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? + fpu_fState_S8$D_OUT[65:55] : + _theResult___exp__h46359; + 3'd3: + _theResult___fst_exp__h46437 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[65:55] : + (fpu_fState_S8$D_OUT[66] ? + _theResult___exp__h46359 : + fpu_fState_S8$D_OUT[65:55]); + 3'd4: _theResult___fst_exp__h46437 = fpu_fState_S8$D_OUT[65:55]; + default: _theResult___fst_exp__h46437 = 11'd0; + endcase + end + always@(fpu_fState_S8$D_OUT) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01, 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = + fpu_fState_S8$D_OUT[66]; + 2'd3: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = + fpu_fState_S8$D_OUT[2:1] == 2'b11 && fpu_fState_S8$D_OUT[66]; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13; + 3'd1: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[66] : + (fpu_fState_S8$D_OUT[2:1] == 2'b01 || + fpu_fState_S8$D_OUT[2:1] == 2'b10 || + fpu_fState_S8$D_OUT[2:1] == 2'b11) && + fpu_fState_S8$D_OUT[66]; + 3'd2, 3'd3: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + fpu_fState_S8$D_OUT[66]; + default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + fpu_fState_S8$D_OUT[70:68] == 3'd4 && + fpu_fState_S8$D_OUT[66]; + endcase + end + always@(fpu_fState_S8$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = + fpu_fState_S8$D_OUT[65:3]; + 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = + fpu_fState_S8$D_OUT[3] ? + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : + fpu_fState_S8$D_OUT[65:3]; + 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; + endcase + end + always@(fpu_fState_S8$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = + fpu_fState_S8$D_OUT[65:3]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 or + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17; + 3'd1: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18; + 3'd2: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? + fpu_fState_S8$D_OUT[65:3] : + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; + 3'd3: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[65:3] : + (fpu_fState_S8$D_OUT[66] ? + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : + fpu_fState_S8$D_OUT[65:3]); + 3'd4: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + fpu_fState_S8$D_OUT[65:3]; + default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = 63'd0; + endcase + end endmodule // mkDoubleFMA diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v index 22b5f44..9ba65dd 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -7,15 +7,16 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 -// RDY_response_get O 1 +// response_get O 69 reg +// RDY_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// request_put I 67 +// request_put I 67 reg // EN_request_put I 1 // EN_response_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// EN_response_get -> RDY_request_put // // @@ -59,44 +60,5579 @@ module mkDoubleSqrt(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu - wire [68 : 0] fpu$response_get; - wire [66 : 0] fpu$request_put; - wire fpu$EN_request_put, - fpu$EN_response_get, - fpu$RDY_request_put, - fpu$RDY_response_get; + // ports of submodule fpu_fOperand_S0 + wire [66 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; + wire fpu_fOperand_S0$CLR, + fpu_fOperand_S0$DEQ, + fpu_fOperand_S0$EMPTY_N, + fpu_fOperand_S0$ENQ, + fpu_fOperand_S0$FULL_N; + + // ports of submodule fpu_fResult_S5 + wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; + wire fpu_fResult_S5$CLR, + fpu_fResult_S5$DEQ, + fpu_fResult_S5$EMPTY_N, + fpu_fResult_S5$ENQ, + fpu_fResult_S5$FULL_N; + + // ports of submodule fpu_fState_S1 + wire [194 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; + wire fpu_fState_S1$CLR, + fpu_fState_S1$DEQ, + fpu_fState_S1$EMPTY_N, + fpu_fState_S1$ENQ, + fpu_fState_S1$FULL_N; + + // ports of submodule fpu_fState_S2 + wire [136 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; + wire fpu_fState_S2$CLR, + fpu_fState_S2$DEQ, + fpu_fState_S2$EMPTY_N, + fpu_fState_S2$ENQ, + fpu_fState_S2$FULL_N; + + // ports of submodule fpu_fState_S3 + wire [195 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; + wire fpu_fState_S3$CLR, + fpu_fState_S3$DEQ, + fpu_fState_S3$EMPTY_N, + fpu_fState_S3$ENQ, + fpu_fState_S3$FULL_N; + + // ports of submodule fpu_fState_S4 + wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; + wire fpu_fState_S4$CLR, + fpu_fState_S4$DEQ, + fpu_fState_S4$EMPTY_N, + fpu_fState_S4$ENQ, + fpu_fState_S4$FULL_N; + + // ports of submodule int_sqrt_fFirst + wire [464 : 0] int_sqrt_fFirst$D_IN, int_sqrt_fFirst$D_OUT; + wire int_sqrt_fFirst$CLR, + int_sqrt_fFirst$DEQ, + int_sqrt_fFirst$EMPTY_N, + int_sqrt_fFirst$ENQ, + int_sqrt_fFirst$FULL_N; + + // ports of submodule int_sqrt_fNext_0 + wire [464 : 0] int_sqrt_fNext_0$D_IN, int_sqrt_fNext_0$D_OUT; + wire int_sqrt_fNext_0$CLR, + int_sqrt_fNext_0$DEQ, + int_sqrt_fNext_0$EMPTY_N, + int_sqrt_fNext_0$ENQ, + int_sqrt_fNext_0$FULL_N; + + // ports of submodule int_sqrt_fNext_1 + wire [464 : 0] int_sqrt_fNext_1$D_IN, int_sqrt_fNext_1$D_OUT; + wire int_sqrt_fNext_1$CLR, + int_sqrt_fNext_1$DEQ, + int_sqrt_fNext_1$EMPTY_N, + int_sqrt_fNext_1$ENQ, + int_sqrt_fNext_1$FULL_N; + + // ports of submodule int_sqrt_fNext_10 + wire [464 : 0] int_sqrt_fNext_10$D_IN, int_sqrt_fNext_10$D_OUT; + wire int_sqrt_fNext_10$CLR, + int_sqrt_fNext_10$DEQ, + int_sqrt_fNext_10$EMPTY_N, + int_sqrt_fNext_10$ENQ, + int_sqrt_fNext_10$FULL_N; + + // ports of submodule int_sqrt_fNext_11 + wire [464 : 0] int_sqrt_fNext_11$D_IN, int_sqrt_fNext_11$D_OUT; + wire int_sqrt_fNext_11$CLR, + int_sqrt_fNext_11$DEQ, + int_sqrt_fNext_11$EMPTY_N, + int_sqrt_fNext_11$ENQ, + int_sqrt_fNext_11$FULL_N; + + // ports of submodule int_sqrt_fNext_12 + wire [464 : 0] int_sqrt_fNext_12$D_IN, int_sqrt_fNext_12$D_OUT; + wire int_sqrt_fNext_12$CLR, + int_sqrt_fNext_12$DEQ, + int_sqrt_fNext_12$EMPTY_N, + int_sqrt_fNext_12$ENQ, + int_sqrt_fNext_12$FULL_N; + + // ports of submodule int_sqrt_fNext_13 + wire [464 : 0] int_sqrt_fNext_13$D_IN, int_sqrt_fNext_13$D_OUT; + wire int_sqrt_fNext_13$CLR, + int_sqrt_fNext_13$DEQ, + int_sqrt_fNext_13$EMPTY_N, + int_sqrt_fNext_13$ENQ, + int_sqrt_fNext_13$FULL_N; + + // ports of submodule int_sqrt_fNext_14 + wire [464 : 0] int_sqrt_fNext_14$D_IN, int_sqrt_fNext_14$D_OUT; + wire int_sqrt_fNext_14$CLR, + int_sqrt_fNext_14$DEQ, + int_sqrt_fNext_14$EMPTY_N, + int_sqrt_fNext_14$ENQ, + int_sqrt_fNext_14$FULL_N; + + // ports of submodule int_sqrt_fNext_15 + wire [464 : 0] int_sqrt_fNext_15$D_IN, int_sqrt_fNext_15$D_OUT; + wire int_sqrt_fNext_15$CLR, + int_sqrt_fNext_15$DEQ, + int_sqrt_fNext_15$EMPTY_N, + int_sqrt_fNext_15$ENQ, + int_sqrt_fNext_15$FULL_N; + + // ports of submodule int_sqrt_fNext_16 + wire [464 : 0] int_sqrt_fNext_16$D_IN, int_sqrt_fNext_16$D_OUT; + wire int_sqrt_fNext_16$CLR, + int_sqrt_fNext_16$DEQ, + int_sqrt_fNext_16$EMPTY_N, + int_sqrt_fNext_16$ENQ, + int_sqrt_fNext_16$FULL_N; + + // ports of submodule int_sqrt_fNext_17 + wire [464 : 0] int_sqrt_fNext_17$D_IN, int_sqrt_fNext_17$D_OUT; + wire int_sqrt_fNext_17$CLR, + int_sqrt_fNext_17$DEQ, + int_sqrt_fNext_17$EMPTY_N, + int_sqrt_fNext_17$ENQ, + int_sqrt_fNext_17$FULL_N; + + // ports of submodule int_sqrt_fNext_18 + wire [464 : 0] int_sqrt_fNext_18$D_IN, int_sqrt_fNext_18$D_OUT; + wire int_sqrt_fNext_18$CLR, + int_sqrt_fNext_18$DEQ, + int_sqrt_fNext_18$EMPTY_N, + int_sqrt_fNext_18$ENQ, + int_sqrt_fNext_18$FULL_N; + + // ports of submodule int_sqrt_fNext_19 + wire [464 : 0] int_sqrt_fNext_19$D_IN, int_sqrt_fNext_19$D_OUT; + wire int_sqrt_fNext_19$CLR, + int_sqrt_fNext_19$DEQ, + int_sqrt_fNext_19$EMPTY_N, + int_sqrt_fNext_19$ENQ, + int_sqrt_fNext_19$FULL_N; + + // ports of submodule int_sqrt_fNext_2 + wire [464 : 0] int_sqrt_fNext_2$D_IN, int_sqrt_fNext_2$D_OUT; + wire int_sqrt_fNext_2$CLR, + int_sqrt_fNext_2$DEQ, + int_sqrt_fNext_2$EMPTY_N, + int_sqrt_fNext_2$ENQ, + int_sqrt_fNext_2$FULL_N; + + // ports of submodule int_sqrt_fNext_20 + wire [464 : 0] int_sqrt_fNext_20$D_IN, int_sqrt_fNext_20$D_OUT; + wire int_sqrt_fNext_20$CLR, + int_sqrt_fNext_20$DEQ, + int_sqrt_fNext_20$EMPTY_N, + int_sqrt_fNext_20$ENQ, + int_sqrt_fNext_20$FULL_N; + + // ports of submodule int_sqrt_fNext_21 + wire [464 : 0] int_sqrt_fNext_21$D_IN, int_sqrt_fNext_21$D_OUT; + wire int_sqrt_fNext_21$CLR, + int_sqrt_fNext_21$DEQ, + int_sqrt_fNext_21$EMPTY_N, + int_sqrt_fNext_21$ENQ, + int_sqrt_fNext_21$FULL_N; + + // ports of submodule int_sqrt_fNext_22 + wire [464 : 0] int_sqrt_fNext_22$D_IN, int_sqrt_fNext_22$D_OUT; + wire int_sqrt_fNext_22$CLR, + int_sqrt_fNext_22$DEQ, + int_sqrt_fNext_22$EMPTY_N, + int_sqrt_fNext_22$ENQ, + int_sqrt_fNext_22$FULL_N; + + // ports of submodule int_sqrt_fNext_23 + wire [464 : 0] int_sqrt_fNext_23$D_IN, int_sqrt_fNext_23$D_OUT; + wire int_sqrt_fNext_23$CLR, + int_sqrt_fNext_23$DEQ, + int_sqrt_fNext_23$EMPTY_N, + int_sqrt_fNext_23$ENQ, + int_sqrt_fNext_23$FULL_N; + + // ports of submodule int_sqrt_fNext_24 + wire [464 : 0] int_sqrt_fNext_24$D_IN, int_sqrt_fNext_24$D_OUT; + wire int_sqrt_fNext_24$CLR, + int_sqrt_fNext_24$DEQ, + int_sqrt_fNext_24$EMPTY_N, + int_sqrt_fNext_24$ENQ, + int_sqrt_fNext_24$FULL_N; + + // ports of submodule int_sqrt_fNext_25 + wire [464 : 0] int_sqrt_fNext_25$D_IN, int_sqrt_fNext_25$D_OUT; + wire int_sqrt_fNext_25$CLR, + int_sqrt_fNext_25$DEQ, + int_sqrt_fNext_25$EMPTY_N, + int_sqrt_fNext_25$ENQ, + int_sqrt_fNext_25$FULL_N; + + // ports of submodule int_sqrt_fNext_26 + wire [464 : 0] int_sqrt_fNext_26$D_IN, int_sqrt_fNext_26$D_OUT; + wire int_sqrt_fNext_26$CLR, + int_sqrt_fNext_26$DEQ, + int_sqrt_fNext_26$EMPTY_N, + int_sqrt_fNext_26$ENQ, + int_sqrt_fNext_26$FULL_N; + + // ports of submodule int_sqrt_fNext_27 + wire [464 : 0] int_sqrt_fNext_27$D_IN, int_sqrt_fNext_27$D_OUT; + wire int_sqrt_fNext_27$CLR, + int_sqrt_fNext_27$DEQ, + int_sqrt_fNext_27$EMPTY_N, + int_sqrt_fNext_27$ENQ, + int_sqrt_fNext_27$FULL_N; + + // ports of submodule int_sqrt_fNext_28 + wire [464 : 0] int_sqrt_fNext_28$D_IN, int_sqrt_fNext_28$D_OUT; + wire int_sqrt_fNext_28$CLR, + int_sqrt_fNext_28$DEQ, + int_sqrt_fNext_28$EMPTY_N, + int_sqrt_fNext_28$ENQ, + int_sqrt_fNext_28$FULL_N; + + // ports of submodule int_sqrt_fNext_29 + wire [464 : 0] int_sqrt_fNext_29$D_IN, int_sqrt_fNext_29$D_OUT; + wire int_sqrt_fNext_29$CLR, + int_sqrt_fNext_29$DEQ, + int_sqrt_fNext_29$EMPTY_N, + int_sqrt_fNext_29$ENQ, + int_sqrt_fNext_29$FULL_N; + + // ports of submodule int_sqrt_fNext_3 + wire [464 : 0] int_sqrt_fNext_3$D_IN, int_sqrt_fNext_3$D_OUT; + wire int_sqrt_fNext_3$CLR, + int_sqrt_fNext_3$DEQ, + int_sqrt_fNext_3$EMPTY_N, + int_sqrt_fNext_3$ENQ, + int_sqrt_fNext_3$FULL_N; + + // ports of submodule int_sqrt_fNext_30 + wire [464 : 0] int_sqrt_fNext_30$D_IN, int_sqrt_fNext_30$D_OUT; + wire int_sqrt_fNext_30$CLR, + int_sqrt_fNext_30$DEQ, + int_sqrt_fNext_30$EMPTY_N, + int_sqrt_fNext_30$ENQ, + int_sqrt_fNext_30$FULL_N; + + // ports of submodule int_sqrt_fNext_31 + wire [464 : 0] int_sqrt_fNext_31$D_IN, int_sqrt_fNext_31$D_OUT; + wire int_sqrt_fNext_31$CLR, + int_sqrt_fNext_31$DEQ, + int_sqrt_fNext_31$EMPTY_N, + int_sqrt_fNext_31$ENQ, + int_sqrt_fNext_31$FULL_N; + + // ports of submodule int_sqrt_fNext_32 + wire [464 : 0] int_sqrt_fNext_32$D_IN, int_sqrt_fNext_32$D_OUT; + wire int_sqrt_fNext_32$CLR, + int_sqrt_fNext_32$DEQ, + int_sqrt_fNext_32$EMPTY_N, + int_sqrt_fNext_32$ENQ, + int_sqrt_fNext_32$FULL_N; + + // ports of submodule int_sqrt_fNext_33 + wire [464 : 0] int_sqrt_fNext_33$D_IN, int_sqrt_fNext_33$D_OUT; + wire int_sqrt_fNext_33$CLR, + int_sqrt_fNext_33$DEQ, + int_sqrt_fNext_33$EMPTY_N, + int_sqrt_fNext_33$ENQ, + int_sqrt_fNext_33$FULL_N; + + // ports of submodule int_sqrt_fNext_34 + wire [464 : 0] int_sqrt_fNext_34$D_IN, int_sqrt_fNext_34$D_OUT; + wire int_sqrt_fNext_34$CLR, + int_sqrt_fNext_34$DEQ, + int_sqrt_fNext_34$EMPTY_N, + int_sqrt_fNext_34$ENQ, + int_sqrt_fNext_34$FULL_N; + + // ports of submodule int_sqrt_fNext_35 + wire [464 : 0] int_sqrt_fNext_35$D_IN, int_sqrt_fNext_35$D_OUT; + wire int_sqrt_fNext_35$CLR, + int_sqrt_fNext_35$DEQ, + int_sqrt_fNext_35$EMPTY_N, + int_sqrt_fNext_35$ENQ, + int_sqrt_fNext_35$FULL_N; + + // ports of submodule int_sqrt_fNext_36 + wire [464 : 0] int_sqrt_fNext_36$D_IN, int_sqrt_fNext_36$D_OUT; + wire int_sqrt_fNext_36$CLR, + int_sqrt_fNext_36$DEQ, + int_sqrt_fNext_36$EMPTY_N, + int_sqrt_fNext_36$ENQ, + int_sqrt_fNext_36$FULL_N; + + // ports of submodule int_sqrt_fNext_37 + wire [464 : 0] int_sqrt_fNext_37$D_IN, int_sqrt_fNext_37$D_OUT; + wire int_sqrt_fNext_37$CLR, + int_sqrt_fNext_37$DEQ, + int_sqrt_fNext_37$EMPTY_N, + int_sqrt_fNext_37$ENQ, + int_sqrt_fNext_37$FULL_N; + + // ports of submodule int_sqrt_fNext_38 + wire [464 : 0] int_sqrt_fNext_38$D_IN, int_sqrt_fNext_38$D_OUT; + wire int_sqrt_fNext_38$CLR, + int_sqrt_fNext_38$DEQ, + int_sqrt_fNext_38$EMPTY_N, + int_sqrt_fNext_38$ENQ, + int_sqrt_fNext_38$FULL_N; + + // ports of submodule int_sqrt_fNext_39 + wire [464 : 0] int_sqrt_fNext_39$D_IN, int_sqrt_fNext_39$D_OUT; + wire int_sqrt_fNext_39$CLR, + int_sqrt_fNext_39$DEQ, + int_sqrt_fNext_39$EMPTY_N, + int_sqrt_fNext_39$ENQ, + int_sqrt_fNext_39$FULL_N; + + // ports of submodule int_sqrt_fNext_4 + wire [464 : 0] int_sqrt_fNext_4$D_IN, int_sqrt_fNext_4$D_OUT; + wire int_sqrt_fNext_4$CLR, + int_sqrt_fNext_4$DEQ, + int_sqrt_fNext_4$EMPTY_N, + int_sqrt_fNext_4$ENQ, + int_sqrt_fNext_4$FULL_N; + + // ports of submodule int_sqrt_fNext_40 + wire [464 : 0] int_sqrt_fNext_40$D_IN, int_sqrt_fNext_40$D_OUT; + wire int_sqrt_fNext_40$CLR, + int_sqrt_fNext_40$DEQ, + int_sqrt_fNext_40$EMPTY_N, + int_sqrt_fNext_40$ENQ, + int_sqrt_fNext_40$FULL_N; + + // ports of submodule int_sqrt_fNext_41 + wire [464 : 0] int_sqrt_fNext_41$D_IN, int_sqrt_fNext_41$D_OUT; + wire int_sqrt_fNext_41$CLR, + int_sqrt_fNext_41$DEQ, + int_sqrt_fNext_41$EMPTY_N, + int_sqrt_fNext_41$ENQ, + int_sqrt_fNext_41$FULL_N; + + // ports of submodule int_sqrt_fNext_42 + wire [464 : 0] int_sqrt_fNext_42$D_IN, int_sqrt_fNext_42$D_OUT; + wire int_sqrt_fNext_42$CLR, + int_sqrt_fNext_42$DEQ, + int_sqrt_fNext_42$EMPTY_N, + int_sqrt_fNext_42$ENQ, + int_sqrt_fNext_42$FULL_N; + + // ports of submodule int_sqrt_fNext_43 + wire [464 : 0] int_sqrt_fNext_43$D_IN, int_sqrt_fNext_43$D_OUT; + wire int_sqrt_fNext_43$CLR, + int_sqrt_fNext_43$DEQ, + int_sqrt_fNext_43$EMPTY_N, + int_sqrt_fNext_43$ENQ, + int_sqrt_fNext_43$FULL_N; + + // ports of submodule int_sqrt_fNext_44 + wire [464 : 0] int_sqrt_fNext_44$D_IN, int_sqrt_fNext_44$D_OUT; + wire int_sqrt_fNext_44$CLR, + int_sqrt_fNext_44$DEQ, + int_sqrt_fNext_44$EMPTY_N, + int_sqrt_fNext_44$ENQ, + int_sqrt_fNext_44$FULL_N; + + // ports of submodule int_sqrt_fNext_45 + wire [464 : 0] int_sqrt_fNext_45$D_IN, int_sqrt_fNext_45$D_OUT; + wire int_sqrt_fNext_45$CLR, + int_sqrt_fNext_45$DEQ, + int_sqrt_fNext_45$EMPTY_N, + int_sqrt_fNext_45$ENQ, + int_sqrt_fNext_45$FULL_N; + + // ports of submodule int_sqrt_fNext_46 + wire [464 : 0] int_sqrt_fNext_46$D_IN, int_sqrt_fNext_46$D_OUT; + wire int_sqrt_fNext_46$CLR, + int_sqrt_fNext_46$DEQ, + int_sqrt_fNext_46$EMPTY_N, + int_sqrt_fNext_46$ENQ, + int_sqrt_fNext_46$FULL_N; + + // ports of submodule int_sqrt_fNext_47 + wire [464 : 0] int_sqrt_fNext_47$D_IN, int_sqrt_fNext_47$D_OUT; + wire int_sqrt_fNext_47$CLR, + int_sqrt_fNext_47$DEQ, + int_sqrt_fNext_47$EMPTY_N, + int_sqrt_fNext_47$ENQ, + int_sqrt_fNext_47$FULL_N; + + // ports of submodule int_sqrt_fNext_48 + wire [464 : 0] int_sqrt_fNext_48$D_IN, int_sqrt_fNext_48$D_OUT; + wire int_sqrt_fNext_48$CLR, + int_sqrt_fNext_48$DEQ, + int_sqrt_fNext_48$EMPTY_N, + int_sqrt_fNext_48$ENQ, + int_sqrt_fNext_48$FULL_N; + + // ports of submodule int_sqrt_fNext_49 + wire [464 : 0] int_sqrt_fNext_49$D_IN, int_sqrt_fNext_49$D_OUT; + wire int_sqrt_fNext_49$CLR, + int_sqrt_fNext_49$DEQ, + int_sqrt_fNext_49$EMPTY_N, + int_sqrt_fNext_49$ENQ, + int_sqrt_fNext_49$FULL_N; + + // ports of submodule int_sqrt_fNext_5 + wire [464 : 0] int_sqrt_fNext_5$D_IN, int_sqrt_fNext_5$D_OUT; + wire int_sqrt_fNext_5$CLR, + int_sqrt_fNext_5$DEQ, + int_sqrt_fNext_5$EMPTY_N, + int_sqrt_fNext_5$ENQ, + int_sqrt_fNext_5$FULL_N; + + // ports of submodule int_sqrt_fNext_50 + wire [464 : 0] int_sqrt_fNext_50$D_IN, int_sqrt_fNext_50$D_OUT; + wire int_sqrt_fNext_50$CLR, + int_sqrt_fNext_50$DEQ, + int_sqrt_fNext_50$EMPTY_N, + int_sqrt_fNext_50$ENQ, + int_sqrt_fNext_50$FULL_N; + + // ports of submodule int_sqrt_fNext_51 + wire [464 : 0] int_sqrt_fNext_51$D_IN, int_sqrt_fNext_51$D_OUT; + wire int_sqrt_fNext_51$CLR, + int_sqrt_fNext_51$DEQ, + int_sqrt_fNext_51$EMPTY_N, + int_sqrt_fNext_51$ENQ, + int_sqrt_fNext_51$FULL_N; + + // ports of submodule int_sqrt_fNext_52 + wire [464 : 0] int_sqrt_fNext_52$D_IN, int_sqrt_fNext_52$D_OUT; + wire int_sqrt_fNext_52$CLR, + int_sqrt_fNext_52$DEQ, + int_sqrt_fNext_52$EMPTY_N, + int_sqrt_fNext_52$ENQ, + int_sqrt_fNext_52$FULL_N; + + // ports of submodule int_sqrt_fNext_53 + wire [464 : 0] int_sqrt_fNext_53$D_IN, int_sqrt_fNext_53$D_OUT; + wire int_sqrt_fNext_53$CLR, + int_sqrt_fNext_53$DEQ, + int_sqrt_fNext_53$EMPTY_N, + int_sqrt_fNext_53$ENQ, + int_sqrt_fNext_53$FULL_N; + + // ports of submodule int_sqrt_fNext_54 + wire [464 : 0] int_sqrt_fNext_54$D_IN, int_sqrt_fNext_54$D_OUT; + wire int_sqrt_fNext_54$CLR, + int_sqrt_fNext_54$DEQ, + int_sqrt_fNext_54$EMPTY_N, + int_sqrt_fNext_54$ENQ, + int_sqrt_fNext_54$FULL_N; + + // ports of submodule int_sqrt_fNext_55 + wire [464 : 0] int_sqrt_fNext_55$D_IN, int_sqrt_fNext_55$D_OUT; + wire int_sqrt_fNext_55$CLR, + int_sqrt_fNext_55$DEQ, + int_sqrt_fNext_55$EMPTY_N, + int_sqrt_fNext_55$ENQ, + int_sqrt_fNext_55$FULL_N; + + // ports of submodule int_sqrt_fNext_56 + wire [464 : 0] int_sqrt_fNext_56$D_IN, int_sqrt_fNext_56$D_OUT; + wire int_sqrt_fNext_56$CLR, + int_sqrt_fNext_56$DEQ, + int_sqrt_fNext_56$EMPTY_N, + int_sqrt_fNext_56$ENQ, + int_sqrt_fNext_56$FULL_N; + + // ports of submodule int_sqrt_fNext_57 + wire [464 : 0] int_sqrt_fNext_57$D_IN, int_sqrt_fNext_57$D_OUT; + wire int_sqrt_fNext_57$CLR, + int_sqrt_fNext_57$DEQ, + int_sqrt_fNext_57$EMPTY_N, + int_sqrt_fNext_57$ENQ, + int_sqrt_fNext_57$FULL_N; + + // ports of submodule int_sqrt_fNext_58 + wire [464 : 0] int_sqrt_fNext_58$D_IN, int_sqrt_fNext_58$D_OUT; + wire int_sqrt_fNext_58$CLR, + int_sqrt_fNext_58$DEQ, + int_sqrt_fNext_58$EMPTY_N, + int_sqrt_fNext_58$ENQ, + int_sqrt_fNext_58$FULL_N; + + // ports of submodule int_sqrt_fNext_6 + wire [464 : 0] int_sqrt_fNext_6$D_IN, int_sqrt_fNext_6$D_OUT; + wire int_sqrt_fNext_6$CLR, + int_sqrt_fNext_6$DEQ, + int_sqrt_fNext_6$EMPTY_N, + int_sqrt_fNext_6$ENQ, + int_sqrt_fNext_6$FULL_N; + + // ports of submodule int_sqrt_fNext_7 + wire [464 : 0] int_sqrt_fNext_7$D_IN, int_sqrt_fNext_7$D_OUT; + wire int_sqrt_fNext_7$CLR, + int_sqrt_fNext_7$DEQ, + int_sqrt_fNext_7$EMPTY_N, + int_sqrt_fNext_7$ENQ, + int_sqrt_fNext_7$FULL_N; + + // ports of submodule int_sqrt_fNext_8 + wire [464 : 0] int_sqrt_fNext_8$D_IN, int_sqrt_fNext_8$D_OUT; + wire int_sqrt_fNext_8$CLR, + int_sqrt_fNext_8$DEQ, + int_sqrt_fNext_8$EMPTY_N, + int_sqrt_fNext_8$ENQ, + int_sqrt_fNext_8$FULL_N; + + // ports of submodule int_sqrt_fNext_9 + wire [464 : 0] int_sqrt_fNext_9$D_IN, int_sqrt_fNext_9$D_OUT; + wire int_sqrt_fNext_9$CLR, + int_sqrt_fNext_9$DEQ, + int_sqrt_fNext_9$EMPTY_N, + int_sqrt_fNext_9$ENQ, + int_sqrt_fNext_9$FULL_N; + + // ports of submodule int_sqrt_fRequest + wire [115 : 0] int_sqrt_fRequest$D_IN, int_sqrt_fRequest$D_OUT; + wire int_sqrt_fRequest$CLR, + int_sqrt_fRequest$DEQ, + int_sqrt_fRequest$EMPTY_N, + int_sqrt_fRequest$ENQ, + int_sqrt_fRequest$FULL_N; + + // ports of submodule int_sqrt_fResponse + wire [116 : 0] int_sqrt_fResponse$D_IN, int_sqrt_fResponse$D_OUT; + wire int_sqrt_fResponse$CLR, + int_sqrt_fResponse$DEQ, + int_sqrt_fResponse$EMPTY_N, + int_sqrt_fResponse$ENQ, + int_sqrt_fResponse$FULL_N; // rule scheduling signals - wire CAN_FIRE_request_put, + wire CAN_FIRE_RL_fpu_s1_stage, + CAN_FIRE_RL_fpu_s2_stage, + CAN_FIRE_RL_fpu_s3_stage, + CAN_FIRE_RL_fpu_s4_stage, + CAN_FIRE_RL_fpu_s5_stage, + CAN_FIRE_RL_int_sqrt_finish, + CAN_FIRE_RL_int_sqrt_start, + CAN_FIRE_RL_int_sqrt_work, + CAN_FIRE_RL_int_sqrt_work_1, + CAN_FIRE_RL_int_sqrt_work_10, + CAN_FIRE_RL_int_sqrt_work_11, + CAN_FIRE_RL_int_sqrt_work_12, + CAN_FIRE_RL_int_sqrt_work_13, + CAN_FIRE_RL_int_sqrt_work_14, + CAN_FIRE_RL_int_sqrt_work_15, + CAN_FIRE_RL_int_sqrt_work_16, + CAN_FIRE_RL_int_sqrt_work_17, + CAN_FIRE_RL_int_sqrt_work_18, + CAN_FIRE_RL_int_sqrt_work_19, + CAN_FIRE_RL_int_sqrt_work_2, + CAN_FIRE_RL_int_sqrt_work_20, + CAN_FIRE_RL_int_sqrt_work_21, + CAN_FIRE_RL_int_sqrt_work_22, + CAN_FIRE_RL_int_sqrt_work_23, + CAN_FIRE_RL_int_sqrt_work_24, + CAN_FIRE_RL_int_sqrt_work_25, + CAN_FIRE_RL_int_sqrt_work_26, + CAN_FIRE_RL_int_sqrt_work_27, + CAN_FIRE_RL_int_sqrt_work_28, + CAN_FIRE_RL_int_sqrt_work_29, + CAN_FIRE_RL_int_sqrt_work_3, + CAN_FIRE_RL_int_sqrt_work_30, + CAN_FIRE_RL_int_sqrt_work_31, + CAN_FIRE_RL_int_sqrt_work_32, + CAN_FIRE_RL_int_sqrt_work_33, + CAN_FIRE_RL_int_sqrt_work_34, + CAN_FIRE_RL_int_sqrt_work_35, + CAN_FIRE_RL_int_sqrt_work_36, + CAN_FIRE_RL_int_sqrt_work_37, + CAN_FIRE_RL_int_sqrt_work_38, + CAN_FIRE_RL_int_sqrt_work_39, + CAN_FIRE_RL_int_sqrt_work_4, + CAN_FIRE_RL_int_sqrt_work_40, + CAN_FIRE_RL_int_sqrt_work_41, + CAN_FIRE_RL_int_sqrt_work_42, + CAN_FIRE_RL_int_sqrt_work_43, + CAN_FIRE_RL_int_sqrt_work_44, + CAN_FIRE_RL_int_sqrt_work_45, + CAN_FIRE_RL_int_sqrt_work_46, + CAN_FIRE_RL_int_sqrt_work_47, + CAN_FIRE_RL_int_sqrt_work_48, + CAN_FIRE_RL_int_sqrt_work_49, + CAN_FIRE_RL_int_sqrt_work_5, + CAN_FIRE_RL_int_sqrt_work_50, + CAN_FIRE_RL_int_sqrt_work_51, + CAN_FIRE_RL_int_sqrt_work_52, + CAN_FIRE_RL_int_sqrt_work_53, + CAN_FIRE_RL_int_sqrt_work_54, + CAN_FIRE_RL_int_sqrt_work_55, + CAN_FIRE_RL_int_sqrt_work_56, + CAN_FIRE_RL_int_sqrt_work_57, + CAN_FIRE_RL_int_sqrt_work_58, + CAN_FIRE_RL_int_sqrt_work_6, + CAN_FIRE_RL_int_sqrt_work_7, + CAN_FIRE_RL_int_sqrt_work_8, + CAN_FIRE_RL_int_sqrt_work_9, + CAN_FIRE_request_put, CAN_FIRE_response_get, + WILL_FIRE_RL_fpu_s1_stage, + WILL_FIRE_RL_fpu_s2_stage, + WILL_FIRE_RL_fpu_s3_stage, + WILL_FIRE_RL_fpu_s4_stage, + WILL_FIRE_RL_fpu_s5_stage, + WILL_FIRE_RL_int_sqrt_finish, + WILL_FIRE_RL_int_sqrt_start, + WILL_FIRE_RL_int_sqrt_work, + WILL_FIRE_RL_int_sqrt_work_1, + WILL_FIRE_RL_int_sqrt_work_10, + WILL_FIRE_RL_int_sqrt_work_11, + WILL_FIRE_RL_int_sqrt_work_12, + WILL_FIRE_RL_int_sqrt_work_13, + WILL_FIRE_RL_int_sqrt_work_14, + WILL_FIRE_RL_int_sqrt_work_15, + WILL_FIRE_RL_int_sqrt_work_16, + WILL_FIRE_RL_int_sqrt_work_17, + WILL_FIRE_RL_int_sqrt_work_18, + WILL_FIRE_RL_int_sqrt_work_19, + WILL_FIRE_RL_int_sqrt_work_2, + WILL_FIRE_RL_int_sqrt_work_20, + WILL_FIRE_RL_int_sqrt_work_21, + WILL_FIRE_RL_int_sqrt_work_22, + WILL_FIRE_RL_int_sqrt_work_23, + WILL_FIRE_RL_int_sqrt_work_24, + WILL_FIRE_RL_int_sqrt_work_25, + WILL_FIRE_RL_int_sqrt_work_26, + WILL_FIRE_RL_int_sqrt_work_27, + WILL_FIRE_RL_int_sqrt_work_28, + WILL_FIRE_RL_int_sqrt_work_29, + WILL_FIRE_RL_int_sqrt_work_3, + WILL_FIRE_RL_int_sqrt_work_30, + WILL_FIRE_RL_int_sqrt_work_31, + WILL_FIRE_RL_int_sqrt_work_32, + WILL_FIRE_RL_int_sqrt_work_33, + WILL_FIRE_RL_int_sqrt_work_34, + WILL_FIRE_RL_int_sqrt_work_35, + WILL_FIRE_RL_int_sqrt_work_36, + WILL_FIRE_RL_int_sqrt_work_37, + WILL_FIRE_RL_int_sqrt_work_38, + WILL_FIRE_RL_int_sqrt_work_39, + WILL_FIRE_RL_int_sqrt_work_4, + WILL_FIRE_RL_int_sqrt_work_40, + WILL_FIRE_RL_int_sqrt_work_41, + WILL_FIRE_RL_int_sqrt_work_42, + WILL_FIRE_RL_int_sqrt_work_43, + WILL_FIRE_RL_int_sqrt_work_44, + WILL_FIRE_RL_int_sqrt_work_45, + WILL_FIRE_RL_int_sqrt_work_46, + WILL_FIRE_RL_int_sqrt_work_47, + WILL_FIRE_RL_int_sqrt_work_48, + WILL_FIRE_RL_int_sqrt_work_49, + WILL_FIRE_RL_int_sqrt_work_5, + WILL_FIRE_RL_int_sqrt_work_50, + WILL_FIRE_RL_int_sqrt_work_51, + WILL_FIRE_RL_int_sqrt_work_52, + WILL_FIRE_RL_int_sqrt_work_53, + WILL_FIRE_RL_int_sqrt_work_54, + WILL_FIRE_RL_int_sqrt_work_55, + WILL_FIRE_RL_int_sqrt_work_56, + WILL_FIRE_RL_int_sqrt_work_57, + WILL_FIRE_RL_int_sqrt_work_58, + WILL_FIRE_RL_int_sqrt_work_6, + WILL_FIRE_RL_int_sqrt_work_7, + WILL_FIRE_RL_int_sqrt_work_8, + WILL_FIRE_RL_int_sqrt_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; + // remaining internal signals + reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15; + reg [62 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11; + reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, + _theResult___fst_sfd__h76507; + reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4, + _theResult___fst_exp__h76506; + reg CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10; + wire [194 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477; + wire [115 : 0] _theResult___snd_fst__h25299, + _theResult___snd_fst__h25701, + _theResult___snd_fst__h26101, + _theResult___snd_fst__h26501, + _theResult___snd_fst__h26901, + _theResult___snd_fst__h27301, + _theResult___snd_fst__h27701, + _theResult___snd_fst__h28101, + _theResult___snd_fst__h28501, + _theResult___snd_fst__h28901, + _theResult___snd_fst__h29301, + _theResult___snd_fst__h29701, + _theResult___snd_fst__h30101, + _theResult___snd_fst__h30501, + _theResult___snd_fst__h30901, + _theResult___snd_fst__h31301, + _theResult___snd_fst__h31701, + _theResult___snd_fst__h32101, + _theResult___snd_fst__h32501, + _theResult___snd_fst__h32901, + _theResult___snd_fst__h33301, + _theResult___snd_fst__h33701, + _theResult___snd_fst__h34101, + _theResult___snd_fst__h34501, + _theResult___snd_fst__h34901, + _theResult___snd_fst__h35301, + _theResult___snd_fst__h35701, + _theResult___snd_fst__h36101, + _theResult___snd_fst__h36501, + _theResult___snd_fst__h36901, + _theResult___snd_fst__h37301, + _theResult___snd_fst__h37701, + _theResult___snd_fst__h38101, + _theResult___snd_fst__h38501, + _theResult___snd_fst__h38901, + _theResult___snd_fst__h39301, + _theResult___snd_fst__h39701, + _theResult___snd_fst__h40101, + _theResult___snd_fst__h40501, + _theResult___snd_fst__h40901, + _theResult___snd_fst__h41301, + _theResult___snd_fst__h41701, + _theResult___snd_fst__h42101, + _theResult___snd_fst__h42501, + _theResult___snd_fst__h42901, + _theResult___snd_fst__h43301, + _theResult___snd_fst__h43701, + _theResult___snd_fst__h44101, + _theResult___snd_fst__h44501, + _theResult___snd_fst__h44901, + _theResult___snd_fst__h45301, + _theResult___snd_fst__h45701, + _theResult___snd_fst__h46101, + _theResult___snd_fst__h46501, + _theResult___snd_fst__h46901, + _theResult___snd_fst__h47301, + _theResult___snd_fst__h47701, + _theResult___snd_fst__h48101, + _theResult___snd_fst__h48501, + _theResult___snd_snd__h25377, + _theResult___snd_snd__h25777, + _theResult___snd_snd__h26177, + _theResult___snd_snd__h26577, + _theResult___snd_snd__h26977, + _theResult___snd_snd__h27377, + _theResult___snd_snd__h27777, + _theResult___snd_snd__h28177, + _theResult___snd_snd__h28577, + _theResult___snd_snd__h28977, + _theResult___snd_snd__h29377, + _theResult___snd_snd__h29777, + _theResult___snd_snd__h30177, + _theResult___snd_snd__h30577, + _theResult___snd_snd__h30977, + _theResult___snd_snd__h31377, + _theResult___snd_snd__h31777, + _theResult___snd_snd__h32177, + _theResult___snd_snd__h32577, + _theResult___snd_snd__h32977, + _theResult___snd_snd__h33377, + _theResult___snd_snd__h33777, + _theResult___snd_snd__h34177, + _theResult___snd_snd__h34577, + _theResult___snd_snd__h34977, + _theResult___snd_snd__h35377, + _theResult___snd_snd__h35777, + _theResult___snd_snd__h36177, + _theResult___snd_snd__h36577, + _theResult___snd_snd__h36977, + _theResult___snd_snd__h37377, + _theResult___snd_snd__h37777, + _theResult___snd_snd__h38177, + _theResult___snd_snd__h38577, + _theResult___snd_snd__h38977, + _theResult___snd_snd__h39377, + _theResult___snd_snd__h39777, + _theResult___snd_snd__h40177, + _theResult___snd_snd__h40577, + _theResult___snd_snd__h40977, + _theResult___snd_snd__h41377, + _theResult___snd_snd__h41777, + _theResult___snd_snd__h42177, + _theResult___snd_snd__h42577, + _theResult___snd_snd__h42977, + _theResult___snd_snd__h43377, + _theResult___snd_snd__h43777, + _theResult___snd_snd__h44177, + _theResult___snd_snd__h44577, + _theResult___snd_snd__h44977, + _theResult___snd_snd__h45377, + _theResult___snd_snd__h45777, + _theResult___snd_snd__h46177, + _theResult___snd_snd__h46577, + _theResult___snd_snd__h46977, + _theResult___snd_snd__h47377, + _theResult___snd_snd__h47777, + _theResult___snd_snd__h48177, + _theResult___snd_snd__h48577, + b___1__h16687, + b__h25374, + b__h25774, + b__h26174, + b__h26574, + b__h26974, + b__h27374, + b__h27774, + b__h28174, + b__h28574, + b__h28974, + b__h29374, + b__h29774, + b__h30174, + b__h30574, + b__h30974, + b__h31374, + b__h31774, + b__h32174, + b__h32574, + b__h32974, + b__h33374, + b__h33774, + b__h34174, + b__h34574, + b__h34974, + b__h35374, + b__h35774, + b__h36174, + b__h36574, + b__h36974, + b__h37374, + b__h37774, + b__h38174, + b__h38574, + b__h38974, + b__h39374, + b__h39774, + b__h40174, + b__h40574, + b__h40974, + b__h41374, + b__h41774, + b__h42174, + b__h42574, + b__h42974, + b__h43374, + b__h43774, + b__h44174, + b__h44574, + b__h44974, + b__h45374, + b__h45774, + b__h46174, + b__h46574, + b__h46974, + b__h47374, + b__h47774, + b__h48174, + b__h48574, + b__h48712, + r__h25386, + r__h25394, + r__h25786, + r__h25794, + r__h26186, + r__h26194, + r__h26586, + r__h26594, + r__h26986, + r__h26994, + r__h27386, + r__h27394, + r__h27786, + r__h27794, + r__h28186, + r__h28194, + r__h28586, + r__h28594, + r__h28986, + r__h28994, + r__h29386, + r__h29394, + r__h29786, + r__h29794, + r__h30186, + r__h30194, + r__h30586, + r__h30594, + r__h30986, + r__h30994, + r__h31386, + r__h31394, + r__h31786, + r__h31794, + r__h32186, + r__h32194, + r__h32586, + r__h32594, + r__h32986, + r__h32994, + r__h33386, + r__h33394, + r__h33786, + r__h33794, + r__h34186, + r__h34194, + r__h34586, + r__h34594, + r__h34986, + r__h34994, + r__h35386, + r__h35394, + r__h35786, + r__h35794, + r__h36186, + r__h36194, + r__h36586, + r__h36594, + r__h36986, + r__h36994, + r__h37386, + r__h37394, + r__h37786, + r__h37794, + r__h38186, + r__h38194, + r__h38586, + r__h38594, + r__h38986, + r__h38994, + r__h39386, + r__h39394, + r__h39786, + r__h39794, + r__h40186, + r__h40194, + r__h40586, + r__h40594, + r__h40986, + r__h40994, + r__h41386, + r__h41394, + r__h41786, + r__h41794, + r__h42186, + r__h42194, + r__h42586, + r__h42594, + r__h42986, + r__h42994, + r__h43386, + r__h43394, + r__h43786, + r__h43794, + r__h44186, + r__h44194, + r__h44586, + r__h44594, + r__h44986, + r__h44994, + r__h45386, + r__h45394, + r__h45786, + r__h45794, + r__h46186, + r__h46194, + r__h46586, + r__h46594, + r__h46986, + r__h46994, + r__h47386, + r__h47394, + r__h47786, + r__h47794, + r__h48186, + r__h48194, + r__h48586, + r__h48594, + s__h25385, + s__h25785, + s__h26185, + s__h26585, + s__h26985, + s__h27385, + s__h27785, + s__h28185, + s__h28585, + s__h28985, + s__h29385, + s__h29785, + s__h30185, + s__h30585, + s__h30985, + s__h31385, + s__h31785, + s__h32185, + s__h32585, + s__h32985, + s__h33385, + s__h33785, + s__h34185, + s__h34585, + s__h34985, + s__h35385, + s__h35785, + s__h36185, + s__h36585, + s__h36985, + s__h37385, + s__h37785, + s__h38185, + s__h38585, + s__h38985, + s__h39385, + s__h39785, + s__h40185, + s__h40585, + s__h40985, + s__h41385, + s__h41785, + s__h42185, + s__h42585, + s__h42985, + s__h43385, + s__h43785, + s__h44185, + s__h44585, + s__h44985, + s__h45385, + s__h45785, + s__h46185, + s__h46585, + s__h46985, + s__h47385, + s__h47785, + s__h48185, + s__h48585, + sum__h25372, + sum__h25772, + sum__h26172, + sum__h26572, + sum__h26972, + sum__h27372, + sum__h27772, + sum__h28172, + sum__h28572, + sum__h28972, + sum__h29372, + sum__h29772, + sum__h30172, + sum__h30572, + sum__h30972, + sum__h31372, + sum__h31772, + sum__h32172, + sum__h32572, + sum__h32972, + sum__h33372, + sum__h33772, + sum__h34172, + sum__h34572, + sum__h34972, + sum__h35372, + sum__h35772, + sum__h36172, + sum__h36572, + sum__h36972, + sum__h37372, + sum__h37772, + sum__h38172, + sum__h38572, + sum__h38972, + sum__h39372, + sum__h39772, + sum__h40172, + sum__h40572, + sum__h40972, + sum__h41372, + sum__h41772, + sum__h42172, + sum__h42572, + sum__h42972, + sum__h43372, + sum__h43772, + sum__h44172, + sum__h44572, + sum__h44972, + sum__h45372, + sum__h45772, + sum__h46172, + sum__h46572, + sum__h46972, + sum__h47372, + sum__h47772, + sum__h48172, + sum__h48572, + x__h402; + wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866, + IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820; + wire [58 : 0] IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6, + _theResult___snd__h75283, + _theResult___snd__h75298, + _theResult___snd__h75300, + _theResult___snd__h75313, + _theResult___snd__h75319, + _theResult___snd__h75337, + _theResult___snd__h75342, + result__h66451, + sfdin__h75260, + x__h66665; + wire [57 : 0] sfd___1__h65692, sfd__h49936, sfd__h49938, x__h65683; + wire [53 : 0] sfd__h75932, value__h58164; + wire [51 : 0] _theResult___fst_sfd__h76510, + _theResult___sfd__h76429, + out_sfd__h76432, + sfd__h49989; + wire [12 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460, + x__h57541, + x__h57559; + wire [11 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9, + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531, + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774; + wire [10 : 0] IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, + _theResult___exp__h76428, + _theResult___fst_exp__h75266, + _theResult___fst_exp__h75269, + _theResult___fst_exp__h75289, + _theResult___fst_exp__h75305, + _theResult___fst_exp__h75344, + _theResult___fst_exp__h75350, + _theResult___fst_exp__h75353, + _theResult___fst_exp__h76509, + din_inc___2_exp__h76519, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8, + fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5, + out_exp__h76431; + wire [6 : 0] IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237, + x__h24992; + wire [5 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458, + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772, + x__h65722; + wire [2 : 0] IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813; + wire [1 : 0] IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7, + _theResult___snd_fst__h75372, + guard__h66951, + x__h75654; + wire _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775, + int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264, + int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299, + int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649, + int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684, + int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719, + int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754, + int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789, + int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824, + int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859, + int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894, + int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929, + int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964, + int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334, + int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999, + int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034, + int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069, + int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104, + int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139, + int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174, + int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209, + int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244, + int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279, + int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314, + int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369, + int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349, + int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384, + int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419, + int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454, + int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489, + int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524, + int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559, + int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594, + int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629, + int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664, + int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404, + int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699, + int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734, + int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769, + int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804, + int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839, + int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874, + int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909, + int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944, + int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979, + int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014, + int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439, + int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049, + int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084, + int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119, + int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154, + int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189, + int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224, + int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259, + int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294, + int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474, + int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509, + int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544, + int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579, + int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614, + value_BIT_52___h58260; + // action method request_put - assign RDY_request_put = fpu$RDY_request_put ; - assign CAN_FIRE_request_put = fpu$RDY_request_put ; + assign RDY_request_put = fpu_fOperand_S0$FULL_N ; + assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu$response_get ; - assign RDY_response_get = fpu$RDY_response_get ; - assign CAN_FIRE_response_get = fpu$RDY_response_get ; + assign response_get = fpu_fResult_S5$D_OUT ; + assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; + assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu - mkXilinxFpSqrt fpu(.CLK(CLK), - .RST_N(RST_N), - .request_put(fpu$request_put), - .EN_request_put(fpu$EN_request_put), - .EN_response_get(fpu$EN_response_get), - .RDY_request_put(fpu$RDY_request_put), - .response_get(fpu$response_get), - .RDY_response_get(fpu$RDY_response_get)); + // submodule fpu_fOperand_S0 + FIFOL1 #(.width(32'd67)) fpu_fOperand_S0(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fOperand_S0$D_IN), + .ENQ(fpu_fOperand_S0$ENQ), + .DEQ(fpu_fOperand_S0$DEQ), + .CLR(fpu_fOperand_S0$CLR), + .D_OUT(fpu_fOperand_S0$D_OUT), + .FULL_N(fpu_fOperand_S0$FULL_N), + .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); - // submodule fpu - assign fpu$request_put = request_put ; - assign fpu$EN_request_put = EN_request_put ; - assign fpu$EN_response_get = EN_response_get ; + // submodule fpu_fResult_S5 + FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fResult_S5$D_IN), + .ENQ(fpu_fResult_S5$ENQ), + .DEQ(fpu_fResult_S5$DEQ), + .CLR(fpu_fResult_S5$CLR), + .D_OUT(fpu_fResult_S5$D_OUT), + .FULL_N(fpu_fResult_S5$FULL_N), + .EMPTY_N(fpu_fResult_S5$EMPTY_N)); + + // submodule fpu_fState_S1 + FIFOL1 #(.width(32'd195)) fpu_fState_S1(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S1$D_IN), + .ENQ(fpu_fState_S1$ENQ), + .DEQ(fpu_fState_S1$DEQ), + .CLR(fpu_fState_S1$CLR), + .D_OUT(fpu_fState_S1$D_OUT), + .FULL_N(fpu_fState_S1$FULL_N), + .EMPTY_N(fpu_fState_S1$EMPTY_N)); + + // submodule fpu_fState_S2 + FIFOL1 #(.width(32'd137)) fpu_fState_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S2$D_IN), + .ENQ(fpu_fState_S2$ENQ), + .DEQ(fpu_fState_S2$DEQ), + .CLR(fpu_fState_S2$CLR), + .D_OUT(fpu_fState_S2$D_OUT), + .FULL_N(fpu_fState_S2$FULL_N), + .EMPTY_N(fpu_fState_S2$EMPTY_N)); + + // submodule fpu_fState_S3 + FIFOL1 #(.width(32'd196)) fpu_fState_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S3$D_IN), + .ENQ(fpu_fState_S3$ENQ), + .DEQ(fpu_fState_S3$DEQ), + .CLR(fpu_fState_S3$CLR), + .D_OUT(fpu_fState_S3$D_OUT), + .FULL_N(fpu_fState_S3$FULL_N), + .EMPTY_N(fpu_fState_S3$EMPTY_N)); + + // submodule fpu_fState_S4 + FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S4$D_IN), + .ENQ(fpu_fState_S4$ENQ), + .DEQ(fpu_fState_S4$DEQ), + .CLR(fpu_fState_S4$CLR), + .D_OUT(fpu_fState_S4$D_OUT), + .FULL_N(fpu_fState_S4$FULL_N), + .EMPTY_N(fpu_fState_S4$EMPTY_N)); + + // submodule int_sqrt_fFirst + FIFOL1 #(.width(32'd465)) int_sqrt_fFirst(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fFirst$D_IN), + .ENQ(int_sqrt_fFirst$ENQ), + .DEQ(int_sqrt_fFirst$DEQ), + .CLR(int_sqrt_fFirst$CLR), + .D_OUT(int_sqrt_fFirst$D_OUT), + .FULL_N(int_sqrt_fFirst$FULL_N), + .EMPTY_N(int_sqrt_fFirst$EMPTY_N)); + + // submodule int_sqrt_fNext_0 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_0(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_0$D_IN), + .ENQ(int_sqrt_fNext_0$ENQ), + .DEQ(int_sqrt_fNext_0$DEQ), + .CLR(int_sqrt_fNext_0$CLR), + .D_OUT(int_sqrt_fNext_0$D_OUT), + .FULL_N(int_sqrt_fNext_0$FULL_N), + .EMPTY_N(int_sqrt_fNext_0$EMPTY_N)); + + // submodule int_sqrt_fNext_1 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_1(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_1$D_IN), + .ENQ(int_sqrt_fNext_1$ENQ), + .DEQ(int_sqrt_fNext_1$DEQ), + .CLR(int_sqrt_fNext_1$CLR), + .D_OUT(int_sqrt_fNext_1$D_OUT), + .FULL_N(int_sqrt_fNext_1$FULL_N), + .EMPTY_N(int_sqrt_fNext_1$EMPTY_N)); + + // submodule int_sqrt_fNext_10 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_10(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_10$D_IN), + .ENQ(int_sqrt_fNext_10$ENQ), + .DEQ(int_sqrt_fNext_10$DEQ), + .CLR(int_sqrt_fNext_10$CLR), + .D_OUT(int_sqrt_fNext_10$D_OUT), + .FULL_N(int_sqrt_fNext_10$FULL_N), + .EMPTY_N(int_sqrt_fNext_10$EMPTY_N)); + + // submodule int_sqrt_fNext_11 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_11(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_11$D_IN), + .ENQ(int_sqrt_fNext_11$ENQ), + .DEQ(int_sqrt_fNext_11$DEQ), + .CLR(int_sqrt_fNext_11$CLR), + .D_OUT(int_sqrt_fNext_11$D_OUT), + .FULL_N(int_sqrt_fNext_11$FULL_N), + .EMPTY_N(int_sqrt_fNext_11$EMPTY_N)); + + // submodule int_sqrt_fNext_12 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_12(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_12$D_IN), + .ENQ(int_sqrt_fNext_12$ENQ), + .DEQ(int_sqrt_fNext_12$DEQ), + .CLR(int_sqrt_fNext_12$CLR), + .D_OUT(int_sqrt_fNext_12$D_OUT), + .FULL_N(int_sqrt_fNext_12$FULL_N), + .EMPTY_N(int_sqrt_fNext_12$EMPTY_N)); + + // submodule int_sqrt_fNext_13 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_13(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_13$D_IN), + .ENQ(int_sqrt_fNext_13$ENQ), + .DEQ(int_sqrt_fNext_13$DEQ), + .CLR(int_sqrt_fNext_13$CLR), + .D_OUT(int_sqrt_fNext_13$D_OUT), + .FULL_N(int_sqrt_fNext_13$FULL_N), + .EMPTY_N(int_sqrt_fNext_13$EMPTY_N)); + + // submodule int_sqrt_fNext_14 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_14(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_14$D_IN), + .ENQ(int_sqrt_fNext_14$ENQ), + .DEQ(int_sqrt_fNext_14$DEQ), + .CLR(int_sqrt_fNext_14$CLR), + .D_OUT(int_sqrt_fNext_14$D_OUT), + .FULL_N(int_sqrt_fNext_14$FULL_N), + .EMPTY_N(int_sqrt_fNext_14$EMPTY_N)); + + // submodule int_sqrt_fNext_15 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_15(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_15$D_IN), + .ENQ(int_sqrt_fNext_15$ENQ), + .DEQ(int_sqrt_fNext_15$DEQ), + .CLR(int_sqrt_fNext_15$CLR), + .D_OUT(int_sqrt_fNext_15$D_OUT), + .FULL_N(int_sqrt_fNext_15$FULL_N), + .EMPTY_N(int_sqrt_fNext_15$EMPTY_N)); + + // submodule int_sqrt_fNext_16 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_16(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_16$D_IN), + .ENQ(int_sqrt_fNext_16$ENQ), + .DEQ(int_sqrt_fNext_16$DEQ), + .CLR(int_sqrt_fNext_16$CLR), + .D_OUT(int_sqrt_fNext_16$D_OUT), + .FULL_N(int_sqrt_fNext_16$FULL_N), + .EMPTY_N(int_sqrt_fNext_16$EMPTY_N)); + + // submodule int_sqrt_fNext_17 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_17(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_17$D_IN), + .ENQ(int_sqrt_fNext_17$ENQ), + .DEQ(int_sqrt_fNext_17$DEQ), + .CLR(int_sqrt_fNext_17$CLR), + .D_OUT(int_sqrt_fNext_17$D_OUT), + .FULL_N(int_sqrt_fNext_17$FULL_N), + .EMPTY_N(int_sqrt_fNext_17$EMPTY_N)); + + // submodule int_sqrt_fNext_18 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_18(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_18$D_IN), + .ENQ(int_sqrt_fNext_18$ENQ), + .DEQ(int_sqrt_fNext_18$DEQ), + .CLR(int_sqrt_fNext_18$CLR), + .D_OUT(int_sqrt_fNext_18$D_OUT), + .FULL_N(int_sqrt_fNext_18$FULL_N), + .EMPTY_N(int_sqrt_fNext_18$EMPTY_N)); + + // submodule int_sqrt_fNext_19 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_19(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_19$D_IN), + .ENQ(int_sqrt_fNext_19$ENQ), + .DEQ(int_sqrt_fNext_19$DEQ), + .CLR(int_sqrt_fNext_19$CLR), + .D_OUT(int_sqrt_fNext_19$D_OUT), + .FULL_N(int_sqrt_fNext_19$FULL_N), + .EMPTY_N(int_sqrt_fNext_19$EMPTY_N)); + + // submodule int_sqrt_fNext_2 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_2(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_2$D_IN), + .ENQ(int_sqrt_fNext_2$ENQ), + .DEQ(int_sqrt_fNext_2$DEQ), + .CLR(int_sqrt_fNext_2$CLR), + .D_OUT(int_sqrt_fNext_2$D_OUT), + .FULL_N(int_sqrt_fNext_2$FULL_N), + .EMPTY_N(int_sqrt_fNext_2$EMPTY_N)); + + // submodule int_sqrt_fNext_20 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_20(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_20$D_IN), + .ENQ(int_sqrt_fNext_20$ENQ), + .DEQ(int_sqrt_fNext_20$DEQ), + .CLR(int_sqrt_fNext_20$CLR), + .D_OUT(int_sqrt_fNext_20$D_OUT), + .FULL_N(int_sqrt_fNext_20$FULL_N), + .EMPTY_N(int_sqrt_fNext_20$EMPTY_N)); + + // submodule int_sqrt_fNext_21 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_21(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_21$D_IN), + .ENQ(int_sqrt_fNext_21$ENQ), + .DEQ(int_sqrt_fNext_21$DEQ), + .CLR(int_sqrt_fNext_21$CLR), + .D_OUT(int_sqrt_fNext_21$D_OUT), + .FULL_N(int_sqrt_fNext_21$FULL_N), + .EMPTY_N(int_sqrt_fNext_21$EMPTY_N)); + + // submodule int_sqrt_fNext_22 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_22(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_22$D_IN), + .ENQ(int_sqrt_fNext_22$ENQ), + .DEQ(int_sqrt_fNext_22$DEQ), + .CLR(int_sqrt_fNext_22$CLR), + .D_OUT(int_sqrt_fNext_22$D_OUT), + .FULL_N(int_sqrt_fNext_22$FULL_N), + .EMPTY_N(int_sqrt_fNext_22$EMPTY_N)); + + // submodule int_sqrt_fNext_23 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_23(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_23$D_IN), + .ENQ(int_sqrt_fNext_23$ENQ), + .DEQ(int_sqrt_fNext_23$DEQ), + .CLR(int_sqrt_fNext_23$CLR), + .D_OUT(int_sqrt_fNext_23$D_OUT), + .FULL_N(int_sqrt_fNext_23$FULL_N), + .EMPTY_N(int_sqrt_fNext_23$EMPTY_N)); + + // submodule int_sqrt_fNext_24 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_24(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_24$D_IN), + .ENQ(int_sqrt_fNext_24$ENQ), + .DEQ(int_sqrt_fNext_24$DEQ), + .CLR(int_sqrt_fNext_24$CLR), + .D_OUT(int_sqrt_fNext_24$D_OUT), + .FULL_N(int_sqrt_fNext_24$FULL_N), + .EMPTY_N(int_sqrt_fNext_24$EMPTY_N)); + + // submodule int_sqrt_fNext_25 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_25(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_25$D_IN), + .ENQ(int_sqrt_fNext_25$ENQ), + .DEQ(int_sqrt_fNext_25$DEQ), + .CLR(int_sqrt_fNext_25$CLR), + .D_OUT(int_sqrt_fNext_25$D_OUT), + .FULL_N(int_sqrt_fNext_25$FULL_N), + .EMPTY_N(int_sqrt_fNext_25$EMPTY_N)); + + // submodule int_sqrt_fNext_26 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_26(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_26$D_IN), + .ENQ(int_sqrt_fNext_26$ENQ), + .DEQ(int_sqrt_fNext_26$DEQ), + .CLR(int_sqrt_fNext_26$CLR), + .D_OUT(int_sqrt_fNext_26$D_OUT), + .FULL_N(int_sqrt_fNext_26$FULL_N), + .EMPTY_N(int_sqrt_fNext_26$EMPTY_N)); + + // submodule int_sqrt_fNext_27 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_27(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_27$D_IN), + .ENQ(int_sqrt_fNext_27$ENQ), + .DEQ(int_sqrt_fNext_27$DEQ), + .CLR(int_sqrt_fNext_27$CLR), + .D_OUT(int_sqrt_fNext_27$D_OUT), + .FULL_N(int_sqrt_fNext_27$FULL_N), + .EMPTY_N(int_sqrt_fNext_27$EMPTY_N)); + + // submodule int_sqrt_fNext_28 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_28(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_28$D_IN), + .ENQ(int_sqrt_fNext_28$ENQ), + .DEQ(int_sqrt_fNext_28$DEQ), + .CLR(int_sqrt_fNext_28$CLR), + .D_OUT(int_sqrt_fNext_28$D_OUT), + .FULL_N(int_sqrt_fNext_28$FULL_N), + .EMPTY_N(int_sqrt_fNext_28$EMPTY_N)); + + // submodule int_sqrt_fNext_29 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_29(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_29$D_IN), + .ENQ(int_sqrt_fNext_29$ENQ), + .DEQ(int_sqrt_fNext_29$DEQ), + .CLR(int_sqrt_fNext_29$CLR), + .D_OUT(int_sqrt_fNext_29$D_OUT), + .FULL_N(int_sqrt_fNext_29$FULL_N), + .EMPTY_N(int_sqrt_fNext_29$EMPTY_N)); + + // submodule int_sqrt_fNext_3 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_3(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_3$D_IN), + .ENQ(int_sqrt_fNext_3$ENQ), + .DEQ(int_sqrt_fNext_3$DEQ), + .CLR(int_sqrt_fNext_3$CLR), + .D_OUT(int_sqrt_fNext_3$D_OUT), + .FULL_N(int_sqrt_fNext_3$FULL_N), + .EMPTY_N(int_sqrt_fNext_3$EMPTY_N)); + + // submodule int_sqrt_fNext_30 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_30(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_30$D_IN), + .ENQ(int_sqrt_fNext_30$ENQ), + .DEQ(int_sqrt_fNext_30$DEQ), + .CLR(int_sqrt_fNext_30$CLR), + .D_OUT(int_sqrt_fNext_30$D_OUT), + .FULL_N(int_sqrt_fNext_30$FULL_N), + .EMPTY_N(int_sqrt_fNext_30$EMPTY_N)); + + // submodule int_sqrt_fNext_31 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_31(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_31$D_IN), + .ENQ(int_sqrt_fNext_31$ENQ), + .DEQ(int_sqrt_fNext_31$DEQ), + .CLR(int_sqrt_fNext_31$CLR), + .D_OUT(int_sqrt_fNext_31$D_OUT), + .FULL_N(int_sqrt_fNext_31$FULL_N), + .EMPTY_N(int_sqrt_fNext_31$EMPTY_N)); + + // submodule int_sqrt_fNext_32 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_32(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_32$D_IN), + .ENQ(int_sqrt_fNext_32$ENQ), + .DEQ(int_sqrt_fNext_32$DEQ), + .CLR(int_sqrt_fNext_32$CLR), + .D_OUT(int_sqrt_fNext_32$D_OUT), + .FULL_N(int_sqrt_fNext_32$FULL_N), + .EMPTY_N(int_sqrt_fNext_32$EMPTY_N)); + + // submodule int_sqrt_fNext_33 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_33(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_33$D_IN), + .ENQ(int_sqrt_fNext_33$ENQ), + .DEQ(int_sqrt_fNext_33$DEQ), + .CLR(int_sqrt_fNext_33$CLR), + .D_OUT(int_sqrt_fNext_33$D_OUT), + .FULL_N(int_sqrt_fNext_33$FULL_N), + .EMPTY_N(int_sqrt_fNext_33$EMPTY_N)); + + // submodule int_sqrt_fNext_34 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_34(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_34$D_IN), + .ENQ(int_sqrt_fNext_34$ENQ), + .DEQ(int_sqrt_fNext_34$DEQ), + .CLR(int_sqrt_fNext_34$CLR), + .D_OUT(int_sqrt_fNext_34$D_OUT), + .FULL_N(int_sqrt_fNext_34$FULL_N), + .EMPTY_N(int_sqrt_fNext_34$EMPTY_N)); + + // submodule int_sqrt_fNext_35 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_35(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_35$D_IN), + .ENQ(int_sqrt_fNext_35$ENQ), + .DEQ(int_sqrt_fNext_35$DEQ), + .CLR(int_sqrt_fNext_35$CLR), + .D_OUT(int_sqrt_fNext_35$D_OUT), + .FULL_N(int_sqrt_fNext_35$FULL_N), + .EMPTY_N(int_sqrt_fNext_35$EMPTY_N)); + + // submodule int_sqrt_fNext_36 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_36(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_36$D_IN), + .ENQ(int_sqrt_fNext_36$ENQ), + .DEQ(int_sqrt_fNext_36$DEQ), + .CLR(int_sqrt_fNext_36$CLR), + .D_OUT(int_sqrt_fNext_36$D_OUT), + .FULL_N(int_sqrt_fNext_36$FULL_N), + .EMPTY_N(int_sqrt_fNext_36$EMPTY_N)); + + // submodule int_sqrt_fNext_37 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_37(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_37$D_IN), + .ENQ(int_sqrt_fNext_37$ENQ), + .DEQ(int_sqrt_fNext_37$DEQ), + .CLR(int_sqrt_fNext_37$CLR), + .D_OUT(int_sqrt_fNext_37$D_OUT), + .FULL_N(int_sqrt_fNext_37$FULL_N), + .EMPTY_N(int_sqrt_fNext_37$EMPTY_N)); + + // submodule int_sqrt_fNext_38 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_38(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_38$D_IN), + .ENQ(int_sqrt_fNext_38$ENQ), + .DEQ(int_sqrt_fNext_38$DEQ), + .CLR(int_sqrt_fNext_38$CLR), + .D_OUT(int_sqrt_fNext_38$D_OUT), + .FULL_N(int_sqrt_fNext_38$FULL_N), + .EMPTY_N(int_sqrt_fNext_38$EMPTY_N)); + + // submodule int_sqrt_fNext_39 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_39(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_39$D_IN), + .ENQ(int_sqrt_fNext_39$ENQ), + .DEQ(int_sqrt_fNext_39$DEQ), + .CLR(int_sqrt_fNext_39$CLR), + .D_OUT(int_sqrt_fNext_39$D_OUT), + .FULL_N(int_sqrt_fNext_39$FULL_N), + .EMPTY_N(int_sqrt_fNext_39$EMPTY_N)); + + // submodule int_sqrt_fNext_4 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_4(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_4$D_IN), + .ENQ(int_sqrt_fNext_4$ENQ), + .DEQ(int_sqrt_fNext_4$DEQ), + .CLR(int_sqrt_fNext_4$CLR), + .D_OUT(int_sqrt_fNext_4$D_OUT), + .FULL_N(int_sqrt_fNext_4$FULL_N), + .EMPTY_N(int_sqrt_fNext_4$EMPTY_N)); + + // submodule int_sqrt_fNext_40 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_40(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_40$D_IN), + .ENQ(int_sqrt_fNext_40$ENQ), + .DEQ(int_sqrt_fNext_40$DEQ), + .CLR(int_sqrt_fNext_40$CLR), + .D_OUT(int_sqrt_fNext_40$D_OUT), + .FULL_N(int_sqrt_fNext_40$FULL_N), + .EMPTY_N(int_sqrt_fNext_40$EMPTY_N)); + + // submodule int_sqrt_fNext_41 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_41(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_41$D_IN), + .ENQ(int_sqrt_fNext_41$ENQ), + .DEQ(int_sqrt_fNext_41$DEQ), + .CLR(int_sqrt_fNext_41$CLR), + .D_OUT(int_sqrt_fNext_41$D_OUT), + .FULL_N(int_sqrt_fNext_41$FULL_N), + .EMPTY_N(int_sqrt_fNext_41$EMPTY_N)); + + // submodule int_sqrt_fNext_42 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_42(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_42$D_IN), + .ENQ(int_sqrt_fNext_42$ENQ), + .DEQ(int_sqrt_fNext_42$DEQ), + .CLR(int_sqrt_fNext_42$CLR), + .D_OUT(int_sqrt_fNext_42$D_OUT), + .FULL_N(int_sqrt_fNext_42$FULL_N), + .EMPTY_N(int_sqrt_fNext_42$EMPTY_N)); + + // submodule int_sqrt_fNext_43 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_43(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_43$D_IN), + .ENQ(int_sqrt_fNext_43$ENQ), + .DEQ(int_sqrt_fNext_43$DEQ), + .CLR(int_sqrt_fNext_43$CLR), + .D_OUT(int_sqrt_fNext_43$D_OUT), + .FULL_N(int_sqrt_fNext_43$FULL_N), + .EMPTY_N(int_sqrt_fNext_43$EMPTY_N)); + + // submodule int_sqrt_fNext_44 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_44(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_44$D_IN), + .ENQ(int_sqrt_fNext_44$ENQ), + .DEQ(int_sqrt_fNext_44$DEQ), + .CLR(int_sqrt_fNext_44$CLR), + .D_OUT(int_sqrt_fNext_44$D_OUT), + .FULL_N(int_sqrt_fNext_44$FULL_N), + .EMPTY_N(int_sqrt_fNext_44$EMPTY_N)); + + // submodule int_sqrt_fNext_45 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_45(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_45$D_IN), + .ENQ(int_sqrt_fNext_45$ENQ), + .DEQ(int_sqrt_fNext_45$DEQ), + .CLR(int_sqrt_fNext_45$CLR), + .D_OUT(int_sqrt_fNext_45$D_OUT), + .FULL_N(int_sqrt_fNext_45$FULL_N), + .EMPTY_N(int_sqrt_fNext_45$EMPTY_N)); + + // submodule int_sqrt_fNext_46 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_46(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_46$D_IN), + .ENQ(int_sqrt_fNext_46$ENQ), + .DEQ(int_sqrt_fNext_46$DEQ), + .CLR(int_sqrt_fNext_46$CLR), + .D_OUT(int_sqrt_fNext_46$D_OUT), + .FULL_N(int_sqrt_fNext_46$FULL_N), + .EMPTY_N(int_sqrt_fNext_46$EMPTY_N)); + + // submodule int_sqrt_fNext_47 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_47(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_47$D_IN), + .ENQ(int_sqrt_fNext_47$ENQ), + .DEQ(int_sqrt_fNext_47$DEQ), + .CLR(int_sqrt_fNext_47$CLR), + .D_OUT(int_sqrt_fNext_47$D_OUT), + .FULL_N(int_sqrt_fNext_47$FULL_N), + .EMPTY_N(int_sqrt_fNext_47$EMPTY_N)); + + // submodule int_sqrt_fNext_48 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_48(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_48$D_IN), + .ENQ(int_sqrt_fNext_48$ENQ), + .DEQ(int_sqrt_fNext_48$DEQ), + .CLR(int_sqrt_fNext_48$CLR), + .D_OUT(int_sqrt_fNext_48$D_OUT), + .FULL_N(int_sqrt_fNext_48$FULL_N), + .EMPTY_N(int_sqrt_fNext_48$EMPTY_N)); + + // submodule int_sqrt_fNext_49 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_49(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_49$D_IN), + .ENQ(int_sqrt_fNext_49$ENQ), + .DEQ(int_sqrt_fNext_49$DEQ), + .CLR(int_sqrt_fNext_49$CLR), + .D_OUT(int_sqrt_fNext_49$D_OUT), + .FULL_N(int_sqrt_fNext_49$FULL_N), + .EMPTY_N(int_sqrt_fNext_49$EMPTY_N)); + + // submodule int_sqrt_fNext_5 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_5(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_5$D_IN), + .ENQ(int_sqrt_fNext_5$ENQ), + .DEQ(int_sqrt_fNext_5$DEQ), + .CLR(int_sqrt_fNext_5$CLR), + .D_OUT(int_sqrt_fNext_5$D_OUT), + .FULL_N(int_sqrt_fNext_5$FULL_N), + .EMPTY_N(int_sqrt_fNext_5$EMPTY_N)); + + // submodule int_sqrt_fNext_50 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_50(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_50$D_IN), + .ENQ(int_sqrt_fNext_50$ENQ), + .DEQ(int_sqrt_fNext_50$DEQ), + .CLR(int_sqrt_fNext_50$CLR), + .D_OUT(int_sqrt_fNext_50$D_OUT), + .FULL_N(int_sqrt_fNext_50$FULL_N), + .EMPTY_N(int_sqrt_fNext_50$EMPTY_N)); + + // submodule int_sqrt_fNext_51 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_51(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_51$D_IN), + .ENQ(int_sqrt_fNext_51$ENQ), + .DEQ(int_sqrt_fNext_51$DEQ), + .CLR(int_sqrt_fNext_51$CLR), + .D_OUT(int_sqrt_fNext_51$D_OUT), + .FULL_N(int_sqrt_fNext_51$FULL_N), + .EMPTY_N(int_sqrt_fNext_51$EMPTY_N)); + + // submodule int_sqrt_fNext_52 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_52(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_52$D_IN), + .ENQ(int_sqrt_fNext_52$ENQ), + .DEQ(int_sqrt_fNext_52$DEQ), + .CLR(int_sqrt_fNext_52$CLR), + .D_OUT(int_sqrt_fNext_52$D_OUT), + .FULL_N(int_sqrt_fNext_52$FULL_N), + .EMPTY_N(int_sqrt_fNext_52$EMPTY_N)); + + // submodule int_sqrt_fNext_53 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_53(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_53$D_IN), + .ENQ(int_sqrt_fNext_53$ENQ), + .DEQ(int_sqrt_fNext_53$DEQ), + .CLR(int_sqrt_fNext_53$CLR), + .D_OUT(int_sqrt_fNext_53$D_OUT), + .FULL_N(int_sqrt_fNext_53$FULL_N), + .EMPTY_N(int_sqrt_fNext_53$EMPTY_N)); + + // submodule int_sqrt_fNext_54 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_54(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_54$D_IN), + .ENQ(int_sqrt_fNext_54$ENQ), + .DEQ(int_sqrt_fNext_54$DEQ), + .CLR(int_sqrt_fNext_54$CLR), + .D_OUT(int_sqrt_fNext_54$D_OUT), + .FULL_N(int_sqrt_fNext_54$FULL_N), + .EMPTY_N(int_sqrt_fNext_54$EMPTY_N)); + + // submodule int_sqrt_fNext_55 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_55(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_55$D_IN), + .ENQ(int_sqrt_fNext_55$ENQ), + .DEQ(int_sqrt_fNext_55$DEQ), + .CLR(int_sqrt_fNext_55$CLR), + .D_OUT(int_sqrt_fNext_55$D_OUT), + .FULL_N(int_sqrt_fNext_55$FULL_N), + .EMPTY_N(int_sqrt_fNext_55$EMPTY_N)); + + // submodule int_sqrt_fNext_56 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_56(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_56$D_IN), + .ENQ(int_sqrt_fNext_56$ENQ), + .DEQ(int_sqrt_fNext_56$DEQ), + .CLR(int_sqrt_fNext_56$CLR), + .D_OUT(int_sqrt_fNext_56$D_OUT), + .FULL_N(int_sqrt_fNext_56$FULL_N), + .EMPTY_N(int_sqrt_fNext_56$EMPTY_N)); + + // submodule int_sqrt_fNext_57 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_57(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_57$D_IN), + .ENQ(int_sqrt_fNext_57$ENQ), + .DEQ(int_sqrt_fNext_57$DEQ), + .CLR(int_sqrt_fNext_57$CLR), + .D_OUT(int_sqrt_fNext_57$D_OUT), + .FULL_N(int_sqrt_fNext_57$FULL_N), + .EMPTY_N(int_sqrt_fNext_57$EMPTY_N)); + + // submodule int_sqrt_fNext_58 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_58(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_58$D_IN), + .ENQ(int_sqrt_fNext_58$ENQ), + .DEQ(int_sqrt_fNext_58$DEQ), + .CLR(int_sqrt_fNext_58$CLR), + .D_OUT(int_sqrt_fNext_58$D_OUT), + .FULL_N(int_sqrt_fNext_58$FULL_N), + .EMPTY_N(int_sqrt_fNext_58$EMPTY_N)); + + // submodule int_sqrt_fNext_6 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_6(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_6$D_IN), + .ENQ(int_sqrt_fNext_6$ENQ), + .DEQ(int_sqrt_fNext_6$DEQ), + .CLR(int_sqrt_fNext_6$CLR), + .D_OUT(int_sqrt_fNext_6$D_OUT), + .FULL_N(int_sqrt_fNext_6$FULL_N), + .EMPTY_N(int_sqrt_fNext_6$EMPTY_N)); + + // submodule int_sqrt_fNext_7 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_7(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_7$D_IN), + .ENQ(int_sqrt_fNext_7$ENQ), + .DEQ(int_sqrt_fNext_7$DEQ), + .CLR(int_sqrt_fNext_7$CLR), + .D_OUT(int_sqrt_fNext_7$D_OUT), + .FULL_N(int_sqrt_fNext_7$FULL_N), + .EMPTY_N(int_sqrt_fNext_7$EMPTY_N)); + + // submodule int_sqrt_fNext_8 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_8(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_8$D_IN), + .ENQ(int_sqrt_fNext_8$ENQ), + .DEQ(int_sqrt_fNext_8$DEQ), + .CLR(int_sqrt_fNext_8$CLR), + .D_OUT(int_sqrt_fNext_8$D_OUT), + .FULL_N(int_sqrt_fNext_8$FULL_N), + .EMPTY_N(int_sqrt_fNext_8$EMPTY_N)); + + // submodule int_sqrt_fNext_9 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_9(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_9$D_IN), + .ENQ(int_sqrt_fNext_9$ENQ), + .DEQ(int_sqrt_fNext_9$DEQ), + .CLR(int_sqrt_fNext_9$CLR), + .D_OUT(int_sqrt_fNext_9$D_OUT), + .FULL_N(int_sqrt_fNext_9$FULL_N), + .EMPTY_N(int_sqrt_fNext_9$EMPTY_N)); + + // submodule int_sqrt_fRequest + FIFOL1 #(.width(32'd116)) int_sqrt_fRequest(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fRequest$D_IN), + .ENQ(int_sqrt_fRequest$ENQ), + .DEQ(int_sqrt_fRequest$DEQ), + .CLR(int_sqrt_fRequest$CLR), + .D_OUT(int_sqrt_fRequest$D_OUT), + .FULL_N(int_sqrt_fRequest$FULL_N), + .EMPTY_N(int_sqrt_fRequest$EMPTY_N)); + + // submodule int_sqrt_fResponse + FIFOL1 #(.width(32'd117)) int_sqrt_fResponse(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fResponse$D_IN), + .ENQ(int_sqrt_fResponse$ENQ), + .DEQ(int_sqrt_fResponse$DEQ), + .CLR(int_sqrt_fResponse$CLR), + .D_OUT(int_sqrt_fResponse$D_OUT), + .FULL_N(int_sqrt_fResponse$FULL_N), + .EMPTY_N(int_sqrt_fResponse$EMPTY_N)); + + // rule RL_fpu_s5_stage + assign CAN_FIRE_RL_fpu_s5_stage = + fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; + assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; + + // rule RL_fpu_s4_stage + assign CAN_FIRE_RL_fpu_s4_stage = + fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; + assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; + + // rule RL_fpu_s3_stage + assign CAN_FIRE_RL_fpu_s3_stage = + fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && + (fpu_fState_S2$D_OUT[136] || int_sqrt_fResponse$EMPTY_N) ; + assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; + + // rule RL_int_sqrt_finish + assign CAN_FIRE_RL_int_sqrt_finish = + int_sqrt_fNext_58$EMPTY_N && int_sqrt_fResponse$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_finish = CAN_FIRE_RL_int_sqrt_finish ; + + // rule RL_int_sqrt_work_58 + assign CAN_FIRE_RL_int_sqrt_work_58 = + int_sqrt_fNext_57$EMPTY_N && int_sqrt_fNext_58$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_58 = CAN_FIRE_RL_int_sqrt_work_58 ; + + // rule RL_int_sqrt_work_57 + assign CAN_FIRE_RL_int_sqrt_work_57 = + int_sqrt_fNext_56$EMPTY_N && int_sqrt_fNext_57$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_57 = CAN_FIRE_RL_int_sqrt_work_57 ; + + // rule RL_int_sqrt_work_56 + assign CAN_FIRE_RL_int_sqrt_work_56 = + int_sqrt_fNext_55$EMPTY_N && int_sqrt_fNext_56$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_56 = CAN_FIRE_RL_int_sqrt_work_56 ; + + // rule RL_int_sqrt_work_55 + assign CAN_FIRE_RL_int_sqrt_work_55 = + int_sqrt_fNext_54$EMPTY_N && int_sqrt_fNext_55$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_55 = CAN_FIRE_RL_int_sqrt_work_55 ; + + // rule RL_int_sqrt_work_54 + assign CAN_FIRE_RL_int_sqrt_work_54 = + int_sqrt_fNext_53$EMPTY_N && int_sqrt_fNext_54$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_54 = CAN_FIRE_RL_int_sqrt_work_54 ; + + // rule RL_int_sqrt_work_53 + assign CAN_FIRE_RL_int_sqrt_work_53 = + int_sqrt_fNext_52$EMPTY_N && int_sqrt_fNext_53$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_53 = CAN_FIRE_RL_int_sqrt_work_53 ; + + // rule RL_int_sqrt_work_52 + assign CAN_FIRE_RL_int_sqrt_work_52 = + int_sqrt_fNext_51$EMPTY_N && int_sqrt_fNext_52$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_52 = CAN_FIRE_RL_int_sqrt_work_52 ; + + // rule RL_int_sqrt_work_51 + assign CAN_FIRE_RL_int_sqrt_work_51 = + int_sqrt_fNext_50$EMPTY_N && int_sqrt_fNext_51$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_51 = CAN_FIRE_RL_int_sqrt_work_51 ; + + // rule RL_int_sqrt_work_50 + assign CAN_FIRE_RL_int_sqrt_work_50 = + int_sqrt_fNext_49$EMPTY_N && int_sqrt_fNext_50$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_50 = CAN_FIRE_RL_int_sqrt_work_50 ; + + // rule RL_int_sqrt_work_49 + assign CAN_FIRE_RL_int_sqrt_work_49 = + int_sqrt_fNext_48$EMPTY_N && int_sqrt_fNext_49$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_49 = CAN_FIRE_RL_int_sqrt_work_49 ; + + // rule RL_int_sqrt_work_48 + assign CAN_FIRE_RL_int_sqrt_work_48 = + int_sqrt_fNext_47$EMPTY_N && int_sqrt_fNext_48$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_48 = CAN_FIRE_RL_int_sqrt_work_48 ; + + // rule RL_int_sqrt_work_47 + assign CAN_FIRE_RL_int_sqrt_work_47 = + int_sqrt_fNext_46$EMPTY_N && int_sqrt_fNext_47$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_47 = CAN_FIRE_RL_int_sqrt_work_47 ; + + // rule RL_int_sqrt_work_46 + assign CAN_FIRE_RL_int_sqrt_work_46 = + int_sqrt_fNext_45$EMPTY_N && int_sqrt_fNext_46$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_46 = CAN_FIRE_RL_int_sqrt_work_46 ; + + // rule RL_int_sqrt_work_45 + assign CAN_FIRE_RL_int_sqrt_work_45 = + int_sqrt_fNext_44$EMPTY_N && int_sqrt_fNext_45$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_45 = CAN_FIRE_RL_int_sqrt_work_45 ; + + // rule RL_int_sqrt_work_44 + assign CAN_FIRE_RL_int_sqrt_work_44 = + int_sqrt_fNext_43$EMPTY_N && int_sqrt_fNext_44$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_44 = CAN_FIRE_RL_int_sqrt_work_44 ; + + // rule RL_int_sqrt_work_43 + assign CAN_FIRE_RL_int_sqrt_work_43 = + int_sqrt_fNext_42$EMPTY_N && int_sqrt_fNext_43$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_43 = CAN_FIRE_RL_int_sqrt_work_43 ; + + // rule RL_int_sqrt_work_42 + assign CAN_FIRE_RL_int_sqrt_work_42 = + int_sqrt_fNext_41$EMPTY_N && int_sqrt_fNext_42$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_42 = CAN_FIRE_RL_int_sqrt_work_42 ; + + // rule RL_int_sqrt_work_41 + assign CAN_FIRE_RL_int_sqrt_work_41 = + int_sqrt_fNext_40$EMPTY_N && int_sqrt_fNext_41$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_41 = CAN_FIRE_RL_int_sqrt_work_41 ; + + // rule RL_int_sqrt_work_40 + assign CAN_FIRE_RL_int_sqrt_work_40 = + int_sqrt_fNext_39$EMPTY_N && int_sqrt_fNext_40$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_40 = CAN_FIRE_RL_int_sqrt_work_40 ; + + // rule RL_int_sqrt_work_39 + assign CAN_FIRE_RL_int_sqrt_work_39 = + int_sqrt_fNext_38$EMPTY_N && int_sqrt_fNext_39$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_39 = CAN_FIRE_RL_int_sqrt_work_39 ; + + // rule RL_int_sqrt_work_38 + assign CAN_FIRE_RL_int_sqrt_work_38 = + int_sqrt_fNext_37$EMPTY_N && int_sqrt_fNext_38$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_38 = CAN_FIRE_RL_int_sqrt_work_38 ; + + // rule RL_int_sqrt_work_37 + assign CAN_FIRE_RL_int_sqrt_work_37 = + int_sqrt_fNext_36$EMPTY_N && int_sqrt_fNext_37$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_37 = CAN_FIRE_RL_int_sqrt_work_37 ; + + // rule RL_int_sqrt_work_36 + assign CAN_FIRE_RL_int_sqrt_work_36 = + int_sqrt_fNext_35$EMPTY_N && int_sqrt_fNext_36$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_36 = CAN_FIRE_RL_int_sqrt_work_36 ; + + // rule RL_int_sqrt_work_35 + assign CAN_FIRE_RL_int_sqrt_work_35 = + int_sqrt_fNext_34$EMPTY_N && int_sqrt_fNext_35$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_35 = CAN_FIRE_RL_int_sqrt_work_35 ; + + // rule RL_int_sqrt_work_34 + assign CAN_FIRE_RL_int_sqrt_work_34 = + int_sqrt_fNext_33$EMPTY_N && int_sqrt_fNext_34$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_34 = CAN_FIRE_RL_int_sqrt_work_34 ; + + // rule RL_int_sqrt_work_33 + assign CAN_FIRE_RL_int_sqrt_work_33 = + int_sqrt_fNext_32$EMPTY_N && int_sqrt_fNext_33$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_33 = CAN_FIRE_RL_int_sqrt_work_33 ; + + // rule RL_int_sqrt_work_32 + assign CAN_FIRE_RL_int_sqrt_work_32 = + int_sqrt_fNext_31$EMPTY_N && int_sqrt_fNext_32$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_32 = CAN_FIRE_RL_int_sqrt_work_32 ; + + // rule RL_int_sqrt_work_31 + assign CAN_FIRE_RL_int_sqrt_work_31 = + int_sqrt_fNext_30$EMPTY_N && int_sqrt_fNext_31$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_31 = CAN_FIRE_RL_int_sqrt_work_31 ; + + // rule RL_int_sqrt_work_30 + assign CAN_FIRE_RL_int_sqrt_work_30 = + int_sqrt_fNext_29$EMPTY_N && int_sqrt_fNext_30$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_30 = CAN_FIRE_RL_int_sqrt_work_30 ; + + // rule RL_int_sqrt_work_29 + assign CAN_FIRE_RL_int_sqrt_work_29 = + int_sqrt_fNext_28$EMPTY_N && int_sqrt_fNext_29$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_29 = CAN_FIRE_RL_int_sqrt_work_29 ; + + // rule RL_int_sqrt_work_28 + assign CAN_FIRE_RL_int_sqrt_work_28 = + int_sqrt_fNext_27$EMPTY_N && int_sqrt_fNext_28$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_28 = CAN_FIRE_RL_int_sqrt_work_28 ; + + // rule RL_int_sqrt_work_27 + assign CAN_FIRE_RL_int_sqrt_work_27 = + int_sqrt_fNext_26$EMPTY_N && int_sqrt_fNext_27$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_27 = CAN_FIRE_RL_int_sqrt_work_27 ; + + // rule RL_int_sqrt_work_26 + assign CAN_FIRE_RL_int_sqrt_work_26 = + int_sqrt_fNext_25$EMPTY_N && int_sqrt_fNext_26$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_26 = CAN_FIRE_RL_int_sqrt_work_26 ; + + // rule RL_int_sqrt_work_25 + assign CAN_FIRE_RL_int_sqrt_work_25 = + int_sqrt_fNext_24$EMPTY_N && int_sqrt_fNext_25$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_25 = CAN_FIRE_RL_int_sqrt_work_25 ; + + // rule RL_int_sqrt_work_24 + assign CAN_FIRE_RL_int_sqrt_work_24 = + int_sqrt_fNext_23$EMPTY_N && int_sqrt_fNext_24$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_24 = CAN_FIRE_RL_int_sqrt_work_24 ; + + // rule RL_int_sqrt_work_23 + assign CAN_FIRE_RL_int_sqrt_work_23 = + int_sqrt_fNext_22$EMPTY_N && int_sqrt_fNext_23$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_23 = CAN_FIRE_RL_int_sqrt_work_23 ; + + // rule RL_int_sqrt_work_22 + assign CAN_FIRE_RL_int_sqrt_work_22 = + int_sqrt_fNext_21$EMPTY_N && int_sqrt_fNext_22$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_22 = CAN_FIRE_RL_int_sqrt_work_22 ; + + // rule RL_int_sqrt_work_21 + assign CAN_FIRE_RL_int_sqrt_work_21 = + int_sqrt_fNext_20$EMPTY_N && int_sqrt_fNext_21$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_21 = CAN_FIRE_RL_int_sqrt_work_21 ; + + // rule RL_int_sqrt_work_20 + assign CAN_FIRE_RL_int_sqrt_work_20 = + int_sqrt_fNext_19$EMPTY_N && int_sqrt_fNext_20$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_20 = CAN_FIRE_RL_int_sqrt_work_20 ; + + // rule RL_int_sqrt_work_19 + assign CAN_FIRE_RL_int_sqrt_work_19 = + int_sqrt_fNext_18$EMPTY_N && int_sqrt_fNext_19$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_19 = CAN_FIRE_RL_int_sqrt_work_19 ; + + // rule RL_int_sqrt_work_18 + assign CAN_FIRE_RL_int_sqrt_work_18 = + int_sqrt_fNext_17$EMPTY_N && int_sqrt_fNext_18$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_18 = CAN_FIRE_RL_int_sqrt_work_18 ; + + // rule RL_int_sqrt_work_17 + assign CAN_FIRE_RL_int_sqrt_work_17 = + int_sqrt_fNext_16$EMPTY_N && int_sqrt_fNext_17$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_17 = CAN_FIRE_RL_int_sqrt_work_17 ; + + // rule RL_int_sqrt_work_16 + assign CAN_FIRE_RL_int_sqrt_work_16 = + int_sqrt_fNext_15$EMPTY_N && int_sqrt_fNext_16$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_16 = CAN_FIRE_RL_int_sqrt_work_16 ; + + // rule RL_int_sqrt_work_15 + assign CAN_FIRE_RL_int_sqrt_work_15 = + int_sqrt_fNext_14$EMPTY_N && int_sqrt_fNext_15$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_15 = CAN_FIRE_RL_int_sqrt_work_15 ; + + // rule RL_int_sqrt_work_14 + assign CAN_FIRE_RL_int_sqrt_work_14 = + int_sqrt_fNext_13$EMPTY_N && int_sqrt_fNext_14$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_14 = CAN_FIRE_RL_int_sqrt_work_14 ; + + // rule RL_int_sqrt_work_13 + assign CAN_FIRE_RL_int_sqrt_work_13 = + int_sqrt_fNext_12$EMPTY_N && int_sqrt_fNext_13$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_13 = CAN_FIRE_RL_int_sqrt_work_13 ; + + // rule RL_int_sqrt_work_12 + assign CAN_FIRE_RL_int_sqrt_work_12 = + int_sqrt_fNext_11$EMPTY_N && int_sqrt_fNext_12$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_12 = CAN_FIRE_RL_int_sqrt_work_12 ; + + // rule RL_int_sqrt_work_11 + assign CAN_FIRE_RL_int_sqrt_work_11 = + int_sqrt_fNext_10$EMPTY_N && int_sqrt_fNext_11$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_11 = CAN_FIRE_RL_int_sqrt_work_11 ; + + // rule RL_int_sqrt_work_10 + assign CAN_FIRE_RL_int_sqrt_work_10 = + int_sqrt_fNext_9$EMPTY_N && int_sqrt_fNext_10$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_10 = CAN_FIRE_RL_int_sqrt_work_10 ; + + // rule RL_int_sqrt_work_9 + assign CAN_FIRE_RL_int_sqrt_work_9 = + int_sqrt_fNext_8$EMPTY_N && int_sqrt_fNext_9$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_9 = CAN_FIRE_RL_int_sqrt_work_9 ; + + // rule RL_int_sqrt_work_8 + assign CAN_FIRE_RL_int_sqrt_work_8 = + int_sqrt_fNext_7$EMPTY_N && int_sqrt_fNext_8$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_8 = CAN_FIRE_RL_int_sqrt_work_8 ; + + // rule RL_int_sqrt_work_7 + assign CAN_FIRE_RL_int_sqrt_work_7 = + int_sqrt_fNext_6$EMPTY_N && int_sqrt_fNext_7$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_7 = CAN_FIRE_RL_int_sqrt_work_7 ; + + // rule RL_int_sqrt_work_6 + assign CAN_FIRE_RL_int_sqrt_work_6 = + int_sqrt_fNext_5$EMPTY_N && int_sqrt_fNext_6$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_6 = CAN_FIRE_RL_int_sqrt_work_6 ; + + // rule RL_int_sqrt_work_5 + assign CAN_FIRE_RL_int_sqrt_work_5 = + int_sqrt_fNext_4$EMPTY_N && int_sqrt_fNext_5$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_5 = CAN_FIRE_RL_int_sqrt_work_5 ; + + // rule RL_int_sqrt_work_4 + assign CAN_FIRE_RL_int_sqrt_work_4 = + int_sqrt_fNext_3$EMPTY_N && int_sqrt_fNext_4$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_4 = CAN_FIRE_RL_int_sqrt_work_4 ; + + // rule RL_int_sqrt_work_3 + assign CAN_FIRE_RL_int_sqrt_work_3 = + int_sqrt_fNext_2$EMPTY_N && int_sqrt_fNext_3$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_3 = CAN_FIRE_RL_int_sqrt_work_3 ; + + // rule RL_int_sqrt_work_2 + assign CAN_FIRE_RL_int_sqrt_work_2 = + int_sqrt_fNext_1$EMPTY_N && int_sqrt_fNext_2$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_2 = CAN_FIRE_RL_int_sqrt_work_2 ; + + // rule RL_int_sqrt_work_1 + assign CAN_FIRE_RL_int_sqrt_work_1 = + int_sqrt_fNext_0$EMPTY_N && int_sqrt_fNext_1$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_1 = CAN_FIRE_RL_int_sqrt_work_1 ; + + // rule RL_int_sqrt_work + assign CAN_FIRE_RL_int_sqrt_work = + int_sqrt_fFirst$EMPTY_N && int_sqrt_fNext_0$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work = CAN_FIRE_RL_int_sqrt_work ; + + // rule RL_int_sqrt_start + assign CAN_FIRE_RL_int_sqrt_start = + int_sqrt_fRequest$EMPTY_N && int_sqrt_fFirst$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_start = CAN_FIRE_RL_int_sqrt_start ; + + // rule RL_fpu_s2_stage + assign CAN_FIRE_RL_fpu_s2_stage = + fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && + (fpu_fState_S1$D_OUT[194] || int_sqrt_fRequest$FULL_N) ; + assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; + + // rule RL_fpu_s1_stage + assign CAN_FIRE_RL_fpu_s1_stage = + fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; + assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; + + // submodule fpu_fOperand_S0 + assign fpu_fOperand_S0$D_IN = request_put ; + assign fpu_fOperand_S0$ENQ = EN_request_put ; + assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fOperand_S0$CLR = 1'b0 ; + + // submodule fpu_fResult_S5 + assign fpu_fResult_S5$D_IN = + fpu_fState_S4$D_OUT[138] ? + fpu_fState_S4$D_OUT[137:69] : + { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[65:2] : + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15, + fpu_fState_S4$D_OUT[73:69] | + { 2'd0, + _theResult___fst_exp__h76509 == 11'd2047 && + _theResult___fst_sfd__h76510 == 52'd0, + 1'd0, + fpu_fState_S4$D_OUT[64:54] != 11'd2047 && + fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; + assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fResult_S5$DEQ = EN_response_get ; + assign fpu_fResult_S5$CLR = 1'b0 ; + + // submodule fpu_fState_S1 + assign fpu_fState_S1$D_IN = + (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54]) ? + { 1'd1, + fpu_fOperand_S0$D_OUT[66:55], + sfd__h49989, + 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 ; + assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S1$CLR = 1'b0 ; + + // submodule fpu_fState_S2 + assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[194:58] ; + assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S2$CLR = 1'b0 ; + + // submodule fpu_fState_S3 + assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT, x__h66665 } ; + assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S3$CLR = 1'b0 ; + + // submodule fpu_fState_S4 + assign fpu_fState_S4$D_IN = + { fpu_fState_S3$D_OUT[195:131], + fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[130], + fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[129], + IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813, + fpu_fState_S3$D_OUT[125:122], + fpu_fState_S3$D_OUT[195] ? + fpu_fState_S3$D_OUT[121:59] : + IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820, + x__h75654 } ; + assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S4$CLR = 1'b0 ; + + // submodule int_sqrt_fFirst + assign int_sqrt_fFirst$D_IN = + { 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + int_sqrt_fRequest$D_OUT, + 116'd0, + x__h402 } ; + assign int_sqrt_fFirst$ENQ = CAN_FIRE_RL_int_sqrt_start ; + assign int_sqrt_fFirst$DEQ = CAN_FIRE_RL_int_sqrt_work ; + assign int_sqrt_fFirst$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_0 + assign int_sqrt_fNext_0$D_IN = + { int_sqrt_fFirst$D_OUT[464] || + int_sqrt_fFirst$D_OUT[115:0] == 116'd0, + int_sqrt_fFirst$D_OUT[464] ? + int_sqrt_fFirst$D_OUT[463:348] : + ((int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? + int_sqrt_fFirst$D_OUT[231:116] : + int_sqrt_fFirst$D_OUT[463:348]), + int_sqrt_fFirst$D_OUT[464] ? + int_sqrt_fFirst$D_OUT[347:0] : + { _theResult___snd_fst__h25299, + (int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? + int_sqrt_fFirst$D_OUT[231:0] : + { _theResult___snd_snd__h25377, b__h25374 } } } ; + assign int_sqrt_fNext_0$ENQ = CAN_FIRE_RL_int_sqrt_work ; + assign int_sqrt_fNext_0$DEQ = CAN_FIRE_RL_int_sqrt_work_1 ; + assign int_sqrt_fNext_0$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_1 + assign int_sqrt_fNext_1$D_IN = + { int_sqrt_fNext_0$D_OUT[464] || + int_sqrt_fNext_0$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_0$D_OUT[464] ? + int_sqrt_fNext_0$D_OUT[463:348] : + ((int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_0$D_OUT[231:116] : + int_sqrt_fNext_0$D_OUT[463:348]), + int_sqrt_fNext_0$D_OUT[464] ? + int_sqrt_fNext_0$D_OUT[347:0] : + { _theResult___snd_fst__h25701, + (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_0$D_OUT[231:0] : + { _theResult___snd_snd__h25777, b__h25774 } } } ; + assign int_sqrt_fNext_1$ENQ = CAN_FIRE_RL_int_sqrt_work_1 ; + assign int_sqrt_fNext_1$DEQ = CAN_FIRE_RL_int_sqrt_work_2 ; + assign int_sqrt_fNext_1$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_10 + assign int_sqrt_fNext_10$D_IN = + { int_sqrt_fNext_9$D_OUT[464] || + int_sqrt_fNext_9$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_9$D_OUT[464] ? + int_sqrt_fNext_9$D_OUT[463:348] : + ((int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_9$D_OUT[231:116] : + int_sqrt_fNext_9$D_OUT[463:348]), + int_sqrt_fNext_9$D_OUT[464] ? + int_sqrt_fNext_9$D_OUT[347:0] : + { _theResult___snd_fst__h29301, + (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_9$D_OUT[231:0] : + { _theResult___snd_snd__h29377, b__h29374 } } } ; + assign int_sqrt_fNext_10$ENQ = CAN_FIRE_RL_int_sqrt_work_10 ; + assign int_sqrt_fNext_10$DEQ = CAN_FIRE_RL_int_sqrt_work_11 ; + assign int_sqrt_fNext_10$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_11 + assign int_sqrt_fNext_11$D_IN = + { int_sqrt_fNext_10$D_OUT[464] || + int_sqrt_fNext_10$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_10$D_OUT[464] ? + int_sqrt_fNext_10$D_OUT[463:348] : + ((int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_10$D_OUT[231:116] : + int_sqrt_fNext_10$D_OUT[463:348]), + int_sqrt_fNext_10$D_OUT[464] ? + int_sqrt_fNext_10$D_OUT[347:0] : + { _theResult___snd_fst__h29701, + (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_10$D_OUT[231:0] : + { _theResult___snd_snd__h29777, b__h29774 } } } ; + assign int_sqrt_fNext_11$ENQ = CAN_FIRE_RL_int_sqrt_work_11 ; + assign int_sqrt_fNext_11$DEQ = CAN_FIRE_RL_int_sqrt_work_12 ; + assign int_sqrt_fNext_11$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_12 + assign int_sqrt_fNext_12$D_IN = + { int_sqrt_fNext_11$D_OUT[464] || + int_sqrt_fNext_11$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_11$D_OUT[464] ? + int_sqrt_fNext_11$D_OUT[463:348] : + ((int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_11$D_OUT[231:116] : + int_sqrt_fNext_11$D_OUT[463:348]), + int_sqrt_fNext_11$D_OUT[464] ? + int_sqrt_fNext_11$D_OUT[347:0] : + { _theResult___snd_fst__h30101, + (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_11$D_OUT[231:0] : + { _theResult___snd_snd__h30177, b__h30174 } } } ; + assign int_sqrt_fNext_12$ENQ = CAN_FIRE_RL_int_sqrt_work_12 ; + assign int_sqrt_fNext_12$DEQ = CAN_FIRE_RL_int_sqrt_work_13 ; + assign int_sqrt_fNext_12$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_13 + assign int_sqrt_fNext_13$D_IN = + { int_sqrt_fNext_12$D_OUT[464] || + int_sqrt_fNext_12$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_12$D_OUT[464] ? + int_sqrt_fNext_12$D_OUT[463:348] : + ((int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_12$D_OUT[231:116] : + int_sqrt_fNext_12$D_OUT[463:348]), + int_sqrt_fNext_12$D_OUT[464] ? + int_sqrt_fNext_12$D_OUT[347:0] : + { _theResult___snd_fst__h30501, + (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_12$D_OUT[231:0] : + { _theResult___snd_snd__h30577, b__h30574 } } } ; + assign int_sqrt_fNext_13$ENQ = CAN_FIRE_RL_int_sqrt_work_13 ; + assign int_sqrt_fNext_13$DEQ = CAN_FIRE_RL_int_sqrt_work_14 ; + assign int_sqrt_fNext_13$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_14 + assign int_sqrt_fNext_14$D_IN = + { int_sqrt_fNext_13$D_OUT[464] || + int_sqrt_fNext_13$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_13$D_OUT[464] ? + int_sqrt_fNext_13$D_OUT[463:348] : + ((int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_13$D_OUT[231:116] : + int_sqrt_fNext_13$D_OUT[463:348]), + int_sqrt_fNext_13$D_OUT[464] ? + int_sqrt_fNext_13$D_OUT[347:0] : + { _theResult___snd_fst__h30901, + (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_13$D_OUT[231:0] : + { _theResult___snd_snd__h30977, b__h30974 } } } ; + assign int_sqrt_fNext_14$ENQ = CAN_FIRE_RL_int_sqrt_work_14 ; + assign int_sqrt_fNext_14$DEQ = CAN_FIRE_RL_int_sqrt_work_15 ; + assign int_sqrt_fNext_14$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_15 + assign int_sqrt_fNext_15$D_IN = + { int_sqrt_fNext_14$D_OUT[464] || + int_sqrt_fNext_14$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_14$D_OUT[464] ? + int_sqrt_fNext_14$D_OUT[463:348] : + ((int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_14$D_OUT[231:116] : + int_sqrt_fNext_14$D_OUT[463:348]), + int_sqrt_fNext_14$D_OUT[464] ? + int_sqrt_fNext_14$D_OUT[347:0] : + { _theResult___snd_fst__h31301, + (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_14$D_OUT[231:0] : + { _theResult___snd_snd__h31377, b__h31374 } } } ; + assign int_sqrt_fNext_15$ENQ = CAN_FIRE_RL_int_sqrt_work_15 ; + assign int_sqrt_fNext_15$DEQ = CAN_FIRE_RL_int_sqrt_work_16 ; + assign int_sqrt_fNext_15$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_16 + assign int_sqrt_fNext_16$D_IN = + { int_sqrt_fNext_15$D_OUT[464] || + int_sqrt_fNext_15$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_15$D_OUT[464] ? + int_sqrt_fNext_15$D_OUT[463:348] : + ((int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_15$D_OUT[231:116] : + int_sqrt_fNext_15$D_OUT[463:348]), + int_sqrt_fNext_15$D_OUT[464] ? + int_sqrt_fNext_15$D_OUT[347:0] : + { _theResult___snd_fst__h31701, + (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_15$D_OUT[231:0] : + { _theResult___snd_snd__h31777, b__h31774 } } } ; + assign int_sqrt_fNext_16$ENQ = CAN_FIRE_RL_int_sqrt_work_16 ; + assign int_sqrt_fNext_16$DEQ = CAN_FIRE_RL_int_sqrt_work_17 ; + assign int_sqrt_fNext_16$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_17 + assign int_sqrt_fNext_17$D_IN = + { int_sqrt_fNext_16$D_OUT[464] || + int_sqrt_fNext_16$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_16$D_OUT[464] ? + int_sqrt_fNext_16$D_OUT[463:348] : + ((int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_16$D_OUT[231:116] : + int_sqrt_fNext_16$D_OUT[463:348]), + int_sqrt_fNext_16$D_OUT[464] ? + int_sqrt_fNext_16$D_OUT[347:0] : + { _theResult___snd_fst__h32101, + (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_16$D_OUT[231:0] : + { _theResult___snd_snd__h32177, b__h32174 } } } ; + assign int_sqrt_fNext_17$ENQ = CAN_FIRE_RL_int_sqrt_work_17 ; + assign int_sqrt_fNext_17$DEQ = CAN_FIRE_RL_int_sqrt_work_18 ; + assign int_sqrt_fNext_17$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_18 + assign int_sqrt_fNext_18$D_IN = + { int_sqrt_fNext_17$D_OUT[464] || + int_sqrt_fNext_17$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_17$D_OUT[464] ? + int_sqrt_fNext_17$D_OUT[463:348] : + ((int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_17$D_OUT[231:116] : + int_sqrt_fNext_17$D_OUT[463:348]), + int_sqrt_fNext_17$D_OUT[464] ? + int_sqrt_fNext_17$D_OUT[347:0] : + { _theResult___snd_fst__h32501, + (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_17$D_OUT[231:0] : + { _theResult___snd_snd__h32577, b__h32574 } } } ; + assign int_sqrt_fNext_18$ENQ = CAN_FIRE_RL_int_sqrt_work_18 ; + assign int_sqrt_fNext_18$DEQ = CAN_FIRE_RL_int_sqrt_work_19 ; + assign int_sqrt_fNext_18$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_19 + assign int_sqrt_fNext_19$D_IN = + { int_sqrt_fNext_18$D_OUT[464] || + int_sqrt_fNext_18$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_18$D_OUT[464] ? + int_sqrt_fNext_18$D_OUT[463:348] : + ((int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_18$D_OUT[231:116] : + int_sqrt_fNext_18$D_OUT[463:348]), + int_sqrt_fNext_18$D_OUT[464] ? + int_sqrt_fNext_18$D_OUT[347:0] : + { _theResult___snd_fst__h32901, + (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_18$D_OUT[231:0] : + { _theResult___snd_snd__h32977, b__h32974 } } } ; + assign int_sqrt_fNext_19$ENQ = CAN_FIRE_RL_int_sqrt_work_19 ; + assign int_sqrt_fNext_19$DEQ = CAN_FIRE_RL_int_sqrt_work_20 ; + assign int_sqrt_fNext_19$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_2 + assign int_sqrt_fNext_2$D_IN = + { int_sqrt_fNext_1$D_OUT[464] || + int_sqrt_fNext_1$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_1$D_OUT[464] ? + int_sqrt_fNext_1$D_OUT[463:348] : + ((int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_1$D_OUT[231:116] : + int_sqrt_fNext_1$D_OUT[463:348]), + int_sqrt_fNext_1$D_OUT[464] ? + int_sqrt_fNext_1$D_OUT[347:0] : + { _theResult___snd_fst__h26101, + (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_1$D_OUT[231:0] : + { _theResult___snd_snd__h26177, b__h26174 } } } ; + assign int_sqrt_fNext_2$ENQ = CAN_FIRE_RL_int_sqrt_work_2 ; + assign int_sqrt_fNext_2$DEQ = CAN_FIRE_RL_int_sqrt_work_3 ; + assign int_sqrt_fNext_2$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_20 + assign int_sqrt_fNext_20$D_IN = + { int_sqrt_fNext_19$D_OUT[464] || + int_sqrt_fNext_19$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_19$D_OUT[464] ? + int_sqrt_fNext_19$D_OUT[463:348] : + ((int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_19$D_OUT[231:116] : + int_sqrt_fNext_19$D_OUT[463:348]), + int_sqrt_fNext_19$D_OUT[464] ? + int_sqrt_fNext_19$D_OUT[347:0] : + { _theResult___snd_fst__h33301, + (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_19$D_OUT[231:0] : + { _theResult___snd_snd__h33377, b__h33374 } } } ; + assign int_sqrt_fNext_20$ENQ = CAN_FIRE_RL_int_sqrt_work_20 ; + assign int_sqrt_fNext_20$DEQ = CAN_FIRE_RL_int_sqrt_work_21 ; + assign int_sqrt_fNext_20$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_21 + assign int_sqrt_fNext_21$D_IN = + { int_sqrt_fNext_20$D_OUT[464] || + int_sqrt_fNext_20$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_20$D_OUT[464] ? + int_sqrt_fNext_20$D_OUT[463:348] : + ((int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_20$D_OUT[231:116] : + int_sqrt_fNext_20$D_OUT[463:348]), + int_sqrt_fNext_20$D_OUT[464] ? + int_sqrt_fNext_20$D_OUT[347:0] : + { _theResult___snd_fst__h33701, + (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_20$D_OUT[231:0] : + { _theResult___snd_snd__h33777, b__h33774 } } } ; + assign int_sqrt_fNext_21$ENQ = CAN_FIRE_RL_int_sqrt_work_21 ; + assign int_sqrt_fNext_21$DEQ = CAN_FIRE_RL_int_sqrt_work_22 ; + assign int_sqrt_fNext_21$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_22 + assign int_sqrt_fNext_22$D_IN = + { int_sqrt_fNext_21$D_OUT[464] || + int_sqrt_fNext_21$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_21$D_OUT[464] ? + int_sqrt_fNext_21$D_OUT[463:348] : + ((int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_21$D_OUT[231:116] : + int_sqrt_fNext_21$D_OUT[463:348]), + int_sqrt_fNext_21$D_OUT[464] ? + int_sqrt_fNext_21$D_OUT[347:0] : + { _theResult___snd_fst__h34101, + (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_21$D_OUT[231:0] : + { _theResult___snd_snd__h34177, b__h34174 } } } ; + assign int_sqrt_fNext_22$ENQ = CAN_FIRE_RL_int_sqrt_work_22 ; + assign int_sqrt_fNext_22$DEQ = CAN_FIRE_RL_int_sqrt_work_23 ; + assign int_sqrt_fNext_22$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_23 + assign int_sqrt_fNext_23$D_IN = + { int_sqrt_fNext_22$D_OUT[464] || + int_sqrt_fNext_22$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_22$D_OUT[464] ? + int_sqrt_fNext_22$D_OUT[463:348] : + ((int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_22$D_OUT[231:116] : + int_sqrt_fNext_22$D_OUT[463:348]), + int_sqrt_fNext_22$D_OUT[464] ? + int_sqrt_fNext_22$D_OUT[347:0] : + { _theResult___snd_fst__h34501, + (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_22$D_OUT[231:0] : + { _theResult___snd_snd__h34577, b__h34574 } } } ; + assign int_sqrt_fNext_23$ENQ = CAN_FIRE_RL_int_sqrt_work_23 ; + assign int_sqrt_fNext_23$DEQ = CAN_FIRE_RL_int_sqrt_work_24 ; + assign int_sqrt_fNext_23$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_24 + assign int_sqrt_fNext_24$D_IN = + { int_sqrt_fNext_23$D_OUT[464] || + int_sqrt_fNext_23$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_23$D_OUT[464] ? + int_sqrt_fNext_23$D_OUT[463:348] : + ((int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_23$D_OUT[231:116] : + int_sqrt_fNext_23$D_OUT[463:348]), + int_sqrt_fNext_23$D_OUT[464] ? + int_sqrt_fNext_23$D_OUT[347:0] : + { _theResult___snd_fst__h34901, + (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_23$D_OUT[231:0] : + { _theResult___snd_snd__h34977, b__h34974 } } } ; + assign int_sqrt_fNext_24$ENQ = CAN_FIRE_RL_int_sqrt_work_24 ; + assign int_sqrt_fNext_24$DEQ = CAN_FIRE_RL_int_sqrt_work_25 ; + assign int_sqrt_fNext_24$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_25 + assign int_sqrt_fNext_25$D_IN = + { int_sqrt_fNext_24$D_OUT[464] || + int_sqrt_fNext_24$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_24$D_OUT[464] ? + int_sqrt_fNext_24$D_OUT[463:348] : + ((int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_24$D_OUT[231:116] : + int_sqrt_fNext_24$D_OUT[463:348]), + int_sqrt_fNext_24$D_OUT[464] ? + int_sqrt_fNext_24$D_OUT[347:0] : + { _theResult___snd_fst__h35301, + (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_24$D_OUT[231:0] : + { _theResult___snd_snd__h35377, b__h35374 } } } ; + assign int_sqrt_fNext_25$ENQ = CAN_FIRE_RL_int_sqrt_work_25 ; + assign int_sqrt_fNext_25$DEQ = CAN_FIRE_RL_int_sqrt_work_26 ; + assign int_sqrt_fNext_25$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_26 + assign int_sqrt_fNext_26$D_IN = + { int_sqrt_fNext_25$D_OUT[464] || + int_sqrt_fNext_25$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_25$D_OUT[464] ? + int_sqrt_fNext_25$D_OUT[463:348] : + ((int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_25$D_OUT[231:116] : + int_sqrt_fNext_25$D_OUT[463:348]), + int_sqrt_fNext_25$D_OUT[464] ? + int_sqrt_fNext_25$D_OUT[347:0] : + { _theResult___snd_fst__h35701, + (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_25$D_OUT[231:0] : + { _theResult___snd_snd__h35777, b__h35774 } } } ; + assign int_sqrt_fNext_26$ENQ = CAN_FIRE_RL_int_sqrt_work_26 ; + assign int_sqrt_fNext_26$DEQ = CAN_FIRE_RL_int_sqrt_work_27 ; + assign int_sqrt_fNext_26$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_27 + assign int_sqrt_fNext_27$D_IN = + { int_sqrt_fNext_26$D_OUT[464] || + int_sqrt_fNext_26$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_26$D_OUT[464] ? + int_sqrt_fNext_26$D_OUT[463:348] : + ((int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_26$D_OUT[231:116] : + int_sqrt_fNext_26$D_OUT[463:348]), + int_sqrt_fNext_26$D_OUT[464] ? + int_sqrt_fNext_26$D_OUT[347:0] : + { _theResult___snd_fst__h36101, + (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_26$D_OUT[231:0] : + { _theResult___snd_snd__h36177, b__h36174 } } } ; + assign int_sqrt_fNext_27$ENQ = CAN_FIRE_RL_int_sqrt_work_27 ; + assign int_sqrt_fNext_27$DEQ = CAN_FIRE_RL_int_sqrt_work_28 ; + assign int_sqrt_fNext_27$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_28 + assign int_sqrt_fNext_28$D_IN = + { int_sqrt_fNext_27$D_OUT[464] || + int_sqrt_fNext_27$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_27$D_OUT[464] ? + int_sqrt_fNext_27$D_OUT[463:348] : + ((int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_27$D_OUT[231:116] : + int_sqrt_fNext_27$D_OUT[463:348]), + int_sqrt_fNext_27$D_OUT[464] ? + int_sqrt_fNext_27$D_OUT[347:0] : + { _theResult___snd_fst__h36501, + (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_27$D_OUT[231:0] : + { _theResult___snd_snd__h36577, b__h36574 } } } ; + assign int_sqrt_fNext_28$ENQ = CAN_FIRE_RL_int_sqrt_work_28 ; + assign int_sqrt_fNext_28$DEQ = CAN_FIRE_RL_int_sqrt_work_29 ; + assign int_sqrt_fNext_28$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_29 + assign int_sqrt_fNext_29$D_IN = + { int_sqrt_fNext_28$D_OUT[464] || + int_sqrt_fNext_28$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_28$D_OUT[464] ? + int_sqrt_fNext_28$D_OUT[463:348] : + ((int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_28$D_OUT[231:116] : + int_sqrt_fNext_28$D_OUT[463:348]), + int_sqrt_fNext_28$D_OUT[464] ? + int_sqrt_fNext_28$D_OUT[347:0] : + { _theResult___snd_fst__h36901, + (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_28$D_OUT[231:0] : + { _theResult___snd_snd__h36977, b__h36974 } } } ; + assign int_sqrt_fNext_29$ENQ = CAN_FIRE_RL_int_sqrt_work_29 ; + assign int_sqrt_fNext_29$DEQ = CAN_FIRE_RL_int_sqrt_work_30 ; + assign int_sqrt_fNext_29$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_3 + assign int_sqrt_fNext_3$D_IN = + { int_sqrt_fNext_2$D_OUT[464] || + int_sqrt_fNext_2$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_2$D_OUT[464] ? + int_sqrt_fNext_2$D_OUT[463:348] : + ((int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_2$D_OUT[231:116] : + int_sqrt_fNext_2$D_OUT[463:348]), + int_sqrt_fNext_2$D_OUT[464] ? + int_sqrt_fNext_2$D_OUT[347:0] : + { _theResult___snd_fst__h26501, + (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_2$D_OUT[231:0] : + { _theResult___snd_snd__h26577, b__h26574 } } } ; + assign int_sqrt_fNext_3$ENQ = CAN_FIRE_RL_int_sqrt_work_3 ; + assign int_sqrt_fNext_3$DEQ = CAN_FIRE_RL_int_sqrt_work_4 ; + assign int_sqrt_fNext_3$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_30 + assign int_sqrt_fNext_30$D_IN = + { int_sqrt_fNext_29$D_OUT[464] || + int_sqrt_fNext_29$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_29$D_OUT[464] ? + int_sqrt_fNext_29$D_OUT[463:348] : + ((int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_29$D_OUT[231:116] : + int_sqrt_fNext_29$D_OUT[463:348]), + int_sqrt_fNext_29$D_OUT[464] ? + int_sqrt_fNext_29$D_OUT[347:0] : + { _theResult___snd_fst__h37301, + (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_29$D_OUT[231:0] : + { _theResult___snd_snd__h37377, b__h37374 } } } ; + assign int_sqrt_fNext_30$ENQ = CAN_FIRE_RL_int_sqrt_work_30 ; + assign int_sqrt_fNext_30$DEQ = CAN_FIRE_RL_int_sqrt_work_31 ; + assign int_sqrt_fNext_30$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_31 + assign int_sqrt_fNext_31$D_IN = + { int_sqrt_fNext_30$D_OUT[464] || + int_sqrt_fNext_30$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_30$D_OUT[464] ? + int_sqrt_fNext_30$D_OUT[463:348] : + ((int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_30$D_OUT[231:116] : + int_sqrt_fNext_30$D_OUT[463:348]), + int_sqrt_fNext_30$D_OUT[464] ? + int_sqrt_fNext_30$D_OUT[347:0] : + { _theResult___snd_fst__h37701, + (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_30$D_OUT[231:0] : + { _theResult___snd_snd__h37777, b__h37774 } } } ; + assign int_sqrt_fNext_31$ENQ = CAN_FIRE_RL_int_sqrt_work_31 ; + assign int_sqrt_fNext_31$DEQ = CAN_FIRE_RL_int_sqrt_work_32 ; + assign int_sqrt_fNext_31$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_32 + assign int_sqrt_fNext_32$D_IN = + { int_sqrt_fNext_31$D_OUT[464] || + int_sqrt_fNext_31$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_31$D_OUT[464] ? + int_sqrt_fNext_31$D_OUT[463:348] : + ((int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_31$D_OUT[231:116] : + int_sqrt_fNext_31$D_OUT[463:348]), + int_sqrt_fNext_31$D_OUT[464] ? + int_sqrt_fNext_31$D_OUT[347:0] : + { _theResult___snd_fst__h38101, + (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_31$D_OUT[231:0] : + { _theResult___snd_snd__h38177, b__h38174 } } } ; + assign int_sqrt_fNext_32$ENQ = CAN_FIRE_RL_int_sqrt_work_32 ; + assign int_sqrt_fNext_32$DEQ = CAN_FIRE_RL_int_sqrt_work_33 ; + assign int_sqrt_fNext_32$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_33 + assign int_sqrt_fNext_33$D_IN = + { int_sqrt_fNext_32$D_OUT[464] || + int_sqrt_fNext_32$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_32$D_OUT[464] ? + int_sqrt_fNext_32$D_OUT[463:348] : + ((int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_32$D_OUT[231:116] : + int_sqrt_fNext_32$D_OUT[463:348]), + int_sqrt_fNext_32$D_OUT[464] ? + int_sqrt_fNext_32$D_OUT[347:0] : + { _theResult___snd_fst__h38501, + (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_32$D_OUT[231:0] : + { _theResult___snd_snd__h38577, b__h38574 } } } ; + assign int_sqrt_fNext_33$ENQ = CAN_FIRE_RL_int_sqrt_work_33 ; + assign int_sqrt_fNext_33$DEQ = CAN_FIRE_RL_int_sqrt_work_34 ; + assign int_sqrt_fNext_33$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_34 + assign int_sqrt_fNext_34$D_IN = + { int_sqrt_fNext_33$D_OUT[464] || + int_sqrt_fNext_33$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_33$D_OUT[464] ? + int_sqrt_fNext_33$D_OUT[463:348] : + ((int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_33$D_OUT[231:116] : + int_sqrt_fNext_33$D_OUT[463:348]), + int_sqrt_fNext_33$D_OUT[464] ? + int_sqrt_fNext_33$D_OUT[347:0] : + { _theResult___snd_fst__h38901, + (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_33$D_OUT[231:0] : + { _theResult___snd_snd__h38977, b__h38974 } } } ; + assign int_sqrt_fNext_34$ENQ = CAN_FIRE_RL_int_sqrt_work_34 ; + assign int_sqrt_fNext_34$DEQ = CAN_FIRE_RL_int_sqrt_work_35 ; + assign int_sqrt_fNext_34$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_35 + assign int_sqrt_fNext_35$D_IN = + { int_sqrt_fNext_34$D_OUT[464] || + int_sqrt_fNext_34$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_34$D_OUT[464] ? + int_sqrt_fNext_34$D_OUT[463:348] : + ((int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_34$D_OUT[231:116] : + int_sqrt_fNext_34$D_OUT[463:348]), + int_sqrt_fNext_34$D_OUT[464] ? + int_sqrt_fNext_34$D_OUT[347:0] : + { _theResult___snd_fst__h39301, + (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_34$D_OUT[231:0] : + { _theResult___snd_snd__h39377, b__h39374 } } } ; + assign int_sqrt_fNext_35$ENQ = CAN_FIRE_RL_int_sqrt_work_35 ; + assign int_sqrt_fNext_35$DEQ = CAN_FIRE_RL_int_sqrt_work_36 ; + assign int_sqrt_fNext_35$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_36 + assign int_sqrt_fNext_36$D_IN = + { int_sqrt_fNext_35$D_OUT[464] || + int_sqrt_fNext_35$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_35$D_OUT[464] ? + int_sqrt_fNext_35$D_OUT[463:348] : + ((int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_35$D_OUT[231:116] : + int_sqrt_fNext_35$D_OUT[463:348]), + int_sqrt_fNext_35$D_OUT[464] ? + int_sqrt_fNext_35$D_OUT[347:0] : + { _theResult___snd_fst__h39701, + (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_35$D_OUT[231:0] : + { _theResult___snd_snd__h39777, b__h39774 } } } ; + assign int_sqrt_fNext_36$ENQ = CAN_FIRE_RL_int_sqrt_work_36 ; + assign int_sqrt_fNext_36$DEQ = CAN_FIRE_RL_int_sqrt_work_37 ; + assign int_sqrt_fNext_36$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_37 + assign int_sqrt_fNext_37$D_IN = + { int_sqrt_fNext_36$D_OUT[464] || + int_sqrt_fNext_36$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_36$D_OUT[464] ? + int_sqrt_fNext_36$D_OUT[463:348] : + ((int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_36$D_OUT[231:116] : + int_sqrt_fNext_36$D_OUT[463:348]), + int_sqrt_fNext_36$D_OUT[464] ? + int_sqrt_fNext_36$D_OUT[347:0] : + { _theResult___snd_fst__h40101, + (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_36$D_OUT[231:0] : + { _theResult___snd_snd__h40177, b__h40174 } } } ; + assign int_sqrt_fNext_37$ENQ = CAN_FIRE_RL_int_sqrt_work_37 ; + assign int_sqrt_fNext_37$DEQ = CAN_FIRE_RL_int_sqrt_work_38 ; + assign int_sqrt_fNext_37$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_38 + assign int_sqrt_fNext_38$D_IN = + { int_sqrt_fNext_37$D_OUT[464] || + int_sqrt_fNext_37$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_37$D_OUT[464] ? + int_sqrt_fNext_37$D_OUT[463:348] : + ((int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_37$D_OUT[231:116] : + int_sqrt_fNext_37$D_OUT[463:348]), + int_sqrt_fNext_37$D_OUT[464] ? + int_sqrt_fNext_37$D_OUT[347:0] : + { _theResult___snd_fst__h40501, + (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_37$D_OUT[231:0] : + { _theResult___snd_snd__h40577, b__h40574 } } } ; + assign int_sqrt_fNext_38$ENQ = CAN_FIRE_RL_int_sqrt_work_38 ; + assign int_sqrt_fNext_38$DEQ = CAN_FIRE_RL_int_sqrt_work_39 ; + assign int_sqrt_fNext_38$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_39 + assign int_sqrt_fNext_39$D_IN = + { int_sqrt_fNext_38$D_OUT[464] || + int_sqrt_fNext_38$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_38$D_OUT[464] ? + int_sqrt_fNext_38$D_OUT[463:348] : + ((int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_38$D_OUT[231:116] : + int_sqrt_fNext_38$D_OUT[463:348]), + int_sqrt_fNext_38$D_OUT[464] ? + int_sqrt_fNext_38$D_OUT[347:0] : + { _theResult___snd_fst__h40901, + (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_38$D_OUT[231:0] : + { _theResult___snd_snd__h40977, b__h40974 } } } ; + assign int_sqrt_fNext_39$ENQ = CAN_FIRE_RL_int_sqrt_work_39 ; + assign int_sqrt_fNext_39$DEQ = CAN_FIRE_RL_int_sqrt_work_40 ; + assign int_sqrt_fNext_39$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_4 + assign int_sqrt_fNext_4$D_IN = + { int_sqrt_fNext_3$D_OUT[464] || + int_sqrt_fNext_3$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_3$D_OUT[464] ? + int_sqrt_fNext_3$D_OUT[463:348] : + ((int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_3$D_OUT[231:116] : + int_sqrt_fNext_3$D_OUT[463:348]), + int_sqrt_fNext_3$D_OUT[464] ? + int_sqrt_fNext_3$D_OUT[347:0] : + { _theResult___snd_fst__h26901, + (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_3$D_OUT[231:0] : + { _theResult___snd_snd__h26977, b__h26974 } } } ; + assign int_sqrt_fNext_4$ENQ = CAN_FIRE_RL_int_sqrt_work_4 ; + assign int_sqrt_fNext_4$DEQ = CAN_FIRE_RL_int_sqrt_work_5 ; + assign int_sqrt_fNext_4$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_40 + assign int_sqrt_fNext_40$D_IN = + { int_sqrt_fNext_39$D_OUT[464] || + int_sqrt_fNext_39$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_39$D_OUT[464] ? + int_sqrt_fNext_39$D_OUT[463:348] : + ((int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_39$D_OUT[231:116] : + int_sqrt_fNext_39$D_OUT[463:348]), + int_sqrt_fNext_39$D_OUT[464] ? + int_sqrt_fNext_39$D_OUT[347:0] : + { _theResult___snd_fst__h41301, + (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_39$D_OUT[231:0] : + { _theResult___snd_snd__h41377, b__h41374 } } } ; + assign int_sqrt_fNext_40$ENQ = CAN_FIRE_RL_int_sqrt_work_40 ; + assign int_sqrt_fNext_40$DEQ = CAN_FIRE_RL_int_sqrt_work_41 ; + assign int_sqrt_fNext_40$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_41 + assign int_sqrt_fNext_41$D_IN = + { int_sqrt_fNext_40$D_OUT[464] || + int_sqrt_fNext_40$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_40$D_OUT[464] ? + int_sqrt_fNext_40$D_OUT[463:348] : + ((int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_40$D_OUT[231:116] : + int_sqrt_fNext_40$D_OUT[463:348]), + int_sqrt_fNext_40$D_OUT[464] ? + int_sqrt_fNext_40$D_OUT[347:0] : + { _theResult___snd_fst__h41701, + (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_40$D_OUT[231:0] : + { _theResult___snd_snd__h41777, b__h41774 } } } ; + assign int_sqrt_fNext_41$ENQ = CAN_FIRE_RL_int_sqrt_work_41 ; + assign int_sqrt_fNext_41$DEQ = CAN_FIRE_RL_int_sqrt_work_42 ; + assign int_sqrt_fNext_41$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_42 + assign int_sqrt_fNext_42$D_IN = + { int_sqrt_fNext_41$D_OUT[464] || + int_sqrt_fNext_41$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_41$D_OUT[464] ? + int_sqrt_fNext_41$D_OUT[463:348] : + ((int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_41$D_OUT[231:116] : + int_sqrt_fNext_41$D_OUT[463:348]), + int_sqrt_fNext_41$D_OUT[464] ? + int_sqrt_fNext_41$D_OUT[347:0] : + { _theResult___snd_fst__h42101, + (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_41$D_OUT[231:0] : + { _theResult___snd_snd__h42177, b__h42174 } } } ; + assign int_sqrt_fNext_42$ENQ = CAN_FIRE_RL_int_sqrt_work_42 ; + assign int_sqrt_fNext_42$DEQ = CAN_FIRE_RL_int_sqrt_work_43 ; + assign int_sqrt_fNext_42$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_43 + assign int_sqrt_fNext_43$D_IN = + { int_sqrt_fNext_42$D_OUT[464] || + int_sqrt_fNext_42$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_42$D_OUT[464] ? + int_sqrt_fNext_42$D_OUT[463:348] : + ((int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_42$D_OUT[231:116] : + int_sqrt_fNext_42$D_OUT[463:348]), + int_sqrt_fNext_42$D_OUT[464] ? + int_sqrt_fNext_42$D_OUT[347:0] : + { _theResult___snd_fst__h42501, + (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_42$D_OUT[231:0] : + { _theResult___snd_snd__h42577, b__h42574 } } } ; + assign int_sqrt_fNext_43$ENQ = CAN_FIRE_RL_int_sqrt_work_43 ; + assign int_sqrt_fNext_43$DEQ = CAN_FIRE_RL_int_sqrt_work_44 ; + assign int_sqrt_fNext_43$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_44 + assign int_sqrt_fNext_44$D_IN = + { int_sqrt_fNext_43$D_OUT[464] || + int_sqrt_fNext_43$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_43$D_OUT[464] ? + int_sqrt_fNext_43$D_OUT[463:348] : + ((int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_43$D_OUT[231:116] : + int_sqrt_fNext_43$D_OUT[463:348]), + int_sqrt_fNext_43$D_OUT[464] ? + int_sqrt_fNext_43$D_OUT[347:0] : + { _theResult___snd_fst__h42901, + (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_43$D_OUT[231:0] : + { _theResult___snd_snd__h42977, b__h42974 } } } ; + assign int_sqrt_fNext_44$ENQ = CAN_FIRE_RL_int_sqrt_work_44 ; + assign int_sqrt_fNext_44$DEQ = CAN_FIRE_RL_int_sqrt_work_45 ; + assign int_sqrt_fNext_44$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_45 + assign int_sqrt_fNext_45$D_IN = + { int_sqrt_fNext_44$D_OUT[464] || + int_sqrt_fNext_44$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_44$D_OUT[464] ? + int_sqrt_fNext_44$D_OUT[463:348] : + ((int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_44$D_OUT[231:116] : + int_sqrt_fNext_44$D_OUT[463:348]), + int_sqrt_fNext_44$D_OUT[464] ? + int_sqrt_fNext_44$D_OUT[347:0] : + { _theResult___snd_fst__h43301, + (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_44$D_OUT[231:0] : + { _theResult___snd_snd__h43377, b__h43374 } } } ; + assign int_sqrt_fNext_45$ENQ = CAN_FIRE_RL_int_sqrt_work_45 ; + assign int_sqrt_fNext_45$DEQ = CAN_FIRE_RL_int_sqrt_work_46 ; + assign int_sqrt_fNext_45$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_46 + assign int_sqrt_fNext_46$D_IN = + { int_sqrt_fNext_45$D_OUT[464] || + int_sqrt_fNext_45$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_45$D_OUT[464] ? + int_sqrt_fNext_45$D_OUT[463:348] : + ((int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_45$D_OUT[231:116] : + int_sqrt_fNext_45$D_OUT[463:348]), + int_sqrt_fNext_45$D_OUT[464] ? + int_sqrt_fNext_45$D_OUT[347:0] : + { _theResult___snd_fst__h43701, + (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_45$D_OUT[231:0] : + { _theResult___snd_snd__h43777, b__h43774 } } } ; + assign int_sqrt_fNext_46$ENQ = CAN_FIRE_RL_int_sqrt_work_46 ; + assign int_sqrt_fNext_46$DEQ = CAN_FIRE_RL_int_sqrt_work_47 ; + assign int_sqrt_fNext_46$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_47 + assign int_sqrt_fNext_47$D_IN = + { int_sqrt_fNext_46$D_OUT[464] || + int_sqrt_fNext_46$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_46$D_OUT[464] ? + int_sqrt_fNext_46$D_OUT[463:348] : + ((int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_46$D_OUT[231:116] : + int_sqrt_fNext_46$D_OUT[463:348]), + int_sqrt_fNext_46$D_OUT[464] ? + int_sqrt_fNext_46$D_OUT[347:0] : + { _theResult___snd_fst__h44101, + (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_46$D_OUT[231:0] : + { _theResult___snd_snd__h44177, b__h44174 } } } ; + assign int_sqrt_fNext_47$ENQ = CAN_FIRE_RL_int_sqrt_work_47 ; + assign int_sqrt_fNext_47$DEQ = CAN_FIRE_RL_int_sqrt_work_48 ; + assign int_sqrt_fNext_47$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_48 + assign int_sqrt_fNext_48$D_IN = + { int_sqrt_fNext_47$D_OUT[464] || + int_sqrt_fNext_47$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_47$D_OUT[464] ? + int_sqrt_fNext_47$D_OUT[463:348] : + ((int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_47$D_OUT[231:116] : + int_sqrt_fNext_47$D_OUT[463:348]), + int_sqrt_fNext_47$D_OUT[464] ? + int_sqrt_fNext_47$D_OUT[347:0] : + { _theResult___snd_fst__h44501, + (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_47$D_OUT[231:0] : + { _theResult___snd_snd__h44577, b__h44574 } } } ; + assign int_sqrt_fNext_48$ENQ = CAN_FIRE_RL_int_sqrt_work_48 ; + assign int_sqrt_fNext_48$DEQ = CAN_FIRE_RL_int_sqrt_work_49 ; + assign int_sqrt_fNext_48$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_49 + assign int_sqrt_fNext_49$D_IN = + { int_sqrt_fNext_48$D_OUT[464] || + int_sqrt_fNext_48$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_48$D_OUT[464] ? + int_sqrt_fNext_48$D_OUT[463:348] : + ((int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_48$D_OUT[231:116] : + int_sqrt_fNext_48$D_OUT[463:348]), + int_sqrt_fNext_48$D_OUT[464] ? + int_sqrt_fNext_48$D_OUT[347:0] : + { _theResult___snd_fst__h44901, + (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_48$D_OUT[231:0] : + { _theResult___snd_snd__h44977, b__h44974 } } } ; + assign int_sqrt_fNext_49$ENQ = CAN_FIRE_RL_int_sqrt_work_49 ; + assign int_sqrt_fNext_49$DEQ = CAN_FIRE_RL_int_sqrt_work_50 ; + assign int_sqrt_fNext_49$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_5 + assign int_sqrt_fNext_5$D_IN = + { int_sqrt_fNext_4$D_OUT[464] || + int_sqrt_fNext_4$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_4$D_OUT[464] ? + int_sqrt_fNext_4$D_OUT[463:348] : + ((int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_4$D_OUT[231:116] : + int_sqrt_fNext_4$D_OUT[463:348]), + int_sqrt_fNext_4$D_OUT[464] ? + int_sqrt_fNext_4$D_OUT[347:0] : + { _theResult___snd_fst__h27301, + (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_4$D_OUT[231:0] : + { _theResult___snd_snd__h27377, b__h27374 } } } ; + assign int_sqrt_fNext_5$ENQ = CAN_FIRE_RL_int_sqrt_work_5 ; + assign int_sqrt_fNext_5$DEQ = CAN_FIRE_RL_int_sqrt_work_6 ; + assign int_sqrt_fNext_5$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_50 + assign int_sqrt_fNext_50$D_IN = + { int_sqrt_fNext_49$D_OUT[464] || + int_sqrt_fNext_49$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_49$D_OUT[464] ? + int_sqrt_fNext_49$D_OUT[463:348] : + ((int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_49$D_OUT[231:116] : + int_sqrt_fNext_49$D_OUT[463:348]), + int_sqrt_fNext_49$D_OUT[464] ? + int_sqrt_fNext_49$D_OUT[347:0] : + { _theResult___snd_fst__h45301, + (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_49$D_OUT[231:0] : + { _theResult___snd_snd__h45377, b__h45374 } } } ; + assign int_sqrt_fNext_50$ENQ = CAN_FIRE_RL_int_sqrt_work_50 ; + assign int_sqrt_fNext_50$DEQ = CAN_FIRE_RL_int_sqrt_work_51 ; + assign int_sqrt_fNext_50$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_51 + assign int_sqrt_fNext_51$D_IN = + { int_sqrt_fNext_50$D_OUT[464] || + int_sqrt_fNext_50$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_50$D_OUT[464] ? + int_sqrt_fNext_50$D_OUT[463:348] : + ((int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_50$D_OUT[231:116] : + int_sqrt_fNext_50$D_OUT[463:348]), + int_sqrt_fNext_50$D_OUT[464] ? + int_sqrt_fNext_50$D_OUT[347:0] : + { _theResult___snd_fst__h45701, + (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_50$D_OUT[231:0] : + { _theResult___snd_snd__h45777, b__h45774 } } } ; + assign int_sqrt_fNext_51$ENQ = CAN_FIRE_RL_int_sqrt_work_51 ; + assign int_sqrt_fNext_51$DEQ = CAN_FIRE_RL_int_sqrt_work_52 ; + assign int_sqrt_fNext_51$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_52 + assign int_sqrt_fNext_52$D_IN = + { int_sqrt_fNext_51$D_OUT[464] || + int_sqrt_fNext_51$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_51$D_OUT[464] ? + int_sqrt_fNext_51$D_OUT[463:348] : + ((int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_51$D_OUT[231:116] : + int_sqrt_fNext_51$D_OUT[463:348]), + int_sqrt_fNext_51$D_OUT[464] ? + int_sqrt_fNext_51$D_OUT[347:0] : + { _theResult___snd_fst__h46101, + (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_51$D_OUT[231:0] : + { _theResult___snd_snd__h46177, b__h46174 } } } ; + assign int_sqrt_fNext_52$ENQ = CAN_FIRE_RL_int_sqrt_work_52 ; + assign int_sqrt_fNext_52$DEQ = CAN_FIRE_RL_int_sqrt_work_53 ; + assign int_sqrt_fNext_52$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_53 + assign int_sqrt_fNext_53$D_IN = + { int_sqrt_fNext_52$D_OUT[464] || + int_sqrt_fNext_52$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_52$D_OUT[464] ? + int_sqrt_fNext_52$D_OUT[463:348] : + ((int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_52$D_OUT[231:116] : + int_sqrt_fNext_52$D_OUT[463:348]), + int_sqrt_fNext_52$D_OUT[464] ? + int_sqrt_fNext_52$D_OUT[347:0] : + { _theResult___snd_fst__h46501, + (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_52$D_OUT[231:0] : + { _theResult___snd_snd__h46577, b__h46574 } } } ; + assign int_sqrt_fNext_53$ENQ = CAN_FIRE_RL_int_sqrt_work_53 ; + assign int_sqrt_fNext_53$DEQ = CAN_FIRE_RL_int_sqrt_work_54 ; + assign int_sqrt_fNext_53$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_54 + assign int_sqrt_fNext_54$D_IN = + { int_sqrt_fNext_53$D_OUT[464] || + int_sqrt_fNext_53$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_53$D_OUT[464] ? + int_sqrt_fNext_53$D_OUT[463:348] : + ((int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_53$D_OUT[231:116] : + int_sqrt_fNext_53$D_OUT[463:348]), + int_sqrt_fNext_53$D_OUT[464] ? + int_sqrt_fNext_53$D_OUT[347:0] : + { _theResult___snd_fst__h46901, + (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_53$D_OUT[231:0] : + { _theResult___snd_snd__h46977, b__h46974 } } } ; + assign int_sqrt_fNext_54$ENQ = CAN_FIRE_RL_int_sqrt_work_54 ; + assign int_sqrt_fNext_54$DEQ = CAN_FIRE_RL_int_sqrt_work_55 ; + assign int_sqrt_fNext_54$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_55 + assign int_sqrt_fNext_55$D_IN = + { int_sqrt_fNext_54$D_OUT[464] || + int_sqrt_fNext_54$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_54$D_OUT[464] ? + int_sqrt_fNext_54$D_OUT[463:348] : + ((int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_54$D_OUT[231:116] : + int_sqrt_fNext_54$D_OUT[463:348]), + int_sqrt_fNext_54$D_OUT[464] ? + int_sqrt_fNext_54$D_OUT[347:0] : + { _theResult___snd_fst__h47301, + (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_54$D_OUT[231:0] : + { _theResult___snd_snd__h47377, b__h47374 } } } ; + assign int_sqrt_fNext_55$ENQ = CAN_FIRE_RL_int_sqrt_work_55 ; + assign int_sqrt_fNext_55$DEQ = CAN_FIRE_RL_int_sqrt_work_56 ; + assign int_sqrt_fNext_55$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_56 + assign int_sqrt_fNext_56$D_IN = + { int_sqrt_fNext_55$D_OUT[464] || + int_sqrt_fNext_55$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_55$D_OUT[464] ? + int_sqrt_fNext_55$D_OUT[463:348] : + ((int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_55$D_OUT[231:116] : + int_sqrt_fNext_55$D_OUT[463:348]), + int_sqrt_fNext_55$D_OUT[464] ? + int_sqrt_fNext_55$D_OUT[347:0] : + { _theResult___snd_fst__h47701, + (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_55$D_OUT[231:0] : + { _theResult___snd_snd__h47777, b__h47774 } } } ; + assign int_sqrt_fNext_56$ENQ = CAN_FIRE_RL_int_sqrt_work_56 ; + assign int_sqrt_fNext_56$DEQ = CAN_FIRE_RL_int_sqrt_work_57 ; + assign int_sqrt_fNext_56$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_57 + assign int_sqrt_fNext_57$D_IN = + { int_sqrt_fNext_56$D_OUT[464] || + int_sqrt_fNext_56$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_56$D_OUT[464] ? + int_sqrt_fNext_56$D_OUT[463:348] : + ((int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_56$D_OUT[231:116] : + int_sqrt_fNext_56$D_OUT[463:348]), + int_sqrt_fNext_56$D_OUT[464] ? + int_sqrt_fNext_56$D_OUT[347:0] : + { _theResult___snd_fst__h48101, + (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_56$D_OUT[231:0] : + { _theResult___snd_snd__h48177, b__h48174 } } } ; + assign int_sqrt_fNext_57$ENQ = CAN_FIRE_RL_int_sqrt_work_57 ; + assign int_sqrt_fNext_57$DEQ = CAN_FIRE_RL_int_sqrt_work_58 ; + assign int_sqrt_fNext_57$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_58 + assign int_sqrt_fNext_58$D_IN = + { int_sqrt_fNext_57$D_OUT[464] || + int_sqrt_fNext_57$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_57$D_OUT[464] ? + int_sqrt_fNext_57$D_OUT[463:348] : + ((int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_57$D_OUT[231:116] : + int_sqrt_fNext_57$D_OUT[463:348]), + int_sqrt_fNext_57$D_OUT[464] ? + int_sqrt_fNext_57$D_OUT[347:0] : + { _theResult___snd_fst__h48501, + (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_57$D_OUT[231:0] : + { _theResult___snd_snd__h48577, b__h48574 } } } ; + assign int_sqrt_fNext_58$ENQ = CAN_FIRE_RL_int_sqrt_work_58 ; + assign int_sqrt_fNext_58$DEQ = CAN_FIRE_RL_int_sqrt_finish ; + assign int_sqrt_fNext_58$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_6 + assign int_sqrt_fNext_6$D_IN = + { int_sqrt_fNext_5$D_OUT[464] || + int_sqrt_fNext_5$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_5$D_OUT[464] ? + int_sqrt_fNext_5$D_OUT[463:348] : + ((int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_5$D_OUT[231:116] : + int_sqrt_fNext_5$D_OUT[463:348]), + int_sqrt_fNext_5$D_OUT[464] ? + int_sqrt_fNext_5$D_OUT[347:0] : + { _theResult___snd_fst__h27701, + (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_5$D_OUT[231:0] : + { _theResult___snd_snd__h27777, b__h27774 } } } ; + assign int_sqrt_fNext_6$ENQ = CAN_FIRE_RL_int_sqrt_work_6 ; + assign int_sqrt_fNext_6$DEQ = CAN_FIRE_RL_int_sqrt_work_7 ; + assign int_sqrt_fNext_6$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_7 + assign int_sqrt_fNext_7$D_IN = + { int_sqrt_fNext_6$D_OUT[464] || + int_sqrt_fNext_6$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_6$D_OUT[464] ? + int_sqrt_fNext_6$D_OUT[463:348] : + ((int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_6$D_OUT[231:116] : + int_sqrt_fNext_6$D_OUT[463:348]), + int_sqrt_fNext_6$D_OUT[464] ? + int_sqrt_fNext_6$D_OUT[347:0] : + { _theResult___snd_fst__h28101, + (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_6$D_OUT[231:0] : + { _theResult___snd_snd__h28177, b__h28174 } } } ; + assign int_sqrt_fNext_7$ENQ = CAN_FIRE_RL_int_sqrt_work_7 ; + assign int_sqrt_fNext_7$DEQ = CAN_FIRE_RL_int_sqrt_work_8 ; + assign int_sqrt_fNext_7$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_8 + assign int_sqrt_fNext_8$D_IN = + { int_sqrt_fNext_7$D_OUT[464] || + int_sqrt_fNext_7$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_7$D_OUT[464] ? + int_sqrt_fNext_7$D_OUT[463:348] : + ((int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_7$D_OUT[231:116] : + int_sqrt_fNext_7$D_OUT[463:348]), + int_sqrt_fNext_7$D_OUT[464] ? + int_sqrt_fNext_7$D_OUT[347:0] : + { _theResult___snd_fst__h28501, + (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_7$D_OUT[231:0] : + { _theResult___snd_snd__h28577, b__h28574 } } } ; + assign int_sqrt_fNext_8$ENQ = CAN_FIRE_RL_int_sqrt_work_8 ; + assign int_sqrt_fNext_8$DEQ = CAN_FIRE_RL_int_sqrt_work_9 ; + assign int_sqrt_fNext_8$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_9 + assign int_sqrt_fNext_9$D_IN = + { int_sqrt_fNext_8$D_OUT[464] || + int_sqrt_fNext_8$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_8$D_OUT[464] ? + int_sqrt_fNext_8$D_OUT[463:348] : + ((int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_8$D_OUT[231:116] : + int_sqrt_fNext_8$D_OUT[463:348]), + int_sqrt_fNext_8$D_OUT[464] ? + int_sqrt_fNext_8$D_OUT[347:0] : + { _theResult___snd_fst__h28901, + (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_8$D_OUT[231:0] : + { _theResult___snd_snd__h28977, b__h28974 } } } ; + assign int_sqrt_fNext_9$ENQ = CAN_FIRE_RL_int_sqrt_work_9 ; + assign int_sqrt_fNext_9$DEQ = CAN_FIRE_RL_int_sqrt_work_10 ; + assign int_sqrt_fNext_9$CLR = 1'b0 ; + + // submodule int_sqrt_fRequest + assign int_sqrt_fRequest$D_IN = { fpu_fState_S1$D_OUT[57:0], 58'd0 } ; + assign int_sqrt_fRequest$ENQ = + WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[194] ; + assign int_sqrt_fRequest$DEQ = CAN_FIRE_RL_int_sqrt_start ; + assign int_sqrt_fRequest$CLR = 1'b0 ; + + // submodule int_sqrt_fResponse + assign int_sqrt_fResponse$D_IN = + { b__h48712, int_sqrt_fNext_58$D_OUT[347:232] != 116'd0 } ; + assign int_sqrt_fResponse$ENQ = CAN_FIRE_RL_int_sqrt_finish ; + assign int_sqrt_fResponse$DEQ = + WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[136] ; + assign int_sqrt_fResponse$CLR = 1'b0 ; + + // remaining internal signals + assign IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6 = + _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 ? + _theResult___snd__h75342 : + _theResult___snd__h75337 ; + assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 = + sfd__h75932[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 63'h7FF0000000000000 : + { din_inc___2_exp__h76519, sfd__h75932[52:1] }) : + { IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, + sfd__h75932[51:0] } ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 = + (fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? + (fpu_fOperand_S0$D_OUT[54] ? + 6'd2 : + (fpu_fOperand_S0$D_OUT[53] ? + 6'd3 : + (fpu_fOperand_S0$D_OUT[52] ? + 6'd4 : + (fpu_fOperand_S0$D_OUT[51] ? + 6'd5 : + (fpu_fOperand_S0$D_OUT[50] ? + 6'd6 : + (fpu_fOperand_S0$D_OUT[49] ? + 6'd7 : + (fpu_fOperand_S0$D_OUT[48] ? + 6'd8 : + (fpu_fOperand_S0$D_OUT[47] ? + 6'd9 : + (fpu_fOperand_S0$D_OUT[46] ? + 6'd10 : + (fpu_fOperand_S0$D_OUT[45] ? + 6'd11 : + (fpu_fOperand_S0$D_OUT[44] ? + 6'd12 : + (fpu_fOperand_S0$D_OUT[43] ? + 6'd13 : + (fpu_fOperand_S0$D_OUT[42] ? + 6'd14 : + (fpu_fOperand_S0$D_OUT[41] ? + 6'd15 : + (fpu_fOperand_S0$D_OUT[40] ? + 6'd16 : + (fpu_fOperand_S0$D_OUT[39] ? + 6'd17 : + (fpu_fOperand_S0$D_OUT[38] ? + 6'd18 : + (fpu_fOperand_S0$D_OUT[37] ? + 6'd19 : + (fpu_fOperand_S0$D_OUT[36] ? + 6'd20 : + (fpu_fOperand_S0$D_OUT[35] ? + 6'd21 : + (fpu_fOperand_S0$D_OUT[34] ? + 6'd22 : + (fpu_fOperand_S0$D_OUT[33] ? + 6'd23 : + (fpu_fOperand_S0$D_OUT[32] ? + 6'd24 : + (fpu_fOperand_S0$D_OUT[31] ? + 6'd25 : + (fpu_fOperand_S0$D_OUT[30] ? + 6'd26 : + (fpu_fOperand_S0$D_OUT[29] ? + 6'd27 : + (fpu_fOperand_S0$D_OUT[28] ? + 6'd28 : + (fpu_fOperand_S0$D_OUT[27] ? + 6'd29 : + (fpu_fOperand_S0$D_OUT[26] ? + 6'd30 : + (fpu_fOperand_S0$D_OUT[25] ? + 6'd31 : + (fpu_fOperand_S0$D_OUT[24] ? + 6'd32 : + (fpu_fOperand_S0$D_OUT[23] ? + 6'd33 : + (fpu_fOperand_S0$D_OUT[22] ? + 6'd34 : + (fpu_fOperand_S0$D_OUT[21] ? + 6'd35 : + (fpu_fOperand_S0$D_OUT[20] ? + 6'd36 : + (fpu_fOperand_S0$D_OUT[19] ? + 6'd37 : + (fpu_fOperand_S0$D_OUT[18] ? + 6'd38 : + (fpu_fOperand_S0$D_OUT[17] ? + 6'd39 : + (fpu_fOperand_S0$D_OUT[16] ? + 6'd40 : + (fpu_fOperand_S0$D_OUT[15] ? + 6'd41 : + (fpu_fOperand_S0$D_OUT[14] ? + 6'd42 : + (fpu_fOperand_S0$D_OUT[13] ? + 6'd43 : + (fpu_fOperand_S0$D_OUT[12] ? + 6'd44 : + (fpu_fOperand_S0$D_OUT[11] ? + 6'd45 : + (fpu_fOperand_S0$D_OUT[10] ? + 6'd46 : + (fpu_fOperand_S0$D_OUT[9] ? + 6'd47 : + (fpu_fOperand_S0$D_OUT[8] ? + 6'd48 : + (fpu_fOperand_S0$D_OUT[7] ? + 6'd49 : + (fpu_fOperand_S0$D_OUT[6] ? + 6'd50 : + (fpu_fOperand_S0$D_OUT[5] ? + 6'd51 : + (fpu_fOperand_S0$D_OUT[4] ? + 6'd52 : + (fpu_fOperand_S0$D_OUT[3] ? + 6'd53 : + 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : + 6'd1 ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460 = + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8[10]}}, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 }) - + { 7'd0, + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 } ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 = + (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 && + !fpu_fOperand_S0$D_OUT[66]) ? + { 1'd1, + fpu_fOperand_S0$D_OUT[66:3], + 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : + (fpu_fOperand_S0$D_OUT[66] ? + 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : + { 70'h155555555555555540, + fpu_fOperand_S0$D_OUT[2:0], + fpu_fOperand_S0$D_OUT[66], + x__h57541[10:0], + fpu_fOperand_S0$D_OUT[54:3], + x__h65683 }) ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 = + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[12:1] ; + assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 = + (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? + 12'd3074 : + { fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5[10], + fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 } ; + assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 = + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 - + 12'd3074 ; + assign IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813 = + fpu_fState_S3$D_OUT[195] ? + fpu_fState_S3$D_OUT[128:126] : + { fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023, + _theResult___fst_exp__h75269 == 11'd0 && + guard__h66951 != 2'd0, + fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023 } ; + assign IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820 = + (fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h75266, sfdin__h75260[58:7] } ; + assign IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 = + (fpu_fState_S3$D_OUT[58] ? + 6'd0 : + (fpu_fState_S3$D_OUT[57] ? + 6'd1 : + (fpu_fState_S3$D_OUT[56] ? + 6'd2 : + (fpu_fState_S3$D_OUT[55] ? + 6'd3 : + (fpu_fState_S3$D_OUT[54] ? + 6'd4 : + (fpu_fState_S3$D_OUT[53] ? + 6'd5 : + (fpu_fState_S3$D_OUT[52] ? + 6'd6 : + (fpu_fState_S3$D_OUT[51] ? + 6'd7 : + (fpu_fState_S3$D_OUT[50] ? + 6'd8 : + (fpu_fState_S3$D_OUT[49] ? + 6'd9 : + (fpu_fState_S3$D_OUT[48] ? + 6'd10 : + (fpu_fState_S3$D_OUT[47] ? + 6'd11 : + (fpu_fState_S3$D_OUT[46] ? + 6'd12 : + (fpu_fState_S3$D_OUT[45] ? + 6'd13 : + (fpu_fState_S3$D_OUT[44] ? + 6'd14 : + (fpu_fState_S3$D_OUT[43] ? + 6'd15 : + (fpu_fState_S3$D_OUT[42] ? + 6'd16 : + (fpu_fState_S3$D_OUT[41] ? + 6'd17 : + (fpu_fState_S3$D_OUT[40] ? + 6'd18 : + (fpu_fState_S3$D_OUT[39] ? + 6'd19 : + (fpu_fState_S3$D_OUT[38] ? + 6'd20 : + (fpu_fState_S3$D_OUT[37] ? + 6'd21 : + (fpu_fState_S3$D_OUT[36] ? + 6'd22 : + (fpu_fState_S3$D_OUT[35] ? + 6'd23 : + (fpu_fState_S3$D_OUT[34] ? + 6'd24 : + (fpu_fState_S3$D_OUT[33] ? + 6'd25 : + (fpu_fState_S3$D_OUT[32] ? + 6'd26 : + (fpu_fState_S3$D_OUT[31] ? + 6'd27 : + (fpu_fState_S3$D_OUT[30] ? + 6'd28 : + (fpu_fState_S3$D_OUT[29] ? + 6'd29 : + (fpu_fState_S3$D_OUT[28] ? + 6'd30 : + (fpu_fState_S3$D_OUT[27] ? + 6'd31 : + (fpu_fState_S3$D_OUT[26] ? + 6'd32 : + (fpu_fState_S3$D_OUT[25] ? + 6'd33 : + (fpu_fState_S3$D_OUT[24] ? + 6'd34 : + (fpu_fState_S3$D_OUT[23] ? + 6'd35 : + (fpu_fState_S3$D_OUT[22] ? + 6'd36 : + (fpu_fState_S3$D_OUT[21] ? + 6'd37 : + (fpu_fState_S3$D_OUT[20] ? + 6'd38 : + (fpu_fState_S3$D_OUT[19] ? + 6'd39 : + (fpu_fState_S3$D_OUT[18] ? + 6'd40 : + (fpu_fState_S3$D_OUT[17] ? + 6'd41 : + (fpu_fState_S3$D_OUT[16] ? + 6'd42 : + (fpu_fState_S3$D_OUT[15] ? + 6'd43 : + (fpu_fState_S3$D_OUT[14] ? + 6'd44 : + (fpu_fState_S3$D_OUT[13] ? + 6'd45 : + (fpu_fState_S3$D_OUT[12] ? + 6'd46 : + (fpu_fState_S3$D_OUT[11] ? + 6'd47 : + (fpu_fState_S3$D_OUT[10] ? + 6'd48 : + (fpu_fState_S3$D_OUT[9] ? + 6'd49 : + (fpu_fState_S3$D_OUT[8] ? + 6'd50 : + (fpu_fState_S3$D_OUT[7] ? + 6'd51 : + (fpu_fState_S3$D_OUT[6] ? + 6'd52 : + (fpu_fState_S3$D_OUT[5] ? + 6'd53 : + (fpu_fState_S3$D_OUT[4] ? + 6'd54 : + (fpu_fState_S3$D_OUT[3] ? + 6'd55 : + (fpu_fState_S3$D_OUT[2] ? + 6'd56 : + (fpu_fState_S3$D_OUT[1] ? + 6'd57 : + (fpu_fState_S3$D_OUT[0] ? + 6'd58 : + 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 6'd1 ; + assign IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 = + (fpu_fState_S4$D_OUT[64:54] == 11'd0 && + sfd__h75932[53:52] == 2'b01) ? + 11'd1 : + fpu_fState_S4$D_OUT[64:54] ; + assign IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 = + (int_sqrt_fRequest$D_OUT[115] ? + 7'd0 : + (int_sqrt_fRequest$D_OUT[114] ? + 7'd1 : + (int_sqrt_fRequest$D_OUT[113] ? + 7'd2 : + (int_sqrt_fRequest$D_OUT[112] ? + 7'd3 : + (int_sqrt_fRequest$D_OUT[111] ? + 7'd4 : + (int_sqrt_fRequest$D_OUT[110] ? + 7'd5 : + (int_sqrt_fRequest$D_OUT[109] ? + 7'd6 : + (int_sqrt_fRequest$D_OUT[108] ? + 7'd7 : + (int_sqrt_fRequest$D_OUT[107] ? + 7'd8 : + (int_sqrt_fRequest$D_OUT[106] ? + 7'd9 : + (int_sqrt_fRequest$D_OUT[105] ? + 7'd10 : + (int_sqrt_fRequest$D_OUT[104] ? + 7'd11 : + (int_sqrt_fRequest$D_OUT[103] ? + 7'd12 : + (int_sqrt_fRequest$D_OUT[102] ? + 7'd13 : + (int_sqrt_fRequest$D_OUT[101] ? + 7'd14 : + (int_sqrt_fRequest$D_OUT[100] ? + 7'd15 : + (int_sqrt_fRequest$D_OUT[99] ? + 7'd16 : + (int_sqrt_fRequest$D_OUT[98] ? + 7'd17 : + (int_sqrt_fRequest$D_OUT[97] ? + 7'd18 : + (int_sqrt_fRequest$D_OUT[96] ? + 7'd19 : + (int_sqrt_fRequest$D_OUT[95] ? + 7'd20 : + (int_sqrt_fRequest$D_OUT[94] ? + 7'd21 : + (int_sqrt_fRequest$D_OUT[93] ? + 7'd22 : + (int_sqrt_fRequest$D_OUT[92] ? + 7'd23 : + (int_sqrt_fRequest$D_OUT[91] ? + 7'd24 : + (int_sqrt_fRequest$D_OUT[90] ? + 7'd25 : + (int_sqrt_fRequest$D_OUT[89] ? + 7'd26 : + (int_sqrt_fRequest$D_OUT[88] ? + 7'd27 : + (int_sqrt_fRequest$D_OUT[87] ? + 7'd28 : + (int_sqrt_fRequest$D_OUT[86] ? + 7'd29 : + (int_sqrt_fRequest$D_OUT[85] ? + 7'd30 : + (int_sqrt_fRequest$D_OUT[84] ? + 7'd31 : + (int_sqrt_fRequest$D_OUT[83] ? + 7'd32 : + (int_sqrt_fRequest$D_OUT[82] ? + 7'd33 : + (int_sqrt_fRequest$D_OUT[81] ? + 7'd34 : + (int_sqrt_fRequest$D_OUT[80] ? + 7'd35 : + (int_sqrt_fRequest$D_OUT[79] ? + 7'd36 : + (int_sqrt_fRequest$D_OUT[78] ? + 7'd37 : + (int_sqrt_fRequest$D_OUT[77] ? + 7'd38 : + (int_sqrt_fRequest$D_OUT[76] ? + 7'd39 : + (int_sqrt_fRequest$D_OUT[75] ? + 7'd40 : + (int_sqrt_fRequest$D_OUT[74] ? + 7'd41 : + (int_sqrt_fRequest$D_OUT[73] ? + 7'd42 : + (int_sqrt_fRequest$D_OUT[72] ? + 7'd43 : + (int_sqrt_fRequest$D_OUT[71] ? + 7'd44 : + (int_sqrt_fRequest$D_OUT[70] ? + 7'd45 : + (int_sqrt_fRequest$D_OUT[69] ? + 7'd46 : + (int_sqrt_fRequest$D_OUT[68] ? + 7'd47 : + (int_sqrt_fRequest$D_OUT[67] ? + 7'd48 : + (int_sqrt_fRequest$D_OUT[66] ? + 7'd49 : + (int_sqrt_fRequest$D_OUT[65] ? + 7'd50 : + (int_sqrt_fRequest$D_OUT[64] ? + 7'd51 : + (int_sqrt_fRequest$D_OUT[63] ? + 7'd52 : + (int_sqrt_fRequest$D_OUT[62] ? + 7'd53 : + (int_sqrt_fRequest$D_OUT[61] ? + 7'd54 : + (int_sqrt_fRequest$D_OUT[60] ? + 7'd55 : + (int_sqrt_fRequest$D_OUT[59] ? + 7'd56 : + (int_sqrt_fRequest$D_OUT[58] ? + 7'd57 : + (int_sqrt_fRequest$D_OUT[57] ? + 7'd58 : + (int_sqrt_fRequest$D_OUT[56] ? + 7'd59 : + (int_sqrt_fRequest$D_OUT[55] ? + 7'd60 : + (int_sqrt_fRequest$D_OUT[54] ? + 7'd61 : + (int_sqrt_fRequest$D_OUT[53] ? + 7'd62 : + (int_sqrt_fRequest$D_OUT[52] ? + 7'd63 : + (int_sqrt_fRequest$D_OUT[51] ? + 7'd64 : + (int_sqrt_fRequest$D_OUT[50] ? + 7'd65 : + (int_sqrt_fRequest$D_OUT[49] ? + 7'd66 : + (int_sqrt_fRequest$D_OUT[48] ? + 7'd67 : + (int_sqrt_fRequest$D_OUT[47] ? + 7'd68 : + (int_sqrt_fRequest$D_OUT[46] ? + 7'd69 : + (int_sqrt_fRequest$D_OUT[45] ? + 7'd70 : + (int_sqrt_fRequest$D_OUT[44] ? + 7'd71 : + (int_sqrt_fRequest$D_OUT[43] ? + 7'd72 : + (int_sqrt_fRequest$D_OUT[42] ? + 7'd73 : + (int_sqrt_fRequest$D_OUT[41] ? + 7'd74 : + (int_sqrt_fRequest$D_OUT[40] ? + 7'd75 : + (int_sqrt_fRequest$D_OUT[39] ? + 7'd76 : + (int_sqrt_fRequest$D_OUT[38] ? + 7'd77 : + (int_sqrt_fRequest$D_OUT[37] ? + 7'd78 : + (int_sqrt_fRequest$D_OUT[36] ? + 7'd79 : + (int_sqrt_fRequest$D_OUT[35] ? + 7'd80 : + (int_sqrt_fRequest$D_OUT[34] ? + 7'd81 : + (int_sqrt_fRequest$D_OUT[33] ? + 7'd82 : + (int_sqrt_fRequest$D_OUT[32] ? + 7'd83 : + (int_sqrt_fRequest$D_OUT[31] ? + 7'd84 : + (int_sqrt_fRequest$D_OUT[30] ? + 7'd85 : + (int_sqrt_fRequest$D_OUT[29] ? + 7'd86 : + (int_sqrt_fRequest$D_OUT[28] ? + 7'd87 : + (int_sqrt_fRequest$D_OUT[27] ? + 7'd88 : + (int_sqrt_fRequest$D_OUT[26] ? + 7'd89 : + (int_sqrt_fRequest$D_OUT[25] ? + 7'd90 : + (int_sqrt_fRequest$D_OUT[24] ? + 7'd91 : + (int_sqrt_fRequest$D_OUT[23] ? + 7'd92 : + (int_sqrt_fRequest$D_OUT[22] ? + 7'd93 : + (int_sqrt_fRequest$D_OUT[21] ? + 7'd94 : + (int_sqrt_fRequest$D_OUT[20] ? + 7'd95 : + (int_sqrt_fRequest$D_OUT[19] ? + 7'd96 : + (int_sqrt_fRequest$D_OUT[18] ? + 7'd97 : + (int_sqrt_fRequest$D_OUT[17] ? + 7'd98 : + (int_sqrt_fRequest$D_OUT[16] ? + 7'd99 : + (int_sqrt_fRequest$D_OUT[15] ? + 7'd100 : + (int_sqrt_fRequest$D_OUT[14] ? + 7'd101 : + (int_sqrt_fRequest$D_OUT[13] ? + 7'd102 : + (int_sqrt_fRequest$D_OUT[12] ? + 7'd103 : + (int_sqrt_fRequest$D_OUT[11] ? + 7'd104 : + (int_sqrt_fRequest$D_OUT[10] ? + 7'd105 : + (int_sqrt_fRequest$D_OUT[9] ? + 7'd106 : + (int_sqrt_fRequest$D_OUT[8] ? + 7'd107 : + (int_sqrt_fRequest$D_OUT[7] ? + 7'd108 : + (int_sqrt_fRequest$D_OUT[6] ? + 7'd109 : + (int_sqrt_fRequest$D_OUT[5] ? + 7'd110 : + (int_sqrt_fRequest$D_OUT[4] ? + 7'd111 : + (int_sqrt_fRequest$D_OUT[3] ? + 7'd112 : + (int_sqrt_fRequest$D_OUT[2] ? + 7'd113 : + (int_sqrt_fRequest$D_OUT[1] ? + 7'd114 : + (int_sqrt_fRequest$D_OUT[0] ? + 7'd115 : + 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 7'd1 ; + assign IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7 = + sfdin__h75260[6] ? 2'd2 : 2'd0 ; + assign _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 = + ({ 6'd0, + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ^ + 12'h800) <= + (IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ^ + 12'h800) ; + assign _theResult___exp__h76428 = + sfd__h75932[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 11'd2047 : + din_inc___2_exp__h76519) : + IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 ; + assign _theResult___fst_exp__h75266 = + fpu_fState_S3$D_OUT[58] ? + _theResult___fst_exp__h75289 : + _theResult___fst_exp__h75353 ; + assign _theResult___fst_exp__h75269 = + (fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h75266 ; + assign _theResult___fst_exp__h75289 = + (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? + 11'd2 : + fpu_fState_S3$D_OUT[121:111] + 11'd1 ; + assign _theResult___fst_exp__h75305 = + (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? + 11'd1 : + fpu_fState_S3$D_OUT[121:111] ; + assign _theResult___fst_exp__h75344 = + fpu_fState_S3$D_OUT[121:111] - + { 5'd0, + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ; + assign _theResult___fst_exp__h75350 = + (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && + !fpu_fState_S3$D_OUT[56] && + !fpu_fState_S3$D_OUT[55] && + !fpu_fState_S3$D_OUT[54] && + !fpu_fState_S3$D_OUT[53] && + !fpu_fState_S3$D_OUT[52] && + !fpu_fState_S3$D_OUT[51] && + !fpu_fState_S3$D_OUT[50] && + !fpu_fState_S3$D_OUT[49] && + !fpu_fState_S3$D_OUT[48] && + !fpu_fState_S3$D_OUT[47] && + !fpu_fState_S3$D_OUT[46] && + !fpu_fState_S3$D_OUT[45] && + !fpu_fState_S3$D_OUT[44] && + !fpu_fState_S3$D_OUT[43] && + !fpu_fState_S3$D_OUT[42] && + !fpu_fState_S3$D_OUT[41] && + !fpu_fState_S3$D_OUT[40] && + !fpu_fState_S3$D_OUT[39] && + !fpu_fState_S3$D_OUT[38] && + !fpu_fState_S3$D_OUT[37] && + !fpu_fState_S3$D_OUT[36] && + !fpu_fState_S3$D_OUT[35] && + !fpu_fState_S3$D_OUT[34] && + !fpu_fState_S3$D_OUT[33] && + !fpu_fState_S3$D_OUT[32] && + !fpu_fState_S3$D_OUT[31] && + !fpu_fState_S3$D_OUT[30] && + !fpu_fState_S3$D_OUT[29] && + !fpu_fState_S3$D_OUT[28] && + !fpu_fState_S3$D_OUT[27] && + !fpu_fState_S3$D_OUT[26] && + !fpu_fState_S3$D_OUT[25] && + !fpu_fState_S3$D_OUT[24] && + !fpu_fState_S3$D_OUT[23] && + !fpu_fState_S3$D_OUT[22] && + !fpu_fState_S3$D_OUT[21] && + !fpu_fState_S3$D_OUT[20] && + !fpu_fState_S3$D_OUT[19] && + !fpu_fState_S3$D_OUT[18] && + !fpu_fState_S3$D_OUT[17] && + !fpu_fState_S3$D_OUT[16] && + !fpu_fState_S3$D_OUT[15] && + !fpu_fState_S3$D_OUT[14] && + !fpu_fState_S3$D_OUT[13] && + !fpu_fState_S3$D_OUT[12] && + !fpu_fState_S3$D_OUT[11] && + !fpu_fState_S3$D_OUT[10] && + !fpu_fState_S3$D_OUT[9] && + !fpu_fState_S3$D_OUT[8] && + !fpu_fState_S3$D_OUT[7] && + !fpu_fState_S3$D_OUT[6] && + !fpu_fState_S3$D_OUT[5] && + !fpu_fState_S3$D_OUT[4] && + !fpu_fState_S3$D_OUT[3] && + !fpu_fState_S3$D_OUT[2] && + !fpu_fState_S3$D_OUT[1] && + !fpu_fState_S3$D_OUT[0] || + !_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775) ? + 11'd0 : + _theResult___fst_exp__h75344 ; + assign _theResult___fst_exp__h75353 = + (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? + _theResult___fst_exp__h75305 : + _theResult___fst_exp__h75350 ; + assign _theResult___fst_exp__h76509 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___fst_exp__h76506 ; + assign _theResult___fst_sfd__h76510 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___fst_sfd__h76507 ; + assign _theResult___sfd__h76429 = + sfd__h75932[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 52'd0 : + sfd__h75932[52:1]) : + sfd__h75932[51:0] ; + assign _theResult___snd__h75283 = { fpu_fState_S3$D_OUT[57:0], 1'd0 } ; + assign _theResult___snd__h75298 = + (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? + _theResult___snd__h75300 : + _theResult___snd__h75313 ; + assign _theResult___snd__h75300 = { fpu_fState_S3$D_OUT[56:0], 2'd0 } ; + assign _theResult___snd__h75313 = + (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && + !fpu_fState_S3$D_OUT[56] && + !fpu_fState_S3$D_OUT[55] && + !fpu_fState_S3$D_OUT[54] && + !fpu_fState_S3$D_OUT[53] && + !fpu_fState_S3$D_OUT[52] && + !fpu_fState_S3$D_OUT[51] && + !fpu_fState_S3$D_OUT[50] && + !fpu_fState_S3$D_OUT[49] && + !fpu_fState_S3$D_OUT[48] && + !fpu_fState_S3$D_OUT[47] && + !fpu_fState_S3$D_OUT[46] && + !fpu_fState_S3$D_OUT[45] && + !fpu_fState_S3$D_OUT[44] && + !fpu_fState_S3$D_OUT[43] && + !fpu_fState_S3$D_OUT[42] && + !fpu_fState_S3$D_OUT[41] && + !fpu_fState_S3$D_OUT[40] && + !fpu_fState_S3$D_OUT[39] && + !fpu_fState_S3$D_OUT[38] && + !fpu_fState_S3$D_OUT[37] && + !fpu_fState_S3$D_OUT[36] && + !fpu_fState_S3$D_OUT[35] && + !fpu_fState_S3$D_OUT[34] && + !fpu_fState_S3$D_OUT[33] && + !fpu_fState_S3$D_OUT[32] && + !fpu_fState_S3$D_OUT[31] && + !fpu_fState_S3$D_OUT[30] && + !fpu_fState_S3$D_OUT[29] && + !fpu_fState_S3$D_OUT[28] && + !fpu_fState_S3$D_OUT[27] && + !fpu_fState_S3$D_OUT[26] && + !fpu_fState_S3$D_OUT[25] && + !fpu_fState_S3$D_OUT[24] && + !fpu_fState_S3$D_OUT[23] && + !fpu_fState_S3$D_OUT[22] && + !fpu_fState_S3$D_OUT[21] && + !fpu_fState_S3$D_OUT[20] && + !fpu_fState_S3$D_OUT[19] && + !fpu_fState_S3$D_OUT[18] && + !fpu_fState_S3$D_OUT[17] && + !fpu_fState_S3$D_OUT[16] && + !fpu_fState_S3$D_OUT[15] && + !fpu_fState_S3$D_OUT[14] && + !fpu_fState_S3$D_OUT[13] && + !fpu_fState_S3$D_OUT[12] && + !fpu_fState_S3$D_OUT[11] && + !fpu_fState_S3$D_OUT[10] && + !fpu_fState_S3$D_OUT[9] && + !fpu_fState_S3$D_OUT[8] && + !fpu_fState_S3$D_OUT[7] && + !fpu_fState_S3$D_OUT[6] && + !fpu_fState_S3$D_OUT[5] && + !fpu_fState_S3$D_OUT[4] && + !fpu_fState_S3$D_OUT[3] && + !fpu_fState_S3$D_OUT[2] && + !fpu_fState_S3$D_OUT[1] && + !fpu_fState_S3$D_OUT[0]) ? + fpu_fState_S3$D_OUT[58:0] : + _theResult___snd__h75319 ; + assign _theResult___snd__h75319 = + { IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6[56:0], + 2'd0 } ; + assign _theResult___snd__h75337 = + fpu_fState_S3$D_OUT[58:0] << + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ; + assign _theResult___snd__h75342 = + fpu_fState_S3$D_OUT[58:0] << + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 ; + assign _theResult___snd_fst__h25299 = + (int_sqrt_fFirst$D_OUT[115:0] == 116'd0 || + int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264) ? + int_sqrt_fFirst$D_OUT[347:232] : + s__h25385 ; + assign _theResult___snd_fst__h25701 = + (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299) ? + int_sqrt_fNext_0$D_OUT[347:232] : + s__h25785 ; + assign _theResult___snd_fst__h26101 = + (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334) ? + int_sqrt_fNext_1$D_OUT[347:232] : + s__h26185 ; + assign _theResult___snd_fst__h26501 = + (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369) ? + int_sqrt_fNext_2$D_OUT[347:232] : + s__h26585 ; + assign _theResult___snd_fst__h26901 = + (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404) ? + int_sqrt_fNext_3$D_OUT[347:232] : + s__h26985 ; + assign _theResult___snd_fst__h27301 = + (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439) ? + int_sqrt_fNext_4$D_OUT[347:232] : + s__h27385 ; + assign _theResult___snd_fst__h27701 = + (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474) ? + int_sqrt_fNext_5$D_OUT[347:232] : + s__h27785 ; + assign _theResult___snd_fst__h28101 = + (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509) ? + int_sqrt_fNext_6$D_OUT[347:232] : + s__h28185 ; + assign _theResult___snd_fst__h28501 = + (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544) ? + int_sqrt_fNext_7$D_OUT[347:232] : + s__h28585 ; + assign _theResult___snd_fst__h28901 = + (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579) ? + int_sqrt_fNext_8$D_OUT[347:232] : + s__h28985 ; + assign _theResult___snd_fst__h29301 = + (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614) ? + int_sqrt_fNext_9$D_OUT[347:232] : + s__h29385 ; + assign _theResult___snd_fst__h29701 = + (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649) ? + int_sqrt_fNext_10$D_OUT[347:232] : + s__h29785 ; + assign _theResult___snd_fst__h30101 = + (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684) ? + int_sqrt_fNext_11$D_OUT[347:232] : + s__h30185 ; + assign _theResult___snd_fst__h30501 = + (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719) ? + int_sqrt_fNext_12$D_OUT[347:232] : + s__h30585 ; + assign _theResult___snd_fst__h30901 = + (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754) ? + int_sqrt_fNext_13$D_OUT[347:232] : + s__h30985 ; + assign _theResult___snd_fst__h31301 = + (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789) ? + int_sqrt_fNext_14$D_OUT[347:232] : + s__h31385 ; + assign _theResult___snd_fst__h31701 = + (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824) ? + int_sqrt_fNext_15$D_OUT[347:232] : + s__h31785 ; + assign _theResult___snd_fst__h32101 = + (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859) ? + int_sqrt_fNext_16$D_OUT[347:232] : + s__h32185 ; + assign _theResult___snd_fst__h32501 = + (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894) ? + int_sqrt_fNext_17$D_OUT[347:232] : + s__h32585 ; + assign _theResult___snd_fst__h32901 = + (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929) ? + int_sqrt_fNext_18$D_OUT[347:232] : + s__h32985 ; + assign _theResult___snd_fst__h33301 = + (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964) ? + int_sqrt_fNext_19$D_OUT[347:232] : + s__h33385 ; + assign _theResult___snd_fst__h33701 = + (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999) ? + int_sqrt_fNext_20$D_OUT[347:232] : + s__h33785 ; + assign _theResult___snd_fst__h34101 = + (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034) ? + int_sqrt_fNext_21$D_OUT[347:232] : + s__h34185 ; + assign _theResult___snd_fst__h34501 = + (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069) ? + int_sqrt_fNext_22$D_OUT[347:232] : + s__h34585 ; + assign _theResult___snd_fst__h34901 = + (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104) ? + int_sqrt_fNext_23$D_OUT[347:232] : + s__h34985 ; + assign _theResult___snd_fst__h35301 = + (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139) ? + int_sqrt_fNext_24$D_OUT[347:232] : + s__h35385 ; + assign _theResult___snd_fst__h35701 = + (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174) ? + int_sqrt_fNext_25$D_OUT[347:232] : + s__h35785 ; + assign _theResult___snd_fst__h36101 = + (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209) ? + int_sqrt_fNext_26$D_OUT[347:232] : + s__h36185 ; + assign _theResult___snd_fst__h36501 = + (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244) ? + int_sqrt_fNext_27$D_OUT[347:232] : + s__h36585 ; + assign _theResult___snd_fst__h36901 = + (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279) ? + int_sqrt_fNext_28$D_OUT[347:232] : + s__h36985 ; + assign _theResult___snd_fst__h37301 = + (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314) ? + int_sqrt_fNext_29$D_OUT[347:232] : + s__h37385 ; + assign _theResult___snd_fst__h37701 = + (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349) ? + int_sqrt_fNext_30$D_OUT[347:232] : + s__h37785 ; + assign _theResult___snd_fst__h38101 = + (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384) ? + int_sqrt_fNext_31$D_OUT[347:232] : + s__h38185 ; + assign _theResult___snd_fst__h38501 = + (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419) ? + int_sqrt_fNext_32$D_OUT[347:232] : + s__h38585 ; + assign _theResult___snd_fst__h38901 = + (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454) ? + int_sqrt_fNext_33$D_OUT[347:232] : + s__h38985 ; + assign _theResult___snd_fst__h39301 = + (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489) ? + int_sqrt_fNext_34$D_OUT[347:232] : + s__h39385 ; + assign _theResult___snd_fst__h39701 = + (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524) ? + int_sqrt_fNext_35$D_OUT[347:232] : + s__h39785 ; + assign _theResult___snd_fst__h40101 = + (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559) ? + int_sqrt_fNext_36$D_OUT[347:232] : + s__h40185 ; + assign _theResult___snd_fst__h40501 = + (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594) ? + int_sqrt_fNext_37$D_OUT[347:232] : + s__h40585 ; + assign _theResult___snd_fst__h40901 = + (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629) ? + int_sqrt_fNext_38$D_OUT[347:232] : + s__h40985 ; + assign _theResult___snd_fst__h41301 = + (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664) ? + int_sqrt_fNext_39$D_OUT[347:232] : + s__h41385 ; + assign _theResult___snd_fst__h41701 = + (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699) ? + int_sqrt_fNext_40$D_OUT[347:232] : + s__h41785 ; + assign _theResult___snd_fst__h42101 = + (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734) ? + int_sqrt_fNext_41$D_OUT[347:232] : + s__h42185 ; + assign _theResult___snd_fst__h42501 = + (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769) ? + int_sqrt_fNext_42$D_OUT[347:232] : + s__h42585 ; + assign _theResult___snd_fst__h42901 = + (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804) ? + int_sqrt_fNext_43$D_OUT[347:232] : + s__h42985 ; + assign _theResult___snd_fst__h43301 = + (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839) ? + int_sqrt_fNext_44$D_OUT[347:232] : + s__h43385 ; + assign _theResult___snd_fst__h43701 = + (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874) ? + int_sqrt_fNext_45$D_OUT[347:232] : + s__h43785 ; + assign _theResult___snd_fst__h44101 = + (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909) ? + int_sqrt_fNext_46$D_OUT[347:232] : + s__h44185 ; + assign _theResult___snd_fst__h44501 = + (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944) ? + int_sqrt_fNext_47$D_OUT[347:232] : + s__h44585 ; + assign _theResult___snd_fst__h44901 = + (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979) ? + int_sqrt_fNext_48$D_OUT[347:232] : + s__h44985 ; + assign _theResult___snd_fst__h45301 = + (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014) ? + int_sqrt_fNext_49$D_OUT[347:232] : + s__h45385 ; + assign _theResult___snd_fst__h45701 = + (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049) ? + int_sqrt_fNext_50$D_OUT[347:232] : + s__h45785 ; + assign _theResult___snd_fst__h46101 = + (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084) ? + int_sqrt_fNext_51$D_OUT[347:232] : + s__h46185 ; + assign _theResult___snd_fst__h46501 = + (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119) ? + int_sqrt_fNext_52$D_OUT[347:232] : + s__h46585 ; + assign _theResult___snd_fst__h46901 = + (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154) ? + int_sqrt_fNext_53$D_OUT[347:232] : + s__h46985 ; + assign _theResult___snd_fst__h47301 = + (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189) ? + int_sqrt_fNext_54$D_OUT[347:232] : + s__h47385 ; + assign _theResult___snd_fst__h47701 = + (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224) ? + int_sqrt_fNext_55$D_OUT[347:232] : + s__h47785 ; + assign _theResult___snd_fst__h48101 = + (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259) ? + int_sqrt_fNext_56$D_OUT[347:232] : + s__h48185 ; + assign _theResult___snd_fst__h48501 = + (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294) ? + int_sqrt_fNext_57$D_OUT[347:232] : + s__h48585 ; + assign _theResult___snd_fst__h75372 = + { IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7[1], + { sfdin__h75260[5:0], 52'd0 } != 58'd0 } ; + assign _theResult___snd_snd__h25377 = + int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 ? + r__h25394 : + r__h25386 ; + assign _theResult___snd_snd__h25777 = + int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 ? + r__h25794 : + r__h25786 ; + assign _theResult___snd_snd__h26177 = + int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 ? + r__h26194 : + r__h26186 ; + assign _theResult___snd_snd__h26577 = + int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 ? + r__h26594 : + r__h26586 ; + assign _theResult___snd_snd__h26977 = + int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 ? + r__h26994 : + r__h26986 ; + assign _theResult___snd_snd__h27377 = + int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 ? + r__h27394 : + r__h27386 ; + assign _theResult___snd_snd__h27777 = + int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 ? + r__h27794 : + r__h27786 ; + assign _theResult___snd_snd__h28177 = + int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 ? + r__h28194 : + r__h28186 ; + assign _theResult___snd_snd__h28577 = + int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 ? + r__h28594 : + r__h28586 ; + assign _theResult___snd_snd__h28977 = + int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 ? + r__h28994 : + r__h28986 ; + assign _theResult___snd_snd__h29377 = + int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 ? + r__h29394 : + r__h29386 ; + assign _theResult___snd_snd__h29777 = + int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 ? + r__h29794 : + r__h29786 ; + assign _theResult___snd_snd__h30177 = + int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 ? + r__h30194 : + r__h30186 ; + assign _theResult___snd_snd__h30577 = + int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 ? + r__h30594 : + r__h30586 ; + assign _theResult___snd_snd__h30977 = + int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 ? + r__h30994 : + r__h30986 ; + assign _theResult___snd_snd__h31377 = + int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 ? + r__h31394 : + r__h31386 ; + assign _theResult___snd_snd__h31777 = + int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 ? + r__h31794 : + r__h31786 ; + assign _theResult___snd_snd__h32177 = + int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 ? + r__h32194 : + r__h32186 ; + assign _theResult___snd_snd__h32577 = + int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 ? + r__h32594 : + r__h32586 ; + assign _theResult___snd_snd__h32977 = + int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 ? + r__h32994 : + r__h32986 ; + assign _theResult___snd_snd__h33377 = + int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 ? + r__h33394 : + r__h33386 ; + assign _theResult___snd_snd__h33777 = + int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 ? + r__h33794 : + r__h33786 ; + assign _theResult___snd_snd__h34177 = + int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 ? + r__h34194 : + r__h34186 ; + assign _theResult___snd_snd__h34577 = + int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 ? + r__h34594 : + r__h34586 ; + assign _theResult___snd_snd__h34977 = + int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 ? + r__h34994 : + r__h34986 ; + assign _theResult___snd_snd__h35377 = + int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 ? + r__h35394 : + r__h35386 ; + assign _theResult___snd_snd__h35777 = + int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 ? + r__h35794 : + r__h35786 ; + assign _theResult___snd_snd__h36177 = + int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 ? + r__h36194 : + r__h36186 ; + assign _theResult___snd_snd__h36577 = + int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 ? + r__h36594 : + r__h36586 ; + assign _theResult___snd_snd__h36977 = + int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 ? + r__h36994 : + r__h36986 ; + assign _theResult___snd_snd__h37377 = + int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 ? + r__h37394 : + r__h37386 ; + assign _theResult___snd_snd__h37777 = + int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 ? + r__h37794 : + r__h37786 ; + assign _theResult___snd_snd__h38177 = + int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 ? + r__h38194 : + r__h38186 ; + assign _theResult___snd_snd__h38577 = + int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 ? + r__h38594 : + r__h38586 ; + assign _theResult___snd_snd__h38977 = + int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 ? + r__h38994 : + r__h38986 ; + assign _theResult___snd_snd__h39377 = + int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 ? + r__h39394 : + r__h39386 ; + assign _theResult___snd_snd__h39777 = + int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 ? + r__h39794 : + r__h39786 ; + assign _theResult___snd_snd__h40177 = + int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 ? + r__h40194 : + r__h40186 ; + assign _theResult___snd_snd__h40577 = + int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 ? + r__h40594 : + r__h40586 ; + assign _theResult___snd_snd__h40977 = + int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 ? + r__h40994 : + r__h40986 ; + assign _theResult___snd_snd__h41377 = + int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 ? + r__h41394 : + r__h41386 ; + assign _theResult___snd_snd__h41777 = + int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 ? + r__h41794 : + r__h41786 ; + assign _theResult___snd_snd__h42177 = + int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 ? + r__h42194 : + r__h42186 ; + assign _theResult___snd_snd__h42577 = + int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 ? + r__h42594 : + r__h42586 ; + assign _theResult___snd_snd__h42977 = + int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 ? + r__h42994 : + r__h42986 ; + assign _theResult___snd_snd__h43377 = + int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 ? + r__h43394 : + r__h43386 ; + assign _theResult___snd_snd__h43777 = + int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 ? + r__h43794 : + r__h43786 ; + assign _theResult___snd_snd__h44177 = + int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 ? + r__h44194 : + r__h44186 ; + assign _theResult___snd_snd__h44577 = + int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 ? + r__h44594 : + r__h44586 ; + assign _theResult___snd_snd__h44977 = + int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 ? + r__h44994 : + r__h44986 ; + assign _theResult___snd_snd__h45377 = + int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 ? + r__h45394 : + r__h45386 ; + assign _theResult___snd_snd__h45777 = + int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 ? + r__h45794 : + r__h45786 ; + assign _theResult___snd_snd__h46177 = + int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 ? + r__h46194 : + r__h46186 ; + assign _theResult___snd_snd__h46577 = + int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 ? + r__h46594 : + r__h46586 ; + assign _theResult___snd_snd__h46977 = + int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 ? + r__h46994 : + r__h46986 ; + assign _theResult___snd_snd__h47377 = + int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 ? + r__h47394 : + r__h47386 ; + assign _theResult___snd_snd__h47777 = + int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 ? + r__h47794 : + r__h47786 ; + assign _theResult___snd_snd__h48177 = + int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 ? + r__h48194 : + r__h48186 ; + assign _theResult___snd_snd__h48577 = + int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 ? + r__h48594 : + r__h48586 ; + assign b___1__h16687 = 116'h40000000000000000000000000000 >> x__h24992 ; + assign b__h25374 = { 2'd0, int_sqrt_fFirst$D_OUT[115:2] } ; + assign b__h25774 = { 2'd0, int_sqrt_fNext_0$D_OUT[115:2] } ; + assign b__h26174 = { 2'd0, int_sqrt_fNext_1$D_OUT[115:2] } ; + assign b__h26574 = { 2'd0, int_sqrt_fNext_2$D_OUT[115:2] } ; + assign b__h26974 = { 2'd0, int_sqrt_fNext_3$D_OUT[115:2] } ; + assign b__h27374 = { 2'd0, int_sqrt_fNext_4$D_OUT[115:2] } ; + assign b__h27774 = { 2'd0, int_sqrt_fNext_5$D_OUT[115:2] } ; + assign b__h28174 = { 2'd0, int_sqrt_fNext_6$D_OUT[115:2] } ; + assign b__h28574 = { 2'd0, int_sqrt_fNext_7$D_OUT[115:2] } ; + assign b__h28974 = { 2'd0, int_sqrt_fNext_8$D_OUT[115:2] } ; + assign b__h29374 = { 2'd0, int_sqrt_fNext_9$D_OUT[115:2] } ; + assign b__h29774 = { 2'd0, int_sqrt_fNext_10$D_OUT[115:2] } ; + assign b__h30174 = { 2'd0, int_sqrt_fNext_11$D_OUT[115:2] } ; + assign b__h30574 = { 2'd0, int_sqrt_fNext_12$D_OUT[115:2] } ; + assign b__h30974 = { 2'd0, int_sqrt_fNext_13$D_OUT[115:2] } ; + assign b__h31374 = { 2'd0, int_sqrt_fNext_14$D_OUT[115:2] } ; + assign b__h31774 = { 2'd0, int_sqrt_fNext_15$D_OUT[115:2] } ; + assign b__h32174 = { 2'd0, int_sqrt_fNext_16$D_OUT[115:2] } ; + assign b__h32574 = { 2'd0, int_sqrt_fNext_17$D_OUT[115:2] } ; + assign b__h32974 = { 2'd0, int_sqrt_fNext_18$D_OUT[115:2] } ; + assign b__h33374 = { 2'd0, int_sqrt_fNext_19$D_OUT[115:2] } ; + assign b__h33774 = { 2'd0, int_sqrt_fNext_20$D_OUT[115:2] } ; + assign b__h34174 = { 2'd0, int_sqrt_fNext_21$D_OUT[115:2] } ; + assign b__h34574 = { 2'd0, int_sqrt_fNext_22$D_OUT[115:2] } ; + assign b__h34974 = { 2'd0, int_sqrt_fNext_23$D_OUT[115:2] } ; + assign b__h35374 = { 2'd0, int_sqrt_fNext_24$D_OUT[115:2] } ; + assign b__h35774 = { 2'd0, int_sqrt_fNext_25$D_OUT[115:2] } ; + assign b__h36174 = { 2'd0, int_sqrt_fNext_26$D_OUT[115:2] } ; + assign b__h36574 = { 2'd0, int_sqrt_fNext_27$D_OUT[115:2] } ; + assign b__h36974 = { 2'd0, int_sqrt_fNext_28$D_OUT[115:2] } ; + assign b__h37374 = { 2'd0, int_sqrt_fNext_29$D_OUT[115:2] } ; + assign b__h37774 = { 2'd0, int_sqrt_fNext_30$D_OUT[115:2] } ; + assign b__h38174 = { 2'd0, int_sqrt_fNext_31$D_OUT[115:2] } ; + assign b__h38574 = { 2'd0, int_sqrt_fNext_32$D_OUT[115:2] } ; + assign b__h38974 = { 2'd0, int_sqrt_fNext_33$D_OUT[115:2] } ; + assign b__h39374 = { 2'd0, int_sqrt_fNext_34$D_OUT[115:2] } ; + assign b__h39774 = { 2'd0, int_sqrt_fNext_35$D_OUT[115:2] } ; + assign b__h40174 = { 2'd0, int_sqrt_fNext_36$D_OUT[115:2] } ; + assign b__h40574 = { 2'd0, int_sqrt_fNext_37$D_OUT[115:2] } ; + assign b__h40974 = { 2'd0, int_sqrt_fNext_38$D_OUT[115:2] } ; + assign b__h41374 = { 2'd0, int_sqrt_fNext_39$D_OUT[115:2] } ; + assign b__h41774 = { 2'd0, int_sqrt_fNext_40$D_OUT[115:2] } ; + assign b__h42174 = { 2'd0, int_sqrt_fNext_41$D_OUT[115:2] } ; + assign b__h42574 = { 2'd0, int_sqrt_fNext_42$D_OUT[115:2] } ; + assign b__h42974 = { 2'd0, int_sqrt_fNext_43$D_OUT[115:2] } ; + assign b__h43374 = { 2'd0, int_sqrt_fNext_44$D_OUT[115:2] } ; + assign b__h43774 = { 2'd0, int_sqrt_fNext_45$D_OUT[115:2] } ; + assign b__h44174 = { 2'd0, int_sqrt_fNext_46$D_OUT[115:2] } ; + assign b__h44574 = { 2'd0, int_sqrt_fNext_47$D_OUT[115:2] } ; + assign b__h44974 = { 2'd0, int_sqrt_fNext_48$D_OUT[115:2] } ; + assign b__h45374 = { 2'd0, int_sqrt_fNext_49$D_OUT[115:2] } ; + assign b__h45774 = { 2'd0, int_sqrt_fNext_50$D_OUT[115:2] } ; + assign b__h46174 = { 2'd0, int_sqrt_fNext_51$D_OUT[115:2] } ; + assign b__h46574 = { 2'd0, int_sqrt_fNext_52$D_OUT[115:2] } ; + assign b__h46974 = { 2'd0, int_sqrt_fNext_53$D_OUT[115:2] } ; + assign b__h47374 = { 2'd0, int_sqrt_fNext_54$D_OUT[115:2] } ; + assign b__h47774 = { 2'd0, int_sqrt_fNext_55$D_OUT[115:2] } ; + assign b__h48174 = { 2'd0, int_sqrt_fNext_56$D_OUT[115:2] } ; + assign b__h48574 = { 2'd0, int_sqrt_fNext_57$D_OUT[115:2] } ; + assign b__h48712 = + int_sqrt_fNext_58$D_OUT[464] ? + int_sqrt_fNext_58$D_OUT[463:348] : + 116'd0 ; + assign din_inc___2_exp__h76519 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; + assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 = + fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; + assign fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 = + fpu_fState_S3$D_OUT[121:111] - 11'd1023 ; + assign guard__h66951 = x__h75654 ; + assign int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 = + int_sqrt_fFirst$D_OUT[347:232] < sum__h25372 ; + assign int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 = + int_sqrt_fNext_0$D_OUT[347:232] < sum__h25772 ; + assign int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 = + int_sqrt_fNext_10$D_OUT[347:232] < sum__h29772 ; + assign int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 = + int_sqrt_fNext_11$D_OUT[347:232] < sum__h30172 ; + assign int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 = + int_sqrt_fNext_12$D_OUT[347:232] < sum__h30572 ; + assign int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 = + int_sqrt_fNext_13$D_OUT[347:232] < sum__h30972 ; + assign int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 = + int_sqrt_fNext_14$D_OUT[347:232] < sum__h31372 ; + assign int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 = + int_sqrt_fNext_15$D_OUT[347:232] < sum__h31772 ; + assign int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 = + int_sqrt_fNext_16$D_OUT[347:232] < sum__h32172 ; + assign int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 = + int_sqrt_fNext_17$D_OUT[347:232] < sum__h32572 ; + assign int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 = + int_sqrt_fNext_18$D_OUT[347:232] < sum__h32972 ; + assign int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 = + int_sqrt_fNext_19$D_OUT[347:232] < sum__h33372 ; + assign int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 = + int_sqrt_fNext_1$D_OUT[347:232] < sum__h26172 ; + assign int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 = + int_sqrt_fNext_20$D_OUT[347:232] < sum__h33772 ; + assign int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 = + int_sqrt_fNext_21$D_OUT[347:232] < sum__h34172 ; + assign int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 = + int_sqrt_fNext_22$D_OUT[347:232] < sum__h34572 ; + assign int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 = + int_sqrt_fNext_23$D_OUT[347:232] < sum__h34972 ; + assign int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 = + int_sqrt_fNext_24$D_OUT[347:232] < sum__h35372 ; + assign int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 = + int_sqrt_fNext_25$D_OUT[347:232] < sum__h35772 ; + assign int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 = + int_sqrt_fNext_26$D_OUT[347:232] < sum__h36172 ; + assign int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 = + int_sqrt_fNext_27$D_OUT[347:232] < sum__h36572 ; + assign int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 = + int_sqrt_fNext_28$D_OUT[347:232] < sum__h36972 ; + assign int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 = + int_sqrt_fNext_29$D_OUT[347:232] < sum__h37372 ; + assign int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 = + int_sqrt_fNext_2$D_OUT[347:232] < sum__h26572 ; + assign int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 = + int_sqrt_fNext_30$D_OUT[347:232] < sum__h37772 ; + assign int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 = + int_sqrt_fNext_31$D_OUT[347:232] < sum__h38172 ; + assign int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 = + int_sqrt_fNext_32$D_OUT[347:232] < sum__h38572 ; + assign int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 = + int_sqrt_fNext_33$D_OUT[347:232] < sum__h38972 ; + assign int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 = + int_sqrt_fNext_34$D_OUT[347:232] < sum__h39372 ; + assign int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 = + int_sqrt_fNext_35$D_OUT[347:232] < sum__h39772 ; + assign int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 = + int_sqrt_fNext_36$D_OUT[347:232] < sum__h40172 ; + assign int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 = + int_sqrt_fNext_37$D_OUT[347:232] < sum__h40572 ; + assign int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 = + int_sqrt_fNext_38$D_OUT[347:232] < sum__h40972 ; + assign int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 = + int_sqrt_fNext_39$D_OUT[347:232] < sum__h41372 ; + assign int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 = + int_sqrt_fNext_3$D_OUT[347:232] < sum__h26972 ; + assign int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 = + int_sqrt_fNext_40$D_OUT[347:232] < sum__h41772 ; + assign int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 = + int_sqrt_fNext_41$D_OUT[347:232] < sum__h42172 ; + assign int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 = + int_sqrt_fNext_42$D_OUT[347:232] < sum__h42572 ; + assign int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 = + int_sqrt_fNext_43$D_OUT[347:232] < sum__h42972 ; + assign int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 = + int_sqrt_fNext_44$D_OUT[347:232] < sum__h43372 ; + assign int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 = + int_sqrt_fNext_45$D_OUT[347:232] < sum__h43772 ; + assign int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 = + int_sqrt_fNext_46$D_OUT[347:232] < sum__h44172 ; + assign int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 = + int_sqrt_fNext_47$D_OUT[347:232] < sum__h44572 ; + assign int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 = + int_sqrt_fNext_48$D_OUT[347:232] < sum__h44972 ; + assign int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 = + int_sqrt_fNext_49$D_OUT[347:232] < sum__h45372 ; + assign int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 = + int_sqrt_fNext_4$D_OUT[347:232] < sum__h27372 ; + assign int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 = + int_sqrt_fNext_50$D_OUT[347:232] < sum__h45772 ; + assign int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 = + int_sqrt_fNext_51$D_OUT[347:232] < sum__h46172 ; + assign int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 = + int_sqrt_fNext_52$D_OUT[347:232] < sum__h46572 ; + assign int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 = + int_sqrt_fNext_53$D_OUT[347:232] < sum__h46972 ; + assign int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 = + int_sqrt_fNext_54$D_OUT[347:232] < sum__h47372 ; + assign int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 = + int_sqrt_fNext_55$D_OUT[347:232] < sum__h47772 ; + assign int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 = + int_sqrt_fNext_56$D_OUT[347:232] < sum__h48172 ; + assign int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 = + int_sqrt_fNext_57$D_OUT[347:232] < sum__h48572 ; + assign int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 = + int_sqrt_fNext_5$D_OUT[347:232] < sum__h27772 ; + assign int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 = + int_sqrt_fNext_6$D_OUT[347:232] < sum__h28172 ; + assign int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 = + int_sqrt_fNext_7$D_OUT[347:232] < sum__h28572 ; + assign int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 = + int_sqrt_fNext_8$D_OUT[347:232] < sum__h28972 ; + assign int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 = + int_sqrt_fNext_9$D_OUT[347:232] < sum__h29372 ; + assign out_exp__h76431 = + fpu_fState_S4$D_OUT[2] ? + _theResult___exp__h76428 : + fpu_fState_S4$D_OUT[64:54] ; + assign out_sfd__h76432 = + fpu_fState_S4$D_OUT[2] ? + _theResult___sfd__h76429 : + fpu_fState_S4$D_OUT[53:2] ; + assign r__h25386 = r__h25394 + int_sqrt_fFirst$D_OUT[115:0] ; + assign r__h25394 = { 1'd0, int_sqrt_fFirst$D_OUT[231:117] } ; + assign r__h25786 = r__h25794 + int_sqrt_fNext_0$D_OUT[115:0] ; + assign r__h25794 = { 1'd0, int_sqrt_fNext_0$D_OUT[231:117] } ; + assign r__h26186 = r__h26194 + int_sqrt_fNext_1$D_OUT[115:0] ; + assign r__h26194 = { 1'd0, int_sqrt_fNext_1$D_OUT[231:117] } ; + assign r__h26586 = r__h26594 + int_sqrt_fNext_2$D_OUT[115:0] ; + assign r__h26594 = { 1'd0, int_sqrt_fNext_2$D_OUT[231:117] } ; + assign r__h26986 = r__h26994 + int_sqrt_fNext_3$D_OUT[115:0] ; + assign r__h26994 = { 1'd0, int_sqrt_fNext_3$D_OUT[231:117] } ; + assign r__h27386 = r__h27394 + int_sqrt_fNext_4$D_OUT[115:0] ; + assign r__h27394 = { 1'd0, int_sqrt_fNext_4$D_OUT[231:117] } ; + assign r__h27786 = r__h27794 + int_sqrt_fNext_5$D_OUT[115:0] ; + assign r__h27794 = { 1'd0, int_sqrt_fNext_5$D_OUT[231:117] } ; + assign r__h28186 = r__h28194 + int_sqrt_fNext_6$D_OUT[115:0] ; + assign r__h28194 = { 1'd0, int_sqrt_fNext_6$D_OUT[231:117] } ; + assign r__h28586 = r__h28594 + int_sqrt_fNext_7$D_OUT[115:0] ; + assign r__h28594 = { 1'd0, int_sqrt_fNext_7$D_OUT[231:117] } ; + assign r__h28986 = r__h28994 + int_sqrt_fNext_8$D_OUT[115:0] ; + assign r__h28994 = { 1'd0, int_sqrt_fNext_8$D_OUT[231:117] } ; + assign r__h29386 = r__h29394 + int_sqrt_fNext_9$D_OUT[115:0] ; + assign r__h29394 = { 1'd0, int_sqrt_fNext_9$D_OUT[231:117] } ; + assign r__h29786 = r__h29794 + int_sqrt_fNext_10$D_OUT[115:0] ; + assign r__h29794 = { 1'd0, int_sqrt_fNext_10$D_OUT[231:117] } ; + assign r__h30186 = r__h30194 + int_sqrt_fNext_11$D_OUT[115:0] ; + assign r__h30194 = { 1'd0, int_sqrt_fNext_11$D_OUT[231:117] } ; + assign r__h30586 = r__h30594 + int_sqrt_fNext_12$D_OUT[115:0] ; + assign r__h30594 = { 1'd0, int_sqrt_fNext_12$D_OUT[231:117] } ; + assign r__h30986 = r__h30994 + int_sqrt_fNext_13$D_OUT[115:0] ; + assign r__h30994 = { 1'd0, int_sqrt_fNext_13$D_OUT[231:117] } ; + assign r__h31386 = r__h31394 + int_sqrt_fNext_14$D_OUT[115:0] ; + assign r__h31394 = { 1'd0, int_sqrt_fNext_14$D_OUT[231:117] } ; + assign r__h31786 = r__h31794 + int_sqrt_fNext_15$D_OUT[115:0] ; + assign r__h31794 = { 1'd0, int_sqrt_fNext_15$D_OUT[231:117] } ; + assign r__h32186 = r__h32194 + int_sqrt_fNext_16$D_OUT[115:0] ; + assign r__h32194 = { 1'd0, int_sqrt_fNext_16$D_OUT[231:117] } ; + assign r__h32586 = r__h32594 + int_sqrt_fNext_17$D_OUT[115:0] ; + assign r__h32594 = { 1'd0, int_sqrt_fNext_17$D_OUT[231:117] } ; + assign r__h32986 = r__h32994 + int_sqrt_fNext_18$D_OUT[115:0] ; + assign r__h32994 = { 1'd0, int_sqrt_fNext_18$D_OUT[231:117] } ; + assign r__h33386 = r__h33394 + int_sqrt_fNext_19$D_OUT[115:0] ; + assign r__h33394 = { 1'd0, int_sqrt_fNext_19$D_OUT[231:117] } ; + assign r__h33786 = r__h33794 + int_sqrt_fNext_20$D_OUT[115:0] ; + assign r__h33794 = { 1'd0, int_sqrt_fNext_20$D_OUT[231:117] } ; + assign r__h34186 = r__h34194 + int_sqrt_fNext_21$D_OUT[115:0] ; + assign r__h34194 = { 1'd0, int_sqrt_fNext_21$D_OUT[231:117] } ; + assign r__h34586 = r__h34594 + int_sqrt_fNext_22$D_OUT[115:0] ; + assign r__h34594 = { 1'd0, int_sqrt_fNext_22$D_OUT[231:117] } ; + assign r__h34986 = r__h34994 + int_sqrt_fNext_23$D_OUT[115:0] ; + assign r__h34994 = { 1'd0, int_sqrt_fNext_23$D_OUT[231:117] } ; + assign r__h35386 = r__h35394 + int_sqrt_fNext_24$D_OUT[115:0] ; + assign r__h35394 = { 1'd0, int_sqrt_fNext_24$D_OUT[231:117] } ; + assign r__h35786 = r__h35794 + int_sqrt_fNext_25$D_OUT[115:0] ; + assign r__h35794 = { 1'd0, int_sqrt_fNext_25$D_OUT[231:117] } ; + assign r__h36186 = r__h36194 + int_sqrt_fNext_26$D_OUT[115:0] ; + assign r__h36194 = { 1'd0, int_sqrt_fNext_26$D_OUT[231:117] } ; + assign r__h36586 = r__h36594 + int_sqrt_fNext_27$D_OUT[115:0] ; + assign r__h36594 = { 1'd0, int_sqrt_fNext_27$D_OUT[231:117] } ; + assign r__h36986 = r__h36994 + int_sqrt_fNext_28$D_OUT[115:0] ; + assign r__h36994 = { 1'd0, int_sqrt_fNext_28$D_OUT[231:117] } ; + assign r__h37386 = r__h37394 + int_sqrt_fNext_29$D_OUT[115:0] ; + assign r__h37394 = { 1'd0, int_sqrt_fNext_29$D_OUT[231:117] } ; + assign r__h37786 = r__h37794 + int_sqrt_fNext_30$D_OUT[115:0] ; + assign r__h37794 = { 1'd0, int_sqrt_fNext_30$D_OUT[231:117] } ; + assign r__h38186 = r__h38194 + int_sqrt_fNext_31$D_OUT[115:0] ; + assign r__h38194 = { 1'd0, int_sqrt_fNext_31$D_OUT[231:117] } ; + assign r__h38586 = r__h38594 + int_sqrt_fNext_32$D_OUT[115:0] ; + assign r__h38594 = { 1'd0, int_sqrt_fNext_32$D_OUT[231:117] } ; + assign r__h38986 = r__h38994 + int_sqrt_fNext_33$D_OUT[115:0] ; + assign r__h38994 = { 1'd0, int_sqrt_fNext_33$D_OUT[231:117] } ; + assign r__h39386 = r__h39394 + int_sqrt_fNext_34$D_OUT[115:0] ; + assign r__h39394 = { 1'd0, int_sqrt_fNext_34$D_OUT[231:117] } ; + assign r__h39786 = r__h39794 + int_sqrt_fNext_35$D_OUT[115:0] ; + assign r__h39794 = { 1'd0, int_sqrt_fNext_35$D_OUT[231:117] } ; + assign r__h40186 = r__h40194 + int_sqrt_fNext_36$D_OUT[115:0] ; + assign r__h40194 = { 1'd0, int_sqrt_fNext_36$D_OUT[231:117] } ; + assign r__h40586 = r__h40594 + int_sqrt_fNext_37$D_OUT[115:0] ; + assign r__h40594 = { 1'd0, int_sqrt_fNext_37$D_OUT[231:117] } ; + assign r__h40986 = r__h40994 + int_sqrt_fNext_38$D_OUT[115:0] ; + assign r__h40994 = { 1'd0, int_sqrt_fNext_38$D_OUT[231:117] } ; + assign r__h41386 = r__h41394 + int_sqrt_fNext_39$D_OUT[115:0] ; + assign r__h41394 = { 1'd0, int_sqrt_fNext_39$D_OUT[231:117] } ; + assign r__h41786 = r__h41794 + int_sqrt_fNext_40$D_OUT[115:0] ; + assign r__h41794 = { 1'd0, int_sqrt_fNext_40$D_OUT[231:117] } ; + assign r__h42186 = r__h42194 + int_sqrt_fNext_41$D_OUT[115:0] ; + assign r__h42194 = { 1'd0, int_sqrt_fNext_41$D_OUT[231:117] } ; + assign r__h42586 = r__h42594 + int_sqrt_fNext_42$D_OUT[115:0] ; + assign r__h42594 = { 1'd0, int_sqrt_fNext_42$D_OUT[231:117] } ; + assign r__h42986 = r__h42994 + int_sqrt_fNext_43$D_OUT[115:0] ; + assign r__h42994 = { 1'd0, int_sqrt_fNext_43$D_OUT[231:117] } ; + assign r__h43386 = r__h43394 + int_sqrt_fNext_44$D_OUT[115:0] ; + assign r__h43394 = { 1'd0, int_sqrt_fNext_44$D_OUT[231:117] } ; + assign r__h43786 = r__h43794 + int_sqrt_fNext_45$D_OUT[115:0] ; + assign r__h43794 = { 1'd0, int_sqrt_fNext_45$D_OUT[231:117] } ; + assign r__h44186 = r__h44194 + int_sqrt_fNext_46$D_OUT[115:0] ; + assign r__h44194 = { 1'd0, int_sqrt_fNext_46$D_OUT[231:117] } ; + assign r__h44586 = r__h44594 + int_sqrt_fNext_47$D_OUT[115:0] ; + assign r__h44594 = { 1'd0, int_sqrt_fNext_47$D_OUT[231:117] } ; + assign r__h44986 = r__h44994 + int_sqrt_fNext_48$D_OUT[115:0] ; + assign r__h44994 = { 1'd0, int_sqrt_fNext_48$D_OUT[231:117] } ; + assign r__h45386 = r__h45394 + int_sqrt_fNext_49$D_OUT[115:0] ; + assign r__h45394 = { 1'd0, int_sqrt_fNext_49$D_OUT[231:117] } ; + assign r__h45786 = r__h45794 + int_sqrt_fNext_50$D_OUT[115:0] ; + assign r__h45794 = { 1'd0, int_sqrt_fNext_50$D_OUT[231:117] } ; + assign r__h46186 = r__h46194 + int_sqrt_fNext_51$D_OUT[115:0] ; + assign r__h46194 = { 1'd0, int_sqrt_fNext_51$D_OUT[231:117] } ; + assign r__h46586 = r__h46594 + int_sqrt_fNext_52$D_OUT[115:0] ; + assign r__h46594 = { 1'd0, int_sqrt_fNext_52$D_OUT[231:117] } ; + assign r__h46986 = r__h46994 + int_sqrt_fNext_53$D_OUT[115:0] ; + assign r__h46994 = { 1'd0, int_sqrt_fNext_53$D_OUT[231:117] } ; + assign r__h47386 = r__h47394 + int_sqrt_fNext_54$D_OUT[115:0] ; + assign r__h47394 = { 1'd0, int_sqrt_fNext_54$D_OUT[231:117] } ; + assign r__h47786 = r__h47794 + int_sqrt_fNext_55$D_OUT[115:0] ; + assign r__h47794 = { 1'd0, int_sqrt_fNext_55$D_OUT[231:117] } ; + assign r__h48186 = r__h48194 + int_sqrt_fNext_56$D_OUT[115:0] ; + assign r__h48194 = { 1'd0, int_sqrt_fNext_56$D_OUT[231:117] } ; + assign r__h48586 = r__h48594 + int_sqrt_fNext_57$D_OUT[115:0] ; + assign r__h48594 = { 1'd0, int_sqrt_fNext_57$D_OUT[231:117] } ; + assign result__h66451 = { int_sqrt_fResponse$D_OUT[59:2], 1'd1 } ; + assign s__h25385 = int_sqrt_fFirst$D_OUT[347:232] - sum__h25372 ; + assign s__h25785 = int_sqrt_fNext_0$D_OUT[347:232] - sum__h25772 ; + assign s__h26185 = int_sqrt_fNext_1$D_OUT[347:232] - sum__h26172 ; + assign s__h26585 = int_sqrt_fNext_2$D_OUT[347:232] - sum__h26572 ; + assign s__h26985 = int_sqrt_fNext_3$D_OUT[347:232] - sum__h26972 ; + assign s__h27385 = int_sqrt_fNext_4$D_OUT[347:232] - sum__h27372 ; + assign s__h27785 = int_sqrt_fNext_5$D_OUT[347:232] - sum__h27772 ; + assign s__h28185 = int_sqrt_fNext_6$D_OUT[347:232] - sum__h28172 ; + assign s__h28585 = int_sqrt_fNext_7$D_OUT[347:232] - sum__h28572 ; + assign s__h28985 = int_sqrt_fNext_8$D_OUT[347:232] - sum__h28972 ; + assign s__h29385 = int_sqrt_fNext_9$D_OUT[347:232] - sum__h29372 ; + assign s__h29785 = int_sqrt_fNext_10$D_OUT[347:232] - sum__h29772 ; + assign s__h30185 = int_sqrt_fNext_11$D_OUT[347:232] - sum__h30172 ; + assign s__h30585 = int_sqrt_fNext_12$D_OUT[347:232] - sum__h30572 ; + assign s__h30985 = int_sqrt_fNext_13$D_OUT[347:232] - sum__h30972 ; + assign s__h31385 = int_sqrt_fNext_14$D_OUT[347:232] - sum__h31372 ; + assign s__h31785 = int_sqrt_fNext_15$D_OUT[347:232] - sum__h31772 ; + assign s__h32185 = int_sqrt_fNext_16$D_OUT[347:232] - sum__h32172 ; + assign s__h32585 = int_sqrt_fNext_17$D_OUT[347:232] - sum__h32572 ; + assign s__h32985 = int_sqrt_fNext_18$D_OUT[347:232] - sum__h32972 ; + assign s__h33385 = int_sqrt_fNext_19$D_OUT[347:232] - sum__h33372 ; + assign s__h33785 = int_sqrt_fNext_20$D_OUT[347:232] - sum__h33772 ; + assign s__h34185 = int_sqrt_fNext_21$D_OUT[347:232] - sum__h34172 ; + assign s__h34585 = int_sqrt_fNext_22$D_OUT[347:232] - sum__h34572 ; + assign s__h34985 = int_sqrt_fNext_23$D_OUT[347:232] - sum__h34972 ; + assign s__h35385 = int_sqrt_fNext_24$D_OUT[347:232] - sum__h35372 ; + assign s__h35785 = int_sqrt_fNext_25$D_OUT[347:232] - sum__h35772 ; + assign s__h36185 = int_sqrt_fNext_26$D_OUT[347:232] - sum__h36172 ; + assign s__h36585 = int_sqrt_fNext_27$D_OUT[347:232] - sum__h36572 ; + assign s__h36985 = int_sqrt_fNext_28$D_OUT[347:232] - sum__h36972 ; + assign s__h37385 = int_sqrt_fNext_29$D_OUT[347:232] - sum__h37372 ; + assign s__h37785 = int_sqrt_fNext_30$D_OUT[347:232] - sum__h37772 ; + assign s__h38185 = int_sqrt_fNext_31$D_OUT[347:232] - sum__h38172 ; + assign s__h38585 = int_sqrt_fNext_32$D_OUT[347:232] - sum__h38572 ; + assign s__h38985 = int_sqrt_fNext_33$D_OUT[347:232] - sum__h38972 ; + assign s__h39385 = int_sqrt_fNext_34$D_OUT[347:232] - sum__h39372 ; + assign s__h39785 = int_sqrt_fNext_35$D_OUT[347:232] - sum__h39772 ; + assign s__h40185 = int_sqrt_fNext_36$D_OUT[347:232] - sum__h40172 ; + assign s__h40585 = int_sqrt_fNext_37$D_OUT[347:232] - sum__h40572 ; + assign s__h40985 = int_sqrt_fNext_38$D_OUT[347:232] - sum__h40972 ; + assign s__h41385 = int_sqrt_fNext_39$D_OUT[347:232] - sum__h41372 ; + assign s__h41785 = int_sqrt_fNext_40$D_OUT[347:232] - sum__h41772 ; + assign s__h42185 = int_sqrt_fNext_41$D_OUT[347:232] - sum__h42172 ; + assign s__h42585 = int_sqrt_fNext_42$D_OUT[347:232] - sum__h42572 ; + assign s__h42985 = int_sqrt_fNext_43$D_OUT[347:232] - sum__h42972 ; + assign s__h43385 = int_sqrt_fNext_44$D_OUT[347:232] - sum__h43372 ; + assign s__h43785 = int_sqrt_fNext_45$D_OUT[347:232] - sum__h43772 ; + assign s__h44185 = int_sqrt_fNext_46$D_OUT[347:232] - sum__h44172 ; + assign s__h44585 = int_sqrt_fNext_47$D_OUT[347:232] - sum__h44572 ; + assign s__h44985 = int_sqrt_fNext_48$D_OUT[347:232] - sum__h44972 ; + assign s__h45385 = int_sqrt_fNext_49$D_OUT[347:232] - sum__h45372 ; + assign s__h45785 = int_sqrt_fNext_50$D_OUT[347:232] - sum__h45772 ; + assign s__h46185 = int_sqrt_fNext_51$D_OUT[347:232] - sum__h46172 ; + assign s__h46585 = int_sqrt_fNext_52$D_OUT[347:232] - sum__h46572 ; + assign s__h46985 = int_sqrt_fNext_53$D_OUT[347:232] - sum__h46972 ; + assign s__h47385 = int_sqrt_fNext_54$D_OUT[347:232] - sum__h47372 ; + assign s__h47785 = int_sqrt_fNext_55$D_OUT[347:232] - sum__h47772 ; + assign s__h48185 = int_sqrt_fNext_56$D_OUT[347:232] - sum__h48172 ; + assign s__h48585 = int_sqrt_fNext_57$D_OUT[347:232] - sum__h48572 ; + assign sfd___1__h65692 = { 1'd0, sfd__h49938[57:1] } ; + assign sfd__h49936 = { value__h58164, 4'd0 } ; + assign sfd__h49938 = sfd__h49936 << x__h65722 ; + assign sfd__h49989 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; + assign sfd__h75932 = + { 1'b0, + fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:2] } + + 54'd1 ; + assign sfdin__h75260 = + fpu_fState_S3$D_OUT[58] ? + _theResult___snd__h75283 : + _theResult___snd__h75298 ; + assign sum__h25372 = + int_sqrt_fFirst$D_OUT[231:116] + int_sqrt_fFirst$D_OUT[115:0] ; + assign sum__h25772 = + int_sqrt_fNext_0$D_OUT[231:116] + int_sqrt_fNext_0$D_OUT[115:0] ; + assign sum__h26172 = + int_sqrt_fNext_1$D_OUT[231:116] + int_sqrt_fNext_1$D_OUT[115:0] ; + assign sum__h26572 = + int_sqrt_fNext_2$D_OUT[231:116] + int_sqrt_fNext_2$D_OUT[115:0] ; + assign sum__h26972 = + int_sqrt_fNext_3$D_OUT[231:116] + int_sqrt_fNext_3$D_OUT[115:0] ; + assign sum__h27372 = + int_sqrt_fNext_4$D_OUT[231:116] + int_sqrt_fNext_4$D_OUT[115:0] ; + assign sum__h27772 = + int_sqrt_fNext_5$D_OUT[231:116] + int_sqrt_fNext_5$D_OUT[115:0] ; + assign sum__h28172 = + int_sqrt_fNext_6$D_OUT[231:116] + int_sqrt_fNext_6$D_OUT[115:0] ; + assign sum__h28572 = + int_sqrt_fNext_7$D_OUT[231:116] + int_sqrt_fNext_7$D_OUT[115:0] ; + assign sum__h28972 = + int_sqrt_fNext_8$D_OUT[231:116] + int_sqrt_fNext_8$D_OUT[115:0] ; + assign sum__h29372 = + int_sqrt_fNext_9$D_OUT[231:116] + int_sqrt_fNext_9$D_OUT[115:0] ; + assign sum__h29772 = + int_sqrt_fNext_10$D_OUT[231:116] + + int_sqrt_fNext_10$D_OUT[115:0] ; + assign sum__h30172 = + int_sqrt_fNext_11$D_OUT[231:116] + + int_sqrt_fNext_11$D_OUT[115:0] ; + assign sum__h30572 = + int_sqrt_fNext_12$D_OUT[231:116] + + int_sqrt_fNext_12$D_OUT[115:0] ; + assign sum__h30972 = + int_sqrt_fNext_13$D_OUT[231:116] + + int_sqrt_fNext_13$D_OUT[115:0] ; + assign sum__h31372 = + int_sqrt_fNext_14$D_OUT[231:116] + + int_sqrt_fNext_14$D_OUT[115:0] ; + assign sum__h31772 = + int_sqrt_fNext_15$D_OUT[231:116] + + int_sqrt_fNext_15$D_OUT[115:0] ; + assign sum__h32172 = + int_sqrt_fNext_16$D_OUT[231:116] + + int_sqrt_fNext_16$D_OUT[115:0] ; + assign sum__h32572 = + int_sqrt_fNext_17$D_OUT[231:116] + + int_sqrt_fNext_17$D_OUT[115:0] ; + assign sum__h32972 = + int_sqrt_fNext_18$D_OUT[231:116] + + int_sqrt_fNext_18$D_OUT[115:0] ; + assign sum__h33372 = + int_sqrt_fNext_19$D_OUT[231:116] + + int_sqrt_fNext_19$D_OUT[115:0] ; + assign sum__h33772 = + int_sqrt_fNext_20$D_OUT[231:116] + + int_sqrt_fNext_20$D_OUT[115:0] ; + assign sum__h34172 = + int_sqrt_fNext_21$D_OUT[231:116] + + int_sqrt_fNext_21$D_OUT[115:0] ; + assign sum__h34572 = + int_sqrt_fNext_22$D_OUT[231:116] + + int_sqrt_fNext_22$D_OUT[115:0] ; + assign sum__h34972 = + int_sqrt_fNext_23$D_OUT[231:116] + + int_sqrt_fNext_23$D_OUT[115:0] ; + assign sum__h35372 = + int_sqrt_fNext_24$D_OUT[231:116] + + int_sqrt_fNext_24$D_OUT[115:0] ; + assign sum__h35772 = + int_sqrt_fNext_25$D_OUT[231:116] + + int_sqrt_fNext_25$D_OUT[115:0] ; + assign sum__h36172 = + int_sqrt_fNext_26$D_OUT[231:116] + + int_sqrt_fNext_26$D_OUT[115:0] ; + assign sum__h36572 = + int_sqrt_fNext_27$D_OUT[231:116] + + int_sqrt_fNext_27$D_OUT[115:0] ; + assign sum__h36972 = + int_sqrt_fNext_28$D_OUT[231:116] + + int_sqrt_fNext_28$D_OUT[115:0] ; + assign sum__h37372 = + int_sqrt_fNext_29$D_OUT[231:116] + + int_sqrt_fNext_29$D_OUT[115:0] ; + assign sum__h37772 = + int_sqrt_fNext_30$D_OUT[231:116] + + int_sqrt_fNext_30$D_OUT[115:0] ; + assign sum__h38172 = + int_sqrt_fNext_31$D_OUT[231:116] + + int_sqrt_fNext_31$D_OUT[115:0] ; + assign sum__h38572 = + int_sqrt_fNext_32$D_OUT[231:116] + + int_sqrt_fNext_32$D_OUT[115:0] ; + assign sum__h38972 = + int_sqrt_fNext_33$D_OUT[231:116] + + int_sqrt_fNext_33$D_OUT[115:0] ; + assign sum__h39372 = + int_sqrt_fNext_34$D_OUT[231:116] + + int_sqrt_fNext_34$D_OUT[115:0] ; + assign sum__h39772 = + int_sqrt_fNext_35$D_OUT[231:116] + + int_sqrt_fNext_35$D_OUT[115:0] ; + assign sum__h40172 = + int_sqrt_fNext_36$D_OUT[231:116] + + int_sqrt_fNext_36$D_OUT[115:0] ; + assign sum__h40572 = + int_sqrt_fNext_37$D_OUT[231:116] + + int_sqrt_fNext_37$D_OUT[115:0] ; + assign sum__h40972 = + int_sqrt_fNext_38$D_OUT[231:116] + + int_sqrt_fNext_38$D_OUT[115:0] ; + assign sum__h41372 = + int_sqrt_fNext_39$D_OUT[231:116] + + int_sqrt_fNext_39$D_OUT[115:0] ; + assign sum__h41772 = + int_sqrt_fNext_40$D_OUT[231:116] + + int_sqrt_fNext_40$D_OUT[115:0] ; + assign sum__h42172 = + int_sqrt_fNext_41$D_OUT[231:116] + + int_sqrt_fNext_41$D_OUT[115:0] ; + assign sum__h42572 = + int_sqrt_fNext_42$D_OUT[231:116] + + int_sqrt_fNext_42$D_OUT[115:0] ; + assign sum__h42972 = + int_sqrt_fNext_43$D_OUT[231:116] + + int_sqrt_fNext_43$D_OUT[115:0] ; + assign sum__h43372 = + int_sqrt_fNext_44$D_OUT[231:116] + + int_sqrt_fNext_44$D_OUT[115:0] ; + assign sum__h43772 = + int_sqrt_fNext_45$D_OUT[231:116] + + int_sqrt_fNext_45$D_OUT[115:0] ; + assign sum__h44172 = + int_sqrt_fNext_46$D_OUT[231:116] + + int_sqrt_fNext_46$D_OUT[115:0] ; + assign sum__h44572 = + int_sqrt_fNext_47$D_OUT[231:116] + + int_sqrt_fNext_47$D_OUT[115:0] ; + assign sum__h44972 = + int_sqrt_fNext_48$D_OUT[231:116] + + int_sqrt_fNext_48$D_OUT[115:0] ; + assign sum__h45372 = + int_sqrt_fNext_49$D_OUT[231:116] + + int_sqrt_fNext_49$D_OUT[115:0] ; + assign sum__h45772 = + int_sqrt_fNext_50$D_OUT[231:116] + + int_sqrt_fNext_50$D_OUT[115:0] ; + assign sum__h46172 = + int_sqrt_fNext_51$D_OUT[231:116] + + int_sqrt_fNext_51$D_OUT[115:0] ; + assign sum__h46572 = + int_sqrt_fNext_52$D_OUT[231:116] + + int_sqrt_fNext_52$D_OUT[115:0] ; + assign sum__h46972 = + int_sqrt_fNext_53$D_OUT[231:116] + + int_sqrt_fNext_53$D_OUT[115:0] ; + assign sum__h47372 = + int_sqrt_fNext_54$D_OUT[231:116] + + int_sqrt_fNext_54$D_OUT[115:0] ; + assign sum__h47772 = + int_sqrt_fNext_55$D_OUT[231:116] + + int_sqrt_fNext_55$D_OUT[115:0] ; + assign sum__h48172 = + int_sqrt_fNext_56$D_OUT[231:116] + + int_sqrt_fNext_56$D_OUT[115:0] ; + assign sum__h48572 = + int_sqrt_fNext_57$D_OUT[231:116] + + int_sqrt_fNext_57$D_OUT[115:0] ; + assign value_BIT_52___h58260 = fpu_fOperand_S0$D_OUT[65:55] != 11'd0 ; + assign value__h58164 = + { 1'b0, value_BIT_52___h58260, fpu_fOperand_S0$D_OUT[54:3] } ; + assign x__h24992 = + IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237[0] ? + IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 + + 7'd1 : + IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 ; + assign x__h402 = + int_sqrt_fRequest$D_OUT[115] ? + 116'h40000000000000000000000000000 : + b___1__h16687 ; + assign x__h57541 = x__h57559 + 13'd1024 ; + assign x__h57559 = + { IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9[11], + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 } ; + assign x__h65683 = + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[0] ? + sfd__h49938 : + sfd___1__h65692 ; + assign x__h65722 = + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 - + 6'd1 ; + assign x__h66665 = + int_sqrt_fResponse$D_OUT[0] ? + result__h66451 : + int_sqrt_fResponse$D_OUT[59:1] ; + assign x__h75654 = + (fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h75372 ; + always@(fpu_fState_S4$D_OUT or out_sfd__h76432 or _theResult___sfd__h76429) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + fpu_fState_S4$D_OUT[53:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + out_sfd__h76432; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + _theResult___sfd__h76429; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___sfd__h76429) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + fpu_fState_S4$D_OUT[53:2]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + _theResult___sfd__h76429; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or + _theResult___sfd__h76429) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_sfd__h76507 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; + 3'd1: + _theResult___fst_sfd__h76507 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; + 3'd2: + _theResult___fst_sfd__h76507 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___sfd__h76429; + 3'd3: + _theResult___fst_sfd__h76507 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[53:2] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___sfd__h76429 : + fpu_fState_S4$D_OUT[53:2]); + 3'd4: _theResult___fst_sfd__h76507 = fpu_fState_S4$D_OUT[53:2]; + default: _theResult___fst_sfd__h76507 = 52'd0; + endcase + end + always@(fpu_fState_S4$D_OUT or out_exp__h76431 or _theResult___exp__h76428) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = + fpu_fState_S4$D_OUT[64:54]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = + out_exp__h76431; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = + _theResult___exp__h76428; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___exp__h76428) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = + fpu_fState_S4$D_OUT[64:54]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = + _theResult___exp__h76428; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 or + _theResult___exp__h76428) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_exp__h76506 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3; + 3'd1: + _theResult___fst_exp__h76506 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4; + 3'd2: + _theResult___fst_exp__h76506 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___exp__h76428; + 3'd3: + _theResult___fst_exp__h76506 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:54] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___exp__h76428 : + fpu_fState_S4$D_OUT[64:54]); + 3'd4: _theResult___fst_exp__h76506 = fpu_fState_S4$D_OUT[64:54]; + default: _theResult___fst_exp__h76506 = 11'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2, 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = + fpu_fState_S4$D_OUT[65]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = + fpu_fState_S4$D_OUT[68:66] == 3'd4 && + fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:2] : + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; + 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:2] : + (fpu_fState_S4$D_OUT[65] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : + fpu_fState_S4$D_OUT[64:2]); + 3'd4: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = + fpu_fState_S4$D_OUT[64:2]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = 63'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01, 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = + fpu_fState_S4$D_OUT[65]; + 2'd3: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = + fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[64:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[2] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : + fpu_fState_S4$D_OUT[64:2]; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = 63'd0; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = + { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 }; + 3'd1: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[65:2] : + { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || + fpu_fState_S4$D_OUT[1:0] == 2'b10 || + fpu_fState_S4$D_OUT[1:0] == 2'b11) && + fpu_fState_S4$D_OUT[65], + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 }; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = + { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 }; + endcase + end endmodule // mkDoubleSqrt diff --git a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v index 7242060..9d6c366 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v index ccb122d..e6946a8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v index 31207ea..25e8f29 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v +++ b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index d9cea29..6f1d821 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -786,8 +786,8 @@ module mkFetchStage(CLK, out_fifo_enqueueElement_1_dummy_1_0$wget, out_fifo_enqueueFifo_lat_0$whas, out_fifo_enqueueFifo_lat_1$whas, - pc_reg_dummy_1_0$whas, - pc_reg_lat_0$whas; + pc_reg_lat_0$whas, + pc_reg_lat_1$whas; // register decode_epoch reg decode_epoch; @@ -4818,7 +4818,7 @@ module mkFetchStage(CLK, // inlined wires assign pc_reg_lat_0$whas = EN_start || WILL_FIRE_RL_doFetch1 ; - assign pc_reg_dummy_1_0$whas = + assign pc_reg_lat_1$whas = WILL_FIRE_RL_doDecode && SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447 ; @@ -9130,7 +9130,7 @@ module mkFetchStage(CLK, // submodule pc_reg_dummy2_1 assign pc_reg_dummy2_1$D_IN = 1'd1 ; - assign pc_reg_dummy2_1$EN = pc_reg_dummy_1_0$whas ; + assign pc_reg_dummy2_1$EN = pc_reg_lat_1$whas ; // submodule pc_reg_dummy2_2 assign pc_reg_dummy2_2$D_IN = 1'd1 ; @@ -11527,7 +11527,7 @@ module mkFetchStage(CLK, assign IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 = x__h115849 + 64'd4 ; assign IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9 = - pc_reg_dummy_1_0$whas ? + pc_reg_lat_1$whas ? upd__h1659 : (pc_reg_lat_0$whas ? upd__h1686 : pc_reg_rl) ; assign IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 = diff --git a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v index 19077ae..9bec235 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index 1ac4e8b..3999df6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 15d044c..2a255b9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v index 582c46c..5c24b1f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v index a99ba17..a94e505 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v index 8f2496d..b420b9a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v index 633084f..f9897e7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v index fb6650c..ab96233 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v index 0f647fc..87e4954 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkICoCache.v b/src_SSITH_P3/Verilog_RTL/mkICoCache.v index a18b0ec..434f48e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkICoCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v index 5290f98..ba18f4f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v index 3234ef8..cc3465d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkITlb.v b/src_SSITH_P3/Verilog_RTL/mkITlb.v index 8337f28..c5a0864 100644 --- a/src_SSITH_P3/Verilog_RTL/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkITlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v index 6cbc0b2..805dcc5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index b2795ea..41a36dc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index 1c6cfe3..f15ec88 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -10516,75 +10516,6 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3399; endcase end - always@(way__h173542 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626) - begin - case (way__h173542) - 4'd0: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311; - 4'd1: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336; - 4'd2: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352; - 4'd3: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380; - 4'd4: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399; - 4'd5: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415; - 4'd6: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430; - 4'd7: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462; - 4'd8: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482; - 4'd9: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501; - 4'd10: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517; - 4'd11: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538; - 4'd12: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556; - 4'd13: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572; - 4'd14: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587; - 4'd15: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626; - endcase - end always@(way__h173542 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224 or @@ -10654,6 +10585,75 @@ module mkLLPipeline(CLK, IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308; endcase end + always@(way__h173542 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626) + begin + case (way__h173542) + 4'd0: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311; + 4'd1: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336; + 4'd2: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352; + 4'd3: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380; + 4'd4: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399; + 4'd5: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415; + 4'd6: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430; + 4'd7: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462; + 4'd8: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482; + 4'd9: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501; + 4'd10: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517; + 4'd11: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538; + 4'd12: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556; + 4'd13: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572; + 4'd14: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587; + 4'd15: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626; + endcase + end always@(way__h173542 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3406 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3411 or diff --git a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v index 4b0453f..b4fa4a6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index 68735ad..63a9d74 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v index b0ef48d..08033b6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v index b257c36..b7a1045 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v index 2eea032..0848cfa 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v index 7254a62..3e2332b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v index 62600d8..8ce1ce4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v index 7ef963e..086d61c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v index a186981..a7de61e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index 382f1e2..e4d4458 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -1347,9 +1347,9 @@ module mkP3_Core(CLK, .axi_out_tlast(tv_xactor$axi_out_tlast)); // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = WILL_FIRE_RL_rl_once ; - assign WILL_FIRE_RL_rl_once = + assign CAN_FIRE_RL_rl_once = corew$RDY_cpu_reset_server_request_put && !rg_once ; + assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; // rule RL_rl_reset_response assign CAN_FIRE_RL_rl_reset_response = @@ -1637,7 +1637,7 @@ module mkP3_Core(CLK, assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = WILL_FIRE_RL_rl_once ; + assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; assign corew$EN_cpu_reset_server_response_get = corew$RDY_cpu_reset_server_response_get ; assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; diff --git a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v index 7490ccc..7dfaf3e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index d8462cb..1e25443 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -2114,7 +2114,7 @@ module mkProc(CLK, EN_hart0_server_reset_response_get ; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = CAN_FIRE_start ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -5967,6 +5967,27 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end + always@(mmioPlatform_curReq or + result__h46297 or + result__h46324 or result__h46351 or result__h46378) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46297; + 3'h2: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46324; + 3'h4: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46351; + 3'h6: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46378; + default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + 64'd0; + endcase + end always@(mmioPlatform_curReq or result__h46064 or result__h46091 or @@ -6002,27 +6023,6 @@ module mkProc(CLK, result__h46253; endcase end - always@(mmioPlatform_curReq or - result__h46297 or - result__h46324 or result__h46351 or result__h46378) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46297; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46324; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46351; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46378; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - 64'd0; - endcase - end always@(mmioPlatform_curReq or result__h46418 or result__h46445) begin case (mmioPlatform_curReq[2:0]) diff --git a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v index a181d0f..955c79f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRas.v b/src_SSITH_P3/Verilog_RTL/mkRas.v index 9192168..0399a9b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL/mkRas.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v index 7b123fe..473ebaa 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v index bc0bb5b..3e76786 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v index 6484f82..c07ff78 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -15638,71 +15638,6 @@ module mkReservationStationAlu(CLK, m_data_15[1]; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_0[72]; - 4'd1: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_1[72]; - 4'd2: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_2[72]; - 4'd3: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_3[72]; - 4'd4: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_4[72]; - 4'd5: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_5[72]; - 4'd6: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_6[72]; - 4'd7: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_7[72]; - 4'd8: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_8[72]; - 4'd9: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_9[72]; - 4'd10: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_10[72]; - 4'd11: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_11[72]; - 4'd12: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_12[72]; - 4'd13: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_13[72]; - 4'd14: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_14[72]; - 4'd15: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_15[72]; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -15768,6 +15703,71 @@ module mkReservationStationAlu(CLK, m_data_15[70]; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_0[72]; + 4'd1: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_1[72]; + 4'd2: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_2[72]; + 4'd3: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_3[72]; + 4'd4: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_4[72]; + 4'd5: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_5[72]; + 4'd6: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_6[72]; + 4'd7: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_7[72]; + 4'd8: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_8[72]; + 4'd9: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_9[72]; + 4'd10: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_10[72]; + 4'd11: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_11[72]; + 4'd12: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_12[72]; + 4'd13: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_13[72]; + 4'd14: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_14[72]; + 4'd15: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_15[72]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v index b21ff7c..35e774f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v index 62c6ac0..7350806 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v index 5153b0f..2725b41 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v index 46f17d4..6bc3736 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v index 6c29b38..e1af2db 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v index 4071131..2aafd79 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v index a2dfe07..5662f10 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v index 689b342..f161a85 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v index ea8ce28..cc2c578 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v index 4437b39..fd3654a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v index a0aef54..1762326 100644 --- a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v b/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v index 4ce5fb1..d07abc0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v +++ b/src_SSITH_P3/Verilog_RTL/mkTV_Xactor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v index a049da6..d7059a8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPred.v b/src_SSITH_P3/Verilog_RTL/mkTourPred.v index 6cef5a7..f4f9439 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v index 7ab9bb7..417af0c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_alu.v b/src_SSITH_P3/Verilog_RTL/module_alu.v index 3ca27d9..a3dc704 100644 --- a/src_SSITH_P3/Verilog_RTL/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL/module_alu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_aluBr.v b/src_SSITH_P3/Verilog_RTL/module_aluBr.v index 9ec85ca..b602264 100644 --- a/src_SSITH_P3/Verilog_RTL/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL/module_aluBr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_amoExec.v b/src_SSITH_P3/Verilog_RTL/module_amoExec.v index fe0dcca..b530943 100644 --- a/src_SSITH_P3/Verilog_RTL/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_amoExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_basicExec.v b/src_SSITH_P3/Verilog_RTL/module_basicExec.v index c47f51b..062a838 100644 --- a/src_SSITH_P3/Verilog_RTL/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_basicExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v index 2ffba0b..fcd8244 100644 --- a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_checkForException.v b/src_SSITH_P3/Verilog_RTL/module_checkForException.v index b645a07..e98a4f4 100644 --- a/src_SSITH_P3/Verilog_RTL/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL/module_checkForException.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_decode.v b/src_SSITH_P3/Verilog_RTL/module_decode.v index 8d04782..1e08888 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL/module_decode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v index 76da3ab..b9f2cd4 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v index edefcc7..1c8195c 100644 --- a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v b/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v index 9e73d6c..da452c1 100644 --- a/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v +++ b/src_SSITH_P3/Verilog_RTL/module_getControlFlow.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v index 7aac7c0..71be41e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v index 580b173..b9fa4af 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v index a4c7e30..e1e9a5b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v index bbc0dff..d689f0a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 8457547..0165684 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -3939,7 +3939,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3, @@ -4028,7 +4028,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_4, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -4060,33 +4060,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9929, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871, - addr__h287286, - curData__h190136, - rVal1__h605865, - rVal1__h629397, - trap_val__h693211, - x__h194346; + addr__h287289, + curData__h190139, + rVal1__h605870, + rVal1__h629405, + trap_val__h693220, + x__h194349; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211, - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212, - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209, - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210, - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197, - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198, - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199, - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200, - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201, - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202, - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213, - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214, - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215, - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216, - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217, - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218, - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207, - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208, + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211, + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212, + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209, + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210, + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197, + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198, + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199, + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200, + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201, + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202, + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213, + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214, + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215, + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216, + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217, + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218, + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207, + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624, @@ -4098,45 +4098,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78, - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79, - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80, - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81, - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111, - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112, - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41, - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42, - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109, - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110, - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39, - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40, - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113, - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114, - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43, - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44, - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115, - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116, - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45, - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46, - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76, - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77, - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74, - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75, - _theResult___fst_sfd__h343282, - _theResult___fst_sfd__h352005, - _theResult___fst_sfd__h360587, - _theResult___fst_sfd__h369771, - _theResult___fst_sfd__h378407, - _theResult___fst_sfd__h388974, - _theResult___fst_sfd__h397695, - _theResult___fst_sfd__h406277, - _theResult___fst_sfd__h415461, - _theResult___fst_sfd__h424097, - _theResult___fst_sfd__h434662, - _theResult___fst_sfd__h443383, - _theResult___fst_sfd__h451965, - _theResult___fst_sfd__h461149, - _theResult___fst_sfd__h469785; + reg [22 : 0] CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78, + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79, + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80, + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81, + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111, + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112, + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41, + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42, + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109, + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110, + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39, + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40, + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113, + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114, + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43, + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44, + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115, + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116, + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45, + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46, + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76, + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77, + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74, + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75, + _theResult___fst_sfd__h343285, + _theResult___fst_sfd__h352008, + _theResult___fst_sfd__h360590, + _theResult___fst_sfd__h369774, + _theResult___fst_sfd__h378410, + _theResult___fst_sfd__h388977, + _theResult___fst_sfd__h397698, + _theResult___fst_sfd__h406280, + _theResult___fst_sfd__h415464, + _theResult___fst_sfd__h424100, + _theResult___fst_sfd__h434665, + _theResult___fst_sfd__h443386, + _theResult___fst_sfd__h451968, + _theResult___fst_sfd__h461152, + _theResult___fst_sfd__h469788; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4160,24 +4160,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203, - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204, - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205, - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206, - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175, - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176, - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177, - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178, - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179, - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180, - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152, - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153, - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183, - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184, - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181, - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182, - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135, - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136, + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203, + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204, + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205, + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206, + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175, + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176, + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177, + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178, + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179, + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180, + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152, + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153, + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183, + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184, + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181, + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182, + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135, + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553, @@ -4187,47 +4187,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790; - reg [7 : 0] CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67, - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68, - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72, - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73, - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96, - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97, - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26, - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27, - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94, - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95, - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24, - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25, - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102, - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103, - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32, - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33, - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107, - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108, - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37, - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38, - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61, - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62, - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59, - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60, + reg [7 : 0] CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67, + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68, + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72, + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73, + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96, + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97, + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26, + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27, + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94, + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95, + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24, + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25, + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102, + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103, + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32, + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33, + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107, + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108, + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37, + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38, + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61, + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62, + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59, + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h343281, - _theResult___fst_exp__h352004, - _theResult___fst_exp__h360586, - _theResult___fst_exp__h369770, - _theResult___fst_exp__h378406, - _theResult___fst_exp__h388973, - _theResult___fst_exp__h397694, - _theResult___fst_exp__h406276, - _theResult___fst_exp__h415460, - _theResult___fst_exp__h424096, - _theResult___fst_exp__h434661, - _theResult___fst_exp__h443382, - _theResult___fst_exp__h451964, - _theResult___fst_exp__h461148, - _theResult___fst_exp__h469784; + _theResult___fst_exp__h343284, + _theResult___fst_exp__h352007, + _theResult___fst_exp__h360589, + _theResult___fst_exp__h369773, + _theResult___fst_exp__h378409, + _theResult___fst_exp__h388976, + _theResult___fst_exp__h397697, + _theResult___fst_exp__h406279, + _theResult___fst_exp__h415463, + _theResult___fst_exp__h424099, + _theResult___fst_exp__h434664, + _theResult___fst_exp__h443385, + _theResult___fst_exp__h451967, + _theResult___fst_exp__h461151, + _theResult___fst_exp__h469787; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262, @@ -4238,15 +4238,15 @@ module mkCore(CLK, CASE_checkForException_2839_BITS_3_TO_0_0_chec_ETC__q226, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13868, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d12949, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13995, - i__h692195, - i__h692355; + i__h692204, + i__h692364; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266, @@ -4260,8 +4260,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10695, - x__h283065, - x__h288835; + x__h283068, + x__h288838; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, @@ -4292,46 +4292,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87, + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86, + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89, + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88, + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118, + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117, + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47, + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50, + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122, + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121, + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51, + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124, + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54, + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83, + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82, + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85, + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84, + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, @@ -4448,152 +4448,152 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663, - _theResult___fst__h600257, - _theResult___snd__h600258, - a___1__h599976, - a___1__h600262, - a__h599835, + _theResult___fst__h600261, + _theResult___snd__h600262, + a___1__h599980, + a___1__h600266, + a__h599839, amoExec___d880, - b___1__h599977, - b___1__h600307, - b__h599836, - base__h694782, - base__h694985, - data___1__h472204, - data___1__h473012, - data__h472478, - fcsr_csr__read__h606143, - fflags_csr__read__h606118, - frm_csr__read__h606129, - mcause_csr__read__h607790, - mcounteren_csr__read__h607535, - medeleg_csr__read__h607135, - mideleg_csr__read__h607230, - mie_csr__read__h607361, - mip_csr__read__h608030, - mstatus_csr__read__h606987, - mtvec_csr__read__h607443, - n___1__h195749, - n__h191674, - n__read__h608134, - n__read__h608325, + b___1__h599981, + b___1__h600311, + b__h599840, + base__h694791, + base__h694994, + data___1__h472207, + data___1__h473015, + data__h472481, + fcsr_csr__read__h606148, + fflags_csr__read__h606123, + frm_csr__read__h606134, + mcause_csr__read__h607795, + mcounteren_csr__read__h607540, + medeleg_csr__read__h607140, + mideleg_csr__read__h607235, + mie_csr__read__h607366, + mip_csr__read__h608035, + mstatus_csr__read__h606992, + mtvec_csr__read__h607448, + n___1__h195752, + n__h191677, + n__read__h608139, + n__read__h608330, n__read__h6134, - n__read__h703190, - next_pc__h702533, - q___1__h473077, - rVal1__h478957, - rVal2__h478958, - r___1__h473103, - res_data__h335086, - res_data__h335091, - res_data__h380781, - res_data__h380786, - res_data__h426469, - res_data__h426474, - resp_addr__h289190, + n__read__h703199, + next_pc__h702542, + q___1__h473080, + rVal1__h478961, + rVal2__h478962, + r___1__h473106, + res_data__h335089, + res_data__h335094, + res_data__h380784, + res_data__h380789, + res_data__h426472, + res_data__h426477, + resp_addr__h289193, robdeqPort_0_deq_data_BITS_95_TO_32__q261, - satp_csr__read__h606844, - scause_csr__read__h606642, - scounteren_csr__read__h606504, - shiftData__h180513, - sie_csr__read__h606408, - sip_csr__read__h606781, - sstatus_csr__read__h606339, - stvec_csr__read__h606451, + satp_csr__read__h606849, + scause_csr__read__h606647, + scounteren_csr__read__h606509, + shiftData__h180516, + sie_csr__read__h606413, + sip_csr__read__h606786, + sstatus_csr__read__h606344, + stvec_csr__read__h606456, upd__h3639, upd__h4956, - v__h604750, - v__h628436, - vaddr__h180508, - x__h152889, - x__h156436, - x__h159250, - x__h161098, + v__h604754, + v__h628444, + vaddr__h180511, + x__h152890, + x__h156437, + x__h159251, + x__h161099, x__h17672, - x__h180422, - x__h180423, + x__h180425, + x__h180426, x__h20210, - x__h284510, - x__h286364, + x__h284513, + x__h286367, x__h45579, - x__h478866, - x__h478867, - x__h478868, + x__h478870, + x__h478871, + x__h478872, x__h48115, - x__h613028, - x__h613029, - x__h634247, - x__h634248, - x__h688716, - x_addr__h311294, - x_quotient__h472392, - x_reg_ifc__read__h606248, - x_remainder__h472393, - y__h705641, - y_avValue__h179510, - y_avValue__h180116, - y_avValue__h476002, - y_avValue__h476610, - y_avValue__h477212, - y_avValue__h605655, - y_avValue__h610917, - y_avValue__h629189, - y_avValue__h632146, - y_avValue__h693058, - y_avValue__h694819, - y_avValue_snd_snd_snd_snd_snd__h705141, - y_avValue_snd_snd_snd_snd_snd__h705694, - y_avValue_snd_snd_snd_snd_snd__h705723; + x__h613033, + x__h613034, + x__h634256, + x__h634257, + x__h688725, + x_addr__h311296, + x_quotient__h472395, + x_reg_ifc__read__h606253, + x_remainder__h472396, + y__h705650, + y_avValue__h179513, + y_avValue__h180119, + y_avValue__h476006, + y_avValue__h476614, + y_avValue__h477216, + y_avValue__h605660, + y_avValue__h610922, + y_avValue__h629197, + y_avValue__h632155, + y_avValue__h693067, + y_avValue__h694828, + y_avValue_snd_snd_snd_snd_snd__h705150, + y_avValue_snd_snd_snd_snd_snd__h705703, + y_avValue_snd_snd_snd_snd_snd__h705732; wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869, - r1__read__h608832, - r1__read__h609236, - r1__read__h609766, + r1__read__h608837, + r1__read__h609241, r1__read__h609771, - r1__read__h609790, - r1__read__h610043, - r1__read__h610221, - r1__read__h610339, + r1__read__h609776, + r1__read__h609795, + r1__read__h610048, + r1__read__h610226, r1__read__h610344, - r1__read__h610363; - wire [61 : 0] r1__read__h608834, - r1__read__h609238, - r1__read__h609773, - r1__read__h609792, - r1__read__h610045, - r1__read__h610197, - r1__read__h610223, - r1__read__h610346, - r1__read__h610365; - wire [60 : 0] r1__read__h610047, - r1__read__h610199, - r1__read__h610225, - r1__read__h610367; - wire [59 : 0] r1__read__h608836, - r1__read__h609240, - r1__read__h609784, - r1__read__h609794, - r1__read__h610049, - r1__read__h610227, - r1__read__h610357, - r1__read__h610369; - wire [58 : 0] r1__read__h608838, - r1__read__h609242, - r1__read__h609796, - r1__read__h610051, - r1__read__h610229, - r1__read__h610371; + r1__read__h610349, + r1__read__h610368; + wire [61 : 0] r1__read__h608839, + r1__read__h609243, + r1__read__h609778, + r1__read__h609797, + r1__read__h610050, + r1__read__h610202, + r1__read__h610228, + r1__read__h610351, + r1__read__h610370; + wire [60 : 0] r1__read__h610052, + r1__read__h610204, + r1__read__h610230, + r1__read__h610372; + wire [59 : 0] r1__read__h608841, + r1__read__h609245, + r1__read__h609789, + r1__read__h609799, + r1__read__h610054, + r1__read__h610232, + r1__read__h610362, + r1__read__h610374; + wire [58 : 0] r1__read__h608843, + r1__read__h609247, + r1__read__h609801, + r1__read__h610056, + r1__read__h610234, + r1__read__h610376; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, - r1__read__h608840, - r1__read__h609244, - r1__read__h609798, - r1__read__h610053, - r1__read__h610201, - r1__read__h610231, - r1__read__h610373, - y__h252023; + r1__read__h608845, + r1__read__h609249, + r1__read__h609803, + r1__read__h610058, + r1__read__h610206, + r1__read__h610236, + r1__read__h610378, + y__h252026; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90, @@ -4621,187 +4621,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355, - _theResult____h343299, - _theResult____h360938, - _theResult____h388991, - _theResult____h406628, - _theResult____h434679, - _theResult____h452316, - _theResult____h500013, - _theResult____h538814, - _theResult____h578015, - _theResult___snd__h351421, - _theResult___snd__h351432, - _theResult___snd__h351434, - _theResult___snd__h351444, - _theResult___snd__h351450, - _theResult___snd__h351473, - _theResult___snd__h360017, - _theResult___snd__h360019, - _theResult___snd__h360026, - _theResult___snd__h360032, - _theResult___snd__h360055, - _theResult___snd__h369187, - _theResult___snd__h369198, - _theResult___snd__h369200, - _theResult___snd__h369210, - _theResult___snd__h369216, - _theResult___snd__h369239, - _theResult___snd__h377807, - _theResult___snd__h377821, - _theResult___snd__h377827, - _theResult___snd__h377845, - _theResult___snd__h397111, - _theResult___snd__h397122, - _theResult___snd__h397124, - _theResult___snd__h397134, - _theResult___snd__h397140, - _theResult___snd__h397163, - _theResult___snd__h405707, - _theResult___snd__h405709, - _theResult___snd__h405716, - _theResult___snd__h405722, - _theResult___snd__h405745, - _theResult___snd__h414877, - _theResult___snd__h414888, - _theResult___snd__h414890, - _theResult___snd__h414900, - _theResult___snd__h414906, - _theResult___snd__h414929, - _theResult___snd__h423497, - _theResult___snd__h423511, - _theResult___snd__h423517, - _theResult___snd__h423535, - _theResult___snd__h442799, - _theResult___snd__h442810, - _theResult___snd__h442812, - _theResult___snd__h442822, - _theResult___snd__h442828, - _theResult___snd__h442851, - _theResult___snd__h451395, - _theResult___snd__h451397, - _theResult___snd__h451404, - _theResult___snd__h451410, - _theResult___snd__h451433, - _theResult___snd__h460565, - _theResult___snd__h460576, - _theResult___snd__h460578, - _theResult___snd__h460588, - _theResult___snd__h460594, - _theResult___snd__h460617, - _theResult___snd__h469185, - _theResult___snd__h469199, - _theResult___snd__h469205, - _theResult___snd__h469223, - _theResult___snd__h498623, - _theResult___snd__h498625, - _theResult___snd__h498632, - _theResult___snd__h498638, - _theResult___snd__h498661, - _theResult___snd__h508260, - _theResult___snd__h508271, - _theResult___snd__h508273, - _theResult___snd__h508283, - _theResult___snd__h508289, - _theResult___snd__h508312, - _theResult___snd__h517028, - _theResult___snd__h517042, - _theResult___snd__h517048, - _theResult___snd__h517066, - _theResult___snd__h537424, - _theResult___snd__h537426, - _theResult___snd__h537433, - _theResult___snd__h537439, - _theResult___snd__h537462, - _theResult___snd__h547061, - _theResult___snd__h547072, - _theResult___snd__h547074, - _theResult___snd__h547084, - _theResult___snd__h547090, - _theResult___snd__h547113, - _theResult___snd__h555829, - _theResult___snd__h555843, - _theResult___snd__h555849, - _theResult___snd__h555867, - _theResult___snd__h576625, - _theResult___snd__h576627, - _theResult___snd__h576634, - _theResult___snd__h576640, - _theResult___snd__h576663, - _theResult___snd__h586262, - _theResult___snd__h586273, - _theResult___snd__h586275, - _theResult___snd__h586285, - _theResult___snd__h586291, - _theResult___snd__h586314, - _theResult___snd__h595030, - _theResult___snd__h595044, - _theResult___snd__h595050, - _theResult___snd__h595068, - r1__read__h610055, - r1__read__h610203, - r1__read__h610233, - r1__read__h610375, - result__h361551, - result__h407241, - result__h452929, - result__h500626, - result__h539427, - result__h578628, - sfd__h335694, - sfd__h381389, - sfd__h427077, - sfd__h479671, - sfd__h518613, - sfd__h557814, - sfdin__h351404, - sfdin__h369170, - sfdin__h397094, - sfdin__h414860, - sfdin__h442782, - sfdin__h460548, - sfdin__h508243, - sfdin__h547044, - sfdin__h586245, - x__h361648, - x__h407338, - x__h453026, - x__h500721, - x__h539522, - x__h578723; - wire [55 : 0] r1__read__h608842, - r1__read__h609246, - r1__read__h609800, - r1__read__h610057, - r1__read__h610235, - r1__read__h610377; - wire [54 : 0] r1__read__h608844, - r1__read__h609248, - r1__read__h609802, - r1__read__h610059, - r1__read__h610237, - r1__read__h610379; - wire [53 : 0] r1__read__h610180, - r1__read__h610205, - r1__read__h610239, - r1__read__h610381, - sfd__h498690, - sfd__h508341, - sfd__h517101, - sfd__h537491, - sfd__h547142, - sfd__h555902, - sfd__h576692, - sfd__h586343, - sfd__h595103, - value__h343921, - value__h389611, - value__h435299; - wire [52 : 0] r1__read__h610061, - r1__read__h610182, - r1__read__h610207, - r1__read__h610241, - r1__read__h610383; + _theResult____h343302, + _theResult____h360941, + _theResult____h388994, + _theResult____h406631, + _theResult____h434682, + _theResult____h452319, + _theResult____h500017, + _theResult____h538818, + _theResult____h578019, + _theResult___snd__h351424, + _theResult___snd__h351435, + _theResult___snd__h351437, + _theResult___snd__h351447, + _theResult___snd__h351453, + _theResult___snd__h351476, + _theResult___snd__h360020, + _theResult___snd__h360022, + _theResult___snd__h360029, + _theResult___snd__h360035, + _theResult___snd__h360058, + _theResult___snd__h369190, + _theResult___snd__h369201, + _theResult___snd__h369203, + _theResult___snd__h369213, + _theResult___snd__h369219, + _theResult___snd__h369242, + _theResult___snd__h377810, + _theResult___snd__h377824, + _theResult___snd__h377830, + _theResult___snd__h377848, + _theResult___snd__h397114, + _theResult___snd__h397125, + _theResult___snd__h397127, + _theResult___snd__h397137, + _theResult___snd__h397143, + _theResult___snd__h397166, + _theResult___snd__h405710, + _theResult___snd__h405712, + _theResult___snd__h405719, + _theResult___snd__h405725, + _theResult___snd__h405748, + _theResult___snd__h414880, + _theResult___snd__h414891, + _theResult___snd__h414893, + _theResult___snd__h414903, + _theResult___snd__h414909, + _theResult___snd__h414932, + _theResult___snd__h423500, + _theResult___snd__h423514, + _theResult___snd__h423520, + _theResult___snd__h423538, + _theResult___snd__h442802, + _theResult___snd__h442813, + _theResult___snd__h442815, + _theResult___snd__h442825, + _theResult___snd__h442831, + _theResult___snd__h442854, + _theResult___snd__h451398, + _theResult___snd__h451400, + _theResult___snd__h451407, + _theResult___snd__h451413, + _theResult___snd__h451436, + _theResult___snd__h460568, + _theResult___snd__h460579, + _theResult___snd__h460581, + _theResult___snd__h460591, + _theResult___snd__h460597, + _theResult___snd__h460620, + _theResult___snd__h469188, + _theResult___snd__h469202, + _theResult___snd__h469208, + _theResult___snd__h469226, + _theResult___snd__h498627, + _theResult___snd__h498629, + _theResult___snd__h498636, + _theResult___snd__h498642, + _theResult___snd__h498665, + _theResult___snd__h508264, + _theResult___snd__h508275, + _theResult___snd__h508277, + _theResult___snd__h508287, + _theResult___snd__h508293, + _theResult___snd__h508316, + _theResult___snd__h517032, + _theResult___snd__h517046, + _theResult___snd__h517052, + _theResult___snd__h517070, + _theResult___snd__h537428, + _theResult___snd__h537430, + _theResult___snd__h537437, + _theResult___snd__h537443, + _theResult___snd__h537466, + _theResult___snd__h547065, + _theResult___snd__h547076, + _theResult___snd__h547078, + _theResult___snd__h547088, + _theResult___snd__h547094, + _theResult___snd__h547117, + _theResult___snd__h555833, + _theResult___snd__h555847, + _theResult___snd__h555853, + _theResult___snd__h555871, + _theResult___snd__h576629, + _theResult___snd__h576631, + _theResult___snd__h576638, + _theResult___snd__h576644, + _theResult___snd__h576667, + _theResult___snd__h586266, + _theResult___snd__h586277, + _theResult___snd__h586279, + _theResult___snd__h586289, + _theResult___snd__h586295, + _theResult___snd__h586318, + _theResult___snd__h595034, + _theResult___snd__h595048, + _theResult___snd__h595054, + _theResult___snd__h595072, + r1__read__h610060, + r1__read__h610208, + r1__read__h610238, + r1__read__h610380, + result__h361554, + result__h407244, + result__h452932, + result__h500630, + result__h539431, + result__h578632, + sfd__h335697, + sfd__h381392, + sfd__h427080, + sfd__h479675, + sfd__h518617, + sfd__h557818, + sfdin__h351407, + sfdin__h369173, + sfdin__h397097, + sfdin__h414863, + sfdin__h442785, + sfdin__h460551, + sfdin__h508247, + sfdin__h547048, + sfdin__h586249, + x__h361651, + x__h407341, + x__h453029, + x__h500725, + x__h539526, + x__h578727; + wire [55 : 0] r1__read__h608847, + r1__read__h609251, + r1__read__h609805, + r1__read__h610062, + r1__read__h610240, + r1__read__h610382; + wire [54 : 0] r1__read__h608849, + r1__read__h609253, + r1__read__h609807, + r1__read__h610064, + r1__read__h610242, + r1__read__h610384; + wire [53 : 0] r1__read__h610185, + r1__read__h610210, + r1__read__h610244, + r1__read__h610386, + sfd__h498694, + sfd__h508345, + sfd__h517105, + sfd__h537495, + sfd__h547146, + sfd__h555906, + sfd__h576696, + sfd__h586347, + sfd__h595107, + value__h343924, + value__h389614, + value__h435302; + wire [52 : 0] r1__read__h610066, + r1__read__h610187, + r1__read__h610212, + r1__read__h610246, + r1__read__h610388; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132, @@ -4820,110 +4820,110 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857, - _theResult___fst_sfd__h483600, - _theResult___fst_sfd__h499428, - _theResult___fst_sfd__h499431, - _theResult___fst_sfd__h509079, - _theResult___fst_sfd__h509082, - _theResult___fst_sfd__h517863, - _theResult___fst_sfd__h517866, - _theResult___fst_sfd__h517875, - _theResult___fst_sfd__h517881, - _theResult___fst_sfd__h522401, - _theResult___fst_sfd__h538229, - _theResult___fst_sfd__h538232, - _theResult___fst_sfd__h547880, - _theResult___fst_sfd__h547883, - _theResult___fst_sfd__h556664, - _theResult___fst_sfd__h556667, - _theResult___fst_sfd__h556676, - _theResult___fst_sfd__h556682, - _theResult___fst_sfd__h561602, - _theResult___fst_sfd__h577430, - _theResult___fst_sfd__h577433, - _theResult___fst_sfd__h587081, - _theResult___fst_sfd__h587084, - _theResult___fst_sfd__h595865, - _theResult___fst_sfd__h595868, - _theResult___fst_sfd__h595877, - _theResult___fst_sfd__h595883, - _theResult___sfd__h499328, - _theResult___sfd__h508979, - _theResult___sfd__h517763, - _theResult___sfd__h538129, - _theResult___sfd__h547780, - _theResult___sfd__h556564, - _theResult___sfd__h577330, - _theResult___sfd__h586981, - _theResult___sfd__h595765, - _theResult___snd_fst_sfd__h479625, - _theResult___snd_fst_sfd__h499434, - _theResult___snd_fst_sfd__h517869, - _theResult___snd_fst_sfd__h518567, - _theResult___snd_fst_sfd__h538235, - _theResult___snd_fst_sfd__h556670, - _theResult___snd_fst_sfd__h557768, - _theResult___snd_fst_sfd__h577436, - _theResult___snd_fst_sfd__h595871, - out___1_sfd__h479374, - out___1_sfd__h518316, - out___1_sfd__h557517, - out_sfd__h499331, - out_sfd__h508982, - out_sfd__h517766, - out_sfd__h538132, - out_sfd__h547783, - out_sfd__h556567, - out_sfd__h577333, - out_sfd__h586984, - out_sfd__h595768, - r1__read__h610385; - wire [50 : 0] r1__read__h608846, r1__read__h610063; - wire [49 : 0] r1__read__h610184, r1__read__h610387; - wire [48 : 0] r1__read__h608848, r1__read__h610065, r1__read__h610186; - wire [46 : 0] r1__read__h608850, r1__read__h610067; - wire [45 : 0] r1__read__h608852, r1__read__h610069; - wire [44 : 0] r1__read__h608854, r1__read__h610071; - wire [43 : 0] r1__read__h608856, r1__read__h610073; - wire [42 : 0] r1__read__h610075; - wire [41 : 0] r1__read__h610077; - wire [40 : 0] r1__read__h610079; + _theResult___fst_sfd__h483604, + _theResult___fst_sfd__h499432, + _theResult___fst_sfd__h499435, + _theResult___fst_sfd__h509083, + _theResult___fst_sfd__h509086, + _theResult___fst_sfd__h517867, + _theResult___fst_sfd__h517870, + _theResult___fst_sfd__h517879, + _theResult___fst_sfd__h517885, + _theResult___fst_sfd__h522405, + _theResult___fst_sfd__h538233, + _theResult___fst_sfd__h538236, + _theResult___fst_sfd__h547884, + _theResult___fst_sfd__h547887, + _theResult___fst_sfd__h556668, + _theResult___fst_sfd__h556671, + _theResult___fst_sfd__h556680, + _theResult___fst_sfd__h556686, + _theResult___fst_sfd__h561606, + _theResult___fst_sfd__h577434, + _theResult___fst_sfd__h577437, + _theResult___fst_sfd__h587085, + _theResult___fst_sfd__h587088, + _theResult___fst_sfd__h595869, + _theResult___fst_sfd__h595872, + _theResult___fst_sfd__h595881, + _theResult___fst_sfd__h595887, + _theResult___sfd__h499332, + _theResult___sfd__h508983, + _theResult___sfd__h517767, + _theResult___sfd__h538133, + _theResult___sfd__h547784, + _theResult___sfd__h556568, + _theResult___sfd__h577334, + _theResult___sfd__h586985, + _theResult___sfd__h595769, + _theResult___snd_fst_sfd__h479629, + _theResult___snd_fst_sfd__h499438, + _theResult___snd_fst_sfd__h517873, + _theResult___snd_fst_sfd__h518571, + _theResult___snd_fst_sfd__h538239, + _theResult___snd_fst_sfd__h556674, + _theResult___snd_fst_sfd__h557772, + _theResult___snd_fst_sfd__h577440, + _theResult___snd_fst_sfd__h595875, + out___1_sfd__h479378, + out___1_sfd__h518320, + out___1_sfd__h557521, + out_sfd__h499335, + out_sfd__h508986, + out_sfd__h517770, + out_sfd__h538136, + out_sfd__h547787, + out_sfd__h556571, + out_sfd__h577337, + out_sfd__h586988, + out_sfd__h595772, + r1__read__h610390; + wire [50 : 0] r1__read__h608851, r1__read__h610068; + wire [49 : 0] r1__read__h610189, r1__read__h610392; + wire [48 : 0] r1__read__h608853, r1__read__h610070, r1__read__h610191; + wire [46 : 0] r1__read__h608855, r1__read__h610072; + wire [45 : 0] r1__read__h608857, r1__read__h610074; + wire [44 : 0] r1__read__h608859, r1__read__h610076; + wire [43 : 0] r1__read__h608861, r1__read__h610078; + wire [42 : 0] r1__read__h610080; + wire [41 : 0] r1__read__h610082; + wire [40 : 0] r1__read__h610084; wire [37 : 0] IF_fetchStage_pipelines_0_first__2605_BIT_160__ETC___d13871, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4, - data72478_BITS_31_TO_0__q5, - imm__h649445, - r1__read__h608858, - r1__read__h610081, - x__h190899, - x__h335098, - x__h380793, - x__h426481, + data72481_BITS_31_TO_0__q5, + imm__h649454, + r1__read__h608863, + r1__read__h610086, + x__h190902, + x__h335101, + x__h380796, + x__h426484, x__h75524, x_data__h65373, - x_data_imm__h667940, - x_data_imm__h682683; - wire [29 : 0] r1__read__h608860, r1__read__h610083; - wire [27 : 0] r1__read__h610085; + x_data_imm__h667949, + x_data_imm__h682692; + wire [29 : 0] r1__read__h608865, r1__read__h610088; + wire [27 : 0] r1__read__h610090; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13903, - sfd__h351502, - sfd__h360084, - sfd__h369268, - sfd__h377880, - sfd__h397192, - sfd__h405774, - sfd__h414958, - sfd__h423570, - sfd__h442880, - sfd__h451462, - sfd__h460646, - sfd__h469258, - value__h484229, - value__h523030, - value__h562231; + sfd__h351505, + sfd__h360087, + sfd__h369271, + sfd__h377883, + sfd__h397195, + sfd__h405777, + sfd__h414961, + sfd__h423573, + sfd__h442883, + sfd__h451465, + sfd__h460649, + sfd__h469261, + value__h484233, + value__h523034, + value__h562235; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345, @@ -4948,72 +4948,72 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804, - _theResult___fst_sfd__h352008, - _theResult___fst_sfd__h360590, - _theResult___fst_sfd__h369774, - _theResult___fst_sfd__h378410, - _theResult___fst_sfd__h378419, - _theResult___fst_sfd__h378425, - _theResult___fst_sfd__h397698, - _theResult___fst_sfd__h406280, - _theResult___fst_sfd__h415464, - _theResult___fst_sfd__h424100, - _theResult___fst_sfd__h424109, - _theResult___fst_sfd__h424115, - _theResult___fst_sfd__h443386, - _theResult___fst_sfd__h451968, - _theResult___fst_sfd__h461152, - _theResult___fst_sfd__h469788, - _theResult___fst_sfd__h469797, - _theResult___fst_sfd__h469803, - _theResult___sfd__h351927, - _theResult___sfd__h360509, - _theResult___sfd__h369693, - _theResult___sfd__h378329, - _theResult___sfd__h378431, - _theResult___sfd__h397617, - _theResult___sfd__h406199, - _theResult___sfd__h415383, - _theResult___sfd__h424019, - _theResult___sfd__h424121, - _theResult___sfd__h443305, - _theResult___sfd__h451887, - _theResult___sfd__h461071, - _theResult___sfd__h469707, - _theResult___sfd__h469809, - _theResult___snd_fst_sfd__h335644, - _theResult___snd_fst_sfd__h360593, - _theResult___snd_fst_sfd__h378413, - _theResult___snd_fst_sfd__h381339, - _theResult___snd_fst_sfd__h406283, - _theResult___snd_fst_sfd__h424103, - _theResult___snd_fst_sfd__h427027, - _theResult___snd_fst_sfd__h451971, - _theResult___snd_fst_sfd__h469791, - out_f_sfd__h378708, - out_f_sfd__h424398, - out_f_sfd__h470086, - out_sfd__h351930, - out_sfd__h360512, - out_sfd__h369696, - out_sfd__h378332, - out_sfd__h397620, - out_sfd__h406202, - out_sfd__h415386, - out_sfd__h424022, - out_sfd__h443308, - out_sfd__h451890, - out_sfd__h461074, - out_sfd__h469710; - wire [19 : 0] r1__read__h610020; + _theResult___fst_sfd__h352011, + _theResult___fst_sfd__h360593, + _theResult___fst_sfd__h369777, + _theResult___fst_sfd__h378413, + _theResult___fst_sfd__h378422, + _theResult___fst_sfd__h378428, + _theResult___fst_sfd__h397701, + _theResult___fst_sfd__h406283, + _theResult___fst_sfd__h415467, + _theResult___fst_sfd__h424103, + _theResult___fst_sfd__h424112, + _theResult___fst_sfd__h424118, + _theResult___fst_sfd__h443389, + _theResult___fst_sfd__h451971, + _theResult___fst_sfd__h461155, + _theResult___fst_sfd__h469791, + _theResult___fst_sfd__h469800, + _theResult___fst_sfd__h469806, + _theResult___sfd__h351930, + _theResult___sfd__h360512, + _theResult___sfd__h369696, + _theResult___sfd__h378332, + _theResult___sfd__h378434, + _theResult___sfd__h397620, + _theResult___sfd__h406202, + _theResult___sfd__h415386, + _theResult___sfd__h424022, + _theResult___sfd__h424124, + _theResult___sfd__h443308, + _theResult___sfd__h451890, + _theResult___sfd__h461074, + _theResult___sfd__h469710, + _theResult___sfd__h469812, + _theResult___snd_fst_sfd__h335647, + _theResult___snd_fst_sfd__h360596, + _theResult___snd_fst_sfd__h378416, + _theResult___snd_fst_sfd__h381342, + _theResult___snd_fst_sfd__h406286, + _theResult___snd_fst_sfd__h424106, + _theResult___snd_fst_sfd__h427030, + _theResult___snd_fst_sfd__h451974, + _theResult___snd_fst_sfd__h469794, + out_f_sfd__h378711, + out_f_sfd__h424401, + out_f_sfd__h470089, + out_sfd__h351933, + out_sfd__h360515, + out_sfd__h369699, + out_sfd__h378335, + out_sfd__h397623, + out_sfd__h406205, + out_sfd__h415389, + out_sfd__h424025, + out_sfd__h443311, + out_sfd__h451893, + out_sfd__h461077, + out_sfd__h469713; + wire [19 : 0] r1__read__h610025; wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674, - _theResult____h645389, - enabled_ints___1__h645886, - enabled_ints__h645933, - pend_ints__h645387, - y__h645898; + _theResult____h645398, + enabled_ints___1__h645895, + enabled_ints__h645942, + pend_ints__h645396, + y__h645907; wire [12 : 0] fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, - r1__read_BITS_12_TO_0___h645909; + r1__read_BITS_12_TO_0___h645918; wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938, IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648, @@ -5043,24 +5043,24 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334, - renaming_spec_bits__h675339, - result__h641096, - result__h641147, - spec_bits__h678434, - w__h641091, - x__h361681, - x__h407371, - x__h453059, - x__h500754, - x__h539555, - x__h578756, - x__h641095, - x__h641146, - y__h641125, - y__h678447, - y_avValue_fst__h671831, - y_avValue_snd_fst__h672105, - y_avValue_snd_fst__h672140; + renaming_spec_bits__h675348, + result__h641105, + result__h641156, + spec_bits__h678443, + w__h641100, + x__h361684, + x__h407374, + x__h453062, + x__h500758, + x__h539559, + x__h578760, + x__h641104, + x__h641155, + y__h641134, + y__h678456, + y_avValue_fst__h671840, + y_avValue_snd_fst__h672114, + y_avValue_snd_fst__h672149; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048, @@ -5082,103 +5082,103 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149, SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172, - _theResult___exp__h499327, - _theResult___exp__h508978, - _theResult___exp__h517762, - _theResult___exp__h538128, - _theResult___exp__h547779, - _theResult___exp__h556563, - _theResult___exp__h577329, - _theResult___exp__h586980, - _theResult___exp__h595764, - _theResult___fst_exp__h483599, - _theResult___fst_exp__h498663, - _theResult___fst_exp__h498669, - _theResult___fst_exp__h498672, - _theResult___fst_exp__h499427, - _theResult___fst_exp__h499430, - _theResult___fst_exp__h508249, - _theResult___fst_exp__h508314, - _theResult___fst_exp__h508320, - _theResult___fst_exp__h508323, - _theResult___fst_exp__h509078, - _theResult___fst_exp__h509081, - _theResult___fst_exp__h517034, - _theResult___fst_exp__h517073, - _theResult___fst_exp__h517079, - _theResult___fst_exp__h517082, - _theResult___fst_exp__h517862, - _theResult___fst_exp__h517865, - _theResult___fst_exp__h517874, - _theResult___fst_exp__h517877, - _theResult___fst_exp__h522400, - _theResult___fst_exp__h537464, - _theResult___fst_exp__h537470, - _theResult___fst_exp__h537473, - _theResult___fst_exp__h538228, - _theResult___fst_exp__h538231, - _theResult___fst_exp__h547050, - _theResult___fst_exp__h547115, - _theResult___fst_exp__h547121, - _theResult___fst_exp__h547124, - _theResult___fst_exp__h547879, - _theResult___fst_exp__h547882, - _theResult___fst_exp__h555835, - _theResult___fst_exp__h555874, - _theResult___fst_exp__h555880, - _theResult___fst_exp__h555883, - _theResult___fst_exp__h556663, - _theResult___fst_exp__h556666, - _theResult___fst_exp__h556675, - _theResult___fst_exp__h556678, - _theResult___fst_exp__h561601, - _theResult___fst_exp__h576665, - _theResult___fst_exp__h576671, - _theResult___fst_exp__h576674, - _theResult___fst_exp__h577429, - _theResult___fst_exp__h577432, - _theResult___fst_exp__h586251, - _theResult___fst_exp__h586316, - _theResult___fst_exp__h586322, - _theResult___fst_exp__h586325, - _theResult___fst_exp__h587080, - _theResult___fst_exp__h587083, - _theResult___fst_exp__h595036, - _theResult___fst_exp__h595075, - _theResult___fst_exp__h595081, - _theResult___fst_exp__h595084, - _theResult___fst_exp__h595864, - _theResult___fst_exp__h595867, - _theResult___fst_exp__h595876, - _theResult___fst_exp__h595879, - _theResult___snd_fst_exp__h499433, - _theResult___snd_fst_exp__h517868, - _theResult___snd_fst_exp__h538234, - _theResult___snd_fst_exp__h556669, - _theResult___snd_fst_exp__h577435, - _theResult___snd_fst_exp__h595870, + _theResult___exp__h499331, + _theResult___exp__h508982, + _theResult___exp__h517766, + _theResult___exp__h538132, + _theResult___exp__h547783, + _theResult___exp__h556567, + _theResult___exp__h577333, + _theResult___exp__h586984, + _theResult___exp__h595768, + _theResult___fst_exp__h483603, + _theResult___fst_exp__h498667, + _theResult___fst_exp__h498673, + _theResult___fst_exp__h498676, + _theResult___fst_exp__h499431, + _theResult___fst_exp__h499434, + _theResult___fst_exp__h508253, + _theResult___fst_exp__h508318, + _theResult___fst_exp__h508324, + _theResult___fst_exp__h508327, + _theResult___fst_exp__h509082, + _theResult___fst_exp__h509085, + _theResult___fst_exp__h517038, + _theResult___fst_exp__h517077, + _theResult___fst_exp__h517083, + _theResult___fst_exp__h517086, + _theResult___fst_exp__h517866, + _theResult___fst_exp__h517869, + _theResult___fst_exp__h517878, + _theResult___fst_exp__h517881, + _theResult___fst_exp__h522404, + _theResult___fst_exp__h537468, + _theResult___fst_exp__h537474, + _theResult___fst_exp__h537477, + _theResult___fst_exp__h538232, + _theResult___fst_exp__h538235, + _theResult___fst_exp__h547054, + _theResult___fst_exp__h547119, + _theResult___fst_exp__h547125, + _theResult___fst_exp__h547128, + _theResult___fst_exp__h547883, + _theResult___fst_exp__h547886, + _theResult___fst_exp__h555839, + _theResult___fst_exp__h555878, + _theResult___fst_exp__h555884, + _theResult___fst_exp__h555887, + _theResult___fst_exp__h556667, + _theResult___fst_exp__h556670, + _theResult___fst_exp__h556679, + _theResult___fst_exp__h556682, + _theResult___fst_exp__h561605, + _theResult___fst_exp__h576669, + _theResult___fst_exp__h576675, + _theResult___fst_exp__h576678, + _theResult___fst_exp__h577433, + _theResult___fst_exp__h577436, + _theResult___fst_exp__h586255, + _theResult___fst_exp__h586320, + _theResult___fst_exp__h586326, + _theResult___fst_exp__h586329, + _theResult___fst_exp__h587084, + _theResult___fst_exp__h587087, + _theResult___fst_exp__h595040, + _theResult___fst_exp__h595079, + _theResult___fst_exp__h595085, + _theResult___fst_exp__h595088, + _theResult___fst_exp__h595868, + _theResult___fst_exp__h595871, + _theResult___fst_exp__h595880, + _theResult___fst_exp__h595883, + _theResult___snd_fst_exp__h499437, + _theResult___snd_fst_exp__h517872, + _theResult___snd_fst_exp__h538238, + _theResult___snd_fst_exp__h556673, + _theResult___snd_fst_exp__h577439, + _theResult___snd_fst_exp__h595874, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98, csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, - din_inc___2_exp__h517922, - din_inc___2_exp__h517957, - din_inc___2_exp__h517983, - din_inc___2_exp__h556723, - din_inc___2_exp__h556758, - din_inc___2_exp__h556784, - din_inc___2_exp__h595924, - din_inc___2_exp__h595959, - din_inc___2_exp__h595985, - out_exp__h499330, - out_exp__h508981, - out_exp__h517765, - out_exp__h538131, - out_exp__h547782, - out_exp__h556566, - out_exp__h577332, - out_exp__h586983, - out_exp__h595767; + din_inc___2_exp__h517926, + din_inc___2_exp__h517961, + din_inc___2_exp__h517987, + din_inc___2_exp__h556727, + din_inc___2_exp__h556762, + din_inc___2_exp__h556788, + din_inc___2_exp__h595928, + din_inc___2_exp__h595963, + din_inc___2_exp__h595989, + out_exp__h499334, + out_exp__h508985, + out_exp__h517769, + out_exp__h538135, + out_exp__h547786, + out_exp__h556570, + out_exp__h577336, + out_exp__h586987, + out_exp__h595771; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652; @@ -5209,121 +5209,121 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104, - _theResult___exp__h351926, - _theResult___exp__h360508, - _theResult___exp__h369692, - _theResult___exp__h378328, - _theResult___exp__h378430, - _theResult___exp__h397616, - _theResult___exp__h406198, - _theResult___exp__h415382, - _theResult___exp__h424018, - _theResult___exp__h424120, - _theResult___exp__h443304, - _theResult___exp__h451886, - _theResult___exp__h461070, - _theResult___exp__h469706, - _theResult___exp__h469808, - _theResult___fst_exp__h351410, - _theResult___fst_exp__h351475, - _theResult___fst_exp__h351481, + _theResult___exp__h351929, + _theResult___exp__h360511, + _theResult___exp__h369695, + _theResult___exp__h378331, + _theResult___exp__h378433, + _theResult___exp__h397619, + _theResult___exp__h406201, + _theResult___exp__h415385, + _theResult___exp__h424021, + _theResult___exp__h424123, + _theResult___exp__h443307, + _theResult___exp__h451889, + _theResult___exp__h461073, + _theResult___exp__h469709, + _theResult___exp__h469811, + _theResult___fst_exp__h351413, + _theResult___fst_exp__h351478, _theResult___fst_exp__h351484, - _theResult___fst_exp__h352007, - _theResult___fst_exp__h360057, - _theResult___fst_exp__h360063, + _theResult___fst_exp__h351487, + _theResult___fst_exp__h352010, + _theResult___fst_exp__h360060, _theResult___fst_exp__h360066, - _theResult___fst_exp__h360589, - _theResult___fst_exp__h369176, - _theResult___fst_exp__h369241, - _theResult___fst_exp__h369247, + _theResult___fst_exp__h360069, + _theResult___fst_exp__h360592, + _theResult___fst_exp__h369179, + _theResult___fst_exp__h369244, _theResult___fst_exp__h369250, - _theResult___fst_exp__h369773, - _theResult___fst_exp__h377813, - _theResult___fst_exp__h377852, - _theResult___fst_exp__h377858, + _theResult___fst_exp__h369253, + _theResult___fst_exp__h369776, + _theResult___fst_exp__h377816, + _theResult___fst_exp__h377855, _theResult___fst_exp__h377861, - _theResult___fst_exp__h378409, - _theResult___fst_exp__h378418, + _theResult___fst_exp__h377864, + _theResult___fst_exp__h378412, _theResult___fst_exp__h378421, - _theResult___fst_exp__h397100, - _theResult___fst_exp__h397165, - _theResult___fst_exp__h397171, + _theResult___fst_exp__h378424, + _theResult___fst_exp__h397103, + _theResult___fst_exp__h397168, _theResult___fst_exp__h397174, - _theResult___fst_exp__h397697, - _theResult___fst_exp__h405747, - _theResult___fst_exp__h405753, + _theResult___fst_exp__h397177, + _theResult___fst_exp__h397700, + _theResult___fst_exp__h405750, _theResult___fst_exp__h405756, - _theResult___fst_exp__h406279, - _theResult___fst_exp__h414866, - _theResult___fst_exp__h414931, - _theResult___fst_exp__h414937, + _theResult___fst_exp__h405759, + _theResult___fst_exp__h406282, + _theResult___fst_exp__h414869, + _theResult___fst_exp__h414934, _theResult___fst_exp__h414940, - _theResult___fst_exp__h415463, - _theResult___fst_exp__h423503, - _theResult___fst_exp__h423542, - _theResult___fst_exp__h423548, + _theResult___fst_exp__h414943, + _theResult___fst_exp__h415466, + _theResult___fst_exp__h423506, + _theResult___fst_exp__h423545, _theResult___fst_exp__h423551, - _theResult___fst_exp__h424099, - _theResult___fst_exp__h424108, + _theResult___fst_exp__h423554, + _theResult___fst_exp__h424102, _theResult___fst_exp__h424111, - _theResult___fst_exp__h442788, - _theResult___fst_exp__h442853, - _theResult___fst_exp__h442859, + _theResult___fst_exp__h424114, + _theResult___fst_exp__h442791, + _theResult___fst_exp__h442856, _theResult___fst_exp__h442862, - _theResult___fst_exp__h443385, - _theResult___fst_exp__h451435, - _theResult___fst_exp__h451441, + _theResult___fst_exp__h442865, + _theResult___fst_exp__h443388, + _theResult___fst_exp__h451438, _theResult___fst_exp__h451444, - _theResult___fst_exp__h451967, - _theResult___fst_exp__h460554, - _theResult___fst_exp__h460619, - _theResult___fst_exp__h460625, + _theResult___fst_exp__h451447, + _theResult___fst_exp__h451970, + _theResult___fst_exp__h460557, + _theResult___fst_exp__h460622, _theResult___fst_exp__h460628, - _theResult___fst_exp__h461151, - _theResult___fst_exp__h469191, - _theResult___fst_exp__h469230, - _theResult___fst_exp__h469236, + _theResult___fst_exp__h460631, + _theResult___fst_exp__h461154, + _theResult___fst_exp__h469194, + _theResult___fst_exp__h469233, _theResult___fst_exp__h469239, - _theResult___fst_exp__h469787, - _theResult___fst_exp__h469796, + _theResult___fst_exp__h469242, + _theResult___fst_exp__h469790, _theResult___fst_exp__h469799, - _theResult___snd_fst_exp__h360592, - _theResult___snd_fst_exp__h378412, - _theResult___snd_fst_exp__h406282, - _theResult___snd_fst_exp__h424102, - _theResult___snd_fst_exp__h451970, - _theResult___snd_fst_exp__h469790, + _theResult___fst_exp__h469802, + _theResult___snd_fst_exp__h360595, + _theResult___snd_fst_exp__h378415, + _theResult___snd_fst_exp__h406285, + _theResult___snd_fst_exp__h424105, + _theResult___snd_fst_exp__h451973, + _theResult___snd_fst_exp__h469793, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145, - din_inc___2_exp__h378443, - din_inc___2_exp__h378467, - din_inc___2_exp__h378497, - din_inc___2_exp__h378521, - din_inc___2_exp__h424133, - din_inc___2_exp__h424157, - din_inc___2_exp__h424187, - din_inc___2_exp__h424211, - din_inc___2_exp__h469821, - din_inc___2_exp__h469845, - din_inc___2_exp__h469875, - din_inc___2_exp__h469899, - out_exp__h351929, - out_exp__h360511, - out_exp__h369695, - out_exp__h378331, - out_exp__h397619, - out_exp__h406201, - out_exp__h415385, - out_exp__h424021, - out_exp__h443307, - out_exp__h451889, - out_exp__h461073, - out_exp__h469709, - out_f_exp__h378707, - out_f_exp__h424397, - out_f_exp__h470085, - x__h608817; + din_inc___2_exp__h378446, + din_inc___2_exp__h378470, + din_inc___2_exp__h378500, + din_inc___2_exp__h378524, + din_inc___2_exp__h424136, + din_inc___2_exp__h424160, + din_inc___2_exp__h424190, + din_inc___2_exp__h424214, + din_inc___2_exp__h469824, + din_inc___2_exp__h469848, + din_inc___2_exp__h469878, + din_inc___2_exp__h469902, + out_exp__h351932, + out_exp__h360514, + out_exp__h369698, + out_exp__h378334, + out_exp__h397622, + out_exp__h406204, + out_exp__h415388, + out_exp__h424024, + out_exp__h443310, + out_exp__h451892, + out_exp__h461076, + out_exp__h469712, + out_f_exp__h378710, + out_f_exp__h424400, + out_f_exp__h470088, + x__h608822; wire [6 : 0] csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12642; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635, @@ -5345,8 +5345,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890, - x__h180645, - x__h694797; + x__h180648, + x__h694806; wire [4 : 0] IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165, @@ -5366,18 +5366,18 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804, checkForException___d12839, checkForException___d13458, - fflags__h705618, - res_fflags__h335087, - res_fflags__h380782, - res_fflags__h426470, - rs1__h649444, - x__h152883, - x__h156430, - x__h159246, - x__h284498, - y_avValue_snd_fst__h705125, - y_avValue_snd_fst__h705678, - y_avValue_snd_fst__h705707; + fflags__h705627, + res_fflags__h335090, + res_fflags__h380785, + res_fflags__h426473, + rs1__h649453, + x__h152884, + x__h156431, + x__h159247, + x__h284501, + y_avValue_snd_fst__h705134, + y_avValue_snd_fst__h705687, + y_avValue_snd_fst__h705716; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849, IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851, @@ -5404,74 +5404,74 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, IF_fetchStage_pipelines_0_first__2605_BIT_68_2_ETC___d13074, - cause_code__h692180, - vm_mode_reg__read__h610026; + cause_code__h692189, + vm_mode_reg__read__h610031; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h293741, - next_deqP___1__h294020, - v__h293161, - v__h293392, - x__h299371, - x_decodeInfo_frm__h649128; + _theResult_____2__h293743, + next_deqP___1__h294022, + v__h293163, + v__h293394, + x__h299373, + x_decodeInfo_frm__h649137; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771, - IF_sfdin08243_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin14860_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin42782_BIT_33_THEN_2_ELSE_0__q91, - IF_sfdin47044_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin51404_BIT_33_THEN_2_ELSE_0__q21, - IF_sfdin60548_BIT_33_THEN_2_ELSE_0__q101, - IF_sfdin69170_BIT_33_THEN_2_ELSE_0__q31, - IF_sfdin86245_BIT_4_THEN_2_ELSE_0__q148, - IF_sfdin97094_BIT_33_THEN_2_ELSE_0__q56, - IF_theResult___snd05707_BIT_33_THEN_2_ELSE_0__q58, - IF_theResult___snd17028_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd23497_BIT_33_THEN_2_ELSE_0__q71, - IF_theResult___snd37424_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd51395_BIT_33_THEN_2_ELSE_0__q93, - IF_theResult___snd55829_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd60017_BIT_33_THEN_2_ELSE_0__q23, - IF_theResult___snd69185_BIT_33_THEN_2_ELSE_0__q106, - IF_theResult___snd76625_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd77807_BIT_33_THEN_2_ELSE_0__q36, - IF_theResult___snd95030_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd98623_BIT_4_THEN_2_ELSE_0__q127, - guard__h343309, - guard__h352018, - guard__h360948, - guard__h369784, - guard__h389001, - guard__h397708, - guard__h406638, - guard__h415474, - guard__h434689, - guard__h443396, - guard__h452326, - guard__h461162, - guard__h490711, - guard__h500023, - guard__h509092, - guard__h529512, - guard__h538824, - guard__h547893, - guard__h568713, - guard__h578025, - guard__h587094, - prv__h707133, - prv__h707177, - r1__read_BITS_13_TO_12___h649313, - sbIdx__h156309, - v__h600770, - v__h600780, - v__h601415, - x__h702593, - x__h705866, - y_avValue_snd_snd_snd_fst__h705135, - y_avValue_snd_snd_snd_fst__h705688, - y_avValue_snd_snd_snd_fst__h705717; + IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66, + IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91, + IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21, + IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101, + IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31, + IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148, + IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56, + IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58, + IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71, + IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93, + IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23, + IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106, + IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36, + IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127, + guard__h343312, + guard__h352021, + guard__h360951, + guard__h369787, + guard__h389004, + guard__h397711, + guard__h406641, + guard__h415477, + guard__h434692, + guard__h443399, + guard__h452329, + guard__h461165, + guard__h490715, + guard__h500027, + guard__h509096, + guard__h529516, + guard__h538828, + guard__h547897, + guard__h568717, + guard__h578029, + guard__h587098, + prv__h707142, + prv__h707186, + r1__read_BITS_13_TO_12___h649322, + sbIdx__h156310, + v__h600774, + v__h600784, + v__h601419, + x__h702602, + x__h705875, + y_avValue_snd_snd_snd_fst__h705144, + y_avValue_snd_snd_snd_fst__h705697, + y_avValue_snd_snd_snd_fst__h705726; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457, @@ -5872,7 +5872,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo26, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -5898,11 +5898,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h301737, - _theResult_____2__h307731, - _theResult_____2__h315585, - _theResult_____2__h325929, - _theResult_____2__h329154, + _theResult_____2__h301739, + _theResult_____2__h307733, + _theResult_____2__h315587, + _theResult_____2__h325931, + _theResult_____2__h329156, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101, coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12140, coreFix_aluExe_0_bypassWire_1_wget__2112_BITS__ETC___d12114, @@ -6036,14 +6036,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2614_BITS_194_TO_ETC___d13720, fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555, fetchStage_pipelines_1_first__2614_BIT_68_3335_ETC___d13724, - guard__h361546, - guard__h407236, - guard__h452924, - guard__h500621, - guard__h539422, - guard__h578623, - idx__h675470, - k__h661036, + guard__h361549, + guard__h407239, + guard__h452927, + guard__h500625, + guard__h539426, + guard__h578627, + idx__h675479, + k__h661045, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6055,13 +6055,13 @@ module mkCore(CLK, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75409, - next_deqP___1__h302016, - next_deqP___1__h308297, - next_deqP___1__h316151, - next_deqP___1__h326208, - next_deqP___1__h329433, - r1__read_BIT_20___h649941, - r__h608864, + next_deqP___1__h302018, + next_deqP___1__h308299, + next_deqP___1__h316153, + next_deqP___1__h326210, + next_deqP___1__h329435, + r1__read_BIT_20___h649950, + r__h608869, regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688, regRenamingTable_RDY_rename_1_getRename__3744__ETC___d13762, regRenamingTable_rename_0_canRename__3183_AND__ETC___d13258, @@ -6082,17 +6082,17 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631, - v__h296506, - v__h297024, - v__h307020, - v__h307251, - v__h310896, - v__h311127, - v__h325497, - v__h325728, - v__h328722, - v__h328953, - x__h600271; + v__h296508, + v__h297026, + v__h307022, + v__h307253, + v__h310898, + v__h311129, + v__h325499, + v__h325730, + v__h328724, + v__h328955, + x__h600275; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -9449,7 +9449,6 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9499,7 +9498,6 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9597,7 +9595,6 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9628,7 +9625,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -10423,7 +10419,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$RDY_first && IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && + !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = @@ -10783,7 +10783,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -10795,7 +10795,7 @@ module mkCore(CLK, assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = @@ -10803,7 +10803,7 @@ module mkCore(CLK, (rob$deqPort_0_deq_data[186:182] == 5'd19 || rob$deqPort_0_deq_data[186:182] == 5'd20) ; assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -10837,7 +10837,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; assign MUX_rf$write_3_wr_2__SEL_5 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -10860,7 +10860,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[282:219], - x__h688716, + x__h688725, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q259 : @@ -10868,9 +10868,9 @@ module mkCore(CLK, assign MUX_commitStage_rg_instret$write_1__VAL_1 = commitStage_rg_instret + 64'd1 ; assign MUX_commitStage_rg_instret$write_1__VAL_2 = - commitStage_rg_instret + y__h705641 ; + commitStage_rg_instret + y__h705650 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h661036 == 1'd0 && + (k__h661045 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -10891,7 +10891,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -10994,7 +10994,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709, @@ -11008,10 +11008,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h283065 } ; + x__h283068 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h284510, + x__h284513, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11019,7 +11019,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h287286, + addr__h287289, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11032,12 +11032,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h152883, x__h152889, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h152884, x__h152890, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h156430, x__h156436, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h156431, x__h156437, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h159246, - x__h159250, + { x__h159247, + x__h159251, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -11048,7 +11048,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161098, + x__h161099, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -11061,7 +11061,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h289190, + resp_addr__h289193, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11141,7 +11141,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h194346 } ; + x__h194349 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11176,8 +11176,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h190136 : - { {32{x__h190899[31]}}, x__h190899 } } ; + curData__h190139 : + { {32{x__h190902[31]}}, x__h190902 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[325:321], @@ -11206,7 +11206,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h705618 ; + csrf_fflags_reg | fflags__h705627 ; always@(IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 or robdeqPort_0_deq_data_BITS_95_TO_32__q261) begin @@ -11232,9 +11232,9 @@ module mkCore(CLK, csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h703190 + 64'd1 ; + n__read__h703199 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h703190 + { 62'd0, x__h705866 } ; + n__read__h703199 + { 62'd0, x__h705875 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd13 && IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == @@ -11242,7 +11242,7 @@ module mkCore(CLK, MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[4] ? 64'd0 : trap_val__h693211 ; + commitStage_commitTrap[4] ? 64'd0 : trap_val__h693220 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[186:182] != 5'd13 || @@ -11258,7 +11258,7 @@ module mkCore(CLK, MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[186:182] == 5'd19) ? - x__h702593 : + x__h702602 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? @@ -11278,15 +11278,15 @@ module mkCore(CLK, MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ? - y_avValue__h693058 : - y_avValue__h694819 ; + y_avValue__h693067 : + y_avValue__h694828 ; always@(rob$deqPort_0_deq_data or - next_pc__h702533 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h702542 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[186:182]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702533; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h702542; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11321,23 +11321,23 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h473012 : - data__h472478 ; + data___1__h473015 : + data__h472481 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h335091 : - res_data__h335086 ; + res_data__h335094 : + res_data__h335089 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h380786 : - res_data__h380781 ; + res_data__h380789 : + res_data__h380784 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h426474 : - res_data__h426469 ; + res_data__h426477 : + res_data__h426472 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h472204 : + data___1__h472207 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? @@ -11407,24 +11407,24 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h335087 ; + res_fflags__h335090 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h380782 ; + res_fflags__h380785 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h426470 ; + res_fflags__h426473 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -11739,8 +11739,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h601415 : - v__h600770 ; + v__h601419 : + v__h600774 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -11847,7 +11847,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h293741 ; + _theResult_____2__h293743 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -11869,7 +11869,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h293161 ; + v__h293163 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -11915,7 +11915,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - _theResult_____2__h301737 ; + _theResult_____2__h301739 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -11933,7 +11933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 && - v__h296506 ; + v__h296508 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12033,7 +12033,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - _theResult_____2__h307731 ; + _theResult_____2__h307733 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12051,7 +12051,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 && - v__h307020 ; + v__h307022 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12072,7 +12072,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h311294, + { x_addr__h311296, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12102,7 +12102,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - _theResult_____2__h315585 ; + _theResult_____2__h315587 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12120,7 +12120,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 && - v__h310896 ; + v__h310898 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12197,7 +12197,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - _theResult_____2__h329154 ; + _theResult_____2__h329156 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12215,7 +12215,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 && - v__h328722 ; + v__h328724 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12258,7 +12258,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - _theResult_____2__h325929 ; + _theResult_____2__h325931 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12276,7 +12276,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 && - v__h325497 ; + v__h325499 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12554,7 +12554,7 @@ module mkCore(CLK, MUX_csrf_ie_vec_1$write_1__SEL_1 && MUX_csrf_ie_vec_1$write_1__VAL_1 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12570,7 +12570,7 @@ module mkCore(CLK, // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_2 ? - cause_code__h692180 : + cause_code__h692189 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12787,7 +12787,7 @@ module mkCore(CLK, MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : csrf_ie_vec_1 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -12815,7 +12815,7 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_2 ? - cause_code__h692180 : + cause_code__h692189 : csrf_mscratch_csr$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -12933,7 +12933,7 @@ module mkCore(CLK, MUX_csrf_spp_reg$write_1__VAL_1 : csrf_prv_reg[0] ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2633_ULE_1_4189_AND_IF_comm_ETC___d14229 ; @@ -13472,8 +13472,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h634247, - x__h634248, + x__h634256, + x__h634257, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -13762,8 +13762,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h613028, - x__h613029, + x__h613033, + x__h613034, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -13805,7 +13805,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h661036 == 1'd1 && + (k__h661045 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d12731, @@ -13826,7 +13826,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -13924,7 +13924,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h661036 == 1'd1 && + (k__h661045 == 1'd1 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd1 && @@ -14310,19 +14310,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h600257 : - a__h599835 ; + _theResult___fst__h600261 : + a__h599839 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h599836 == 64'd0, - a__h599835, + { b__h599840 == 64'd0, + a__h599839, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h600271, - a__h599835[63], + x__h600275, + a__h599839[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h600258 : - b__h599836 ; + _theResult___snd__h600262 : + b__h599840 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14383,20 +14383,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599835 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599836 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599839 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599840 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h599835 ; + a__h599839 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h599836 ; + b__h599840 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h599835 ; + a__h599839 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h599836 ; + b__h599840 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -14425,9 +14425,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h478866, - x__h478867, - x__h478868, + x__h478870, + x__h478871, + x__h478872, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -14456,7 +14456,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || @@ -14479,7 +14479,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14633,8 +14633,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h284498, - x__h284510, + { x__h284501, + x__h284513, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793, @@ -14645,13 +14645,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824, - x__h286364, + x__h286367, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h283065 ; + x__h283068 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15288,13 +15288,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h180508[2:0], - vaddr__h180508, + coreFix_memExe_lsq$getOrigBE << vaddr__h180511[2:0], + vaddr__h180511, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h180508[2:0] != 3'd0 : + vaddr__h180511[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h180508[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180508[0]), + vaddr__h180511[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180511[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15324,8 +15324,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h707177, - prv__h707177 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h707186, + prv__h707186 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15450,7 +15450,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13875) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675339 ; + renaming_spec_bits__h675348 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? @@ -15470,7 +15470,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3183_AND__ETC___d13883) ? specTagManager$currentSpecBits : - renaming_spec_bits__h675339 ; + renaming_spec_bits__h675348 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15550,7 +15550,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h180513 ; + shiftData__h180516 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15650,8 +15650,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h180422, - x__h180423, + x__h180425, + x__h180426, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 ; @@ -15915,7 +15915,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BIT_160__ETC___d13998, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h675339, + renaming_spec_bits__h675348, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16624,7 +16624,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h675339 ; + renaming_spec_bits__h675348 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -16883,7 +16883,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_191_ETC___d13992, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d14039, 7'd32, - renaming_spec_bits__h675339 } ; + renaming_spec_bits__h675348 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -16893,24 +16893,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -17102,16 +17102,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -17385,10 +17385,10 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h190136), + .amoExec_current_data(curData__h190139), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h191674)); + .amoExec(n__h191677)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, @@ -17425,7 +17425,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2605_BITS_172_ETC___d12805 }, fetchStage$pipelines_0_first[160], - x_data_imm__h667940 } }), + x_data_imm__h667949 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17434,12 +17434,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649128, - r1__read_BITS_13_TO_12___h649313 != + .checkForException_csrState({ x_decodeInfo_frm__h649137, + r1__read_BITS_13_TO_12___h649322 != 2'd0, - { prv__h707133, + { prv__h707142, csrf_tvm_reg, - { r1__read_BIT_20___h649941, + { r1__read_BIT_20___h649950, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17455,7 +17455,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2614_BITS_194_ETC___d13361, { fetchStage_pipelines_1_first__2614_BIT_173_336_ETC___d13437, fetchStage$pipelines_1_first[160], - x_data_imm__h682683 } }), + x_data_imm__h682692 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17464,12 +17464,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } }), - .checkForException_csrState({ x_decodeInfo_frm__h649128, - r1__read_BITS_13_TO_12___h649313 != + .checkForException_csrState({ x_decodeInfo_frm__h649137, + r1__read_BITS_13_TO_12___h649322 != 2'd0, - { prv__h707133, + { prv__h707142, csrf_tvm_reg, - { r1__read_BIT_20___h649941, + { r1__read_BIT_20___h649950, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17484,139 +17484,139 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h478957), - .execFpuSimple_rVal2(rVal2__h478958), + .execFpuSimple_rVal1(rVal1__h478961), + .execFpuSimple_rVal2(rVal2__h478962), .execFpuSimple(execFpuSimple___d11034)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ? - _theResult___snd__h351473 : - _theResult____h343299 ; + _theResult___snd__h351476 : + _theResult____h343302 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ? - _theResult___snd__h397163 : - _theResult____h388991 ; + _theResult___snd__h397166 : + _theResult____h388994 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ? - _theResult___snd__h442851 : - _theResult____h434679 ; + _theResult___snd__h442854 : + _theResult____h434682 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 ? - _theResult___snd__h508312 : - _theResult____h500013 ; + _theResult___snd__h508316 : + _theResult____h500017 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599 ? - _theResult___snd__h586314 : - _theResult____h578015 ; + _theResult___snd__h586318 : + _theResult____h578019 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 ? - _theResult___snd__h547113 : - _theResult____h538814 ; + _theResult___snd__h547117 : + _theResult____h538818 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ? - _theResult___snd__h460617 : - _theResult____h452316 ; + _theResult___snd__h460620 : + _theResult____h452319 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ? - _theResult___snd__h369239 : - _theResult____h360938 ; + _theResult___snd__h369242 : + _theResult____h360941 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ? - _theResult___snd__h414929 : - _theResult____h406628 ; + _theResult___snd__h414932 : + _theResult____h406631 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ? - _theResult___snd__h451433 : - _theResult___snd__h469223 ; + _theResult___snd__h451436 : + _theResult___snd__h469226 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ? - _theResult___snd__h360055 : + _theResult___snd__h360058 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ? - _theResult___snd__h360055 : - _theResult___snd__h377845 ; + _theResult___snd__h360058 : + _theResult___snd__h377848 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ? - _theResult___snd__h405745 : + _theResult___snd__h405748 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ? - _theResult___snd__h405745 : - _theResult___snd__h423535 ; + _theResult___snd__h405748 : + _theResult___snd__h423538 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ? - _theResult___snd__h451433 : + _theResult___snd__h451436 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 ? - _theResult___snd__h498661 : + _theResult___snd__h498665 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939 ? - _theResult___snd__h498661 : - _theResult___snd__h517066 ; + _theResult___snd__h498665 : + _theResult___snd__h517070 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302 ? - _theResult___snd__h576663 : + _theResult___snd__h576667 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649 ? - _theResult___snd__h576663 : - _theResult___snd__h595068 ; + _theResult___snd__h576667 : + _theResult___snd__h595072 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 ? - _theResult___snd__h537462 : + _theResult___snd__h537466 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412 ? - _theResult___snd__h537462 : - _theResult___snd__h555867 ; + _theResult___snd__h537466 : + _theResult___snd__h555871 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351410 == 8'd255) ? + ((_theResult___fst_exp__h351413 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) : - ((_theResult___fst_exp__h360066 == 8'd255) ? + ((_theResult___fst_exp__h360069 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - ((_theResult___fst_exp__h351410 == 8'd255) ? + ((_theResult___fst_exp__h351413 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) : - ((_theResult___fst_exp__h360066 == 8'd255) ? + ((_theResult___fst_exp__h360069 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397100 == 8'd255) ? + ((_theResult___fst_exp__h397103 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) : - ((_theResult___fst_exp__h405756 == 8'd255) ? + ((_theResult___fst_exp__h405759 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - ((_theResult___fst_exp__h397100 == 8'd255) ? + ((_theResult___fst_exp__h397103 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) : - ((_theResult___fst_exp__h405756 == 8'd255) ? + ((_theResult___fst_exp__h405759 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442788 == 8'd255) ? + ((_theResult___fst_exp__h442791 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) : - ((_theResult___fst_exp__h451444 == 8'd255) ? + ((_theResult___fst_exp__h451447 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - ((_theResult___fst_exp__h442788 == 8'd255) ? + ((_theResult___fst_exp__h442791 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) : - ((_theResult___fst_exp__h451444 == 8'd255) ? + ((_theResult___fst_exp__h451447 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ; assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10657 = @@ -17632,1571 +17632,1571 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892) : !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 = - (_theResult____h343299[56] ? + (_theResult____h343302[56] ? 6'd0 : - (_theResult____h343299[55] ? + (_theResult____h343302[55] ? 6'd1 : - (_theResult____h343299[54] ? + (_theResult____h343302[54] ? 6'd2 : - (_theResult____h343299[53] ? + (_theResult____h343302[53] ? 6'd3 : - (_theResult____h343299[52] ? + (_theResult____h343302[52] ? 6'd4 : - (_theResult____h343299[51] ? + (_theResult____h343302[51] ? 6'd5 : - (_theResult____h343299[50] ? + (_theResult____h343302[50] ? 6'd6 : - (_theResult____h343299[49] ? + (_theResult____h343302[49] ? 6'd7 : - (_theResult____h343299[48] ? + (_theResult____h343302[48] ? 6'd8 : - (_theResult____h343299[47] ? + (_theResult____h343302[47] ? 6'd9 : - (_theResult____h343299[46] ? + (_theResult____h343302[46] ? 6'd10 : - (_theResult____h343299[45] ? + (_theResult____h343302[45] ? 6'd11 : - (_theResult____h343299[44] ? + (_theResult____h343302[44] ? 6'd12 : - (_theResult____h343299[43] ? + (_theResult____h343302[43] ? 6'd13 : - (_theResult____h343299[42] ? + (_theResult____h343302[42] ? 6'd14 : - (_theResult____h343299[41] ? + (_theResult____h343302[41] ? 6'd15 : - (_theResult____h343299[40] ? + (_theResult____h343302[40] ? 6'd16 : - (_theResult____h343299[39] ? + (_theResult____h343302[39] ? 6'd17 : - (_theResult____h343299[38] ? + (_theResult____h343302[38] ? 6'd18 : - (_theResult____h343299[37] ? + (_theResult____h343302[37] ? 6'd19 : - (_theResult____h343299[36] ? + (_theResult____h343302[36] ? 6'd20 : - (_theResult____h343299[35] ? + (_theResult____h343302[35] ? 6'd21 : - (_theResult____h343299[34] ? + (_theResult____h343302[34] ? 6'd22 : - (_theResult____h343299[33] ? + (_theResult____h343302[33] ? 6'd23 : - (_theResult____h343299[32] ? + (_theResult____h343302[32] ? 6'd24 : - (_theResult____h343299[31] ? + (_theResult____h343302[31] ? 6'd25 : - (_theResult____h343299[30] ? + (_theResult____h343302[30] ? 6'd26 : - (_theResult____h343299[29] ? + (_theResult____h343302[29] ? 6'd27 : - (_theResult____h343299[28] ? + (_theResult____h343302[28] ? 6'd28 : - (_theResult____h343299[27] ? + (_theResult____h343302[27] ? 6'd29 : - (_theResult____h343299[26] ? + (_theResult____h343302[26] ? 6'd30 : - (_theResult____h343299[25] ? + (_theResult____h343302[25] ? 6'd31 : - (_theResult____h343299[24] ? + (_theResult____h343302[24] ? 6'd32 : - (_theResult____h343299[23] ? + (_theResult____h343302[23] ? 6'd33 : - (_theResult____h343299[22] ? + (_theResult____h343302[22] ? 6'd34 : - (_theResult____h343299[21] ? + (_theResult____h343302[21] ? 6'd35 : - (_theResult____h343299[20] ? + (_theResult____h343302[20] ? 6'd36 : - (_theResult____h343299[19] ? + (_theResult____h343302[19] ? 6'd37 : - (_theResult____h343299[18] ? + (_theResult____h343302[18] ? 6'd38 : - (_theResult____h343299[17] ? + (_theResult____h343302[17] ? 6'd39 : - (_theResult____h343299[16] ? + (_theResult____h343302[16] ? 6'd40 : - (_theResult____h343299[15] ? + (_theResult____h343302[15] ? 6'd41 : - (_theResult____h343299[14] ? + (_theResult____h343302[14] ? 6'd42 : - (_theResult____h343299[13] ? + (_theResult____h343302[13] ? 6'd43 : - (_theResult____h343299[12] ? + (_theResult____h343302[12] ? 6'd44 : - (_theResult____h343299[11] ? + (_theResult____h343302[11] ? 6'd45 : - (_theResult____h343299[10] ? + (_theResult____h343302[10] ? 6'd46 : - (_theResult____h343299[9] ? + (_theResult____h343302[9] ? 6'd47 : - (_theResult____h343299[8] ? + (_theResult____h343302[8] ? 6'd48 : - (_theResult____h343299[7] ? + (_theResult____h343302[7] ? 6'd49 : - (_theResult____h343299[6] ? + (_theResult____h343302[6] ? 6'd50 : - (_theResult____h343299[5] ? + (_theResult____h343302[5] ? 6'd51 : - (_theResult____h343299[4] ? + (_theResult____h343302[4] ? 6'd52 : - (_theResult____h343299[3] ? + (_theResult____h343302[3] ? 6'd53 : - (_theResult____h343299[2] ? + (_theResult____h343302[2] ? 6'd54 : - (_theResult____h343299[1] ? + (_theResult____h343302[1] ? 6'd55 : - (_theResult____h343299[0] ? + (_theResult____h343302[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 = - (_theResult____h388991[56] ? + (_theResult____h388994[56] ? 6'd0 : - (_theResult____h388991[55] ? + (_theResult____h388994[55] ? 6'd1 : - (_theResult____h388991[54] ? + (_theResult____h388994[54] ? 6'd2 : - (_theResult____h388991[53] ? + (_theResult____h388994[53] ? 6'd3 : - (_theResult____h388991[52] ? + (_theResult____h388994[52] ? 6'd4 : - (_theResult____h388991[51] ? + (_theResult____h388994[51] ? 6'd5 : - (_theResult____h388991[50] ? + (_theResult____h388994[50] ? 6'd6 : - (_theResult____h388991[49] ? + (_theResult____h388994[49] ? 6'd7 : - (_theResult____h388991[48] ? + (_theResult____h388994[48] ? 6'd8 : - (_theResult____h388991[47] ? + (_theResult____h388994[47] ? 6'd9 : - (_theResult____h388991[46] ? + (_theResult____h388994[46] ? 6'd10 : - (_theResult____h388991[45] ? + (_theResult____h388994[45] ? 6'd11 : - (_theResult____h388991[44] ? + (_theResult____h388994[44] ? 6'd12 : - (_theResult____h388991[43] ? + (_theResult____h388994[43] ? 6'd13 : - (_theResult____h388991[42] ? + (_theResult____h388994[42] ? 6'd14 : - (_theResult____h388991[41] ? + (_theResult____h388994[41] ? 6'd15 : - (_theResult____h388991[40] ? + (_theResult____h388994[40] ? 6'd16 : - (_theResult____h388991[39] ? + (_theResult____h388994[39] ? 6'd17 : - (_theResult____h388991[38] ? + (_theResult____h388994[38] ? 6'd18 : - (_theResult____h388991[37] ? + (_theResult____h388994[37] ? 6'd19 : - (_theResult____h388991[36] ? + (_theResult____h388994[36] ? 6'd20 : - (_theResult____h388991[35] ? + (_theResult____h388994[35] ? 6'd21 : - (_theResult____h388991[34] ? + (_theResult____h388994[34] ? 6'd22 : - (_theResult____h388991[33] ? + (_theResult____h388994[33] ? 6'd23 : - (_theResult____h388991[32] ? + (_theResult____h388994[32] ? 6'd24 : - (_theResult____h388991[31] ? + (_theResult____h388994[31] ? 6'd25 : - (_theResult____h388991[30] ? + (_theResult____h388994[30] ? 6'd26 : - (_theResult____h388991[29] ? + (_theResult____h388994[29] ? 6'd27 : - (_theResult____h388991[28] ? + (_theResult____h388994[28] ? 6'd28 : - (_theResult____h388991[27] ? + (_theResult____h388994[27] ? 6'd29 : - (_theResult____h388991[26] ? + (_theResult____h388994[26] ? 6'd30 : - (_theResult____h388991[25] ? + (_theResult____h388994[25] ? 6'd31 : - (_theResult____h388991[24] ? + (_theResult____h388994[24] ? 6'd32 : - (_theResult____h388991[23] ? + (_theResult____h388994[23] ? 6'd33 : - (_theResult____h388991[22] ? + (_theResult____h388994[22] ? 6'd34 : - (_theResult____h388991[21] ? + (_theResult____h388994[21] ? 6'd35 : - (_theResult____h388991[20] ? + (_theResult____h388994[20] ? 6'd36 : - (_theResult____h388991[19] ? + (_theResult____h388994[19] ? 6'd37 : - (_theResult____h388991[18] ? + (_theResult____h388994[18] ? 6'd38 : - (_theResult____h388991[17] ? + (_theResult____h388994[17] ? 6'd39 : - (_theResult____h388991[16] ? + (_theResult____h388994[16] ? 6'd40 : - (_theResult____h388991[15] ? + (_theResult____h388994[15] ? 6'd41 : - (_theResult____h388991[14] ? + (_theResult____h388994[14] ? 6'd42 : - (_theResult____h388991[13] ? + (_theResult____h388994[13] ? 6'd43 : - (_theResult____h388991[12] ? + (_theResult____h388994[12] ? 6'd44 : - (_theResult____h388991[11] ? + (_theResult____h388994[11] ? 6'd45 : - (_theResult____h388991[10] ? + (_theResult____h388994[10] ? 6'd46 : - (_theResult____h388991[9] ? + (_theResult____h388994[9] ? 6'd47 : - (_theResult____h388991[8] ? + (_theResult____h388994[8] ? 6'd48 : - (_theResult____h388991[7] ? + (_theResult____h388994[7] ? 6'd49 : - (_theResult____h388991[6] ? + (_theResult____h388994[6] ? 6'd50 : - (_theResult____h388991[5] ? + (_theResult____h388994[5] ? 6'd51 : - (_theResult____h388991[4] ? + (_theResult____h388994[4] ? 6'd52 : - (_theResult____h388991[3] ? + (_theResult____h388994[3] ? 6'd53 : - (_theResult____h388991[2] ? + (_theResult____h388994[2] ? 6'd54 : - (_theResult____h388991[1] ? + (_theResult____h388994[1] ? 6'd55 : - (_theResult____h388991[0] ? + (_theResult____h388994[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 = - (_theResult____h434679[56] ? + (_theResult____h434682[56] ? 6'd0 : - (_theResult____h434679[55] ? + (_theResult____h434682[55] ? 6'd1 : - (_theResult____h434679[54] ? + (_theResult____h434682[54] ? 6'd2 : - (_theResult____h434679[53] ? + (_theResult____h434682[53] ? 6'd3 : - (_theResult____h434679[52] ? + (_theResult____h434682[52] ? 6'd4 : - (_theResult____h434679[51] ? + (_theResult____h434682[51] ? 6'd5 : - (_theResult____h434679[50] ? + (_theResult____h434682[50] ? 6'd6 : - (_theResult____h434679[49] ? + (_theResult____h434682[49] ? 6'd7 : - (_theResult____h434679[48] ? + (_theResult____h434682[48] ? 6'd8 : - (_theResult____h434679[47] ? + (_theResult____h434682[47] ? 6'd9 : - (_theResult____h434679[46] ? + (_theResult____h434682[46] ? 6'd10 : - (_theResult____h434679[45] ? + (_theResult____h434682[45] ? 6'd11 : - (_theResult____h434679[44] ? + (_theResult____h434682[44] ? 6'd12 : - (_theResult____h434679[43] ? + (_theResult____h434682[43] ? 6'd13 : - (_theResult____h434679[42] ? + (_theResult____h434682[42] ? 6'd14 : - (_theResult____h434679[41] ? + (_theResult____h434682[41] ? 6'd15 : - (_theResult____h434679[40] ? + (_theResult____h434682[40] ? 6'd16 : - (_theResult____h434679[39] ? + (_theResult____h434682[39] ? 6'd17 : - (_theResult____h434679[38] ? + (_theResult____h434682[38] ? 6'd18 : - (_theResult____h434679[37] ? + (_theResult____h434682[37] ? 6'd19 : - (_theResult____h434679[36] ? + (_theResult____h434682[36] ? 6'd20 : - (_theResult____h434679[35] ? + (_theResult____h434682[35] ? 6'd21 : - (_theResult____h434679[34] ? + (_theResult____h434682[34] ? 6'd22 : - (_theResult____h434679[33] ? + (_theResult____h434682[33] ? 6'd23 : - (_theResult____h434679[32] ? + (_theResult____h434682[32] ? 6'd24 : - (_theResult____h434679[31] ? + (_theResult____h434682[31] ? 6'd25 : - (_theResult____h434679[30] ? + (_theResult____h434682[30] ? 6'd26 : - (_theResult____h434679[29] ? + (_theResult____h434682[29] ? 6'd27 : - (_theResult____h434679[28] ? + (_theResult____h434682[28] ? 6'd28 : - (_theResult____h434679[27] ? + (_theResult____h434682[27] ? 6'd29 : - (_theResult____h434679[26] ? + (_theResult____h434682[26] ? 6'd30 : - (_theResult____h434679[25] ? + (_theResult____h434682[25] ? 6'd31 : - (_theResult____h434679[24] ? + (_theResult____h434682[24] ? 6'd32 : - (_theResult____h434679[23] ? + (_theResult____h434682[23] ? 6'd33 : - (_theResult____h434679[22] ? + (_theResult____h434682[22] ? 6'd34 : - (_theResult____h434679[21] ? + (_theResult____h434682[21] ? 6'd35 : - (_theResult____h434679[20] ? + (_theResult____h434682[20] ? 6'd36 : - (_theResult____h434679[19] ? + (_theResult____h434682[19] ? 6'd37 : - (_theResult____h434679[18] ? + (_theResult____h434682[18] ? 6'd38 : - (_theResult____h434679[17] ? + (_theResult____h434682[17] ? 6'd39 : - (_theResult____h434679[16] ? + (_theResult____h434682[16] ? 6'd40 : - (_theResult____h434679[15] ? + (_theResult____h434682[15] ? 6'd41 : - (_theResult____h434679[14] ? + (_theResult____h434682[14] ? 6'd42 : - (_theResult____h434679[13] ? + (_theResult____h434682[13] ? 6'd43 : - (_theResult____h434679[12] ? + (_theResult____h434682[12] ? 6'd44 : - (_theResult____h434679[11] ? + (_theResult____h434682[11] ? 6'd45 : - (_theResult____h434679[10] ? + (_theResult____h434682[10] ? 6'd46 : - (_theResult____h434679[9] ? + (_theResult____h434682[9] ? 6'd47 : - (_theResult____h434679[8] ? + (_theResult____h434682[8] ? 6'd48 : - (_theResult____h434679[7] ? + (_theResult____h434682[7] ? 6'd49 : - (_theResult____h434679[6] ? + (_theResult____h434682[6] ? 6'd50 : - (_theResult____h434679[5] ? + (_theResult____h434682[5] ? 6'd51 : - (_theResult____h434679[4] ? + (_theResult____h434682[4] ? 6'd52 : - (_theResult____h434679[3] ? + (_theResult____h434682[3] ? 6'd53 : - (_theResult____h434679[2] ? + (_theResult____h434682[2] ? 6'd54 : - (_theResult____h434679[1] ? + (_theResult____h434682[1] ? 6'd55 : - (_theResult____h434679[0] ? + (_theResult____h434682[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 = - (_theResult____h538814[56] ? + (_theResult____h538818[56] ? 6'd0 : - (_theResult____h538814[55] ? + (_theResult____h538818[55] ? 6'd1 : - (_theResult____h538814[54] ? + (_theResult____h538818[54] ? 6'd2 : - (_theResult____h538814[53] ? + (_theResult____h538818[53] ? 6'd3 : - (_theResult____h538814[52] ? + (_theResult____h538818[52] ? 6'd4 : - (_theResult____h538814[51] ? + (_theResult____h538818[51] ? 6'd5 : - (_theResult____h538814[50] ? + (_theResult____h538818[50] ? 6'd6 : - (_theResult____h538814[49] ? + (_theResult____h538818[49] ? 6'd7 : - (_theResult____h538814[48] ? + (_theResult____h538818[48] ? 6'd8 : - (_theResult____h538814[47] ? + (_theResult____h538818[47] ? 6'd9 : - (_theResult____h538814[46] ? + (_theResult____h538818[46] ? 6'd10 : - (_theResult____h538814[45] ? + (_theResult____h538818[45] ? 6'd11 : - (_theResult____h538814[44] ? + (_theResult____h538818[44] ? 6'd12 : - (_theResult____h538814[43] ? + (_theResult____h538818[43] ? 6'd13 : - (_theResult____h538814[42] ? + (_theResult____h538818[42] ? 6'd14 : - (_theResult____h538814[41] ? + (_theResult____h538818[41] ? 6'd15 : - (_theResult____h538814[40] ? + (_theResult____h538818[40] ? 6'd16 : - (_theResult____h538814[39] ? + (_theResult____h538818[39] ? 6'd17 : - (_theResult____h538814[38] ? + (_theResult____h538818[38] ? 6'd18 : - (_theResult____h538814[37] ? + (_theResult____h538818[37] ? 6'd19 : - (_theResult____h538814[36] ? + (_theResult____h538818[36] ? 6'd20 : - (_theResult____h538814[35] ? + (_theResult____h538818[35] ? 6'd21 : - (_theResult____h538814[34] ? + (_theResult____h538818[34] ? 6'd22 : - (_theResult____h538814[33] ? + (_theResult____h538818[33] ? 6'd23 : - (_theResult____h538814[32] ? + (_theResult____h538818[32] ? 6'd24 : - (_theResult____h538814[31] ? + (_theResult____h538818[31] ? 6'd25 : - (_theResult____h538814[30] ? + (_theResult____h538818[30] ? 6'd26 : - (_theResult____h538814[29] ? + (_theResult____h538818[29] ? 6'd27 : - (_theResult____h538814[28] ? + (_theResult____h538818[28] ? 6'd28 : - (_theResult____h538814[27] ? + (_theResult____h538818[27] ? 6'd29 : - (_theResult____h538814[26] ? + (_theResult____h538818[26] ? 6'd30 : - (_theResult____h538814[25] ? + (_theResult____h538818[25] ? 6'd31 : - (_theResult____h538814[24] ? + (_theResult____h538818[24] ? 6'd32 : - (_theResult____h538814[23] ? + (_theResult____h538818[23] ? 6'd33 : - (_theResult____h538814[22] ? + (_theResult____h538818[22] ? 6'd34 : - (_theResult____h538814[21] ? + (_theResult____h538818[21] ? 6'd35 : - (_theResult____h538814[20] ? + (_theResult____h538818[20] ? 6'd36 : - (_theResult____h538814[19] ? + (_theResult____h538818[19] ? 6'd37 : - (_theResult____h538814[18] ? + (_theResult____h538818[18] ? 6'd38 : - (_theResult____h538814[17] ? + (_theResult____h538818[17] ? 6'd39 : - (_theResult____h538814[16] ? + (_theResult____h538818[16] ? 6'd40 : - (_theResult____h538814[15] ? + (_theResult____h538818[15] ? 6'd41 : - (_theResult____h538814[14] ? + (_theResult____h538818[14] ? 6'd42 : - (_theResult____h538814[13] ? + (_theResult____h538818[13] ? 6'd43 : - (_theResult____h538814[12] ? + (_theResult____h538818[12] ? 6'd44 : - (_theResult____h538814[11] ? + (_theResult____h538818[11] ? 6'd45 : - (_theResult____h538814[10] ? + (_theResult____h538818[10] ? 6'd46 : - (_theResult____h538814[9] ? + (_theResult____h538818[9] ? 6'd47 : - (_theResult____h538814[8] ? + (_theResult____h538818[8] ? 6'd48 : - (_theResult____h538814[7] ? + (_theResult____h538818[7] ? 6'd49 : - (_theResult____h538814[6] ? + (_theResult____h538818[6] ? 6'd50 : - (_theResult____h538814[5] ? + (_theResult____h538818[5] ? 6'd51 : - (_theResult____h538814[4] ? + (_theResult____h538818[4] ? 6'd52 : - (_theResult____h538814[3] ? + (_theResult____h538818[3] ? 6'd53 : - (_theResult____h538814[2] ? + (_theResult____h538818[2] ? 6'd54 : - (_theResult____h538814[1] ? + (_theResult____h538818[1] ? 6'd55 : - (_theResult____h538814[0] ? + (_theResult____h538818[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 = - (_theResult____h500013[56] ? + (_theResult____h500017[56] ? 6'd0 : - (_theResult____h500013[55] ? + (_theResult____h500017[55] ? 6'd1 : - (_theResult____h500013[54] ? + (_theResult____h500017[54] ? 6'd2 : - (_theResult____h500013[53] ? + (_theResult____h500017[53] ? 6'd3 : - (_theResult____h500013[52] ? + (_theResult____h500017[52] ? 6'd4 : - (_theResult____h500013[51] ? + (_theResult____h500017[51] ? 6'd5 : - (_theResult____h500013[50] ? + (_theResult____h500017[50] ? 6'd6 : - (_theResult____h500013[49] ? + (_theResult____h500017[49] ? 6'd7 : - (_theResult____h500013[48] ? + (_theResult____h500017[48] ? 6'd8 : - (_theResult____h500013[47] ? + (_theResult____h500017[47] ? 6'd9 : - (_theResult____h500013[46] ? + (_theResult____h500017[46] ? 6'd10 : - (_theResult____h500013[45] ? + (_theResult____h500017[45] ? 6'd11 : - (_theResult____h500013[44] ? + (_theResult____h500017[44] ? 6'd12 : - (_theResult____h500013[43] ? + (_theResult____h500017[43] ? 6'd13 : - (_theResult____h500013[42] ? + (_theResult____h500017[42] ? 6'd14 : - (_theResult____h500013[41] ? + (_theResult____h500017[41] ? 6'd15 : - (_theResult____h500013[40] ? + (_theResult____h500017[40] ? 6'd16 : - (_theResult____h500013[39] ? + (_theResult____h500017[39] ? 6'd17 : - (_theResult____h500013[38] ? + (_theResult____h500017[38] ? 6'd18 : - (_theResult____h500013[37] ? + (_theResult____h500017[37] ? 6'd19 : - (_theResult____h500013[36] ? + (_theResult____h500017[36] ? 6'd20 : - (_theResult____h500013[35] ? + (_theResult____h500017[35] ? 6'd21 : - (_theResult____h500013[34] ? + (_theResult____h500017[34] ? 6'd22 : - (_theResult____h500013[33] ? + (_theResult____h500017[33] ? 6'd23 : - (_theResult____h500013[32] ? + (_theResult____h500017[32] ? 6'd24 : - (_theResult____h500013[31] ? + (_theResult____h500017[31] ? 6'd25 : - (_theResult____h500013[30] ? + (_theResult____h500017[30] ? 6'd26 : - (_theResult____h500013[29] ? + (_theResult____h500017[29] ? 6'd27 : - (_theResult____h500013[28] ? + (_theResult____h500017[28] ? 6'd28 : - (_theResult____h500013[27] ? + (_theResult____h500017[27] ? 6'd29 : - (_theResult____h500013[26] ? + (_theResult____h500017[26] ? 6'd30 : - (_theResult____h500013[25] ? + (_theResult____h500017[25] ? 6'd31 : - (_theResult____h500013[24] ? + (_theResult____h500017[24] ? 6'd32 : - (_theResult____h500013[23] ? + (_theResult____h500017[23] ? 6'd33 : - (_theResult____h500013[22] ? + (_theResult____h500017[22] ? 6'd34 : - (_theResult____h500013[21] ? + (_theResult____h500017[21] ? 6'd35 : - (_theResult____h500013[20] ? + (_theResult____h500017[20] ? 6'd36 : - (_theResult____h500013[19] ? + (_theResult____h500017[19] ? 6'd37 : - (_theResult____h500013[18] ? + (_theResult____h500017[18] ? 6'd38 : - (_theResult____h500013[17] ? + (_theResult____h500017[17] ? 6'd39 : - (_theResult____h500013[16] ? + (_theResult____h500017[16] ? 6'd40 : - (_theResult____h500013[15] ? + (_theResult____h500017[15] ? 6'd41 : - (_theResult____h500013[14] ? + (_theResult____h500017[14] ? 6'd42 : - (_theResult____h500013[13] ? + (_theResult____h500017[13] ? 6'd43 : - (_theResult____h500013[12] ? + (_theResult____h500017[12] ? 6'd44 : - (_theResult____h500013[11] ? + (_theResult____h500017[11] ? 6'd45 : - (_theResult____h500013[10] ? + (_theResult____h500017[10] ? 6'd46 : - (_theResult____h500013[9] ? + (_theResult____h500017[9] ? 6'd47 : - (_theResult____h500013[8] ? + (_theResult____h500017[8] ? 6'd48 : - (_theResult____h500013[7] ? + (_theResult____h500017[7] ? 6'd49 : - (_theResult____h500013[6] ? + (_theResult____h500017[6] ? 6'd50 : - (_theResult____h500013[5] ? + (_theResult____h500017[5] ? 6'd51 : - (_theResult____h500013[4] ? + (_theResult____h500017[4] ? 6'd52 : - (_theResult____h500013[3] ? + (_theResult____h500017[3] ? 6'd53 : - (_theResult____h500013[2] ? + (_theResult____h500017[2] ? 6'd54 : - (_theResult____h500013[1] ? + (_theResult____h500017[1] ? 6'd55 : - (_theResult____h500013[0] ? + (_theResult____h500017[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 = - (_theResult____h578015[56] ? + (_theResult____h578019[56] ? 6'd0 : - (_theResult____h578015[55] ? + (_theResult____h578019[55] ? 6'd1 : - (_theResult____h578015[54] ? + (_theResult____h578019[54] ? 6'd2 : - (_theResult____h578015[53] ? + (_theResult____h578019[53] ? 6'd3 : - (_theResult____h578015[52] ? + (_theResult____h578019[52] ? 6'd4 : - (_theResult____h578015[51] ? + (_theResult____h578019[51] ? 6'd5 : - (_theResult____h578015[50] ? + (_theResult____h578019[50] ? 6'd6 : - (_theResult____h578015[49] ? + (_theResult____h578019[49] ? 6'd7 : - (_theResult____h578015[48] ? + (_theResult____h578019[48] ? 6'd8 : - (_theResult____h578015[47] ? + (_theResult____h578019[47] ? 6'd9 : - (_theResult____h578015[46] ? + (_theResult____h578019[46] ? 6'd10 : - (_theResult____h578015[45] ? + (_theResult____h578019[45] ? 6'd11 : - (_theResult____h578015[44] ? + (_theResult____h578019[44] ? 6'd12 : - (_theResult____h578015[43] ? + (_theResult____h578019[43] ? 6'd13 : - (_theResult____h578015[42] ? + (_theResult____h578019[42] ? 6'd14 : - (_theResult____h578015[41] ? + (_theResult____h578019[41] ? 6'd15 : - (_theResult____h578015[40] ? + (_theResult____h578019[40] ? 6'd16 : - (_theResult____h578015[39] ? + (_theResult____h578019[39] ? 6'd17 : - (_theResult____h578015[38] ? + (_theResult____h578019[38] ? 6'd18 : - (_theResult____h578015[37] ? + (_theResult____h578019[37] ? 6'd19 : - (_theResult____h578015[36] ? + (_theResult____h578019[36] ? 6'd20 : - (_theResult____h578015[35] ? + (_theResult____h578019[35] ? 6'd21 : - (_theResult____h578015[34] ? + (_theResult____h578019[34] ? 6'd22 : - (_theResult____h578015[33] ? + (_theResult____h578019[33] ? 6'd23 : - (_theResult____h578015[32] ? + (_theResult____h578019[32] ? 6'd24 : - (_theResult____h578015[31] ? + (_theResult____h578019[31] ? 6'd25 : - (_theResult____h578015[30] ? + (_theResult____h578019[30] ? 6'd26 : - (_theResult____h578015[29] ? + (_theResult____h578019[29] ? 6'd27 : - (_theResult____h578015[28] ? + (_theResult____h578019[28] ? 6'd28 : - (_theResult____h578015[27] ? + (_theResult____h578019[27] ? 6'd29 : - (_theResult____h578015[26] ? + (_theResult____h578019[26] ? 6'd30 : - (_theResult____h578015[25] ? + (_theResult____h578019[25] ? 6'd31 : - (_theResult____h578015[24] ? + (_theResult____h578019[24] ? 6'd32 : - (_theResult____h578015[23] ? + (_theResult____h578019[23] ? 6'd33 : - (_theResult____h578015[22] ? + (_theResult____h578019[22] ? 6'd34 : - (_theResult____h578015[21] ? + (_theResult____h578019[21] ? 6'd35 : - (_theResult____h578015[20] ? + (_theResult____h578019[20] ? 6'd36 : - (_theResult____h578015[19] ? + (_theResult____h578019[19] ? 6'd37 : - (_theResult____h578015[18] ? + (_theResult____h578019[18] ? 6'd38 : - (_theResult____h578015[17] ? + (_theResult____h578019[17] ? 6'd39 : - (_theResult____h578015[16] ? + (_theResult____h578019[16] ? 6'd40 : - (_theResult____h578015[15] ? + (_theResult____h578019[15] ? 6'd41 : - (_theResult____h578015[14] ? + (_theResult____h578019[14] ? 6'd42 : - (_theResult____h578015[13] ? + (_theResult____h578019[13] ? 6'd43 : - (_theResult____h578015[12] ? + (_theResult____h578019[12] ? 6'd44 : - (_theResult____h578015[11] ? + (_theResult____h578019[11] ? 6'd45 : - (_theResult____h578015[10] ? + (_theResult____h578019[10] ? 6'd46 : - (_theResult____h578015[9] ? + (_theResult____h578019[9] ? 6'd47 : - (_theResult____h578015[8] ? + (_theResult____h578019[8] ? 6'd48 : - (_theResult____h578015[7] ? + (_theResult____h578019[7] ? 6'd49 : - (_theResult____h578015[6] ? + (_theResult____h578019[6] ? 6'd50 : - (_theResult____h578015[5] ? + (_theResult____h578019[5] ? 6'd51 : - (_theResult____h578015[4] ? + (_theResult____h578019[4] ? 6'd52 : - (_theResult____h578015[3] ? + (_theResult____h578019[3] ? 6'd53 : - (_theResult____h578015[2] ? + (_theResult____h578019[2] ? 6'd54 : - (_theResult____h578015[1] ? + (_theResult____h578019[1] ? 6'd55 : - (_theResult____h578015[0] ? + (_theResult____h578019[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 = - (_theResult____h360938[56] ? + (_theResult____h360941[56] ? 6'd0 : - (_theResult____h360938[55] ? + (_theResult____h360941[55] ? 6'd1 : - (_theResult____h360938[54] ? + (_theResult____h360941[54] ? 6'd2 : - (_theResult____h360938[53] ? + (_theResult____h360941[53] ? 6'd3 : - (_theResult____h360938[52] ? + (_theResult____h360941[52] ? 6'd4 : - (_theResult____h360938[51] ? + (_theResult____h360941[51] ? 6'd5 : - (_theResult____h360938[50] ? + (_theResult____h360941[50] ? 6'd6 : - (_theResult____h360938[49] ? + (_theResult____h360941[49] ? 6'd7 : - (_theResult____h360938[48] ? + (_theResult____h360941[48] ? 6'd8 : - (_theResult____h360938[47] ? + (_theResult____h360941[47] ? 6'd9 : - (_theResult____h360938[46] ? + (_theResult____h360941[46] ? 6'd10 : - (_theResult____h360938[45] ? + (_theResult____h360941[45] ? 6'd11 : - (_theResult____h360938[44] ? + (_theResult____h360941[44] ? 6'd12 : - (_theResult____h360938[43] ? + (_theResult____h360941[43] ? 6'd13 : - (_theResult____h360938[42] ? + (_theResult____h360941[42] ? 6'd14 : - (_theResult____h360938[41] ? + (_theResult____h360941[41] ? 6'd15 : - (_theResult____h360938[40] ? + (_theResult____h360941[40] ? 6'd16 : - (_theResult____h360938[39] ? + (_theResult____h360941[39] ? 6'd17 : - (_theResult____h360938[38] ? + (_theResult____h360941[38] ? 6'd18 : - (_theResult____h360938[37] ? + (_theResult____h360941[37] ? 6'd19 : - (_theResult____h360938[36] ? + (_theResult____h360941[36] ? 6'd20 : - (_theResult____h360938[35] ? + (_theResult____h360941[35] ? 6'd21 : - (_theResult____h360938[34] ? + (_theResult____h360941[34] ? 6'd22 : - (_theResult____h360938[33] ? + (_theResult____h360941[33] ? 6'd23 : - (_theResult____h360938[32] ? + (_theResult____h360941[32] ? 6'd24 : - (_theResult____h360938[31] ? + (_theResult____h360941[31] ? 6'd25 : - (_theResult____h360938[30] ? + (_theResult____h360941[30] ? 6'd26 : - (_theResult____h360938[29] ? + (_theResult____h360941[29] ? 6'd27 : - (_theResult____h360938[28] ? + (_theResult____h360941[28] ? 6'd28 : - (_theResult____h360938[27] ? + (_theResult____h360941[27] ? 6'd29 : - (_theResult____h360938[26] ? + (_theResult____h360941[26] ? 6'd30 : - (_theResult____h360938[25] ? + (_theResult____h360941[25] ? 6'd31 : - (_theResult____h360938[24] ? + (_theResult____h360941[24] ? 6'd32 : - (_theResult____h360938[23] ? + (_theResult____h360941[23] ? 6'd33 : - (_theResult____h360938[22] ? + (_theResult____h360941[22] ? 6'd34 : - (_theResult____h360938[21] ? + (_theResult____h360941[21] ? 6'd35 : - (_theResult____h360938[20] ? + (_theResult____h360941[20] ? 6'd36 : - (_theResult____h360938[19] ? + (_theResult____h360941[19] ? 6'd37 : - (_theResult____h360938[18] ? + (_theResult____h360941[18] ? 6'd38 : - (_theResult____h360938[17] ? + (_theResult____h360941[17] ? 6'd39 : - (_theResult____h360938[16] ? + (_theResult____h360941[16] ? 6'd40 : - (_theResult____h360938[15] ? + (_theResult____h360941[15] ? 6'd41 : - (_theResult____h360938[14] ? + (_theResult____h360941[14] ? 6'd42 : - (_theResult____h360938[13] ? + (_theResult____h360941[13] ? 6'd43 : - (_theResult____h360938[12] ? + (_theResult____h360941[12] ? 6'd44 : - (_theResult____h360938[11] ? + (_theResult____h360941[11] ? 6'd45 : - (_theResult____h360938[10] ? + (_theResult____h360941[10] ? 6'd46 : - (_theResult____h360938[9] ? + (_theResult____h360941[9] ? 6'd47 : - (_theResult____h360938[8] ? + (_theResult____h360941[8] ? 6'd48 : - (_theResult____h360938[7] ? + (_theResult____h360941[7] ? 6'd49 : - (_theResult____h360938[6] ? + (_theResult____h360941[6] ? 6'd50 : - (_theResult____h360938[5] ? + (_theResult____h360941[5] ? 6'd51 : - (_theResult____h360938[4] ? + (_theResult____h360941[4] ? 6'd52 : - (_theResult____h360938[3] ? + (_theResult____h360941[3] ? 6'd53 : - (_theResult____h360938[2] ? + (_theResult____h360941[2] ? 6'd54 : - (_theResult____h360938[1] ? + (_theResult____h360941[1] ? 6'd55 : - (_theResult____h360938[0] ? + (_theResult____h360941[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 = - (_theResult____h406628[56] ? + (_theResult____h406631[56] ? 6'd0 : - (_theResult____h406628[55] ? + (_theResult____h406631[55] ? 6'd1 : - (_theResult____h406628[54] ? + (_theResult____h406631[54] ? 6'd2 : - (_theResult____h406628[53] ? + (_theResult____h406631[53] ? 6'd3 : - (_theResult____h406628[52] ? + (_theResult____h406631[52] ? 6'd4 : - (_theResult____h406628[51] ? + (_theResult____h406631[51] ? 6'd5 : - (_theResult____h406628[50] ? + (_theResult____h406631[50] ? 6'd6 : - (_theResult____h406628[49] ? + (_theResult____h406631[49] ? 6'd7 : - (_theResult____h406628[48] ? + (_theResult____h406631[48] ? 6'd8 : - (_theResult____h406628[47] ? + (_theResult____h406631[47] ? 6'd9 : - (_theResult____h406628[46] ? + (_theResult____h406631[46] ? 6'd10 : - (_theResult____h406628[45] ? + (_theResult____h406631[45] ? 6'd11 : - (_theResult____h406628[44] ? + (_theResult____h406631[44] ? 6'd12 : - (_theResult____h406628[43] ? + (_theResult____h406631[43] ? 6'd13 : - (_theResult____h406628[42] ? + (_theResult____h406631[42] ? 6'd14 : - (_theResult____h406628[41] ? + (_theResult____h406631[41] ? 6'd15 : - (_theResult____h406628[40] ? + (_theResult____h406631[40] ? 6'd16 : - (_theResult____h406628[39] ? + (_theResult____h406631[39] ? 6'd17 : - (_theResult____h406628[38] ? + (_theResult____h406631[38] ? 6'd18 : - (_theResult____h406628[37] ? + (_theResult____h406631[37] ? 6'd19 : - (_theResult____h406628[36] ? + (_theResult____h406631[36] ? 6'd20 : - (_theResult____h406628[35] ? + (_theResult____h406631[35] ? 6'd21 : - (_theResult____h406628[34] ? + (_theResult____h406631[34] ? 6'd22 : - (_theResult____h406628[33] ? + (_theResult____h406631[33] ? 6'd23 : - (_theResult____h406628[32] ? + (_theResult____h406631[32] ? 6'd24 : - (_theResult____h406628[31] ? + (_theResult____h406631[31] ? 6'd25 : - (_theResult____h406628[30] ? + (_theResult____h406631[30] ? 6'd26 : - (_theResult____h406628[29] ? + (_theResult____h406631[29] ? 6'd27 : - (_theResult____h406628[28] ? + (_theResult____h406631[28] ? 6'd28 : - (_theResult____h406628[27] ? + (_theResult____h406631[27] ? 6'd29 : - (_theResult____h406628[26] ? + (_theResult____h406631[26] ? 6'd30 : - (_theResult____h406628[25] ? + (_theResult____h406631[25] ? 6'd31 : - (_theResult____h406628[24] ? + (_theResult____h406631[24] ? 6'd32 : - (_theResult____h406628[23] ? + (_theResult____h406631[23] ? 6'd33 : - (_theResult____h406628[22] ? + (_theResult____h406631[22] ? 6'd34 : - (_theResult____h406628[21] ? + (_theResult____h406631[21] ? 6'd35 : - (_theResult____h406628[20] ? + (_theResult____h406631[20] ? 6'd36 : - (_theResult____h406628[19] ? + (_theResult____h406631[19] ? 6'd37 : - (_theResult____h406628[18] ? + (_theResult____h406631[18] ? 6'd38 : - (_theResult____h406628[17] ? + (_theResult____h406631[17] ? 6'd39 : - (_theResult____h406628[16] ? + (_theResult____h406631[16] ? 6'd40 : - (_theResult____h406628[15] ? + (_theResult____h406631[15] ? 6'd41 : - (_theResult____h406628[14] ? + (_theResult____h406631[14] ? 6'd42 : - (_theResult____h406628[13] ? + (_theResult____h406631[13] ? 6'd43 : - (_theResult____h406628[12] ? + (_theResult____h406631[12] ? 6'd44 : - (_theResult____h406628[11] ? + (_theResult____h406631[11] ? 6'd45 : - (_theResult____h406628[10] ? + (_theResult____h406631[10] ? 6'd46 : - (_theResult____h406628[9] ? + (_theResult____h406631[9] ? 6'd47 : - (_theResult____h406628[8] ? + (_theResult____h406631[8] ? 6'd48 : - (_theResult____h406628[7] ? + (_theResult____h406631[7] ? 6'd49 : - (_theResult____h406628[6] ? + (_theResult____h406631[6] ? 6'd50 : - (_theResult____h406628[5] ? + (_theResult____h406631[5] ? 6'd51 : - (_theResult____h406628[4] ? + (_theResult____h406631[4] ? 6'd52 : - (_theResult____h406628[3] ? + (_theResult____h406631[3] ? 6'd53 : - (_theResult____h406628[2] ? + (_theResult____h406631[2] ? 6'd54 : - (_theResult____h406628[1] ? + (_theResult____h406631[1] ? 6'd55 : - (_theResult____h406628[0] ? + (_theResult____h406631[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 = - (_theResult____h452316[56] ? + (_theResult____h452319[56] ? 6'd0 : - (_theResult____h452316[55] ? + (_theResult____h452319[55] ? 6'd1 : - (_theResult____h452316[54] ? + (_theResult____h452319[54] ? 6'd2 : - (_theResult____h452316[53] ? + (_theResult____h452319[53] ? 6'd3 : - (_theResult____h452316[52] ? + (_theResult____h452319[52] ? 6'd4 : - (_theResult____h452316[51] ? + (_theResult____h452319[51] ? 6'd5 : - (_theResult____h452316[50] ? + (_theResult____h452319[50] ? 6'd6 : - (_theResult____h452316[49] ? + (_theResult____h452319[49] ? 6'd7 : - (_theResult____h452316[48] ? + (_theResult____h452319[48] ? 6'd8 : - (_theResult____h452316[47] ? + (_theResult____h452319[47] ? 6'd9 : - (_theResult____h452316[46] ? + (_theResult____h452319[46] ? 6'd10 : - (_theResult____h452316[45] ? + (_theResult____h452319[45] ? 6'd11 : - (_theResult____h452316[44] ? + (_theResult____h452319[44] ? 6'd12 : - (_theResult____h452316[43] ? + (_theResult____h452319[43] ? 6'd13 : - (_theResult____h452316[42] ? + (_theResult____h452319[42] ? 6'd14 : - (_theResult____h452316[41] ? + (_theResult____h452319[41] ? 6'd15 : - (_theResult____h452316[40] ? + (_theResult____h452319[40] ? 6'd16 : - (_theResult____h452316[39] ? + (_theResult____h452319[39] ? 6'd17 : - (_theResult____h452316[38] ? + (_theResult____h452319[38] ? 6'd18 : - (_theResult____h452316[37] ? + (_theResult____h452319[37] ? 6'd19 : - (_theResult____h452316[36] ? + (_theResult____h452319[36] ? 6'd20 : - (_theResult____h452316[35] ? + (_theResult____h452319[35] ? 6'd21 : - (_theResult____h452316[34] ? + (_theResult____h452319[34] ? 6'd22 : - (_theResult____h452316[33] ? + (_theResult____h452319[33] ? 6'd23 : - (_theResult____h452316[32] ? + (_theResult____h452319[32] ? 6'd24 : - (_theResult____h452316[31] ? + (_theResult____h452319[31] ? 6'd25 : - (_theResult____h452316[30] ? + (_theResult____h452319[30] ? 6'd26 : - (_theResult____h452316[29] ? + (_theResult____h452319[29] ? 6'd27 : - (_theResult____h452316[28] ? + (_theResult____h452319[28] ? 6'd28 : - (_theResult____h452316[27] ? + (_theResult____h452319[27] ? 6'd29 : - (_theResult____h452316[26] ? + (_theResult____h452319[26] ? 6'd30 : - (_theResult____h452316[25] ? + (_theResult____h452319[25] ? 6'd31 : - (_theResult____h452316[24] ? + (_theResult____h452319[24] ? 6'd32 : - (_theResult____h452316[23] ? + (_theResult____h452319[23] ? 6'd33 : - (_theResult____h452316[22] ? + (_theResult____h452319[22] ? 6'd34 : - (_theResult____h452316[21] ? + (_theResult____h452319[21] ? 6'd35 : - (_theResult____h452316[20] ? + (_theResult____h452319[20] ? 6'd36 : - (_theResult____h452316[19] ? + (_theResult____h452319[19] ? 6'd37 : - (_theResult____h452316[18] ? + (_theResult____h452319[18] ? 6'd38 : - (_theResult____h452316[17] ? + (_theResult____h452319[17] ? 6'd39 : - (_theResult____h452316[16] ? + (_theResult____h452319[16] ? 6'd40 : - (_theResult____h452316[15] ? + (_theResult____h452319[15] ? 6'd41 : - (_theResult____h452316[14] ? + (_theResult____h452319[14] ? 6'd42 : - (_theResult____h452316[13] ? + (_theResult____h452319[13] ? 6'd43 : - (_theResult____h452316[12] ? + (_theResult____h452319[12] ? 6'd44 : - (_theResult____h452316[11] ? + (_theResult____h452319[11] ? 6'd45 : - (_theResult____h452316[10] ? + (_theResult____h452319[10] ? 6'd46 : - (_theResult____h452316[9] ? + (_theResult____h452319[9] ? 6'd47 : - (_theResult____h452316[8] ? + (_theResult____h452319[8] ? 6'd48 : - (_theResult____h452316[7] ? + (_theResult____h452319[7] ? 6'd49 : - (_theResult____h452316[6] ? + (_theResult____h452319[6] ? 6'd50 : - (_theResult____h452316[5] ? + (_theResult____h452319[5] ? 6'd51 : - (_theResult____h452316[4] ? + (_theResult____h452319[4] ? 6'd52 : - (_theResult____h452316[3] ? + (_theResult____h452319[3] ? 6'd53 : - (_theResult____h452316[2] ? + (_theResult____h452319[2] ? 6'd54 : - (_theResult____h452316[1] ? + (_theResult____h452319[1] ? 6'd55 : - (_theResult____h452316[0] ? + (_theResult____h452319[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10404 = - (_theResult___fst_exp__h547050 == 11'd2047) ? + (_theResult___fst_exp__h547054 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10669 = - (_theResult___fst_exp__h547050 == 11'd2047) ? + (_theResult___fst_exp__h547054 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8931 = - (_theResult___fst_exp__h508249 == 11'd2047) ? + (_theResult___fst_exp__h508253 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9641 = - (_theResult___fst_exp__h586251 == 11'd2047) ? + (_theResult___fst_exp__h586255 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9907 = - (_theResult___fst_exp__h586251 == 11'd2047) ? + (_theResult___fst_exp__h586255 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 = - (guard__h343309 == 2'b0 || + (guard__h343312 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h351410 : - _theResult___exp__h351926 ; + _theResult___fst_exp__h351413 : + _theResult___exp__h351929 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 = - (guard__h343309 == 2'b0) ? - _theResult___fst_exp__h351410 : + (guard__h343312 == 2'b0) ? + _theResult___fst_exp__h351413 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h351926 : - _theResult___fst_exp__h351410) ; + _theResult___exp__h351929 : + _theResult___fst_exp__h351413) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 = - (guard__h343309 == 2'b0 || + (guard__h343312 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h351404[56:34] : - _theResult___sfd__h351927 ; + sfdin__h351407[56:34] : + _theResult___sfd__h351930 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 = - (guard__h343309 == 2'b0) ? - sfdin__h351404[56:34] : + (guard__h343312 == 2'b0) ? + sfdin__h351407[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h351927 : - sfdin__h351404[56:34]) ; + _theResult___sfd__h351930 : + sfdin__h351407[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 = - (guard__h389001 == 2'b0 || + (guard__h389004 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h397100 : - _theResult___exp__h397616 ; + _theResult___fst_exp__h397103 : + _theResult___exp__h397619 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 = - (guard__h389001 == 2'b0) ? - _theResult___fst_exp__h397100 : + (guard__h389004 == 2'b0) ? + _theResult___fst_exp__h397103 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h397616 : - _theResult___fst_exp__h397100) ; + _theResult___exp__h397619 : + _theResult___fst_exp__h397103) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 = - (guard__h389001 == 2'b0 || + (guard__h389004 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h397094[56:34] : - _theResult___sfd__h397617 ; + sfdin__h397097[56:34] : + _theResult___sfd__h397620 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 = - (guard__h389001 == 2'b0) ? - sfdin__h397094[56:34] : + (guard__h389004 == 2'b0) ? + sfdin__h397097[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h397617 : - sfdin__h397094[56:34]) ; + _theResult___sfd__h397620 : + sfdin__h397097[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 = - (guard__h434689 == 2'b0 || + (guard__h434692 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h442788 : - _theResult___exp__h443304 ; + _theResult___fst_exp__h442791 : + _theResult___exp__h443307 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 = - (guard__h434689 == 2'b0) ? - _theResult___fst_exp__h442788 : + (guard__h434692 == 2'b0) ? + _theResult___fst_exp__h442791 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h443304 : - _theResult___fst_exp__h442788) ; + _theResult___exp__h443307 : + _theResult___fst_exp__h442791) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 = - (guard__h434689 == 2'b0 || + (guard__h434692 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h442782[56:34] : - _theResult___sfd__h443305 ; + sfdin__h442785[56:34] : + _theResult___sfd__h443308 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 = - (guard__h434689 == 2'b0) ? - sfdin__h442782[56:34] : + (guard__h434692 == 2'b0) ? + sfdin__h442785[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h443305 : - sfdin__h442782[56:34]) ; + _theResult___sfd__h443308 : + sfdin__h442785[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 = - (guard__h538824 == 2'b0 || + (guard__h538828 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h547050 : - _theResult___exp__h547779 ; + _theResult___fst_exp__h547054 : + _theResult___exp__h547783 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 = - (guard__h538824 == 2'b0) ? - _theResult___fst_exp__h547050 : + (guard__h538828 == 2'b0) ? + _theResult___fst_exp__h547054 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h547779 : - _theResult___fst_exp__h547050) ; + _theResult___exp__h547783 : + _theResult___fst_exp__h547054) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 = - (guard__h538824 == 2'b0 || + (guard__h538828 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h547044[56:5] : - _theResult___sfd__h547780 ; + sfdin__h547048[56:5] : + _theResult___sfd__h547784 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 = - (guard__h538824 == 2'b0) ? - sfdin__h547044[56:5] : + (guard__h538828 == 2'b0) ? + sfdin__h547048[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h547780 : - sfdin__h547044[56:5]) ; + _theResult___sfd__h547784 : + sfdin__h547048[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 = - (guard__h500023 == 2'b0 || + (guard__h500027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h508249 : - _theResult___exp__h508978 ; + _theResult___fst_exp__h508253 : + _theResult___exp__h508982 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 = - (guard__h500023 == 2'b0) ? - _theResult___fst_exp__h508249 : + (guard__h500027 == 2'b0) ? + _theResult___fst_exp__h508253 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h508978 : - _theResult___fst_exp__h508249) ; + _theResult___exp__h508982 : + _theResult___fst_exp__h508253) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 = - (guard__h500023 == 2'b0 || + (guard__h500027 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h508243[56:5] : - _theResult___sfd__h508979 ; + sfdin__h508247[56:5] : + _theResult___sfd__h508983 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 = - (guard__h500023 == 2'b0) ? - sfdin__h508243[56:5] : + (guard__h500027 == 2'b0) ? + sfdin__h508247[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h508979 : - sfdin__h508243[56:5]) ; + _theResult___sfd__h508983 : + sfdin__h508247[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 = - (guard__h578025 == 2'b0 || + (guard__h578029 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h586251 : - _theResult___exp__h586980 ; + _theResult___fst_exp__h586255 : + _theResult___exp__h586984 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 = - (guard__h578025 == 2'b0) ? - _theResult___fst_exp__h586251 : + (guard__h578029 == 2'b0) ? + _theResult___fst_exp__h586255 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h586980 : - _theResult___fst_exp__h586251) ; + _theResult___exp__h586984 : + _theResult___fst_exp__h586255) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 = - (guard__h578025 == 2'b0 || + (guard__h578029 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h586245[56:5] : - _theResult___sfd__h586981 ; + sfdin__h586249[56:5] : + _theResult___sfd__h586985 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 = - (guard__h578025 == 2'b0) ? - sfdin__h586245[56:5] : + (guard__h578029 == 2'b0) ? + sfdin__h586249[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h586981 : - sfdin__h586245[56:5]) ; + _theResult___sfd__h586985 : + sfdin__h586249[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 = - (guard__h360948 == 2'b0 || + (guard__h360951 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h369176 : - _theResult___exp__h369692 ; + _theResult___fst_exp__h369179 : + _theResult___exp__h369695 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 = - (guard__h360948 == 2'b0) ? - _theResult___fst_exp__h369176 : + (guard__h360951 == 2'b0) ? + _theResult___fst_exp__h369179 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h369692 : - _theResult___fst_exp__h369176) ; + _theResult___exp__h369695 : + _theResult___fst_exp__h369179) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 = - (guard__h360948 == 2'b0 || + (guard__h360951 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h369170[56:34] : - _theResult___sfd__h369693 ; + sfdin__h369173[56:34] : + _theResult___sfd__h369696 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 = - (guard__h360948 == 2'b0) ? - sfdin__h369170[56:34] : + (guard__h360951 == 2'b0) ? + sfdin__h369173[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h369693 : - sfdin__h369170[56:34]) ; + _theResult___sfd__h369696 : + sfdin__h369173[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 = - (guard__h406638 == 2'b0 || + (guard__h406641 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h414866 : - _theResult___exp__h415382 ; + _theResult___fst_exp__h414869 : + _theResult___exp__h415385 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 = - (guard__h406638 == 2'b0) ? - _theResult___fst_exp__h414866 : + (guard__h406641 == 2'b0) ? + _theResult___fst_exp__h414869 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h415382 : - _theResult___fst_exp__h414866) ; + _theResult___exp__h415385 : + _theResult___fst_exp__h414869) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 = - (guard__h406638 == 2'b0 || + (guard__h406641 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h414860[56:34] : - _theResult___sfd__h415383 ; + sfdin__h414863[56:34] : + _theResult___sfd__h415386 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 = - (guard__h406638 == 2'b0) ? - sfdin__h414860[56:34] : + (guard__h406641 == 2'b0) ? + sfdin__h414863[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h415383 : - sfdin__h414860[56:34]) ; + _theResult___sfd__h415386 : + sfdin__h414863[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 = - (guard__h452326 == 2'b0 || + (guard__h452329 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h460554 : - _theResult___exp__h461070 ; + _theResult___fst_exp__h460557 : + _theResult___exp__h461073 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 = - (guard__h452326 == 2'b0) ? - _theResult___fst_exp__h460554 : + (guard__h452329 == 2'b0) ? + _theResult___fst_exp__h460557 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h461070 : - _theResult___fst_exp__h460554) ; + _theResult___exp__h461073 : + _theResult___fst_exp__h460557) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 = - (guard__h452326 == 2'b0 || + (guard__h452329 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h460548[56:34] : - _theResult___sfd__h461071 ; + sfdin__h460551[56:34] : + _theResult___sfd__h461074 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 = - (guard__h452326 == 2'b0) ? - sfdin__h460548[56:34] : + (guard__h452329 == 2'b0) ? + sfdin__h460551[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h461071 : - sfdin__h460548[56:34]) ; + _theResult___sfd__h461074 : + sfdin__h460551[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 = - (guard__h352018 == 2'b0 || + (guard__h352021 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h360066 : - _theResult___exp__h360508 ; + _theResult___fst_exp__h360069 : + _theResult___exp__h360511 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 = - (guard__h352018 == 2'b0) ? - _theResult___fst_exp__h360066 : + (guard__h352021 == 2'b0) ? + _theResult___fst_exp__h360069 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h360508 : - _theResult___fst_exp__h360066) ; + _theResult___exp__h360511 : + _theResult___fst_exp__h360069) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 = - (guard__h369784 == 2'b0 || + (guard__h369787 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h377861 : - _theResult___exp__h378328 ; + _theResult___fst_exp__h377864 : + _theResult___exp__h378331 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 = - (guard__h369784 == 2'b0) ? - _theResult___fst_exp__h377861 : + (guard__h369787 == 2'b0) ? + _theResult___fst_exp__h377864 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h378328 : - _theResult___fst_exp__h377861) ; + _theResult___exp__h378331 : + _theResult___fst_exp__h377864) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 = - (guard__h352018 == 2'b0 || + (guard__h352021 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h360017[56:34] : - _theResult___sfd__h360509 ; + _theResult___snd__h360020[56:34] : + _theResult___sfd__h360512 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 = - (guard__h352018 == 2'b0) ? - _theResult___snd__h360017[56:34] : + (guard__h352021 == 2'b0) ? + _theResult___snd__h360020[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h360509 : - _theResult___snd__h360017[56:34]) ; + _theResult___sfd__h360512 : + _theResult___snd__h360020[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 = - (guard__h369784 == 2'b0 || + (guard__h369787 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h377807[56:34] : - _theResult___sfd__h378329 ; + _theResult___snd__h377810[56:34] : + _theResult___sfd__h378332 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 = - (guard__h369784 == 2'b0) ? - _theResult___snd__h377807[56:34] : + (guard__h369787 == 2'b0) ? + _theResult___snd__h377810[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h378329 : - _theResult___snd__h377807[56:34]) ; + _theResult___sfd__h378332 : + _theResult___snd__h377810[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 = - (guard__h397708 == 2'b0 || + (guard__h397711 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h405756 : - _theResult___exp__h406198 ; + _theResult___fst_exp__h405759 : + _theResult___exp__h406201 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 = - (guard__h397708 == 2'b0) ? - _theResult___fst_exp__h405756 : + (guard__h397711 == 2'b0) ? + _theResult___fst_exp__h405759 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h406198 : - _theResult___fst_exp__h405756) ; + _theResult___exp__h406201 : + _theResult___fst_exp__h405759) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 = - (guard__h415474 == 2'b0 || + (guard__h415477 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h423551 : - _theResult___exp__h424018 ; + _theResult___fst_exp__h423554 : + _theResult___exp__h424021 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 = - (guard__h415474 == 2'b0) ? - _theResult___fst_exp__h423551 : + (guard__h415477 == 2'b0) ? + _theResult___fst_exp__h423554 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h424018 : - _theResult___fst_exp__h423551) ; + _theResult___exp__h424021 : + _theResult___fst_exp__h423554) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 = - (guard__h397708 == 2'b0 || + (guard__h397711 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h405707[56:34] : - _theResult___sfd__h406199 ; + _theResult___snd__h405710[56:34] : + _theResult___sfd__h406202 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 = - (guard__h397708 == 2'b0) ? - _theResult___snd__h405707[56:34] : + (guard__h397711 == 2'b0) ? + _theResult___snd__h405710[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h406199 : - _theResult___snd__h405707[56:34]) ; + _theResult___sfd__h406202 : + _theResult___snd__h405710[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 = - (guard__h415474 == 2'b0 || + (guard__h415477 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h423497[56:34] : - _theResult___sfd__h424019 ; + _theResult___snd__h423500[56:34] : + _theResult___sfd__h424022 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 = - (guard__h415474 == 2'b0) ? - _theResult___snd__h423497[56:34] : + (guard__h415477 == 2'b0) ? + _theResult___snd__h423500[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h424019 : - _theResult___snd__h423497[56:34]) ; + _theResult___sfd__h424022 : + _theResult___snd__h423500[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 = - (guard__h443396 == 2'b0 || + (guard__h443399 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h451444 : - _theResult___exp__h451886 ; + _theResult___fst_exp__h451447 : + _theResult___exp__h451889 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 = - (guard__h443396 == 2'b0) ? - _theResult___fst_exp__h451444 : + (guard__h443399 == 2'b0) ? + _theResult___fst_exp__h451447 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h451886 : - _theResult___fst_exp__h451444) ; + _theResult___exp__h451889 : + _theResult___fst_exp__h451447) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 = - (guard__h461162 == 2'b0 || + (guard__h461165 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h469239 : - _theResult___exp__h469706 ; + _theResult___fst_exp__h469242 : + _theResult___exp__h469709 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 = - (guard__h461162 == 2'b0) ? - _theResult___fst_exp__h469239 : + (guard__h461165 == 2'b0) ? + _theResult___fst_exp__h469242 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h469706 : - _theResult___fst_exp__h469239) ; + _theResult___exp__h469709 : + _theResult___fst_exp__h469242) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 = - (guard__h443396 == 2'b0 || + (guard__h443399 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h451395[56:34] : - _theResult___sfd__h451887 ; + _theResult___snd__h451398[56:34] : + _theResult___sfd__h451890 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 = - (guard__h443396 == 2'b0) ? - _theResult___snd__h451395[56:34] : + (guard__h443399 == 2'b0) ? + _theResult___snd__h451398[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h451887 : - _theResult___snd__h451395[56:34]) ; + _theResult___sfd__h451890 : + _theResult___snd__h451398[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 = - (guard__h461162 == 2'b0 || + (guard__h461165 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h469185[56:34] : - _theResult___sfd__h469707 ; + _theResult___snd__h469188[56:34] : + _theResult___sfd__h469710 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 = - (guard__h461162 == 2'b0) ? - _theResult___snd__h469185[56:34] : + (guard__h461165 == 2'b0) ? + _theResult___snd__h469188[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h469707 : - _theResult___snd__h469185[56:34]) ; + _theResult___sfd__h469710 : + _theResult___snd__h469188[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 = - (guard__h529512 == 2'b0 || + (guard__h529516 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h537473 : - _theResult___exp__h538128 ; + _theResult___fst_exp__h537477 : + _theResult___exp__h538132 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 = - (guard__h529512 == 2'b0) ? - _theResult___fst_exp__h537473 : + (guard__h529516 == 2'b0) ? + _theResult___fst_exp__h537477 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h538128 : - _theResult___fst_exp__h537473) ; + _theResult___exp__h538132 : + _theResult___fst_exp__h537477) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 = - (guard__h547893 == 2'b0 || + (guard__h547897 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555883 : - _theResult___exp__h556563 ; + _theResult___fst_exp__h555887 : + _theResult___exp__h556567 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 = - (guard__h547893 == 2'b0) ? - _theResult___fst_exp__h555883 : + (guard__h547897 == 2'b0) ? + _theResult___fst_exp__h555887 : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___exp__h556563 : - _theResult___fst_exp__h555883) ; + _theResult___exp__h556567 : + _theResult___fst_exp__h555887) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 = - (guard__h529512 == 2'b0 || + (guard__h529516 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h537424[56:5] : - _theResult___sfd__h538129 ; + _theResult___snd__h537428[56:5] : + _theResult___sfd__h538133 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 = - (guard__h529512 == 2'b0) ? - _theResult___snd__h537424[56:5] : + (guard__h529516 == 2'b0) ? + _theResult___snd__h537428[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h538129 : - _theResult___snd__h537424[56:5]) ; + _theResult___sfd__h538133 : + _theResult___snd__h537428[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 = - (guard__h547893 == 2'b0 || + (guard__h547897 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h555829[56:5] : - _theResult___sfd__h556564 ; + _theResult___snd__h555833[56:5] : + _theResult___sfd__h556568 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 = - (guard__h547893 == 2'b0) ? - _theResult___snd__h555829[56:5] : + (guard__h547897 == 2'b0) ? + _theResult___snd__h555833[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[107] ? - _theResult___sfd__h556564 : - _theResult___snd__h555829[56:5]) ; + _theResult___sfd__h556568 : + _theResult___snd__h555833[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 = - (guard__h490711 == 2'b0 || + (guard__h490715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h498672 : - _theResult___exp__h499327 ; + _theResult___fst_exp__h498676 : + _theResult___exp__h499331 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 = - (guard__h490711 == 2'b0) ? - _theResult___fst_exp__h498672 : + (guard__h490715 == 2'b0) ? + _theResult___fst_exp__h498676 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h499327 : - _theResult___fst_exp__h498672) ; + _theResult___exp__h499331 : + _theResult___fst_exp__h498676) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 = - (guard__h509092 == 2'b0 || + (guard__h509096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h517082 : - _theResult___exp__h517762 ; + _theResult___fst_exp__h517086 : + _theResult___exp__h517766 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 = - (guard__h509092 == 2'b0) ? - _theResult___fst_exp__h517082 : + (guard__h509096 == 2'b0) ? + _theResult___fst_exp__h517086 : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___exp__h517762 : - _theResult___fst_exp__h517082) ; + _theResult___exp__h517766 : + _theResult___fst_exp__h517086) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 = - (guard__h490711 == 2'b0 || + (guard__h490715 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h498623[56:5] : - _theResult___sfd__h499328 ; + _theResult___snd__h498627[56:5] : + _theResult___sfd__h499332 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 = - (guard__h490711 == 2'b0) ? - _theResult___snd__h498623[56:5] : + (guard__h490715 == 2'b0) ? + _theResult___snd__h498627[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h499328 : - _theResult___snd__h498623[56:5]) ; + _theResult___sfd__h499332 : + _theResult___snd__h498627[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 = - (guard__h509092 == 2'b0 || + (guard__h509096 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h517028[56:5] : - _theResult___sfd__h517763 ; + _theResult___snd__h517032[56:5] : + _theResult___sfd__h517767 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 = - (guard__h509092 == 2'b0) ? - _theResult___snd__h517028[56:5] : + (guard__h509096 == 2'b0) ? + _theResult___snd__h517032[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[171] ? - _theResult___sfd__h517763 : - _theResult___snd__h517028[56:5]) ; + _theResult___sfd__h517767 : + _theResult___snd__h517032[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 = - (guard__h568713 == 2'b0 || + (guard__h568717 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h576674 : - _theResult___exp__h577329 ; + _theResult___fst_exp__h576678 : + _theResult___exp__h577333 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 = - (guard__h568713 == 2'b0) ? - _theResult___fst_exp__h576674 : + (guard__h568717 == 2'b0) ? + _theResult___fst_exp__h576678 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h577329 : - _theResult___fst_exp__h576674) ; + _theResult___exp__h577333 : + _theResult___fst_exp__h576678) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 = - (guard__h587094 == 2'b0 || + (guard__h587098 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h595084 : - _theResult___exp__h595764 ; + _theResult___fst_exp__h595088 : + _theResult___exp__h595768 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 = - (guard__h587094 == 2'b0) ? - _theResult___fst_exp__h595084 : + (guard__h587098 == 2'b0) ? + _theResult___fst_exp__h595088 : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___exp__h595764 : - _theResult___fst_exp__h595084) ; + _theResult___exp__h595768 : + _theResult___fst_exp__h595088) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 = - (guard__h568713 == 2'b0 || + (guard__h568717 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h576625[56:5] : - _theResult___sfd__h577330 ; + _theResult___snd__h576629[56:5] : + _theResult___sfd__h577334 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 = - (guard__h568713 == 2'b0) ? - _theResult___snd__h576625[56:5] : + (guard__h568717 == 2'b0) ? + _theResult___snd__h576629[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h577330 : - _theResult___snd__h576625[56:5]) ; + _theResult___sfd__h577334 : + _theResult___snd__h576629[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 = - (guard__h587094 == 2'b0 || + (guard__h587098 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h595030[56:5] : - _theResult___sfd__h595765 ; + _theResult___snd__h595034[56:5] : + _theResult___sfd__h595769 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 = - (guard__h587094 == 2'b0) ? - _theResult___snd__h595030[56:5] : + (guard__h587098 == 2'b0) ? + _theResult___snd__h595034[56:5] : (coreFix_fpuMulDivExe_0_regToExeQ$first[43] ? - _theResult___sfd__h595765 : - _theResult___snd__h595030[56:5]) ; + _theResult___sfd__h595769 : + _theResult___snd__h595034[56:5]) ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674 = - (_theResult____h645389 == 15'd0 && + (_theResult____h645398 == 15'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h645933 : - _theResult____h645389 ; + enabled_ints__h645942 : + _theResult____h645398 ; assign IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12881 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] || IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[1] || @@ -19255,67 +19255,67 @@ module mkCore(CLK, checkForException___d13458[4] || csrf_fs_reg_read__1491_EQ_0_2828_AND_fetchStag_ETC___d13547 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10450 = - (_theResult___fst_exp__h555883 == 11'd2047) ? + (_theResult___fst_exp__h555887 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10654 = - (_theResult___fst_exp__h537473 == 11'd2047) ? + (_theResult___fst_exp__h537477 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10681 = - (_theResult___fst_exp__h555883 == 11'd2047) ? + (_theResult___fst_exp__h555887 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8977 = - (_theResult___fst_exp__h517082 == 11'd2047) ? + (_theResult___fst_exp__h517086 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9687 = - (_theResult___fst_exp__h595084 == 11'd2047) ? + (_theResult___fst_exp__h595088 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9892 = - (_theResult___fst_exp__h576674 == 11'd2047) ? + (_theResult___fst_exp__h576678 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9919 = - (_theResult___fst_exp__h595084 == 11'd2047) ? + (_theResult___fst_exp__h595088 == 11'd2047) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 = IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ? @@ -19521,35 +19521,35 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10109 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 || - _theResult___fst_exp__h537473 == 11'd2047) ? + _theResult___fst_exp__h537477 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8636 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 || - _theResult___fst_exp__h498672 == 11'd2047) ? + _theResult___fst_exp__h498676 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9346 = (!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 || _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 || - _theResult___fst_exp__h576674 == 11'd2047) ? + _theResult___fst_exp__h576678 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3__ETC___d13055 = IF_IF_NOT_csrf_prv_reg_read__2633_EQ_3_2634_26_ETC___d12674[0] ? @@ -19987,35 +19987,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369176 == 8'd255) ? + ((_theResult___fst_exp__h369179 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) : - ((_theResult___fst_exp__h377861 == 8'd255) ? + ((_theResult___fst_exp__h377864 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - ((_theResult___fst_exp__h369176 == 8'd255) ? + ((_theResult___fst_exp__h369179 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) : - ((_theResult___fst_exp__h377861 == 8'd255) ? + ((_theResult___fst_exp__h377864 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] : - _theResult___fst_exp__h378409 == 8'd255 && - _theResult___fst_sfd__h378410 == 23'd0 ; + _theResult___fst_exp__h378412 == 8'd255 && + _theResult___fst_sfd__h378413 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] : - _theResult___fst_exp__h377861 == 8'd0 && - guard__h369784 != 2'b0 ; + _theResult___fst_exp__h377864 == 8'd0 && + guard__h369787 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] : - _theResult___fst_exp__h377861 != 8'd255 && - guard__h369784 != 2'b0 ; + _theResult___fst_exp__h377864 != 8'd255 && + guard__h369787 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? @@ -20025,35 +20025,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414866 == 8'd255) ? + ((_theResult___fst_exp__h414869 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) : - ((_theResult___fst_exp__h423551 == 8'd255) ? + ((_theResult___fst_exp__h423554 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - ((_theResult___fst_exp__h414866 == 8'd255) ? + ((_theResult___fst_exp__h414869 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) : - ((_theResult___fst_exp__h423551 == 8'd255) ? + ((_theResult___fst_exp__h423554 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] : - _theResult___fst_exp__h424099 == 8'd255 && - _theResult___fst_sfd__h424100 == 23'd0 ; + _theResult___fst_exp__h424102 == 8'd255 && + _theResult___fst_sfd__h424103 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] : - _theResult___fst_exp__h423551 == 8'd0 && - guard__h415474 != 2'b0 ; + _theResult___fst_exp__h423554 == 8'd0 && + guard__h415477 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] : - _theResult___fst_exp__h423551 != 8'd255 && - guard__h415474 != 2'b0 ; + _theResult___fst_exp__h423554 != 8'd255 && + guard__h415477 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? @@ -20063,35 +20063,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460554 == 8'd255) ? + ((_theResult___fst_exp__h460557 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) : - ((_theResult___fst_exp__h469239 == 8'd255) ? + ((_theResult___fst_exp__h469242 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - ((_theResult___fst_exp__h460554 == 8'd255) ? + ((_theResult___fst_exp__h460557 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) : - ((_theResult___fst_exp__h469239 == 8'd255) ? + ((_theResult___fst_exp__h469242 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] : - _theResult___fst_exp__h469787 == 8'd255 && - _theResult___fst_sfd__h469788 == 23'd0 ; + _theResult___fst_exp__h469790 == 8'd255 && + _theResult___fst_sfd__h469791 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] : - _theResult___fst_exp__h469239 == 8'd0 && - guard__h461162 != 2'b0 ; + _theResult___fst_exp__h469242 == 8'd0 && + guard__h461165 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] : - _theResult___fst_exp__h469239 != 8'd255 && - guard__h461162 != 2'b0 ; + _theResult___fst_exp__h469242 != 8'd255 && + guard__h461165 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? @@ -20114,48 +20114,48 @@ module mkCore(CLK, assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10878 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[2] : - _theResult___fst_exp__h517865 == 11'd2047 && - _theResult___fst_sfd__h517866 == 52'd0 ; + _theResult___fst_exp__h517869 == 11'd2047 && + _theResult___fst_sfd__h517870 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10892 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[2] : - _theResult___fst_exp__h556666 == 11'd2047 && - _theResult___fst_sfd__h556667 == 52'd0 ; + _theResult___fst_exp__h556670 == 11'd2047 && + _theResult___fst_sfd__h556671 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10907 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[2] : - _theResult___fst_exp__h595867 == 11'd2047 && - _theResult___fst_sfd__h595868 == 52'd0 ; + _theResult___fst_exp__h595871 == 11'd2047 && + _theResult___fst_sfd__h595872 == 52'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10924 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[1] : - _theResult___fst_exp__h517082 == 11'd0 && - guard__h509092 != 2'b0 ; + _theResult___fst_exp__h517086 == 11'd0 && + guard__h509096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10936 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[1] : - _theResult___fst_exp__h555883 == 11'd0 && - guard__h547893 != 2'b0 ; + _theResult___fst_exp__h555887 == 11'd0 && + guard__h547897 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10949 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[1] : - _theResult___fst_exp__h595084 == 11'd0 && - guard__h587094 != 2'b0 ; + _theResult___fst_exp__h595088 == 11'd0 && + guard__h587098 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10966 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736[0] : - _theResult___fst_exp__h517082 != 11'd2047 && - guard__h509092 != 2'b0 ; + _theResult___fst_exp__h517086 != 11'd2047 && + guard__h509096 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10978 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777[0] : - _theResult___fst_exp__h555883 != 11'd2047 && - guard__h547893 != 2'b0 ; + _theResult___fst_exp__h555887 != 11'd2047 && + guard__h547897 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10991 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821[0] : - _theResult___fst_exp__h595084 != 11'd2047 && - guard__h587094 != 2'b0 ; + _theResult___fst_exp__h595088 != 11'd2047 && + guard__h587098 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 = ((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? @@ -20877,11 +20877,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10632 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h556678, + _theResult___fst_exp__h556682, (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ? - _theResult___snd_fst_sfd__h518567 : - _theResult___fst_sfd__h556682 } ; + _theResult___snd_fst_sfd__h518571 : + _theResult___fst_sfd__h556686 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10634 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] : @@ -21079,11 +21079,11 @@ module mkCore(CLK, { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8981, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h517877, + _theResult___fst_exp__h517881, (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ? - _theResult___snd_fst_sfd__h479625 : - _theResult___fst_sfd__h517881 } ; + _theResult___snd_fst_sfd__h479629 : + _theResult___fst_sfd__h517885 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9166 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] : @@ -21152,11 +21152,11 @@ module mkCore(CLK, assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 = { (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h595879, + _theResult___fst_exp__h595883, (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ? - _theResult___snd_fst_sfd__h557768 : - _theResult___fst_sfd__h595883 } ; + _theResult___snd_fst_sfd__h557772 : + _theResult___fst_sfd__h595887 } ; assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 = coreFix_fpuMulDivExe_0_regToExeQ$first[225] ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] : @@ -21180,8 +21180,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9869 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12546 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h641096 : - w__h641091 ; + result__h641105 : + w__h641100 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21203,39 +21203,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h195749 : + n___1__h195752 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21288,7 +21288,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h194346 : + x__h194349 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ? 64'd0 : 64'd1) ; @@ -21300,7 +21300,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 = - _theResult_____2__h293741 == v__h293161 ; + _theResult_____2__h293743 == v__h293163 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21309,7 +21309,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 = - _theResult_____2__h301737 == v__h296506 ; + _theResult_____2__h301739 == v__h296508 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21338,7 +21338,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h299371 } ; + x__h299373 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21436,35 +21436,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h191674 : + n__h191677 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21492,7 +21492,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 = - _theResult_____2__h307731 == v__h307020 ; + _theResult_____2__h307733 == v__h307022 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21501,7 +21501,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 = - _theResult_____2__h315585 == v__h310896 ; + _theResult_____2__h315587 == v__h310898 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21653,7 +21653,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 = - _theResult_____2__h329154 == v__h328722 ; + _theResult_____2__h329156 == v__h328724 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -21702,7 +21702,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 = - _theResult_____2__h325929 == v__h325497 ; + _theResult_____2__h325931 == v__h325499 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -21849,60 +21849,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h705141 : + y_avValue_snd_snd_snd_snd_snd__h705150 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705125 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h705134 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h705135 : + y_avValue_snd_snd_snd_fst__h705144 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4562_BIT_25_456_ETC___d14762 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin08243_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h508243[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin14860_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h414860[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin42782_BIT_33_THEN_2_ELSE_0__q91 = - sfdin__h442782[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin47044_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h547044[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin51404_BIT_33_THEN_2_ELSE_0__q21 = - sfdin__h351404[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin60548_BIT_33_THEN_2_ELSE_0__q101 = - sfdin__h460548[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin69170_BIT_33_THEN_2_ELSE_0__q31 = - sfdin__h369170[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin86245_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h586245[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin97094_BIT_33_THEN_2_ELSE_0__q56 = - sfdin__h397094[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd05707_BIT_33_THEN_2_ELSE_0__q58 = - _theResult___snd__h405707[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd17028_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h517028[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd23497_BIT_33_THEN_2_ELSE_0__q71 = - _theResult___snd__h423497[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37424_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h537424[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd51395_BIT_33_THEN_2_ELSE_0__q93 = - _theResult___snd__h451395[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd55829_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h555829[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd60017_BIT_33_THEN_2_ELSE_0__q23 = - _theResult___snd__h360017[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd69185_BIT_33_THEN_2_ELSE_0__q106 = - _theResult___snd__h469185[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76625_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h576625[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd77807_BIT_33_THEN_2_ELSE_0__q36 = - _theResult___snd__h377807[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd95030_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h595030[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98623_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h498623[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h508247[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66 = + sfdin__h414863[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91 = + sfdin__h442785[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h547048[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21 = + sfdin__h351407[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101 = + sfdin__h460551[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31 = + sfdin__h369173[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h586249[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56 = + sfdin__h397097[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58 = + _theResult___snd__h405710[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h517032[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71 = + _theResult___snd__h423500[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h537428[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93 = + _theResult___snd__h451398[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h555833[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23 = + _theResult___snd__h360020[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106 = + _theResult___snd__h469188[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h576629[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36 = + _theResult___snd__h377810[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h595034[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h498627[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? @@ -21991,10 +21991,10 @@ module mkCore(CLK, !checkForException___d13458[4] && NOT_csrf_fs_reg_read__1491_EQ_0_2828_2829_OR_N_ETC___d13483 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4555_4556_OR__ETC___d14768 = - (fflags__h705618 & csrf_fflags_reg) != fflags__h705618 || - !r__h608864 && + (fflags__h705627 & csrf_fflags_reg) != fflags__h705627 || + !r__h608869 && (IF_rob_deqPort_1_canDeq__4559_THEN_IF_NOT_rob__ETC___d14763 || - fflags__h705618 != 5'd0) ; + fflags__h705627 != 5'd0) ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13263 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -22806,8 +22806,8 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13117 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h649444 == 5'd0 && - imm__h649445 == 32'd0 || + rs1__h649453 == 5'd0 && + imm__h649454 == 32'd0 || IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207 = @@ -23142,7 +23142,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934, - x__h288835 } ; + x__h288838 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14890 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -23275,15 +23275,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 = { 3'd0, - _theResult___fst_exp__h351410 == 8'd0 && - (sfdin__h351404[56:34] == 23'd0 || guard__h343309 != 2'b0), + _theResult___fst_exp__h351413 == 8'd0 && + (sfdin__h351407[56:34] == 23'd0 || guard__h343312 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h352007 == 8'd255 && - _theResult___fst_sfd__h352008 == 23'd0, + _theResult___fst_exp__h352010 == 8'd255 && + _theResult___fst_sfd__h352011 == 23'd0, 1'd0, - _theResult___fst_exp__h351410 != 8'd255 && - guard__h343309 != 2'b0 } ; + _theResult___fst_exp__h351413 != 8'd255 && + guard__h343312 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^ @@ -23291,15 +23291,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 = { 3'd0, - _theResult___fst_exp__h397100 == 8'd0 && - (sfdin__h397094[56:34] == 23'd0 || guard__h389001 != 2'b0), + _theResult___fst_exp__h397103 == 8'd0 && + (sfdin__h397097[56:34] == 23'd0 || guard__h389004 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h397697 == 8'd255 && - _theResult___fst_sfd__h397698 == 23'd0, + _theResult___fst_exp__h397700 == 8'd255 && + _theResult___fst_sfd__h397701 == 23'd0, 1'd0, - _theResult___fst_exp__h397100 != 8'd255 && - guard__h389001 != 2'b0 } ; + _theResult___fst_exp__h397103 != 8'd255 && + guard__h389004 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^ @@ -23307,15 +23307,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 = { 3'd0, - _theResult___fst_exp__h442788 == 8'd0 && - (sfdin__h442782[56:34] == 23'd0 || guard__h434689 != 2'b0), + _theResult___fst_exp__h442791 == 8'd0 && + (sfdin__h442785[56:34] == 23'd0 || guard__h434692 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h443385 == 8'd255 && - _theResult___fst_sfd__h443386 == 23'd0, + _theResult___fst_exp__h443388 == 8'd255 && + _theResult___fst_sfd__h443389 == 23'd0, 1'd0, - _theResult___fst_exp__h442788 != 8'd255 && - guard__h434689 != 2'b0 } ; + _theResult___fst_exp__h442791 != 8'd255 && + guard__h434692 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ^ @@ -23323,37 +23323,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10736 = { 3'd0, - _theResult___fst_exp__h508249 == 11'd0 && - (sfdin__h508243[56:5] == 52'd0 || guard__h500023 != 2'b0), + _theResult___fst_exp__h508253 == 11'd0 && + (sfdin__h508247[56:5] == 52'd0 || guard__h500027 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h509081 == 11'd2047 && - _theResult___fst_sfd__h509082 == 52'd0, + _theResult___fst_exp__h509085 == 11'd2047 && + _theResult___fst_sfd__h509086 == 52'd0, 1'd0, - _theResult___fst_exp__h508249 != 11'd2047 && - guard__h500023 != 2'b0 } ; + _theResult___fst_exp__h508253 != 11'd2047 && + guard__h500027 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10777 = { 3'd0, - _theResult___fst_exp__h547050 == 11'd0 && - (sfdin__h547044[56:5] == 52'd0 || guard__h538824 != 2'b0), + _theResult___fst_exp__h547054 == 11'd0 && + (sfdin__h547048[56:5] == 52'd0 || guard__h538828 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h547882 == 11'd2047 && - _theResult___fst_sfd__h547883 == 52'd0, + _theResult___fst_exp__h547886 == 11'd2047 && + _theResult___fst_sfd__h547887 == 52'd0, 1'd0, - _theResult___fst_exp__h547050 != 11'd2047 && - guard__h538824 != 2'b0 } ; + _theResult___fst_exp__h547054 != 11'd2047 && + guard__h538828 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10821 = { 3'd0, - _theResult___fst_exp__h586251 == 11'd0 && - (sfdin__h586245[56:5] == 52'd0 || guard__h578025 != 2'b0), + _theResult___fst_exp__h586255 == 11'd0 && + (sfdin__h586249[56:5] == 52'd0 || guard__h578029 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h587083 == 11'd2047 && - _theResult___fst_sfd__h587084 == 52'd0, + _theResult___fst_exp__h587087 == 11'd2047 && + _theResult___fst_sfd__h587088 == 52'd0, 1'd0, - _theResult___fst_exp__h586251 != 11'd2047 && - guard__h578025 != 2'b0 } ; + _theResult___fst_exp__h586255 != 11'd2047 && + guard__h578029 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ^ @@ -23371,15 +23371,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 = { 3'd0, - _theResult___fst_exp__h369176 == 8'd0 && - (sfdin__h369170[56:34] == 23'd0 || guard__h360948 != 2'b0), + _theResult___fst_exp__h369179 == 8'd0 && + (sfdin__h369173[56:34] == 23'd0 || guard__h360951 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h369773 == 8'd255 && - _theResult___fst_sfd__h369774 == 23'd0, + _theResult___fst_exp__h369776 == 8'd255 && + _theResult___fst_sfd__h369777 == 23'd0, 1'd0, - _theResult___fst_exp__h369176 != 8'd255 && - guard__h360948 != 2'b0 } ; + _theResult___fst_exp__h369179 != 8'd255 && + guard__h360951 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^ @@ -23387,15 +23387,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 = { 3'd0, - _theResult___fst_exp__h414866 == 8'd0 && - (sfdin__h414860[56:34] == 23'd0 || guard__h406638 != 2'b0), + _theResult___fst_exp__h414869 == 8'd0 && + (sfdin__h414863[56:34] == 23'd0 || guard__h406641 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h415463 == 8'd255 && - _theResult___fst_sfd__h415464 == 23'd0, + _theResult___fst_exp__h415466 == 8'd255 && + _theResult___fst_sfd__h415467 == 23'd0, 1'd0, - _theResult___fst_exp__h414866 != 8'd255 && - guard__h406638 != 2'b0 } ; + _theResult___fst_exp__h414869 != 8'd255 && + guard__h406641 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^ @@ -23403,15 +23403,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 = { 3'd0, - _theResult___fst_exp__h460554 == 8'd0 && - (sfdin__h460548[56:34] == 23'd0 || guard__h452326 != 2'b0), + _theResult___fst_exp__h460557 == 8'd0 && + (sfdin__h460551[56:34] == 23'd0 || guard__h452329 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h461151 == 8'd255 && - _theResult___fst_sfd__h461152 == 23'd0, + _theResult___fst_exp__h461154 == 8'd255 && + _theResult___fst_sfd__h461155 == 23'd0, 1'd0, - _theResult___fst_exp__h460554 != 8'd255 && - guard__h452326 != 2'b0 } ; + _theResult___fst_exp__h460557 != 8'd255 && + guard__h452329 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^ @@ -23425,15 +23425,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 = { 3'd0, - _theResult___fst_exp__h360066 == 8'd0 && - guard__h352018 != 2'b0, + _theResult___fst_exp__h360069 == 8'd0 && + guard__h352021 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h360589 == 8'd255 && - _theResult___fst_sfd__h360590 == 23'd0, + _theResult___fst_exp__h360592 == 8'd255 && + _theResult___fst_sfd__h360593 == 23'd0, 1'd0, - _theResult___fst_exp__h360066 != 8'd255 && - guard__h352018 != 2'b0 } ; + _theResult___fst_exp__h360069 != 8'd255 && + guard__h352021 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^ @@ -23447,15 +23447,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 = { 3'd0, - _theResult___fst_exp__h405756 == 8'd0 && - guard__h397708 != 2'b0, + _theResult___fst_exp__h405759 == 8'd0 && + guard__h397711 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h406279 == 8'd255 && - _theResult___fst_sfd__h406280 == 23'd0, + _theResult___fst_exp__h406282 == 8'd255 && + _theResult___fst_sfd__h406283 == 23'd0, 1'd0, - _theResult___fst_exp__h405756 != 8'd255 && - guard__h397708 != 2'b0 } ; + _theResult___fst_exp__h405759 != 8'd255 && + guard__h397711 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^ @@ -23469,15 +23469,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 = { 3'd0, - _theResult___fst_exp__h451444 == 8'd0 && - guard__h443396 != 2'b0, + _theResult___fst_exp__h451447 == 8'd0 && + guard__h443399 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h451967 == 8'd255 && - _theResult___fst_sfd__h451968 == 23'd0, + _theResult___fst_exp__h451970 == 8'd255 && + _theResult___fst_sfd__h451971 == 23'd0, 1'd0, - _theResult___fst_exp__h451444 != 8'd255 && - guard__h443396 != 2'b0 } ; + _theResult___fst_exp__h451447 != 8'd255 && + guard__h443399 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ^ @@ -23491,37 +23491,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10719 = { 3'd0, - _theResult___fst_exp__h498672 == 11'd0 && - guard__h490711 != 2'b0, + _theResult___fst_exp__h498676 == 11'd0 && + guard__h490715 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h499430 == 11'd2047 && - _theResult___fst_sfd__h499431 == 52'd0, + _theResult___fst_exp__h499434 == 11'd2047 && + _theResult___fst_sfd__h499435 == 52'd0, 1'd0, - _theResult___fst_exp__h498672 != 11'd2047 && - guard__h490711 != 2'b0 } ; + _theResult___fst_exp__h498676 != 11'd2047 && + guard__h490715 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10760 = { 3'd0, - _theResult___fst_exp__h537473 == 11'd0 && - guard__h529512 != 2'b0, + _theResult___fst_exp__h537477 == 11'd0 && + guard__h529516 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h538231 == 11'd2047 && - _theResult___fst_sfd__h538232 == 52'd0, + _theResult___fst_exp__h538235 == 11'd2047 && + _theResult___fst_sfd__h538236 == 52'd0, 1'd0, - _theResult___fst_exp__h537473 != 11'd2047 && - guard__h529512 != 2'b0 } ; + _theResult___fst_exp__h537477 != 11'd2047 && + guard__h529516 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10804 = { 3'd0, - _theResult___fst_exp__h576674 == 11'd0 && - guard__h568713 != 2'b0, + _theResult___fst_exp__h576678 == 11'd0 && + guard__h568717 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h577432 == 11'd2047 && - _theResult___fst_sfd__h577433 == 52'd0, + _theResult___fst_exp__h577436 == 11'd2047 && + _theResult___fst_sfd__h577437 == 52'd0, 1'd0, - _theResult___fst_exp__h576674 != 11'd2047 && - guard__h568713 != 2'b0 } ; + _theResult___fst_exp__h576678 != 11'd2047 && + guard__h568717 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577 = ({ 6'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ^ @@ -23547,7 +23547,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2605_BI_ETC___d13675 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2614_BI_ETC___d13760 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -23559,33 +23559,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2614_BITS_199_TO_ETC___d13555 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 = - sfd__h335694 >> + sfd__h335697 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 = - sfd__h381389 >> + sfd__h381392 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 = - sfd__h427077 >> + sfd__h427080 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118 = - sfd__h518613 >> + sfd__h518617 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645 = - sfd__h479671 >> + sfd__h479675 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355 = - sfd__h557814 >> + sfd__h557818 >> _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1598_1599_ETC___d14227 = - medeleg_csr__read__h607135[i__h692195] ; + medeleg_csr__read__h607140[i__h692204] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1606_1607_ETC___d14209 = - mideleg_csr__read__h607230[i__h692355] ; + mideleg_csr__read__h607235[i__h692364] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 = 12'd3074 - { 6'd0, @@ -24180,7 +24180,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2603_2604_O_ETC___d13986 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h661036 == 1'd0 && + k__h661045 == 1'd0 && fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13837 || fetchStage_pipelines_0_canDeq__2603_AND_NOT_fe_ETC___d13924 == 1'd0 && @@ -24199,7 +24199,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd18 || rob$deqPort_0_deq_data[186:182] == 5'd20 ; - assign _dfoo28 = + assign _dfoo26 = rob$deqPort_0_deq_data[186:182] == 5'd13 && (IF_rob_deqPort_0_deq_data__4053_BIT_181_4277_T_ETC___d14351 == 6'd8 || @@ -24287,1430 +24287,1430 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h293741 = + assign _theResult_____2__h293743 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ? - next_deqP___1__h294020 : + next_deqP___1__h294022 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h301737 = + assign _theResult_____2__h301739 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ? - next_deqP___1__h302016 : + next_deqP___1__h302018 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h307731 = + assign _theResult_____2__h307733 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ? - next_deqP___1__h308297 : + next_deqP___1__h308299 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h315585 = + assign _theResult_____2__h315587 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ? - next_deqP___1__h316151 : + next_deqP___1__h316153 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h325929 = + assign _theResult_____2__h325931 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ? - next_deqP___1__h326208 : + next_deqP___1__h326210 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h329154 = + assign _theResult_____2__h329156 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ? - next_deqP___1__h329433 : + next_deqP___1__h329435 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h343299 = - (value__h343921 == 54'd0) ? sfd__h335694 : 57'd1 ; - assign _theResult____h360938 = + assign _theResult____h343302 = + (value__h343924 == 54'd0) ? sfd__h335697 : 57'd1 ; + assign _theResult____h360941 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^ 12'h800) < 12'd2105) ? - result__h361551 : - _theResult____h343299 ; - assign _theResult____h388991 = - (value__h389611 == 54'd0) ? sfd__h381389 : 57'd1 ; - assign _theResult____h406628 = + result__h361554 : + _theResult____h343302 ; + assign _theResult____h388994 = + (value__h389614 == 54'd0) ? sfd__h381392 : 57'd1 ; + assign _theResult____h406631 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^ 12'h800) < 12'd2105) ? - result__h407241 : - _theResult____h388991 ; - assign _theResult____h434679 = - (value__h435299 == 54'd0) ? sfd__h427077 : 57'd1 ; - assign _theResult____h452316 = + result__h407244 : + _theResult____h388994 ; + assign _theResult____h434682 = + (value__h435302 == 54'd0) ? sfd__h427080 : 57'd1 ; + assign _theResult____h452319 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^ 12'h800) < 12'd2105) ? - result__h452929 : - _theResult____h434679 ; - assign _theResult____h500013 = + result__h452932 : + _theResult____h434682 ; + assign _theResult____h500017 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ^ 12'h800) < 12'd2105) ? - result__h500626 : - ((value__h484229 == 25'd0) ? sfd__h479671 : 57'd1) ; - assign _theResult____h538814 = + result__h500630 : + ((value__h484233 == 25'd0) ? sfd__h479675 : 57'd1) ; + assign _theResult____h538818 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ^ 12'h800) < 12'd2105) ? - result__h539427 : - ((value__h523030 == 25'd0) ? sfd__h518613 : 57'd1) ; - assign _theResult____h578015 = + result__h539431 : + ((value__h523034 == 25'd0) ? sfd__h518617 : 57'd1) ; + assign _theResult____h578019 = ((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ^ 12'h800) < 12'd2105) ? - result__h578628 : - ((value__h562231 == 25'd0) ? sfd__h557814 : 57'd1) ; - assign _theResult____h645389 = + result__h578632 : + ((value__h562235 == 25'd0) ? sfd__h557818 : 57'd1) ; + assign _theResult____h645398 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h645886 : + enabled_ints___1__h645895 : 15'd0 ; - assign _theResult___exp__h351926 = - sfd__h351502[24] ? - ((_theResult___fst_exp__h351410 == 8'd254) ? + assign _theResult___exp__h351929 = + sfd__h351505[24] ? + ((_theResult___fst_exp__h351413 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378443) : - ((_theResult___fst_exp__h351410 == 8'd0 && - sfd__h351502[24:23] == 2'b01) ? + din_inc___2_exp__h378446) : + ((_theResult___fst_exp__h351413 == 8'd0 && + sfd__h351505[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h351410) ; - assign _theResult___exp__h360508 = - sfd__h360084[24] ? - ((_theResult___fst_exp__h360066 == 8'd254) ? + _theResult___fst_exp__h351413) ; + assign _theResult___exp__h360511 = + sfd__h360087[24] ? + ((_theResult___fst_exp__h360069 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378467) : - ((_theResult___fst_exp__h360066 == 8'd0 && - sfd__h360084[24:23] == 2'b01) ? + din_inc___2_exp__h378470) : + ((_theResult___fst_exp__h360069 == 8'd0 && + sfd__h360087[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h360066) ; - assign _theResult___exp__h369692 = - sfd__h369268[24] ? - ((_theResult___fst_exp__h369176 == 8'd254) ? + _theResult___fst_exp__h360069) ; + assign _theResult___exp__h369695 = + sfd__h369271[24] ? + ((_theResult___fst_exp__h369179 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378497) : - ((_theResult___fst_exp__h369176 == 8'd0 && - sfd__h369268[24:23] == 2'b01) ? + din_inc___2_exp__h378500) : + ((_theResult___fst_exp__h369179 == 8'd0 && + sfd__h369271[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h369176) ; - assign _theResult___exp__h378328 = - sfd__h377880[24] ? - ((_theResult___fst_exp__h377861 == 8'd254) ? + _theResult___fst_exp__h369179) ; + assign _theResult___exp__h378331 = + sfd__h377883[24] ? + ((_theResult___fst_exp__h377864 == 8'd254) ? 8'd255 : - din_inc___2_exp__h378521) : - ((_theResult___fst_exp__h377861 == 8'd0 && - sfd__h377880[24:23] == 2'b01) ? + din_inc___2_exp__h378524) : + ((_theResult___fst_exp__h377864 == 8'd0 && + sfd__h377883[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h377861) ; - assign _theResult___exp__h378430 = + _theResult___fst_exp__h377864) ; + assign _theResult___exp__h378433 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378421 ; - assign _theResult___exp__h397616 = - sfd__h397192[24] ? - ((_theResult___fst_exp__h397100 == 8'd254) ? + _theResult___fst_exp__h378424 ; + assign _theResult___exp__h397619 = + sfd__h397195[24] ? + ((_theResult___fst_exp__h397103 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424133) : - ((_theResult___fst_exp__h397100 == 8'd0 && - sfd__h397192[24:23] == 2'b01) ? + din_inc___2_exp__h424136) : + ((_theResult___fst_exp__h397103 == 8'd0 && + sfd__h397195[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h397100) ; - assign _theResult___exp__h406198 = - sfd__h405774[24] ? - ((_theResult___fst_exp__h405756 == 8'd254) ? + _theResult___fst_exp__h397103) ; + assign _theResult___exp__h406201 = + sfd__h405777[24] ? + ((_theResult___fst_exp__h405759 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424157) : - ((_theResult___fst_exp__h405756 == 8'd0 && - sfd__h405774[24:23] == 2'b01) ? + din_inc___2_exp__h424160) : + ((_theResult___fst_exp__h405759 == 8'd0 && + sfd__h405777[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h405756) ; - assign _theResult___exp__h415382 = - sfd__h414958[24] ? - ((_theResult___fst_exp__h414866 == 8'd254) ? + _theResult___fst_exp__h405759) ; + assign _theResult___exp__h415385 = + sfd__h414961[24] ? + ((_theResult___fst_exp__h414869 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424187) : - ((_theResult___fst_exp__h414866 == 8'd0 && - sfd__h414958[24:23] == 2'b01) ? + din_inc___2_exp__h424190) : + ((_theResult___fst_exp__h414869 == 8'd0 && + sfd__h414961[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h414866) ; - assign _theResult___exp__h424018 = - sfd__h423570[24] ? - ((_theResult___fst_exp__h423551 == 8'd254) ? + _theResult___fst_exp__h414869) ; + assign _theResult___exp__h424021 = + sfd__h423573[24] ? + ((_theResult___fst_exp__h423554 == 8'd254) ? 8'd255 : - din_inc___2_exp__h424211) : - ((_theResult___fst_exp__h423551 == 8'd0 && - sfd__h423570[24:23] == 2'b01) ? + din_inc___2_exp__h424214) : + ((_theResult___fst_exp__h423554 == 8'd0 && + sfd__h423573[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h423551) ; - assign _theResult___exp__h424120 = + _theResult___fst_exp__h423554) ; + assign _theResult___exp__h424123 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424111 ; - assign _theResult___exp__h443304 = - sfd__h442880[24] ? - ((_theResult___fst_exp__h442788 == 8'd254) ? + _theResult___fst_exp__h424114 ; + assign _theResult___exp__h443307 = + sfd__h442883[24] ? + ((_theResult___fst_exp__h442791 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469821) : - ((_theResult___fst_exp__h442788 == 8'd0 && - sfd__h442880[24:23] == 2'b01) ? + din_inc___2_exp__h469824) : + ((_theResult___fst_exp__h442791 == 8'd0 && + sfd__h442883[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h442788) ; - assign _theResult___exp__h451886 = - sfd__h451462[24] ? - ((_theResult___fst_exp__h451444 == 8'd254) ? + _theResult___fst_exp__h442791) ; + assign _theResult___exp__h451889 = + sfd__h451465[24] ? + ((_theResult___fst_exp__h451447 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469845) : - ((_theResult___fst_exp__h451444 == 8'd0 && - sfd__h451462[24:23] == 2'b01) ? + din_inc___2_exp__h469848) : + ((_theResult___fst_exp__h451447 == 8'd0 && + sfd__h451465[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h451444) ; - assign _theResult___exp__h461070 = - sfd__h460646[24] ? - ((_theResult___fst_exp__h460554 == 8'd254) ? + _theResult___fst_exp__h451447) ; + assign _theResult___exp__h461073 = + sfd__h460649[24] ? + ((_theResult___fst_exp__h460557 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469875) : - ((_theResult___fst_exp__h460554 == 8'd0 && - sfd__h460646[24:23] == 2'b01) ? + din_inc___2_exp__h469878) : + ((_theResult___fst_exp__h460557 == 8'd0 && + sfd__h460649[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h460554) ; - assign _theResult___exp__h469706 = - sfd__h469258[24] ? - ((_theResult___fst_exp__h469239 == 8'd254) ? + _theResult___fst_exp__h460557) ; + assign _theResult___exp__h469709 = + sfd__h469261[24] ? + ((_theResult___fst_exp__h469242 == 8'd254) ? 8'd255 : - din_inc___2_exp__h469899) : - ((_theResult___fst_exp__h469239 == 8'd0 && - sfd__h469258[24:23] == 2'b01) ? + din_inc___2_exp__h469902) : + ((_theResult___fst_exp__h469242 == 8'd0 && + sfd__h469261[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h469239) ; - assign _theResult___exp__h469808 = + _theResult___fst_exp__h469242) ; + assign _theResult___exp__h469811 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469799 ; - assign _theResult___exp__h499327 = - sfd__h498690[53] ? - ((_theResult___fst_exp__h498672 == 11'd2046) ? + _theResult___fst_exp__h469802 ; + assign _theResult___exp__h499331 = + sfd__h498694[53] ? + ((_theResult___fst_exp__h498676 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517922) : - ((_theResult___fst_exp__h498672 == 11'd0 && - sfd__h498690[53:52] == 2'b01) ? + din_inc___2_exp__h517926) : + ((_theResult___fst_exp__h498676 == 11'd0 && + sfd__h498694[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h498672) ; - assign _theResult___exp__h508978 = - sfd__h508341[53] ? - ((_theResult___fst_exp__h508249 == 11'd2046) ? + _theResult___fst_exp__h498676) ; + assign _theResult___exp__h508982 = + sfd__h508345[53] ? + ((_theResult___fst_exp__h508253 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517957) : - ((_theResult___fst_exp__h508249 == 11'd0 && - sfd__h508341[53:52] == 2'b01) ? + din_inc___2_exp__h517961) : + ((_theResult___fst_exp__h508253 == 11'd0 && + sfd__h508345[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h508249) ; - assign _theResult___exp__h517762 = - sfd__h517101[53] ? - ((_theResult___fst_exp__h517082 == 11'd2046) ? + _theResult___fst_exp__h508253) ; + assign _theResult___exp__h517766 = + sfd__h517105[53] ? + ((_theResult___fst_exp__h517086 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h517983) : - ((_theResult___fst_exp__h517082 == 11'd0 && - sfd__h517101[53:52] == 2'b01) ? + din_inc___2_exp__h517987) : + ((_theResult___fst_exp__h517086 == 11'd0 && + sfd__h517105[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h517082) ; - assign _theResult___exp__h538128 = - sfd__h537491[53] ? - ((_theResult___fst_exp__h537473 == 11'd2046) ? + _theResult___fst_exp__h517086) ; + assign _theResult___exp__h538132 = + sfd__h537495[53] ? + ((_theResult___fst_exp__h537477 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556723) : - ((_theResult___fst_exp__h537473 == 11'd0 && - sfd__h537491[53:52] == 2'b01) ? + din_inc___2_exp__h556727) : + ((_theResult___fst_exp__h537477 == 11'd0 && + sfd__h537495[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h537473) ; - assign _theResult___exp__h547779 = - sfd__h547142[53] ? - ((_theResult___fst_exp__h547050 == 11'd2046) ? + _theResult___fst_exp__h537477) ; + assign _theResult___exp__h547783 = + sfd__h547146[53] ? + ((_theResult___fst_exp__h547054 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556758) : - ((_theResult___fst_exp__h547050 == 11'd0 && - sfd__h547142[53:52] == 2'b01) ? + din_inc___2_exp__h556762) : + ((_theResult___fst_exp__h547054 == 11'd0 && + sfd__h547146[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h547050) ; - assign _theResult___exp__h556563 = - sfd__h555902[53] ? - ((_theResult___fst_exp__h555883 == 11'd2046) ? + _theResult___fst_exp__h547054) ; + assign _theResult___exp__h556567 = + sfd__h555906[53] ? + ((_theResult___fst_exp__h555887 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h556784) : - ((_theResult___fst_exp__h555883 == 11'd0 && - sfd__h555902[53:52] == 2'b01) ? + din_inc___2_exp__h556788) : + ((_theResult___fst_exp__h555887 == 11'd0 && + sfd__h555906[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555883) ; - assign _theResult___exp__h577329 = - sfd__h576692[53] ? - ((_theResult___fst_exp__h576674 == 11'd2046) ? + _theResult___fst_exp__h555887) ; + assign _theResult___exp__h577333 = + sfd__h576696[53] ? + ((_theResult___fst_exp__h576678 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595924) : - ((_theResult___fst_exp__h576674 == 11'd0 && - sfd__h576692[53:52] == 2'b01) ? + din_inc___2_exp__h595928) : + ((_theResult___fst_exp__h576678 == 11'd0 && + sfd__h576696[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h576674) ; - assign _theResult___exp__h586980 = - sfd__h586343[53] ? - ((_theResult___fst_exp__h586251 == 11'd2046) ? + _theResult___fst_exp__h576678) ; + assign _theResult___exp__h586984 = + sfd__h586347[53] ? + ((_theResult___fst_exp__h586255 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595959) : - ((_theResult___fst_exp__h586251 == 11'd0 && - sfd__h586343[53:52] == 2'b01) ? + din_inc___2_exp__h595963) : + ((_theResult___fst_exp__h586255 == 11'd0 && + sfd__h586347[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h586251) ; - assign _theResult___exp__h595764 = - sfd__h595103[53] ? - ((_theResult___fst_exp__h595084 == 11'd2046) ? + _theResult___fst_exp__h586255) ; + assign _theResult___exp__h595768 = + sfd__h595107[53] ? + ((_theResult___fst_exp__h595088 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h595985) : - ((_theResult___fst_exp__h595084 == 11'd0 && - sfd__h595103[53:52] == 2'b01) ? + din_inc___2_exp__h595989) : + ((_theResult___fst_exp__h595088 == 11'd0 && + sfd__h595107[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h595084) ; - assign _theResult___fst__h600257 = - a__h599835[63] ? a___1__h600262 : a__h599835 ; - assign _theResult___fst_exp__h351410 = - _theResult____h343299[56] ? + _theResult___fst_exp__h595088) ; + assign _theResult___fst__h600261 = + a__h599839[63] ? a___1__h600266 : a__h599839 ; + assign _theResult___fst_exp__h351413 = + _theResult____h343302[56] ? 8'd2 : - _theResult___fst_exp__h351484 ; - assign _theResult___fst_exp__h351475 = + _theResult___fst_exp__h351487 ; + assign _theResult___fst_exp__h351478 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ; - assign _theResult___fst_exp__h351481 = - (!_theResult____h343299[56] && !_theResult____h343299[55] && - !_theResult____h343299[54] && - !_theResult____h343299[53] && - !_theResult____h343299[52] && - !_theResult____h343299[51] && - !_theResult____h343299[50] && - !_theResult____h343299[49] && - !_theResult____h343299[48] && - !_theResult____h343299[47] && - !_theResult____h343299[46] && - !_theResult____h343299[45] && - !_theResult____h343299[44] && - !_theResult____h343299[43] && - !_theResult____h343299[42] && - !_theResult____h343299[41] && - !_theResult____h343299[40] && - !_theResult____h343299[39] && - !_theResult____h343299[38] && - !_theResult____h343299[37] && - !_theResult____h343299[36] && - !_theResult____h343299[35] && - !_theResult____h343299[34] && - !_theResult____h343299[33] && - !_theResult____h343299[32] && - !_theResult____h343299[31] && - !_theResult____h343299[30] && - !_theResult____h343299[29] && - !_theResult____h343299[28] && - !_theResult____h343299[27] && - !_theResult____h343299[26] && - !_theResult____h343299[25] && - !_theResult____h343299[24] && - !_theResult____h343299[23] && - !_theResult____h343299[22] && - !_theResult____h343299[21] && - !_theResult____h343299[20] && - !_theResult____h343299[19] && - !_theResult____h343299[18] && - !_theResult____h343299[17] && - !_theResult____h343299[16] && - !_theResult____h343299[15] && - !_theResult____h343299[14] && - !_theResult____h343299[13] && - !_theResult____h343299[12] && - !_theResult____h343299[11] && - !_theResult____h343299[10] && - !_theResult____h343299[9] && - !_theResult____h343299[8] && - !_theResult____h343299[7] && - !_theResult____h343299[6] && - !_theResult____h343299[5] && - !_theResult____h343299[4] && - !_theResult____h343299[3] && - !_theResult____h343299[2] && - !_theResult____h343299[1] && - !_theResult____h343299[0] || + assign _theResult___fst_exp__h351484 = + (!_theResult____h343302[56] && !_theResult____h343302[55] && + !_theResult____h343302[54] && + !_theResult____h343302[53] && + !_theResult____h343302[52] && + !_theResult____h343302[51] && + !_theResult____h343302[50] && + !_theResult____h343302[49] && + !_theResult____h343302[48] && + !_theResult____h343302[47] && + !_theResult____h343302[46] && + !_theResult____h343302[45] && + !_theResult____h343302[44] && + !_theResult____h343302[43] && + !_theResult____h343302[42] && + !_theResult____h343302[41] && + !_theResult____h343302[40] && + !_theResult____h343302[39] && + !_theResult____h343302[38] && + !_theResult____h343302[37] && + !_theResult____h343302[36] && + !_theResult____h343302[35] && + !_theResult____h343302[34] && + !_theResult____h343302[33] && + !_theResult____h343302[32] && + !_theResult____h343302[31] && + !_theResult____h343302[30] && + !_theResult____h343302[29] && + !_theResult____h343302[28] && + !_theResult____h343302[27] && + !_theResult____h343302[26] && + !_theResult____h343302[25] && + !_theResult____h343302[24] && + !_theResult____h343302[23] && + !_theResult____h343302[22] && + !_theResult____h343302[21] && + !_theResult____h343302[20] && + !_theResult____h343302[19] && + !_theResult____h343302[18] && + !_theResult____h343302[17] && + !_theResult____h343302[16] && + !_theResult____h343302[15] && + !_theResult____h343302[14] && + !_theResult____h343302[13] && + !_theResult____h343302[12] && + !_theResult____h343302[11] && + !_theResult____h343302[10] && + !_theResult____h343302[9] && + !_theResult____h343302[8] && + !_theResult____h343302[7] && + !_theResult____h343302[6] && + !_theResult____h343302[5] && + !_theResult____h343302[4] && + !_theResult____h343302[3] && + !_theResult____h343302[2] && + !_theResult____h343302[1] && + !_theResult____h343302[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ? 8'd0 : - _theResult___fst_exp__h351475 ; - assign _theResult___fst_exp__h351484 = - (!_theResult____h343299[56] && _theResult____h343299[55]) ? + _theResult___fst_exp__h351478 ; + assign _theResult___fst_exp__h351487 = + (!_theResult____h343302[56] && _theResult____h343302[55]) ? 8'd1 : - _theResult___fst_exp__h351481 ; - assign _theResult___fst_exp__h352007 = - (_theResult___fst_exp__h351410 == 8'd255) ? - _theResult___fst_exp__h351410 : - _theResult___fst_exp__h352004 ; - assign _theResult___fst_exp__h360057 = + _theResult___fst_exp__h351484 ; + assign _theResult___fst_exp__h352010 = + (_theResult___fst_exp__h351413 == 8'd255) ? + _theResult___fst_exp__h351413 : + _theResult___fst_exp__h352007 ; + assign _theResult___fst_exp__h360060 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h360063 = + assign _theResult___fst_exp__h360066 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ? 8'd0 : - _theResult___fst_exp__h360057 ; - assign _theResult___fst_exp__h360066 = + _theResult___fst_exp__h360060 ; + assign _theResult___fst_exp__h360069 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h360063 : - 8'd129 ; - assign _theResult___fst_exp__h360589 = - (_theResult___fst_exp__h360066 == 8'd255) ? _theResult___fst_exp__h360066 : - _theResult___fst_exp__h360586 ; - assign _theResult___fst_exp__h369176 = - _theResult____h360938[56] ? + 8'd129 ; + assign _theResult___fst_exp__h360592 = + (_theResult___fst_exp__h360069 == 8'd255) ? + _theResult___fst_exp__h360069 : + _theResult___fst_exp__h360589 ; + assign _theResult___fst_exp__h369179 = + _theResult____h360941[56] ? 8'd2 : - _theResult___fst_exp__h369250 ; - assign _theResult___fst_exp__h369241 = + _theResult___fst_exp__h369253 ; + assign _theResult___fst_exp__h369244 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ; - assign _theResult___fst_exp__h369247 = - (!_theResult____h360938[56] && !_theResult____h360938[55] && - !_theResult____h360938[54] && - !_theResult____h360938[53] && - !_theResult____h360938[52] && - !_theResult____h360938[51] && - !_theResult____h360938[50] && - !_theResult____h360938[49] && - !_theResult____h360938[48] && - !_theResult____h360938[47] && - !_theResult____h360938[46] && - !_theResult____h360938[45] && - !_theResult____h360938[44] && - !_theResult____h360938[43] && - !_theResult____h360938[42] && - !_theResult____h360938[41] && - !_theResult____h360938[40] && - !_theResult____h360938[39] && - !_theResult____h360938[38] && - !_theResult____h360938[37] && - !_theResult____h360938[36] && - !_theResult____h360938[35] && - !_theResult____h360938[34] && - !_theResult____h360938[33] && - !_theResult____h360938[32] && - !_theResult____h360938[31] && - !_theResult____h360938[30] && - !_theResult____h360938[29] && - !_theResult____h360938[28] && - !_theResult____h360938[27] && - !_theResult____h360938[26] && - !_theResult____h360938[25] && - !_theResult____h360938[24] && - !_theResult____h360938[23] && - !_theResult____h360938[22] && - !_theResult____h360938[21] && - !_theResult____h360938[20] && - !_theResult____h360938[19] && - !_theResult____h360938[18] && - !_theResult____h360938[17] && - !_theResult____h360938[16] && - !_theResult____h360938[15] && - !_theResult____h360938[14] && - !_theResult____h360938[13] && - !_theResult____h360938[12] && - !_theResult____h360938[11] && - !_theResult____h360938[10] && - !_theResult____h360938[9] && - !_theResult____h360938[8] && - !_theResult____h360938[7] && - !_theResult____h360938[6] && - !_theResult____h360938[5] && - !_theResult____h360938[4] && - !_theResult____h360938[3] && - !_theResult____h360938[2] && - !_theResult____h360938[1] && - !_theResult____h360938[0] || + assign _theResult___fst_exp__h369250 = + (!_theResult____h360941[56] && !_theResult____h360941[55] && + !_theResult____h360941[54] && + !_theResult____h360941[53] && + !_theResult____h360941[52] && + !_theResult____h360941[51] && + !_theResult____h360941[50] && + !_theResult____h360941[49] && + !_theResult____h360941[48] && + !_theResult____h360941[47] && + !_theResult____h360941[46] && + !_theResult____h360941[45] && + !_theResult____h360941[44] && + !_theResult____h360941[43] && + !_theResult____h360941[42] && + !_theResult____h360941[41] && + !_theResult____h360941[40] && + !_theResult____h360941[39] && + !_theResult____h360941[38] && + !_theResult____h360941[37] && + !_theResult____h360941[36] && + !_theResult____h360941[35] && + !_theResult____h360941[34] && + !_theResult____h360941[33] && + !_theResult____h360941[32] && + !_theResult____h360941[31] && + !_theResult____h360941[30] && + !_theResult____h360941[29] && + !_theResult____h360941[28] && + !_theResult____h360941[27] && + !_theResult____h360941[26] && + !_theResult____h360941[25] && + !_theResult____h360941[24] && + !_theResult____h360941[23] && + !_theResult____h360941[22] && + !_theResult____h360941[21] && + !_theResult____h360941[20] && + !_theResult____h360941[19] && + !_theResult____h360941[18] && + !_theResult____h360941[17] && + !_theResult____h360941[16] && + !_theResult____h360941[15] && + !_theResult____h360941[14] && + !_theResult____h360941[13] && + !_theResult____h360941[12] && + !_theResult____h360941[11] && + !_theResult____h360941[10] && + !_theResult____h360941[9] && + !_theResult____h360941[8] && + !_theResult____h360941[7] && + !_theResult____h360941[6] && + !_theResult____h360941[5] && + !_theResult____h360941[4] && + !_theResult____h360941[3] && + !_theResult____h360941[2] && + !_theResult____h360941[1] && + !_theResult____h360941[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ? 8'd0 : - _theResult___fst_exp__h369241 ; - assign _theResult___fst_exp__h369250 = - (!_theResult____h360938[56] && _theResult____h360938[55]) ? + _theResult___fst_exp__h369244 ; + assign _theResult___fst_exp__h369253 = + (!_theResult____h360941[56] && _theResult____h360941[55]) ? 8'd1 : - _theResult___fst_exp__h369247 ; - assign _theResult___fst_exp__h369773 = - (_theResult___fst_exp__h369176 == 8'd255) ? - _theResult___fst_exp__h369176 : - _theResult___fst_exp__h369770 ; - assign _theResult___fst_exp__h377813 = + _theResult___fst_exp__h369250 ; + assign _theResult___fst_exp__h369776 = + (_theResult___fst_exp__h369179 == 8'd255) ? + _theResult___fst_exp__h369179 : + _theResult___fst_exp__h369773 ; + assign _theResult___fst_exp__h377816 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ; - assign _theResult___fst_exp__h377852 = + assign _theResult___fst_exp__h377855 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ; - assign _theResult___fst_exp__h377858 = + assign _theResult___fst_exp__h377861 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ? 8'd0 : - _theResult___fst_exp__h377852 ; - assign _theResult___fst_exp__h377861 = + _theResult___fst_exp__h377855 ; + assign _theResult___fst_exp__h377864 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h377858 : - _theResult___fst_exp__h377813 ; - assign _theResult___fst_exp__h378409 = - (_theResult___fst_exp__h377861 == 8'd255) ? _theResult___fst_exp__h377861 : - _theResult___fst_exp__h378406 ; - assign _theResult___fst_exp__h378418 = + _theResult___fst_exp__h377816 ; + assign _theResult___fst_exp__h378412 = + (_theResult___fst_exp__h377864 == 8'd255) ? + _theResult___fst_exp__h377864 : + _theResult___fst_exp__h378409 ; + assign _theResult___fst_exp__h378421 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_exp__h360592 : - _theResult___fst_exp__h343281) : + _theResult___snd_fst_exp__h360595 : + _theResult___fst_exp__h343284) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_exp__h378412 : - _theResult___fst_exp__h343281) ; - assign _theResult___fst_exp__h378421 = + _theResult___snd_fst_exp__h378415 : + _theResult___fst_exp__h343284) ; + assign _theResult___fst_exp__h378424 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h378418 ; - assign _theResult___fst_exp__h397100 = - _theResult____h388991[56] ? + _theResult___fst_exp__h378421 ; + assign _theResult___fst_exp__h397103 = + _theResult____h388994[56] ? 8'd2 : - _theResult___fst_exp__h397174 ; - assign _theResult___fst_exp__h397165 = + _theResult___fst_exp__h397177 ; + assign _theResult___fst_exp__h397168 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ; - assign _theResult___fst_exp__h397171 = - (!_theResult____h388991[56] && !_theResult____h388991[55] && - !_theResult____h388991[54] && - !_theResult____h388991[53] && - !_theResult____h388991[52] && - !_theResult____h388991[51] && - !_theResult____h388991[50] && - !_theResult____h388991[49] && - !_theResult____h388991[48] && - !_theResult____h388991[47] && - !_theResult____h388991[46] && - !_theResult____h388991[45] && - !_theResult____h388991[44] && - !_theResult____h388991[43] && - !_theResult____h388991[42] && - !_theResult____h388991[41] && - !_theResult____h388991[40] && - !_theResult____h388991[39] && - !_theResult____h388991[38] && - !_theResult____h388991[37] && - !_theResult____h388991[36] && - !_theResult____h388991[35] && - !_theResult____h388991[34] && - !_theResult____h388991[33] && - !_theResult____h388991[32] && - !_theResult____h388991[31] && - !_theResult____h388991[30] && - !_theResult____h388991[29] && - !_theResult____h388991[28] && - !_theResult____h388991[27] && - !_theResult____h388991[26] && - !_theResult____h388991[25] && - !_theResult____h388991[24] && - !_theResult____h388991[23] && - !_theResult____h388991[22] && - !_theResult____h388991[21] && - !_theResult____h388991[20] && - !_theResult____h388991[19] && - !_theResult____h388991[18] && - !_theResult____h388991[17] && - !_theResult____h388991[16] && - !_theResult____h388991[15] && - !_theResult____h388991[14] && - !_theResult____h388991[13] && - !_theResult____h388991[12] && - !_theResult____h388991[11] && - !_theResult____h388991[10] && - !_theResult____h388991[9] && - !_theResult____h388991[8] && - !_theResult____h388991[7] && - !_theResult____h388991[6] && - !_theResult____h388991[5] && - !_theResult____h388991[4] && - !_theResult____h388991[3] && - !_theResult____h388991[2] && - !_theResult____h388991[1] && - !_theResult____h388991[0] || + assign _theResult___fst_exp__h397174 = + (!_theResult____h388994[56] && !_theResult____h388994[55] && + !_theResult____h388994[54] && + !_theResult____h388994[53] && + !_theResult____h388994[52] && + !_theResult____h388994[51] && + !_theResult____h388994[50] && + !_theResult____h388994[49] && + !_theResult____h388994[48] && + !_theResult____h388994[47] && + !_theResult____h388994[46] && + !_theResult____h388994[45] && + !_theResult____h388994[44] && + !_theResult____h388994[43] && + !_theResult____h388994[42] && + !_theResult____h388994[41] && + !_theResult____h388994[40] && + !_theResult____h388994[39] && + !_theResult____h388994[38] && + !_theResult____h388994[37] && + !_theResult____h388994[36] && + !_theResult____h388994[35] && + !_theResult____h388994[34] && + !_theResult____h388994[33] && + !_theResult____h388994[32] && + !_theResult____h388994[31] && + !_theResult____h388994[30] && + !_theResult____h388994[29] && + !_theResult____h388994[28] && + !_theResult____h388994[27] && + !_theResult____h388994[26] && + !_theResult____h388994[25] && + !_theResult____h388994[24] && + !_theResult____h388994[23] && + !_theResult____h388994[22] && + !_theResult____h388994[21] && + !_theResult____h388994[20] && + !_theResult____h388994[19] && + !_theResult____h388994[18] && + !_theResult____h388994[17] && + !_theResult____h388994[16] && + !_theResult____h388994[15] && + !_theResult____h388994[14] && + !_theResult____h388994[13] && + !_theResult____h388994[12] && + !_theResult____h388994[11] && + !_theResult____h388994[10] && + !_theResult____h388994[9] && + !_theResult____h388994[8] && + !_theResult____h388994[7] && + !_theResult____h388994[6] && + !_theResult____h388994[5] && + !_theResult____h388994[4] && + !_theResult____h388994[3] && + !_theResult____h388994[2] && + !_theResult____h388994[1] && + !_theResult____h388994[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ? 8'd0 : - _theResult___fst_exp__h397165 ; - assign _theResult___fst_exp__h397174 = - (!_theResult____h388991[56] && _theResult____h388991[55]) ? + _theResult___fst_exp__h397168 ; + assign _theResult___fst_exp__h397177 = + (!_theResult____h388994[56] && _theResult____h388994[55]) ? 8'd1 : - _theResult___fst_exp__h397171 ; - assign _theResult___fst_exp__h397697 = - (_theResult___fst_exp__h397100 == 8'd255) ? - _theResult___fst_exp__h397100 : - _theResult___fst_exp__h397694 ; - assign _theResult___fst_exp__h405747 = + _theResult___fst_exp__h397174 ; + assign _theResult___fst_exp__h397700 = + (_theResult___fst_exp__h397103 == 8'd255) ? + _theResult___fst_exp__h397103 : + _theResult___fst_exp__h397697 ; + assign _theResult___fst_exp__h405750 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h405753 = + assign _theResult___fst_exp__h405756 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ? 8'd0 : - _theResult___fst_exp__h405747 ; - assign _theResult___fst_exp__h405756 = + _theResult___fst_exp__h405750 ; + assign _theResult___fst_exp__h405759 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h405753 : - 8'd129 ; - assign _theResult___fst_exp__h406279 = - (_theResult___fst_exp__h405756 == 8'd255) ? _theResult___fst_exp__h405756 : - _theResult___fst_exp__h406276 ; - assign _theResult___fst_exp__h414866 = - _theResult____h406628[56] ? + 8'd129 ; + assign _theResult___fst_exp__h406282 = + (_theResult___fst_exp__h405759 == 8'd255) ? + _theResult___fst_exp__h405759 : + _theResult___fst_exp__h406279 ; + assign _theResult___fst_exp__h414869 = + _theResult____h406631[56] ? 8'd2 : - _theResult___fst_exp__h414940 ; - assign _theResult___fst_exp__h414931 = + _theResult___fst_exp__h414943 ; + assign _theResult___fst_exp__h414934 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ; - assign _theResult___fst_exp__h414937 = - (!_theResult____h406628[56] && !_theResult____h406628[55] && - !_theResult____h406628[54] && - !_theResult____h406628[53] && - !_theResult____h406628[52] && - !_theResult____h406628[51] && - !_theResult____h406628[50] && - !_theResult____h406628[49] && - !_theResult____h406628[48] && - !_theResult____h406628[47] && - !_theResult____h406628[46] && - !_theResult____h406628[45] && - !_theResult____h406628[44] && - !_theResult____h406628[43] && - !_theResult____h406628[42] && - !_theResult____h406628[41] && - !_theResult____h406628[40] && - !_theResult____h406628[39] && - !_theResult____h406628[38] && - !_theResult____h406628[37] && - !_theResult____h406628[36] && - !_theResult____h406628[35] && - !_theResult____h406628[34] && - !_theResult____h406628[33] && - !_theResult____h406628[32] && - !_theResult____h406628[31] && - !_theResult____h406628[30] && - !_theResult____h406628[29] && - !_theResult____h406628[28] && - !_theResult____h406628[27] && - !_theResult____h406628[26] && - !_theResult____h406628[25] && - !_theResult____h406628[24] && - !_theResult____h406628[23] && - !_theResult____h406628[22] && - !_theResult____h406628[21] && - !_theResult____h406628[20] && - !_theResult____h406628[19] && - !_theResult____h406628[18] && - !_theResult____h406628[17] && - !_theResult____h406628[16] && - !_theResult____h406628[15] && - !_theResult____h406628[14] && - !_theResult____h406628[13] && - !_theResult____h406628[12] && - !_theResult____h406628[11] && - !_theResult____h406628[10] && - !_theResult____h406628[9] && - !_theResult____h406628[8] && - !_theResult____h406628[7] && - !_theResult____h406628[6] && - !_theResult____h406628[5] && - !_theResult____h406628[4] && - !_theResult____h406628[3] && - !_theResult____h406628[2] && - !_theResult____h406628[1] && - !_theResult____h406628[0] || + assign _theResult___fst_exp__h414940 = + (!_theResult____h406631[56] && !_theResult____h406631[55] && + !_theResult____h406631[54] && + !_theResult____h406631[53] && + !_theResult____h406631[52] && + !_theResult____h406631[51] && + !_theResult____h406631[50] && + !_theResult____h406631[49] && + !_theResult____h406631[48] && + !_theResult____h406631[47] && + !_theResult____h406631[46] && + !_theResult____h406631[45] && + !_theResult____h406631[44] && + !_theResult____h406631[43] && + !_theResult____h406631[42] && + !_theResult____h406631[41] && + !_theResult____h406631[40] && + !_theResult____h406631[39] && + !_theResult____h406631[38] && + !_theResult____h406631[37] && + !_theResult____h406631[36] && + !_theResult____h406631[35] && + !_theResult____h406631[34] && + !_theResult____h406631[33] && + !_theResult____h406631[32] && + !_theResult____h406631[31] && + !_theResult____h406631[30] && + !_theResult____h406631[29] && + !_theResult____h406631[28] && + !_theResult____h406631[27] && + !_theResult____h406631[26] && + !_theResult____h406631[25] && + !_theResult____h406631[24] && + !_theResult____h406631[23] && + !_theResult____h406631[22] && + !_theResult____h406631[21] && + !_theResult____h406631[20] && + !_theResult____h406631[19] && + !_theResult____h406631[18] && + !_theResult____h406631[17] && + !_theResult____h406631[16] && + !_theResult____h406631[15] && + !_theResult____h406631[14] && + !_theResult____h406631[13] && + !_theResult____h406631[12] && + !_theResult____h406631[11] && + !_theResult____h406631[10] && + !_theResult____h406631[9] && + !_theResult____h406631[8] && + !_theResult____h406631[7] && + !_theResult____h406631[6] && + !_theResult____h406631[5] && + !_theResult____h406631[4] && + !_theResult____h406631[3] && + !_theResult____h406631[2] && + !_theResult____h406631[1] && + !_theResult____h406631[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ? 8'd0 : - _theResult___fst_exp__h414931 ; - assign _theResult___fst_exp__h414940 = - (!_theResult____h406628[56] && _theResult____h406628[55]) ? + _theResult___fst_exp__h414934 ; + assign _theResult___fst_exp__h414943 = + (!_theResult____h406631[56] && _theResult____h406631[55]) ? 8'd1 : - _theResult___fst_exp__h414937 ; - assign _theResult___fst_exp__h415463 = - (_theResult___fst_exp__h414866 == 8'd255) ? - _theResult___fst_exp__h414866 : - _theResult___fst_exp__h415460 ; - assign _theResult___fst_exp__h423503 = + _theResult___fst_exp__h414940 ; + assign _theResult___fst_exp__h415466 = + (_theResult___fst_exp__h414869 == 8'd255) ? + _theResult___fst_exp__h414869 : + _theResult___fst_exp__h415463 ; + assign _theResult___fst_exp__h423506 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ; - assign _theResult___fst_exp__h423542 = + assign _theResult___fst_exp__h423545 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ; - assign _theResult___fst_exp__h423548 = + assign _theResult___fst_exp__h423551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ? 8'd0 : - _theResult___fst_exp__h423542 ; - assign _theResult___fst_exp__h423551 = + _theResult___fst_exp__h423545 ; + assign _theResult___fst_exp__h423554 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h423548 : - _theResult___fst_exp__h423503 ; - assign _theResult___fst_exp__h424099 = - (_theResult___fst_exp__h423551 == 8'd255) ? _theResult___fst_exp__h423551 : - _theResult___fst_exp__h424096 ; - assign _theResult___fst_exp__h424108 = + _theResult___fst_exp__h423506 ; + assign _theResult___fst_exp__h424102 = + (_theResult___fst_exp__h423554 == 8'd255) ? + _theResult___fst_exp__h423554 : + _theResult___fst_exp__h424099 ; + assign _theResult___fst_exp__h424111 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_exp__h406282 : - _theResult___fst_exp__h388973) : + _theResult___snd_fst_exp__h406285 : + _theResult___fst_exp__h388976) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_exp__h424102 : - _theResult___fst_exp__h388973) ; - assign _theResult___fst_exp__h424111 = + _theResult___snd_fst_exp__h424105 : + _theResult___fst_exp__h388976) ; + assign _theResult___fst_exp__h424114 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h424108 ; - assign _theResult___fst_exp__h442788 = - _theResult____h434679[56] ? + _theResult___fst_exp__h424111 ; + assign _theResult___fst_exp__h442791 = + _theResult____h434682[56] ? 8'd2 : - _theResult___fst_exp__h442862 ; - assign _theResult___fst_exp__h442853 = + _theResult___fst_exp__h442865 ; + assign _theResult___fst_exp__h442856 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ; - assign _theResult___fst_exp__h442859 = - (!_theResult____h434679[56] && !_theResult____h434679[55] && - !_theResult____h434679[54] && - !_theResult____h434679[53] && - !_theResult____h434679[52] && - !_theResult____h434679[51] && - !_theResult____h434679[50] && - !_theResult____h434679[49] && - !_theResult____h434679[48] && - !_theResult____h434679[47] && - !_theResult____h434679[46] && - !_theResult____h434679[45] && - !_theResult____h434679[44] && - !_theResult____h434679[43] && - !_theResult____h434679[42] && - !_theResult____h434679[41] && - !_theResult____h434679[40] && - !_theResult____h434679[39] && - !_theResult____h434679[38] && - !_theResult____h434679[37] && - !_theResult____h434679[36] && - !_theResult____h434679[35] && - !_theResult____h434679[34] && - !_theResult____h434679[33] && - !_theResult____h434679[32] && - !_theResult____h434679[31] && - !_theResult____h434679[30] && - !_theResult____h434679[29] && - !_theResult____h434679[28] && - !_theResult____h434679[27] && - !_theResult____h434679[26] && - !_theResult____h434679[25] && - !_theResult____h434679[24] && - !_theResult____h434679[23] && - !_theResult____h434679[22] && - !_theResult____h434679[21] && - !_theResult____h434679[20] && - !_theResult____h434679[19] && - !_theResult____h434679[18] && - !_theResult____h434679[17] && - !_theResult____h434679[16] && - !_theResult____h434679[15] && - !_theResult____h434679[14] && - !_theResult____h434679[13] && - !_theResult____h434679[12] && - !_theResult____h434679[11] && - !_theResult____h434679[10] && - !_theResult____h434679[9] && - !_theResult____h434679[8] && - !_theResult____h434679[7] && - !_theResult____h434679[6] && - !_theResult____h434679[5] && - !_theResult____h434679[4] && - !_theResult____h434679[3] && - !_theResult____h434679[2] && - !_theResult____h434679[1] && - !_theResult____h434679[0] || + assign _theResult___fst_exp__h442862 = + (!_theResult____h434682[56] && !_theResult____h434682[55] && + !_theResult____h434682[54] && + !_theResult____h434682[53] && + !_theResult____h434682[52] && + !_theResult____h434682[51] && + !_theResult____h434682[50] && + !_theResult____h434682[49] && + !_theResult____h434682[48] && + !_theResult____h434682[47] && + !_theResult____h434682[46] && + !_theResult____h434682[45] && + !_theResult____h434682[44] && + !_theResult____h434682[43] && + !_theResult____h434682[42] && + !_theResult____h434682[41] && + !_theResult____h434682[40] && + !_theResult____h434682[39] && + !_theResult____h434682[38] && + !_theResult____h434682[37] && + !_theResult____h434682[36] && + !_theResult____h434682[35] && + !_theResult____h434682[34] && + !_theResult____h434682[33] && + !_theResult____h434682[32] && + !_theResult____h434682[31] && + !_theResult____h434682[30] && + !_theResult____h434682[29] && + !_theResult____h434682[28] && + !_theResult____h434682[27] && + !_theResult____h434682[26] && + !_theResult____h434682[25] && + !_theResult____h434682[24] && + !_theResult____h434682[23] && + !_theResult____h434682[22] && + !_theResult____h434682[21] && + !_theResult____h434682[20] && + !_theResult____h434682[19] && + !_theResult____h434682[18] && + !_theResult____h434682[17] && + !_theResult____h434682[16] && + !_theResult____h434682[15] && + !_theResult____h434682[14] && + !_theResult____h434682[13] && + !_theResult____h434682[12] && + !_theResult____h434682[11] && + !_theResult____h434682[10] && + !_theResult____h434682[9] && + !_theResult____h434682[8] && + !_theResult____h434682[7] && + !_theResult____h434682[6] && + !_theResult____h434682[5] && + !_theResult____h434682[4] && + !_theResult____h434682[3] && + !_theResult____h434682[2] && + !_theResult____h434682[1] && + !_theResult____h434682[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ? 8'd0 : - _theResult___fst_exp__h442853 ; - assign _theResult___fst_exp__h442862 = - (!_theResult____h434679[56] && _theResult____h434679[55]) ? + _theResult___fst_exp__h442856 ; + assign _theResult___fst_exp__h442865 = + (!_theResult____h434682[56] && _theResult____h434682[55]) ? 8'd1 : - _theResult___fst_exp__h442859 ; - assign _theResult___fst_exp__h443385 = - (_theResult___fst_exp__h442788 == 8'd255) ? - _theResult___fst_exp__h442788 : - _theResult___fst_exp__h443382 ; - assign _theResult___fst_exp__h451435 = + _theResult___fst_exp__h442862 ; + assign _theResult___fst_exp__h443388 = + (_theResult___fst_exp__h442791 == 8'd255) ? + _theResult___fst_exp__h442791 : + _theResult___fst_exp__h443385 ; + assign _theResult___fst_exp__h451438 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h451441 = + assign _theResult___fst_exp__h451444 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ? 8'd0 : - _theResult___fst_exp__h451435 ; - assign _theResult___fst_exp__h451444 = + _theResult___fst_exp__h451438 ; + assign _theResult___fst_exp__h451447 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h451441 : - 8'd129 ; - assign _theResult___fst_exp__h451967 = - (_theResult___fst_exp__h451444 == 8'd255) ? _theResult___fst_exp__h451444 : - _theResult___fst_exp__h451964 ; - assign _theResult___fst_exp__h460554 = - _theResult____h452316[56] ? + 8'd129 ; + assign _theResult___fst_exp__h451970 = + (_theResult___fst_exp__h451447 == 8'd255) ? + _theResult___fst_exp__h451447 : + _theResult___fst_exp__h451967 ; + assign _theResult___fst_exp__h460557 = + _theResult____h452319[56] ? 8'd2 : - _theResult___fst_exp__h460628 ; - assign _theResult___fst_exp__h460619 = + _theResult___fst_exp__h460631 ; + assign _theResult___fst_exp__h460622 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ; - assign _theResult___fst_exp__h460625 = - (!_theResult____h452316[56] && !_theResult____h452316[55] && - !_theResult____h452316[54] && - !_theResult____h452316[53] && - !_theResult____h452316[52] && - !_theResult____h452316[51] && - !_theResult____h452316[50] && - !_theResult____h452316[49] && - !_theResult____h452316[48] && - !_theResult____h452316[47] && - !_theResult____h452316[46] && - !_theResult____h452316[45] && - !_theResult____h452316[44] && - !_theResult____h452316[43] && - !_theResult____h452316[42] && - !_theResult____h452316[41] && - !_theResult____h452316[40] && - !_theResult____h452316[39] && - !_theResult____h452316[38] && - !_theResult____h452316[37] && - !_theResult____h452316[36] && - !_theResult____h452316[35] && - !_theResult____h452316[34] && - !_theResult____h452316[33] && - !_theResult____h452316[32] && - !_theResult____h452316[31] && - !_theResult____h452316[30] && - !_theResult____h452316[29] && - !_theResult____h452316[28] && - !_theResult____h452316[27] && - !_theResult____h452316[26] && - !_theResult____h452316[25] && - !_theResult____h452316[24] && - !_theResult____h452316[23] && - !_theResult____h452316[22] && - !_theResult____h452316[21] && - !_theResult____h452316[20] && - !_theResult____h452316[19] && - !_theResult____h452316[18] && - !_theResult____h452316[17] && - !_theResult____h452316[16] && - !_theResult____h452316[15] && - !_theResult____h452316[14] && - !_theResult____h452316[13] && - !_theResult____h452316[12] && - !_theResult____h452316[11] && - !_theResult____h452316[10] && - !_theResult____h452316[9] && - !_theResult____h452316[8] && - !_theResult____h452316[7] && - !_theResult____h452316[6] && - !_theResult____h452316[5] && - !_theResult____h452316[4] && - !_theResult____h452316[3] && - !_theResult____h452316[2] && - !_theResult____h452316[1] && - !_theResult____h452316[0] || + assign _theResult___fst_exp__h460628 = + (!_theResult____h452319[56] && !_theResult____h452319[55] && + !_theResult____h452319[54] && + !_theResult____h452319[53] && + !_theResult____h452319[52] && + !_theResult____h452319[51] && + !_theResult____h452319[50] && + !_theResult____h452319[49] && + !_theResult____h452319[48] && + !_theResult____h452319[47] && + !_theResult____h452319[46] && + !_theResult____h452319[45] && + !_theResult____h452319[44] && + !_theResult____h452319[43] && + !_theResult____h452319[42] && + !_theResult____h452319[41] && + !_theResult____h452319[40] && + !_theResult____h452319[39] && + !_theResult____h452319[38] && + !_theResult____h452319[37] && + !_theResult____h452319[36] && + !_theResult____h452319[35] && + !_theResult____h452319[34] && + !_theResult____h452319[33] && + !_theResult____h452319[32] && + !_theResult____h452319[31] && + !_theResult____h452319[30] && + !_theResult____h452319[29] && + !_theResult____h452319[28] && + !_theResult____h452319[27] && + !_theResult____h452319[26] && + !_theResult____h452319[25] && + !_theResult____h452319[24] && + !_theResult____h452319[23] && + !_theResult____h452319[22] && + !_theResult____h452319[21] && + !_theResult____h452319[20] && + !_theResult____h452319[19] && + !_theResult____h452319[18] && + !_theResult____h452319[17] && + !_theResult____h452319[16] && + !_theResult____h452319[15] && + !_theResult____h452319[14] && + !_theResult____h452319[13] && + !_theResult____h452319[12] && + !_theResult____h452319[11] && + !_theResult____h452319[10] && + !_theResult____h452319[9] && + !_theResult____h452319[8] && + !_theResult____h452319[7] && + !_theResult____h452319[6] && + !_theResult____h452319[5] && + !_theResult____h452319[4] && + !_theResult____h452319[3] && + !_theResult____h452319[2] && + !_theResult____h452319[1] && + !_theResult____h452319[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ? 8'd0 : - _theResult___fst_exp__h460619 ; - assign _theResult___fst_exp__h460628 = - (!_theResult____h452316[56] && _theResult____h452316[55]) ? + _theResult___fst_exp__h460622 ; + assign _theResult___fst_exp__h460631 = + (!_theResult____h452319[56] && _theResult____h452319[55]) ? 8'd1 : - _theResult___fst_exp__h460625 ; - assign _theResult___fst_exp__h461151 = - (_theResult___fst_exp__h460554 == 8'd255) ? - _theResult___fst_exp__h460554 : - _theResult___fst_exp__h461148 ; - assign _theResult___fst_exp__h469191 = + _theResult___fst_exp__h460628 ; + assign _theResult___fst_exp__h461154 = + (_theResult___fst_exp__h460557 == 8'd255) ? + _theResult___fst_exp__h460557 : + _theResult___fst_exp__h461151 ; + assign _theResult___fst_exp__h469194 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ; - assign _theResult___fst_exp__h469230 = + assign _theResult___fst_exp__h469233 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ; - assign _theResult___fst_exp__h469236 = + assign _theResult___fst_exp__h469239 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ? 8'd0 : - _theResult___fst_exp__h469230 ; - assign _theResult___fst_exp__h469239 = + _theResult___fst_exp__h469233 ; + assign _theResult___fst_exp__h469242 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h469236 : - _theResult___fst_exp__h469191 ; - assign _theResult___fst_exp__h469787 = - (_theResult___fst_exp__h469239 == 8'd255) ? _theResult___fst_exp__h469239 : - _theResult___fst_exp__h469784 ; - assign _theResult___fst_exp__h469796 = + _theResult___fst_exp__h469194 ; + assign _theResult___fst_exp__h469790 = + (_theResult___fst_exp__h469242 == 8'd255) ? + _theResult___fst_exp__h469242 : + _theResult___fst_exp__h469787 ; + assign _theResult___fst_exp__h469799 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_exp__h451970 : - _theResult___fst_exp__h434661) : + _theResult___snd_fst_exp__h451973 : + _theResult___fst_exp__h434664) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_exp__h469790 : - _theResult___fst_exp__h434661) ; - assign _theResult___fst_exp__h469799 = + _theResult___snd_fst_exp__h469793 : + _theResult___fst_exp__h434664) ; + assign _theResult___fst_exp__h469802 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h469796 ; - assign _theResult___fst_exp__h483599 = + _theResult___fst_exp__h469799 ; + assign _theResult___fst_exp__h483603 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ; - assign _theResult___fst_exp__h498663 = + assign _theResult___fst_exp__h498667 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h498669 = + assign _theResult___fst_exp__h498673 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8577) ? 11'd0 : - _theResult___fst_exp__h498663 ; - assign _theResult___fst_exp__h498672 = + _theResult___fst_exp__h498667 ; + assign _theResult___fst_exp__h498676 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h498669 : + _theResult___fst_exp__h498673 : 11'd897 ; - assign _theResult___fst_exp__h499427 = + assign _theResult___fst_exp__h499431 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 : + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 ; - assign _theResult___fst_exp__h499430 = - (_theResult___fst_exp__h498672 == 11'd2047) ? - _theResult___fst_exp__h498672 : - _theResult___fst_exp__h499427 ; - assign _theResult___fst_exp__h508249 = - _theResult____h500013[56] ? + assign _theResult___fst_exp__h499434 = + (_theResult___fst_exp__h498676 == 11'd2047) ? + _theResult___fst_exp__h498676 : + _theResult___fst_exp__h499431 ; + assign _theResult___fst_exp__h508253 = + _theResult____h500017[56] ? 11'd2 : - _theResult___fst_exp__h508323 ; - assign _theResult___fst_exp__h508314 = + _theResult___fst_exp__h508327 ; + assign _theResult___fst_exp__h508318 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 } ; - assign _theResult___fst_exp__h508320 = - (!_theResult____h500013[56] && !_theResult____h500013[55] && - !_theResult____h500013[54] && - !_theResult____h500013[53] && - !_theResult____h500013[52] && - !_theResult____h500013[51] && - !_theResult____h500013[50] && - !_theResult____h500013[49] && - !_theResult____h500013[48] && - !_theResult____h500013[47] && - !_theResult____h500013[46] && - !_theResult____h500013[45] && - !_theResult____h500013[44] && - !_theResult____h500013[43] && - !_theResult____h500013[42] && - !_theResult____h500013[41] && - !_theResult____h500013[40] && - !_theResult____h500013[39] && - !_theResult____h500013[38] && - !_theResult____h500013[37] && - !_theResult____h500013[36] && - !_theResult____h500013[35] && - !_theResult____h500013[34] && - !_theResult____h500013[33] && - !_theResult____h500013[32] && - !_theResult____h500013[31] && - !_theResult____h500013[30] && - !_theResult____h500013[29] && - !_theResult____h500013[28] && - !_theResult____h500013[27] && - !_theResult____h500013[26] && - !_theResult____h500013[25] && - !_theResult____h500013[24] && - !_theResult____h500013[23] && - !_theResult____h500013[22] && - !_theResult____h500013[21] && - !_theResult____h500013[20] && - !_theResult____h500013[19] && - !_theResult____h500013[18] && - !_theResult____h500013[17] && - !_theResult____h500013[16] && - !_theResult____h500013[15] && - !_theResult____h500013[14] && - !_theResult____h500013[13] && - !_theResult____h500013[12] && - !_theResult____h500013[11] && - !_theResult____h500013[10] && - !_theResult____h500013[9] && - !_theResult____h500013[8] && - !_theResult____h500013[7] && - !_theResult____h500013[6] && - !_theResult____h500013[5] && - !_theResult____h500013[4] && - !_theResult____h500013[3] && - !_theResult____h500013[2] && - !_theResult____h500013[1] && - !_theResult____h500013[0] || + assign _theResult___fst_exp__h508324 = + (!_theResult____h500017[56] && !_theResult____h500017[55] && + !_theResult____h500017[54] && + !_theResult____h500017[53] && + !_theResult____h500017[52] && + !_theResult____h500017[51] && + !_theResult____h500017[50] && + !_theResult____h500017[49] && + !_theResult____h500017[48] && + !_theResult____h500017[47] && + !_theResult____h500017[46] && + !_theResult____h500017[45] && + !_theResult____h500017[44] && + !_theResult____h500017[43] && + !_theResult____h500017[42] && + !_theResult____h500017[41] && + !_theResult____h500017[40] && + !_theResult____h500017[39] && + !_theResult____h500017[38] && + !_theResult____h500017[37] && + !_theResult____h500017[36] && + !_theResult____h500017[35] && + !_theResult____h500017[34] && + !_theResult____h500017[33] && + !_theResult____h500017[32] && + !_theResult____h500017[31] && + !_theResult____h500017[30] && + !_theResult____h500017[29] && + !_theResult____h500017[28] && + !_theResult____h500017[27] && + !_theResult____h500017[26] && + !_theResult____h500017[25] && + !_theResult____h500017[24] && + !_theResult____h500017[23] && + !_theResult____h500017[22] && + !_theResult____h500017[21] && + !_theResult____h500017[20] && + !_theResult____h500017[19] && + !_theResult____h500017[18] && + !_theResult____h500017[17] && + !_theResult____h500017[16] && + !_theResult____h500017[15] && + !_theResult____h500017[14] && + !_theResult____h500017[13] && + !_theResult____h500017[12] && + !_theResult____h500017[11] && + !_theResult____h500017[10] && + !_theResult____h500017[9] && + !_theResult____h500017[8] && + !_theResult____h500017[7] && + !_theResult____h500017[6] && + !_theResult____h500017[5] && + !_theResult____h500017[4] && + !_theResult____h500017[3] && + !_theResult____h500017[2] && + !_theResult____h500017[1] && + !_theResult____h500017[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8889) ? 11'd0 : - _theResult___fst_exp__h508314 ; - assign _theResult___fst_exp__h508323 = - (!_theResult____h500013[56] && _theResult____h500013[55]) ? + _theResult___fst_exp__h508318 ; + assign _theResult___fst_exp__h508327 = + (!_theResult____h500017[56] && _theResult____h500017[55]) ? 11'd1 : - _theResult___fst_exp__h508320 ; - assign _theResult___fst_exp__h509078 = + _theResult___fst_exp__h508324 ; + assign _theResult___fst_exp__h509082 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 : + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 ; - assign _theResult___fst_exp__h509081 = - (_theResult___fst_exp__h508249 == 11'd2047) ? - _theResult___fst_exp__h508249 : - _theResult___fst_exp__h509078 ; - assign _theResult___fst_exp__h517034 = + assign _theResult___fst_exp__h509085 = + (_theResult___fst_exp__h508253 == 11'd2047) ? + _theResult___fst_exp__h508253 : + _theResult___fst_exp__h509082 ; + assign _theResult___fst_exp__h517038 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ; - assign _theResult___fst_exp__h517073 = + assign _theResult___fst_exp__h517077 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 } ; - assign _theResult___fst_exp__h517079 = + assign _theResult___fst_exp__h517083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8939) ? 11'd0 : - _theResult___fst_exp__h517073 ; - assign _theResult___fst_exp__h517082 = + _theResult___fst_exp__h517077 ; + assign _theResult___fst_exp__h517086 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___fst_exp__h517079 : - _theResult___fst_exp__h517034 ; - assign _theResult___fst_exp__h517862 = + _theResult___fst_exp__h517083 : + _theResult___fst_exp__h517038 ; + assign _theResult___fst_exp__h517866 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 : + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 ; - assign _theResult___fst_exp__h517865 = - (_theResult___fst_exp__h517082 == 11'd2047) ? - _theResult___fst_exp__h517082 : - _theResult___fst_exp__h517862 ; - assign _theResult___fst_exp__h517874 = + assign _theResult___fst_exp__h517869 = + (_theResult___fst_exp__h517086 == 11'd2047) ? + _theResult___fst_exp__h517086 : + _theResult___fst_exp__h517866 ; + assign _theResult___fst_exp__h517878 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_exp__h499433 : - _theResult___fst_exp__h483599) : + _theResult___snd_fst_exp__h499437 : + _theResult___fst_exp__h483603) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_exp__h517868 : - _theResult___fst_exp__h483599) ; - assign _theResult___fst_exp__h517877 = + _theResult___snd_fst_exp__h517872 : + _theResult___fst_exp__h483603) ; + assign _theResult___fst_exp__h517881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h517874 ; - assign _theResult___fst_exp__h522400 = + _theResult___fst_exp__h517878 ; + assign _theResult___fst_exp__h522404 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_exp__h537464 = + assign _theResult___fst_exp__h537468 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h537470 = + assign _theResult___fst_exp__h537474 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10065) ? 11'd0 : - _theResult___fst_exp__h537464 ; - assign _theResult___fst_exp__h537473 = + _theResult___fst_exp__h537468 ; + assign _theResult___fst_exp__h537477 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h537470 : + _theResult___fst_exp__h537474 : 11'd897 ; - assign _theResult___fst_exp__h538228 = + assign _theResult___fst_exp__h538232 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 : + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 ; - assign _theResult___fst_exp__h538231 = - (_theResult___fst_exp__h537473 == 11'd2047) ? - _theResult___fst_exp__h537473 : - _theResult___fst_exp__h538228 ; - assign _theResult___fst_exp__h547050 = - _theResult____h538814[56] ? + assign _theResult___fst_exp__h538235 = + (_theResult___fst_exp__h537477 == 11'd2047) ? + _theResult___fst_exp__h537477 : + _theResult___fst_exp__h538232 ; + assign _theResult___fst_exp__h547054 = + _theResult____h538818[56] ? 11'd2 : - _theResult___fst_exp__h547124 ; - assign _theResult___fst_exp__h547115 = + _theResult___fst_exp__h547128 ; + assign _theResult___fst_exp__h547119 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 } ; - assign _theResult___fst_exp__h547121 = - (!_theResult____h538814[56] && !_theResult____h538814[55] && - !_theResult____h538814[54] && - !_theResult____h538814[53] && - !_theResult____h538814[52] && - !_theResult____h538814[51] && - !_theResult____h538814[50] && - !_theResult____h538814[49] && - !_theResult____h538814[48] && - !_theResult____h538814[47] && - !_theResult____h538814[46] && - !_theResult____h538814[45] && - !_theResult____h538814[44] && - !_theResult____h538814[43] && - !_theResult____h538814[42] && - !_theResult____h538814[41] && - !_theResult____h538814[40] && - !_theResult____h538814[39] && - !_theResult____h538814[38] && - !_theResult____h538814[37] && - !_theResult____h538814[36] && - !_theResult____h538814[35] && - !_theResult____h538814[34] && - !_theResult____h538814[33] && - !_theResult____h538814[32] && - !_theResult____h538814[31] && - !_theResult____h538814[30] && - !_theResult____h538814[29] && - !_theResult____h538814[28] && - !_theResult____h538814[27] && - !_theResult____h538814[26] && - !_theResult____h538814[25] && - !_theResult____h538814[24] && - !_theResult____h538814[23] && - !_theResult____h538814[22] && - !_theResult____h538814[21] && - !_theResult____h538814[20] && - !_theResult____h538814[19] && - !_theResult____h538814[18] && - !_theResult____h538814[17] && - !_theResult____h538814[16] && - !_theResult____h538814[15] && - !_theResult____h538814[14] && - !_theResult____h538814[13] && - !_theResult____h538814[12] && - !_theResult____h538814[11] && - !_theResult____h538814[10] && - !_theResult____h538814[9] && - !_theResult____h538814[8] && - !_theResult____h538814[7] && - !_theResult____h538814[6] && - !_theResult____h538814[5] && - !_theResult____h538814[4] && - !_theResult____h538814[3] && - !_theResult____h538814[2] && - !_theResult____h538814[1] && - !_theResult____h538814[0] || + assign _theResult___fst_exp__h547125 = + (!_theResult____h538818[56] && !_theResult____h538818[55] && + !_theResult____h538818[54] && + !_theResult____h538818[53] && + !_theResult____h538818[52] && + !_theResult____h538818[51] && + !_theResult____h538818[50] && + !_theResult____h538818[49] && + !_theResult____h538818[48] && + !_theResult____h538818[47] && + !_theResult____h538818[46] && + !_theResult____h538818[45] && + !_theResult____h538818[44] && + !_theResult____h538818[43] && + !_theResult____h538818[42] && + !_theResult____h538818[41] && + !_theResult____h538818[40] && + !_theResult____h538818[39] && + !_theResult____h538818[38] && + !_theResult____h538818[37] && + !_theResult____h538818[36] && + !_theResult____h538818[35] && + !_theResult____h538818[34] && + !_theResult____h538818[33] && + !_theResult____h538818[32] && + !_theResult____h538818[31] && + !_theResult____h538818[30] && + !_theResult____h538818[29] && + !_theResult____h538818[28] && + !_theResult____h538818[27] && + !_theResult____h538818[26] && + !_theResult____h538818[25] && + !_theResult____h538818[24] && + !_theResult____h538818[23] && + !_theResult____h538818[22] && + !_theResult____h538818[21] && + !_theResult____h538818[20] && + !_theResult____h538818[19] && + !_theResult____h538818[18] && + !_theResult____h538818[17] && + !_theResult____h538818[16] && + !_theResult____h538818[15] && + !_theResult____h538818[14] && + !_theResult____h538818[13] && + !_theResult____h538818[12] && + !_theResult____h538818[11] && + !_theResult____h538818[10] && + !_theResult____h538818[9] && + !_theResult____h538818[8] && + !_theResult____h538818[7] && + !_theResult____h538818[6] && + !_theResult____h538818[5] && + !_theResult____h538818[4] && + !_theResult____h538818[3] && + !_theResult____h538818[2] && + !_theResult____h538818[1] && + !_theResult____h538818[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10362) ? 11'd0 : - _theResult___fst_exp__h547115 ; - assign _theResult___fst_exp__h547124 = - (!_theResult____h538814[56] && _theResult____h538814[55]) ? + _theResult___fst_exp__h547119 ; + assign _theResult___fst_exp__h547128 = + (!_theResult____h538818[56] && _theResult____h538818[55]) ? 11'd1 : - _theResult___fst_exp__h547121 ; - assign _theResult___fst_exp__h547879 = + _theResult___fst_exp__h547125 ; + assign _theResult___fst_exp__h547883 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 : + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 ; - assign _theResult___fst_exp__h547882 = - (_theResult___fst_exp__h547050 == 11'd2047) ? - _theResult___fst_exp__h547050 : - _theResult___fst_exp__h547879 ; - assign _theResult___fst_exp__h555835 = + assign _theResult___fst_exp__h547886 = + (_theResult___fst_exp__h547054 == 11'd2047) ? + _theResult___fst_exp__h547054 : + _theResult___fst_exp__h547883 ; + assign _theResult___fst_exp__h555839 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ; - assign _theResult___fst_exp__h555874 = + assign _theResult___fst_exp__h555878 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 } ; - assign _theResult___fst_exp__h555880 = + assign _theResult___fst_exp__h555884 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10412) ? 11'd0 : - _theResult___fst_exp__h555874 ; - assign _theResult___fst_exp__h555883 = + _theResult___fst_exp__h555878 ; + assign _theResult___fst_exp__h555887 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___fst_exp__h555880 : - _theResult___fst_exp__h555835 ; - assign _theResult___fst_exp__h556663 = + _theResult___fst_exp__h555884 : + _theResult___fst_exp__h555839 ; + assign _theResult___fst_exp__h556667 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 : + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 ; - assign _theResult___fst_exp__h556666 = - (_theResult___fst_exp__h555883 == 11'd2047) ? - _theResult___fst_exp__h555883 : - _theResult___fst_exp__h556663 ; - assign _theResult___fst_exp__h556675 = + assign _theResult___fst_exp__h556670 = + (_theResult___fst_exp__h555887 == 11'd2047) ? + _theResult___fst_exp__h555887 : + _theResult___fst_exp__h556667 ; + assign _theResult___fst_exp__h556679 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_exp__h538234 : - _theResult___fst_exp__h522400) : + _theResult___snd_fst_exp__h538238 : + _theResult___fst_exp__h522404) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_exp__h556669 : - _theResult___fst_exp__h522400) ; - assign _theResult___fst_exp__h556678 = + _theResult___snd_fst_exp__h556673 : + _theResult___fst_exp__h522404) ; + assign _theResult___fst_exp__h556682 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h556675 ; - assign _theResult___fst_exp__h561601 = + _theResult___fst_exp__h556679 ; + assign _theResult___fst_exp__h561605 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_exp__h576665 = + assign _theResult___fst_exp__h576669 = 11'd897 - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h576671 = + assign _theResult___fst_exp__h576675 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9302) ? 11'd0 : - _theResult___fst_exp__h576665 ; - assign _theResult___fst_exp__h576674 = + _theResult___fst_exp__h576669 ; + assign _theResult___fst_exp__h576678 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h576671 : + _theResult___fst_exp__h576675 : 11'd897 ; - assign _theResult___fst_exp__h577429 = + assign _theResult___fst_exp__h577433 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 : + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 ; - assign _theResult___fst_exp__h577432 = - (_theResult___fst_exp__h576674 == 11'd2047) ? - _theResult___fst_exp__h576674 : - _theResult___fst_exp__h577429 ; - assign _theResult___fst_exp__h586251 = - _theResult____h578015[56] ? + assign _theResult___fst_exp__h577436 = + (_theResult___fst_exp__h576678 == 11'd2047) ? + _theResult___fst_exp__h576678 : + _theResult___fst_exp__h577433 ; + assign _theResult___fst_exp__h586255 = + _theResult____h578019[56] ? 11'd2 : - _theResult___fst_exp__h586325 ; - assign _theResult___fst_exp__h586316 = + _theResult___fst_exp__h586329 ; + assign _theResult___fst_exp__h586320 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 } ; - assign _theResult___fst_exp__h586322 = - (!_theResult____h578015[56] && !_theResult____h578015[55] && - !_theResult____h578015[54] && - !_theResult____h578015[53] && - !_theResult____h578015[52] && - !_theResult____h578015[51] && - !_theResult____h578015[50] && - !_theResult____h578015[49] && - !_theResult____h578015[48] && - !_theResult____h578015[47] && - !_theResult____h578015[46] && - !_theResult____h578015[45] && - !_theResult____h578015[44] && - !_theResult____h578015[43] && - !_theResult____h578015[42] && - !_theResult____h578015[41] && - !_theResult____h578015[40] && - !_theResult____h578015[39] && - !_theResult____h578015[38] && - !_theResult____h578015[37] && - !_theResult____h578015[36] && - !_theResult____h578015[35] && - !_theResult____h578015[34] && - !_theResult____h578015[33] && - !_theResult____h578015[32] && - !_theResult____h578015[31] && - !_theResult____h578015[30] && - !_theResult____h578015[29] && - !_theResult____h578015[28] && - !_theResult____h578015[27] && - !_theResult____h578015[26] && - !_theResult____h578015[25] && - !_theResult____h578015[24] && - !_theResult____h578015[23] && - !_theResult____h578015[22] && - !_theResult____h578015[21] && - !_theResult____h578015[20] && - !_theResult____h578015[19] && - !_theResult____h578015[18] && - !_theResult____h578015[17] && - !_theResult____h578015[16] && - !_theResult____h578015[15] && - !_theResult____h578015[14] && - !_theResult____h578015[13] && - !_theResult____h578015[12] && - !_theResult____h578015[11] && - !_theResult____h578015[10] && - !_theResult____h578015[9] && - !_theResult____h578015[8] && - !_theResult____h578015[7] && - !_theResult____h578015[6] && - !_theResult____h578015[5] && - !_theResult____h578015[4] && - !_theResult____h578015[3] && - !_theResult____h578015[2] && - !_theResult____h578015[1] && - !_theResult____h578015[0] || + assign _theResult___fst_exp__h586326 = + (!_theResult____h578019[56] && !_theResult____h578019[55] && + !_theResult____h578019[54] && + !_theResult____h578019[53] && + !_theResult____h578019[52] && + !_theResult____h578019[51] && + !_theResult____h578019[50] && + !_theResult____h578019[49] && + !_theResult____h578019[48] && + !_theResult____h578019[47] && + !_theResult____h578019[46] && + !_theResult____h578019[45] && + !_theResult____h578019[44] && + !_theResult____h578019[43] && + !_theResult____h578019[42] && + !_theResult____h578019[41] && + !_theResult____h578019[40] && + !_theResult____h578019[39] && + !_theResult____h578019[38] && + !_theResult____h578019[37] && + !_theResult____h578019[36] && + !_theResult____h578019[35] && + !_theResult____h578019[34] && + !_theResult____h578019[33] && + !_theResult____h578019[32] && + !_theResult____h578019[31] && + !_theResult____h578019[30] && + !_theResult____h578019[29] && + !_theResult____h578019[28] && + !_theResult____h578019[27] && + !_theResult____h578019[26] && + !_theResult____h578019[25] && + !_theResult____h578019[24] && + !_theResult____h578019[23] && + !_theResult____h578019[22] && + !_theResult____h578019[21] && + !_theResult____h578019[20] && + !_theResult____h578019[19] && + !_theResult____h578019[18] && + !_theResult____h578019[17] && + !_theResult____h578019[16] && + !_theResult____h578019[15] && + !_theResult____h578019[14] && + !_theResult____h578019[13] && + !_theResult____h578019[12] && + !_theResult____h578019[11] && + !_theResult____h578019[10] && + !_theResult____h578019[9] && + !_theResult____h578019[8] && + !_theResult____h578019[7] && + !_theResult____h578019[6] && + !_theResult____h578019[5] && + !_theResult____h578019[4] && + !_theResult____h578019[3] && + !_theResult____h578019[2] && + !_theResult____h578019[1] && + !_theResult____h578019[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9599) ? 11'd0 : - _theResult___fst_exp__h586316 ; - assign _theResult___fst_exp__h586325 = - (!_theResult____h578015[56] && _theResult____h578015[55]) ? + _theResult___fst_exp__h586320 ; + assign _theResult___fst_exp__h586329 = + (!_theResult____h578019[56] && _theResult____h578019[55]) ? 11'd1 : - _theResult___fst_exp__h586322 ; - assign _theResult___fst_exp__h587080 = + _theResult___fst_exp__h586326 ; + assign _theResult___fst_exp__h587084 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 : + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 ; - assign _theResult___fst_exp__h587083 = - (_theResult___fst_exp__h586251 == 11'd2047) ? - _theResult___fst_exp__h586251 : - _theResult___fst_exp__h587080 ; - assign _theResult___fst_exp__h595036 = + assign _theResult___fst_exp__h587087 = + (_theResult___fst_exp__h586255 == 11'd2047) ? + _theResult___fst_exp__h586255 : + _theResult___fst_exp__h587084 ; + assign _theResult___fst_exp__h595040 = (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ; - assign _theResult___fst_exp__h595075 = + assign _theResult___fst_exp__h595079 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] - { 5'd0, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 } ; - assign _theResult___fst_exp__h595081 = + assign _theResult___fst_exp__h595085 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9649) ? 11'd0 : - _theResult___fst_exp__h595075 ; - assign _theResult___fst_exp__h595084 = + _theResult___fst_exp__h595079 ; + assign _theResult___fst_exp__h595088 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___fst_exp__h595081 : - _theResult___fst_exp__h595036 ; - assign _theResult___fst_exp__h595864 = + _theResult___fst_exp__h595085 : + _theResult___fst_exp__h595040 ; + assign _theResult___fst_exp__h595868 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 : + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 ; - assign _theResult___fst_exp__h595867 = - (_theResult___fst_exp__h595084 == 11'd2047) ? - _theResult___fst_exp__h595084 : - _theResult___fst_exp__h595864 ; - assign _theResult___fst_exp__h595876 = + assign _theResult___fst_exp__h595871 = + (_theResult___fst_exp__h595088 == 11'd2047) ? + _theResult___fst_exp__h595088 : + _theResult___fst_exp__h595868 ; + assign _theResult___fst_exp__h595880 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_exp__h577435 : - _theResult___fst_exp__h561601) : + _theResult___snd_fst_exp__h577439 : + _theResult___fst_exp__h561605) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_exp__h595870 : - _theResult___fst_exp__h561601) ; - assign _theResult___fst_exp__h595879 = + _theResult___snd_fst_exp__h595874 : + _theResult___fst_exp__h561605) ; + assign _theResult___fst_exp__h595883 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 11'd0 : - _theResult___fst_exp__h595876 ; - assign _theResult___fst_sfd__h352008 = - (_theResult___fst_exp__h351410 == 8'd255) ? - sfdin__h351404[56:34] : - _theResult___fst_sfd__h352005 ; - assign _theResult___fst_sfd__h360590 = - (_theResult___fst_exp__h360066 == 8'd255) ? - _theResult___snd__h360017[56:34] : - _theResult___fst_sfd__h360587 ; - assign _theResult___fst_sfd__h369774 = - (_theResult___fst_exp__h369176 == 8'd255) ? - sfdin__h369170[56:34] : - _theResult___fst_sfd__h369771 ; - assign _theResult___fst_sfd__h378410 = - (_theResult___fst_exp__h377861 == 8'd255) ? - _theResult___snd__h377807[56:34] : - _theResult___fst_sfd__h378407 ; - assign _theResult___fst_sfd__h378419 = + _theResult___fst_exp__h595880 ; + assign _theResult___fst_sfd__h352011 = + (_theResult___fst_exp__h351413 == 8'd255) ? + sfdin__h351407[56:34] : + _theResult___fst_sfd__h352008 ; + assign _theResult___fst_sfd__h360593 = + (_theResult___fst_exp__h360069 == 8'd255) ? + _theResult___snd__h360020[56:34] : + _theResult___fst_sfd__h360590 ; + assign _theResult___fst_sfd__h369777 = + (_theResult___fst_exp__h369179 == 8'd255) ? + sfdin__h369173[56:34] : + _theResult___fst_sfd__h369774 ; + assign _theResult___fst_sfd__h378413 = + (_theResult___fst_exp__h377864 == 8'd255) ? + _theResult___snd__h377810[56:34] : + _theResult___fst_sfd__h378410 ; + assign _theResult___fst_sfd__h378422 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ? - _theResult___snd_fst_sfd__h360593 : - _theResult___fst_sfd__h343282) : + _theResult___snd_fst_sfd__h360596 : + _theResult___fst_sfd__h343285) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ? - _theResult___snd_fst_sfd__h378413 : - _theResult___fst_sfd__h343282) ; - assign _theResult___fst_sfd__h378425 = + _theResult___snd_fst_sfd__h378416 : + _theResult___fst_sfd__h343285) ; + assign _theResult___fst_sfd__h378428 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -25718,33 +25718,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h378419 ; - assign _theResult___fst_sfd__h397698 = - (_theResult___fst_exp__h397100 == 8'd255) ? - sfdin__h397094[56:34] : - _theResult___fst_sfd__h397695 ; - assign _theResult___fst_sfd__h406280 = - (_theResult___fst_exp__h405756 == 8'd255) ? - _theResult___snd__h405707[56:34] : - _theResult___fst_sfd__h406277 ; - assign _theResult___fst_sfd__h415464 = - (_theResult___fst_exp__h414866 == 8'd255) ? - sfdin__h414860[56:34] : - _theResult___fst_sfd__h415461 ; - assign _theResult___fst_sfd__h424100 = - (_theResult___fst_exp__h423551 == 8'd255) ? - _theResult___snd__h423497[56:34] : - _theResult___fst_sfd__h424097 ; - assign _theResult___fst_sfd__h424109 = + _theResult___fst_sfd__h378422 ; + assign _theResult___fst_sfd__h397701 = + (_theResult___fst_exp__h397103 == 8'd255) ? + sfdin__h397097[56:34] : + _theResult___fst_sfd__h397698 ; + assign _theResult___fst_sfd__h406283 = + (_theResult___fst_exp__h405759 == 8'd255) ? + _theResult___snd__h405710[56:34] : + _theResult___fst_sfd__h406280 ; + assign _theResult___fst_sfd__h415467 = + (_theResult___fst_exp__h414869 == 8'd255) ? + sfdin__h414863[56:34] : + _theResult___fst_sfd__h415464 ; + assign _theResult___fst_sfd__h424103 = + (_theResult___fst_exp__h423554 == 8'd255) ? + _theResult___snd__h423500[56:34] : + _theResult___fst_sfd__h424100 ; + assign _theResult___fst_sfd__h424112 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ? - _theResult___snd_fst_sfd__h406283 : - _theResult___fst_sfd__h388974) : + _theResult___snd_fst_sfd__h406286 : + _theResult___fst_sfd__h388977) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ? - _theResult___snd_fst_sfd__h424103 : - _theResult___fst_sfd__h388974) ; - assign _theResult___fst_sfd__h424115 = + _theResult___snd_fst_sfd__h424106 : + _theResult___fst_sfd__h388977) ; + assign _theResult___fst_sfd__h424118 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -25752,33 +25752,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h424109 ; - assign _theResult___fst_sfd__h443386 = - (_theResult___fst_exp__h442788 == 8'd255) ? - sfdin__h442782[56:34] : - _theResult___fst_sfd__h443383 ; - assign _theResult___fst_sfd__h451968 = - (_theResult___fst_exp__h451444 == 8'd255) ? - _theResult___snd__h451395[56:34] : - _theResult___fst_sfd__h451965 ; - assign _theResult___fst_sfd__h461152 = - (_theResult___fst_exp__h460554 == 8'd255) ? - sfdin__h460548[56:34] : - _theResult___fst_sfd__h461149 ; - assign _theResult___fst_sfd__h469788 = - (_theResult___fst_exp__h469239 == 8'd255) ? - _theResult___snd__h469185[56:34] : - _theResult___fst_sfd__h469785 ; - assign _theResult___fst_sfd__h469797 = + _theResult___fst_sfd__h424112 ; + assign _theResult___fst_sfd__h443389 = + (_theResult___fst_exp__h442791 == 8'd255) ? + sfdin__h442785[56:34] : + _theResult___fst_sfd__h443386 ; + assign _theResult___fst_sfd__h451971 = + (_theResult___fst_exp__h451447 == 8'd255) ? + _theResult___snd__h451398[56:34] : + _theResult___fst_sfd__h451968 ; + assign _theResult___fst_sfd__h461155 = + (_theResult___fst_exp__h460557 == 8'd255) ? + sfdin__h460551[56:34] : + _theResult___fst_sfd__h461152 ; + assign _theResult___fst_sfd__h469791 = + (_theResult___fst_exp__h469242 == 8'd255) ? + _theResult___snd__h469188[56:34] : + _theResult___fst_sfd__h469788 ; + assign _theResult___fst_sfd__h469800 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ? - _theResult___snd_fst_sfd__h451971 : - _theResult___fst_sfd__h434662) : + _theResult___snd_fst_sfd__h451974 : + _theResult___fst_sfd__h434665) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ? - _theResult___snd_fst_sfd__h469791 : - _theResult___fst_sfd__h434662) ; - assign _theResult___fst_sfd__h469803 = + _theResult___snd_fst_sfd__h469794 : + _theResult___fst_sfd__h434665) ; + assign _theResult___fst_sfd__h469806 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -25786,1320 +25786,1320 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h469797 ; - assign _theResult___fst_sfd__h483600 = + _theResult___fst_sfd__h469800 ; + assign _theResult___fst_sfd__h483604 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_sfd__h499428 = + assign _theResult___fst_sfd__h499432 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 : + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 ; - assign _theResult___fst_sfd__h499431 = - (_theResult___fst_exp__h498672 == 11'd2047) ? - _theResult___snd__h498623[56:5] : - _theResult___fst_sfd__h499428 ; - assign _theResult___fst_sfd__h509079 = + assign _theResult___fst_sfd__h499435 = + (_theResult___fst_exp__h498676 == 11'd2047) ? + _theResult___snd__h498627[56:5] : + _theResult___fst_sfd__h499432 ; + assign _theResult___fst_sfd__h509083 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 : + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 ; - assign _theResult___fst_sfd__h509082 = - (_theResult___fst_exp__h508249 == 11'd2047) ? - sfdin__h508243[56:5] : - _theResult___fst_sfd__h509079 ; - assign _theResult___fst_sfd__h517863 = + assign _theResult___fst_sfd__h509086 = + (_theResult___fst_exp__h508253 == 11'd2047) ? + sfdin__h508247[56:5] : + _theResult___fst_sfd__h509083 ; + assign _theResult___fst_sfd__h517867 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 : + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 ; - assign _theResult___fst_sfd__h517866 = - (_theResult___fst_exp__h517082 == 11'd2047) ? - _theResult___snd__h517028[56:5] : - _theResult___fst_sfd__h517863 ; - assign _theResult___fst_sfd__h517875 = + assign _theResult___fst_sfd__h517870 = + (_theResult___fst_exp__h517086 == 11'd2047) ? + _theResult___snd__h517032[56:5] : + _theResult___fst_sfd__h517867 ; + assign _theResult___fst_sfd__h517879 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8502 ? - _theResult___snd_fst_sfd__h499434 : - _theResult___fst_sfd__h483600) : + _theResult___snd_fst_sfd__h499438 : + _theResult___fst_sfd__h483604) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8639 ? - _theResult___snd_fst_sfd__h517869 : - _theResult___fst_sfd__h483600) ; - assign _theResult___fst_sfd__h517881 = + _theResult___snd_fst_sfd__h517873 : + _theResult___fst_sfd__h483604) ; + assign _theResult___fst_sfd__h517885 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h517875 ; - assign _theResult___fst_sfd__h522401 = + _theResult___fst_sfd__h517879 ; + assign _theResult___fst_sfd__h522405 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_sfd__h538229 = + assign _theResult___fst_sfd__h538233 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 : + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 ; - assign _theResult___fst_sfd__h538232 = - (_theResult___fst_exp__h537473 == 11'd2047) ? - _theResult___snd__h537424[56:5] : - _theResult___fst_sfd__h538229 ; - assign _theResult___fst_sfd__h547880 = + assign _theResult___fst_sfd__h538236 = + (_theResult___fst_exp__h537477 == 11'd2047) ? + _theResult___snd__h537428[56:5] : + _theResult___fst_sfd__h538233 ; + assign _theResult___fst_sfd__h547884 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 ; - assign _theResult___fst_sfd__h547883 = - (_theResult___fst_exp__h547050 == 11'd2047) ? - sfdin__h547044[56:5] : - _theResult___fst_sfd__h547880 ; - assign _theResult___fst_sfd__h556664 = + assign _theResult___fst_sfd__h547887 = + (_theResult___fst_exp__h547054 == 11'd2047) ? + sfdin__h547048[56:5] : + _theResult___fst_sfd__h547884 ; + assign _theResult___fst_sfd__h556668 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 : + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 ; - assign _theResult___fst_sfd__h556667 = - (_theResult___fst_exp__h555883 == 11'd2047) ? - _theResult___snd__h555829[56:5] : - _theResult___fst_sfd__h556664 ; - assign _theResult___fst_sfd__h556676 = + assign _theResult___fst_sfd__h556671 = + (_theResult___fst_exp__h555887 == 11'd2047) ? + _theResult___snd__h555833[56:5] : + _theResult___fst_sfd__h556668 ; + assign _theResult___fst_sfd__h556680 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9990 ? - _theResult___snd_fst_sfd__h538235 : - _theResult___fst_sfd__h522401) : + _theResult___snd_fst_sfd__h538239 : + _theResult___fst_sfd__h522405) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10112 ? - _theResult___snd_fst_sfd__h556670 : - _theResult___fst_sfd__h522401) ; - assign _theResult___fst_sfd__h556682 = + _theResult___snd_fst_sfd__h556674 : + _theResult___fst_sfd__h522405) ; + assign _theResult___fst_sfd__h556686 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h556676 ; - assign _theResult___fst_sfd__h561602 = + _theResult___fst_sfd__h556680 ; + assign _theResult___fst_sfd__h561606 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_sfd__h577430 = + assign _theResult___fst_sfd__h577434 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 : + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 ; - assign _theResult___fst_sfd__h577433 = - (_theResult___fst_exp__h576674 == 11'd2047) ? - _theResult___snd__h576625[56:5] : - _theResult___fst_sfd__h577430 ; - assign _theResult___fst_sfd__h587081 = + assign _theResult___fst_sfd__h577437 = + (_theResult___fst_exp__h576678 == 11'd2047) ? + _theResult___snd__h576629[56:5] : + _theResult___fst_sfd__h577434 ; + assign _theResult___fst_sfd__h587085 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 ; - assign _theResult___fst_sfd__h587084 = - (_theResult___fst_exp__h586251 == 11'd2047) ? - sfdin__h586245[56:5] : - _theResult___fst_sfd__h587081 ; - assign _theResult___fst_sfd__h595865 = + assign _theResult___fst_sfd__h587088 = + (_theResult___fst_exp__h586255 == 11'd2047) ? + sfdin__h586249[56:5] : + _theResult___fst_sfd__h587085 ; + assign _theResult___fst_sfd__h595869 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 : + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 ; - assign _theResult___fst_sfd__h595868 = - (_theResult___fst_exp__h595084 == 11'd2047) ? - _theResult___snd__h595030[56:5] : - _theResult___fst_sfd__h595865 ; - assign _theResult___fst_sfd__h595877 = + assign _theResult___fst_sfd__h595872 = + (_theResult___fst_exp__h595088 == 11'd2047) ? + _theResult___snd__h595034[56:5] : + _theResult___fst_sfd__h595869 ; + assign _theResult___fst_sfd__h595881 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9227 ? - _theResult___snd_fst_sfd__h577436 : - _theResult___fst_sfd__h561602) : + _theResult___snd_fst_sfd__h577440 : + _theResult___fst_sfd__h561606) : (SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9349 ? - _theResult___snd_fst_sfd__h595871 : - _theResult___fst_sfd__h561602) ; - assign _theResult___fst_sfd__h595883 = + _theResult___snd_fst_sfd__h595875 : + _theResult___fst_sfd__h561606) ; + assign _theResult___fst_sfd__h595887 = ((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 || coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) && coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h595877 ; - assign _theResult___sfd__h351927 = - sfd__h351502[24] ? - ((_theResult___fst_exp__h351410 == 8'd254) ? + _theResult___fst_sfd__h595881 ; + assign _theResult___sfd__h351930 = + sfd__h351505[24] ? + ((_theResult___fst_exp__h351413 == 8'd254) ? 23'd0 : - sfd__h351502[23:1]) : - sfd__h351502[22:0] ; - assign _theResult___sfd__h360509 = - sfd__h360084[24] ? - ((_theResult___fst_exp__h360066 == 8'd254) ? + sfd__h351505[23:1]) : + sfd__h351505[22:0] ; + assign _theResult___sfd__h360512 = + sfd__h360087[24] ? + ((_theResult___fst_exp__h360069 == 8'd254) ? 23'd0 : - sfd__h360084[23:1]) : - sfd__h360084[22:0] ; - assign _theResult___sfd__h369693 = - sfd__h369268[24] ? - ((_theResult___fst_exp__h369176 == 8'd254) ? + sfd__h360087[23:1]) : + sfd__h360087[22:0] ; + assign _theResult___sfd__h369696 = + sfd__h369271[24] ? + ((_theResult___fst_exp__h369179 == 8'd254) ? 23'd0 : - sfd__h369268[23:1]) : - sfd__h369268[22:0] ; - assign _theResult___sfd__h378329 = - sfd__h377880[24] ? - ((_theResult___fst_exp__h377861 == 8'd254) ? + sfd__h369271[23:1]) : + sfd__h369271[22:0] ; + assign _theResult___sfd__h378332 = + sfd__h377883[24] ? + ((_theResult___fst_exp__h377864 == 8'd254) ? 23'd0 : - sfd__h377880[23:1]) : - sfd__h377880[22:0] ; - assign _theResult___sfd__h378431 = + sfd__h377883[23:1]) : + sfd__h377883[22:0] ; + assign _theResult___sfd__h378434 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h335644 : - _theResult___fst_sfd__h378425 ; - assign _theResult___sfd__h397617 = - sfd__h397192[24] ? - ((_theResult___fst_exp__h397100 == 8'd254) ? + _theResult___snd_fst_sfd__h335647 : + _theResult___fst_sfd__h378428 ; + assign _theResult___sfd__h397620 = + sfd__h397195[24] ? + ((_theResult___fst_exp__h397103 == 8'd254) ? 23'd0 : - sfd__h397192[23:1]) : - sfd__h397192[22:0] ; - assign _theResult___sfd__h406199 = - sfd__h405774[24] ? - ((_theResult___fst_exp__h405756 == 8'd254) ? + sfd__h397195[23:1]) : + sfd__h397195[22:0] ; + assign _theResult___sfd__h406202 = + sfd__h405777[24] ? + ((_theResult___fst_exp__h405759 == 8'd254) ? 23'd0 : - sfd__h405774[23:1]) : - sfd__h405774[22:0] ; - assign _theResult___sfd__h415383 = - sfd__h414958[24] ? - ((_theResult___fst_exp__h414866 == 8'd254) ? + sfd__h405777[23:1]) : + sfd__h405777[22:0] ; + assign _theResult___sfd__h415386 = + sfd__h414961[24] ? + ((_theResult___fst_exp__h414869 == 8'd254) ? 23'd0 : - sfd__h414958[23:1]) : - sfd__h414958[22:0] ; - assign _theResult___sfd__h424019 = - sfd__h423570[24] ? - ((_theResult___fst_exp__h423551 == 8'd254) ? + sfd__h414961[23:1]) : + sfd__h414961[22:0] ; + assign _theResult___sfd__h424022 = + sfd__h423573[24] ? + ((_theResult___fst_exp__h423554 == 8'd254) ? 23'd0 : - sfd__h423570[23:1]) : - sfd__h423570[22:0] ; - assign _theResult___sfd__h424121 = + sfd__h423573[23:1]) : + sfd__h423573[22:0] ; + assign _theResult___sfd__h424124 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h381339 : - _theResult___fst_sfd__h424115 ; - assign _theResult___sfd__h443305 = - sfd__h442880[24] ? - ((_theResult___fst_exp__h442788 == 8'd254) ? + _theResult___snd_fst_sfd__h381342 : + _theResult___fst_sfd__h424118 ; + assign _theResult___sfd__h443308 = + sfd__h442883[24] ? + ((_theResult___fst_exp__h442791 == 8'd254) ? 23'd0 : - sfd__h442880[23:1]) : - sfd__h442880[22:0] ; - assign _theResult___sfd__h451887 = - sfd__h451462[24] ? - ((_theResult___fst_exp__h451444 == 8'd254) ? + sfd__h442883[23:1]) : + sfd__h442883[22:0] ; + assign _theResult___sfd__h451890 = + sfd__h451465[24] ? + ((_theResult___fst_exp__h451447 == 8'd254) ? 23'd0 : - sfd__h451462[23:1]) : - sfd__h451462[22:0] ; - assign _theResult___sfd__h461071 = - sfd__h460646[24] ? - ((_theResult___fst_exp__h460554 == 8'd254) ? + sfd__h451465[23:1]) : + sfd__h451465[22:0] ; + assign _theResult___sfd__h461074 = + sfd__h460649[24] ? + ((_theResult___fst_exp__h460557 == 8'd254) ? 23'd0 : - sfd__h460646[23:1]) : - sfd__h460646[22:0] ; - assign _theResult___sfd__h469707 = - sfd__h469258[24] ? - ((_theResult___fst_exp__h469239 == 8'd254) ? + sfd__h460649[23:1]) : + sfd__h460649[22:0] ; + assign _theResult___sfd__h469710 = + sfd__h469261[24] ? + ((_theResult___fst_exp__h469242 == 8'd254) ? 23'd0 : - sfd__h469258[23:1]) : - sfd__h469258[22:0] ; - assign _theResult___sfd__h469809 = + sfd__h469261[23:1]) : + sfd__h469261[22:0] ; + assign _theResult___sfd__h469812 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h427027 : - _theResult___fst_sfd__h469803 ; - assign _theResult___sfd__h499328 = - sfd__h498690[53] ? - ((_theResult___fst_exp__h498672 == 11'd2046) ? + _theResult___snd_fst_sfd__h427030 : + _theResult___fst_sfd__h469806 ; + assign _theResult___sfd__h499332 = + sfd__h498694[53] ? + ((_theResult___fst_exp__h498676 == 11'd2046) ? 52'd0 : - sfd__h498690[52:1]) : - sfd__h498690[51:0] ; - assign _theResult___sfd__h508979 = - sfd__h508341[53] ? - ((_theResult___fst_exp__h508249 == 11'd2046) ? + sfd__h498694[52:1]) : + sfd__h498694[51:0] ; + assign _theResult___sfd__h508983 = + sfd__h508345[53] ? + ((_theResult___fst_exp__h508253 == 11'd2046) ? 52'd0 : - sfd__h508341[52:1]) : - sfd__h508341[51:0] ; - assign _theResult___sfd__h517763 = - sfd__h517101[53] ? - ((_theResult___fst_exp__h517082 == 11'd2046) ? + sfd__h508345[52:1]) : + sfd__h508345[51:0] ; + assign _theResult___sfd__h517767 = + sfd__h517105[53] ? + ((_theResult___fst_exp__h517086 == 11'd2046) ? 52'd0 : - sfd__h517101[52:1]) : - sfd__h517101[51:0] ; - assign _theResult___sfd__h538129 = - sfd__h537491[53] ? - ((_theResult___fst_exp__h537473 == 11'd2046) ? + sfd__h517105[52:1]) : + sfd__h517105[51:0] ; + assign _theResult___sfd__h538133 = + sfd__h537495[53] ? + ((_theResult___fst_exp__h537477 == 11'd2046) ? 52'd0 : - sfd__h537491[52:1]) : - sfd__h537491[51:0] ; - assign _theResult___sfd__h547780 = - sfd__h547142[53] ? - ((_theResult___fst_exp__h547050 == 11'd2046) ? + sfd__h537495[52:1]) : + sfd__h537495[51:0] ; + assign _theResult___sfd__h547784 = + sfd__h547146[53] ? + ((_theResult___fst_exp__h547054 == 11'd2046) ? 52'd0 : - sfd__h547142[52:1]) : - sfd__h547142[51:0] ; - assign _theResult___sfd__h556564 = - sfd__h555902[53] ? - ((_theResult___fst_exp__h555883 == 11'd2046) ? + sfd__h547146[52:1]) : + sfd__h547146[51:0] ; + assign _theResult___sfd__h556568 = + sfd__h555906[53] ? + ((_theResult___fst_exp__h555887 == 11'd2046) ? 52'd0 : - sfd__h555902[52:1]) : - sfd__h555902[51:0] ; - assign _theResult___sfd__h577330 = - sfd__h576692[53] ? - ((_theResult___fst_exp__h576674 == 11'd2046) ? + sfd__h555906[52:1]) : + sfd__h555906[51:0] ; + assign _theResult___sfd__h577334 = + sfd__h576696[53] ? + ((_theResult___fst_exp__h576678 == 11'd2046) ? 52'd0 : - sfd__h576692[52:1]) : - sfd__h576692[51:0] ; - assign _theResult___sfd__h586981 = - sfd__h586343[53] ? - ((_theResult___fst_exp__h586251 == 11'd2046) ? + sfd__h576696[52:1]) : + sfd__h576696[51:0] ; + assign _theResult___sfd__h586985 = + sfd__h586347[53] ? + ((_theResult___fst_exp__h586255 == 11'd2046) ? 52'd0 : - sfd__h586343[52:1]) : - sfd__h586343[51:0] ; - assign _theResult___sfd__h595765 = - sfd__h595103[53] ? - ((_theResult___fst_exp__h595084 == 11'd2046) ? + sfd__h586347[52:1]) : + sfd__h586347[51:0] ; + assign _theResult___sfd__h595769 = + sfd__h595107[53] ? + ((_theResult___fst_exp__h595088 == 11'd2046) ? 52'd0 : - sfd__h595103[52:1]) : - sfd__h595103[51:0] ; - assign _theResult___snd__h351421 = { _theResult____h343299[55:0], 1'd0 } ; - assign _theResult___snd__h351432 = - (!_theResult____h343299[56] && _theResult____h343299[55]) ? - _theResult___snd__h351434 : - _theResult___snd__h351444 ; - assign _theResult___snd__h351434 = { _theResult____h343299[54:0], 2'd0 } ; - assign _theResult___snd__h351444 = - (!_theResult____h343299[56] && !_theResult____h343299[55] && - !_theResult____h343299[54] && - !_theResult____h343299[53] && - !_theResult____h343299[52] && - !_theResult____h343299[51] && - !_theResult____h343299[50] && - !_theResult____h343299[49] && - !_theResult____h343299[48] && - !_theResult____h343299[47] && - !_theResult____h343299[46] && - !_theResult____h343299[45] && - !_theResult____h343299[44] && - !_theResult____h343299[43] && - !_theResult____h343299[42] && - !_theResult____h343299[41] && - !_theResult____h343299[40] && - !_theResult____h343299[39] && - !_theResult____h343299[38] && - !_theResult____h343299[37] && - !_theResult____h343299[36] && - !_theResult____h343299[35] && - !_theResult____h343299[34] && - !_theResult____h343299[33] && - !_theResult____h343299[32] && - !_theResult____h343299[31] && - !_theResult____h343299[30] && - !_theResult____h343299[29] && - !_theResult____h343299[28] && - !_theResult____h343299[27] && - !_theResult____h343299[26] && - !_theResult____h343299[25] && - !_theResult____h343299[24] && - !_theResult____h343299[23] && - !_theResult____h343299[22] && - !_theResult____h343299[21] && - !_theResult____h343299[20] && - !_theResult____h343299[19] && - !_theResult____h343299[18] && - !_theResult____h343299[17] && - !_theResult____h343299[16] && - !_theResult____h343299[15] && - !_theResult____h343299[14] && - !_theResult____h343299[13] && - !_theResult____h343299[12] && - !_theResult____h343299[11] && - !_theResult____h343299[10] && - !_theResult____h343299[9] && - !_theResult____h343299[8] && - !_theResult____h343299[7] && - !_theResult____h343299[6] && - !_theResult____h343299[5] && - !_theResult____h343299[4] && - !_theResult____h343299[3] && - !_theResult____h343299[2] && - !_theResult____h343299[1] && - !_theResult____h343299[0]) ? - _theResult____h343299 : - _theResult___snd__h351450 ; - assign _theResult___snd__h351450 = + sfd__h595107[52:1]) : + sfd__h595107[51:0] ; + assign _theResult___snd__h351424 = { _theResult____h343302[55:0], 1'd0 } ; + assign _theResult___snd__h351435 = + (!_theResult____h343302[56] && _theResult____h343302[55]) ? + _theResult___snd__h351437 : + _theResult___snd__h351447 ; + assign _theResult___snd__h351437 = { _theResult____h343302[54:0], 2'd0 } ; + assign _theResult___snd__h351447 = + (!_theResult____h343302[56] && !_theResult____h343302[55] && + !_theResult____h343302[54] && + !_theResult____h343302[53] && + !_theResult____h343302[52] && + !_theResult____h343302[51] && + !_theResult____h343302[50] && + !_theResult____h343302[49] && + !_theResult____h343302[48] && + !_theResult____h343302[47] && + !_theResult____h343302[46] && + !_theResult____h343302[45] && + !_theResult____h343302[44] && + !_theResult____h343302[43] && + !_theResult____h343302[42] && + !_theResult____h343302[41] && + !_theResult____h343302[40] && + !_theResult____h343302[39] && + !_theResult____h343302[38] && + !_theResult____h343302[37] && + !_theResult____h343302[36] && + !_theResult____h343302[35] && + !_theResult____h343302[34] && + !_theResult____h343302[33] && + !_theResult____h343302[32] && + !_theResult____h343302[31] && + !_theResult____h343302[30] && + !_theResult____h343302[29] && + !_theResult____h343302[28] && + !_theResult____h343302[27] && + !_theResult____h343302[26] && + !_theResult____h343302[25] && + !_theResult____h343302[24] && + !_theResult____h343302[23] && + !_theResult____h343302[22] && + !_theResult____h343302[21] && + !_theResult____h343302[20] && + !_theResult____h343302[19] && + !_theResult____h343302[18] && + !_theResult____h343302[17] && + !_theResult____h343302[16] && + !_theResult____h343302[15] && + !_theResult____h343302[14] && + !_theResult____h343302[13] && + !_theResult____h343302[12] && + !_theResult____h343302[11] && + !_theResult____h343302[10] && + !_theResult____h343302[9] && + !_theResult____h343302[8] && + !_theResult____h343302[7] && + !_theResult____h343302[6] && + !_theResult____h343302[5] && + !_theResult____h343302[4] && + !_theResult____h343302[3] && + !_theResult____h343302[2] && + !_theResult____h343302[1] && + !_theResult____h343302[0]) ? + _theResult____h343302 : + _theResult___snd__h351453 ; + assign _theResult___snd__h351453 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0], 2'd0 } ; - assign _theResult___snd__h351473 = - _theResult____h343299 << + assign _theResult___snd__h351476 = + _theResult____h343302 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ; - assign _theResult___snd__h360017 = + assign _theResult___snd__h360020 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h360026 : - _theResult___snd__h360019 ; - assign _theResult___snd__h360019 = + _theResult___snd__h360029 : + _theResult___snd__h360022 ; + assign _theResult___snd__h360022 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h360026 = + assign _theResult___snd__h360029 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335694 : - _theResult___snd__h360032 ; - assign _theResult___snd__h360032 = + sfd__h335697 : + _theResult___snd__h360035 ; + assign _theResult___snd__h360035 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0], 2'd0 } ; - assign _theResult___snd__h360055 = - sfd__h335694 << + assign _theResult___snd__h360058 = + sfd__h335697 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ; - assign _theResult___snd__h369187 = { _theResult____h360938[55:0], 1'd0 } ; - assign _theResult___snd__h369198 = - (!_theResult____h360938[56] && _theResult____h360938[55]) ? - _theResult___snd__h369200 : - _theResult___snd__h369210 ; - assign _theResult___snd__h369200 = { _theResult____h360938[54:0], 2'd0 } ; - assign _theResult___snd__h369210 = - (!_theResult____h360938[56] && !_theResult____h360938[55] && - !_theResult____h360938[54] && - !_theResult____h360938[53] && - !_theResult____h360938[52] && - !_theResult____h360938[51] && - !_theResult____h360938[50] && - !_theResult____h360938[49] && - !_theResult____h360938[48] && - !_theResult____h360938[47] && - !_theResult____h360938[46] && - !_theResult____h360938[45] && - !_theResult____h360938[44] && - !_theResult____h360938[43] && - !_theResult____h360938[42] && - !_theResult____h360938[41] && - !_theResult____h360938[40] && - !_theResult____h360938[39] && - !_theResult____h360938[38] && - !_theResult____h360938[37] && - !_theResult____h360938[36] && - !_theResult____h360938[35] && - !_theResult____h360938[34] && - !_theResult____h360938[33] && - !_theResult____h360938[32] && - !_theResult____h360938[31] && - !_theResult____h360938[30] && - !_theResult____h360938[29] && - !_theResult____h360938[28] && - !_theResult____h360938[27] && - !_theResult____h360938[26] && - !_theResult____h360938[25] && - !_theResult____h360938[24] && - !_theResult____h360938[23] && - !_theResult____h360938[22] && - !_theResult____h360938[21] && - !_theResult____h360938[20] && - !_theResult____h360938[19] && - !_theResult____h360938[18] && - !_theResult____h360938[17] && - !_theResult____h360938[16] && - !_theResult____h360938[15] && - !_theResult____h360938[14] && - !_theResult____h360938[13] && - !_theResult____h360938[12] && - !_theResult____h360938[11] && - !_theResult____h360938[10] && - !_theResult____h360938[9] && - !_theResult____h360938[8] && - !_theResult____h360938[7] && - !_theResult____h360938[6] && - !_theResult____h360938[5] && - !_theResult____h360938[4] && - !_theResult____h360938[3] && - !_theResult____h360938[2] && - !_theResult____h360938[1] && - !_theResult____h360938[0]) ? - _theResult____h360938 : - _theResult___snd__h369216 ; - assign _theResult___snd__h369216 = + assign _theResult___snd__h369190 = { _theResult____h360941[55:0], 1'd0 } ; + assign _theResult___snd__h369201 = + (!_theResult____h360941[56] && _theResult____h360941[55]) ? + _theResult___snd__h369203 : + _theResult___snd__h369213 ; + assign _theResult___snd__h369203 = { _theResult____h360941[54:0], 2'd0 } ; + assign _theResult___snd__h369213 = + (!_theResult____h360941[56] && !_theResult____h360941[55] && + !_theResult____h360941[54] && + !_theResult____h360941[53] && + !_theResult____h360941[52] && + !_theResult____h360941[51] && + !_theResult____h360941[50] && + !_theResult____h360941[49] && + !_theResult____h360941[48] && + !_theResult____h360941[47] && + !_theResult____h360941[46] && + !_theResult____h360941[45] && + !_theResult____h360941[44] && + !_theResult____h360941[43] && + !_theResult____h360941[42] && + !_theResult____h360941[41] && + !_theResult____h360941[40] && + !_theResult____h360941[39] && + !_theResult____h360941[38] && + !_theResult____h360941[37] && + !_theResult____h360941[36] && + !_theResult____h360941[35] && + !_theResult____h360941[34] && + !_theResult____h360941[33] && + !_theResult____h360941[32] && + !_theResult____h360941[31] && + !_theResult____h360941[30] && + !_theResult____h360941[29] && + !_theResult____h360941[28] && + !_theResult____h360941[27] && + !_theResult____h360941[26] && + !_theResult____h360941[25] && + !_theResult____h360941[24] && + !_theResult____h360941[23] && + !_theResult____h360941[22] && + !_theResult____h360941[21] && + !_theResult____h360941[20] && + !_theResult____h360941[19] && + !_theResult____h360941[18] && + !_theResult____h360941[17] && + !_theResult____h360941[16] && + !_theResult____h360941[15] && + !_theResult____h360941[14] && + !_theResult____h360941[13] && + !_theResult____h360941[12] && + !_theResult____h360941[11] && + !_theResult____h360941[10] && + !_theResult____h360941[9] && + !_theResult____h360941[8] && + !_theResult____h360941[7] && + !_theResult____h360941[6] && + !_theResult____h360941[5] && + !_theResult____h360941[4] && + !_theResult____h360941[3] && + !_theResult____h360941[2] && + !_theResult____h360941[1] && + !_theResult____h360941[0]) ? + _theResult____h360941 : + _theResult___snd__h369219 ; + assign _theResult___snd__h369219 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h369239 = - _theResult____h360938 << + assign _theResult___snd__h369242 = + _theResult____h360941 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ; - assign _theResult___snd__h377807 = + assign _theResult___snd__h377810 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h377821 : - _theResult___snd__h360019 ; - assign _theResult___snd__h377821 = + _theResult___snd__h377824 : + _theResult___snd__h360022 ; + assign _theResult___snd__h377824 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ? - sfd__h335694 : - _theResult___snd__h377827 ; - assign _theResult___snd__h377827 = + sfd__h335697 : + _theResult___snd__h377830 ; + assign _theResult___snd__h377830 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0], 2'd0 } ; - assign _theResult___snd__h377845 = - sfd__h335694 << + assign _theResult___snd__h377848 = + sfd__h335697 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ; - assign _theResult___snd__h397111 = { _theResult____h388991[55:0], 1'd0 } ; - assign _theResult___snd__h397122 = - (!_theResult____h388991[56] && _theResult____h388991[55]) ? - _theResult___snd__h397124 : - _theResult___snd__h397134 ; - assign _theResult___snd__h397124 = { _theResult____h388991[54:0], 2'd0 } ; - assign _theResult___snd__h397134 = - (!_theResult____h388991[56] && !_theResult____h388991[55] && - !_theResult____h388991[54] && - !_theResult____h388991[53] && - !_theResult____h388991[52] && - !_theResult____h388991[51] && - !_theResult____h388991[50] && - !_theResult____h388991[49] && - !_theResult____h388991[48] && - !_theResult____h388991[47] && - !_theResult____h388991[46] && - !_theResult____h388991[45] && - !_theResult____h388991[44] && - !_theResult____h388991[43] && - !_theResult____h388991[42] && - !_theResult____h388991[41] && - !_theResult____h388991[40] && - !_theResult____h388991[39] && - !_theResult____h388991[38] && - !_theResult____h388991[37] && - !_theResult____h388991[36] && - !_theResult____h388991[35] && - !_theResult____h388991[34] && - !_theResult____h388991[33] && - !_theResult____h388991[32] && - !_theResult____h388991[31] && - !_theResult____h388991[30] && - !_theResult____h388991[29] && - !_theResult____h388991[28] && - !_theResult____h388991[27] && - !_theResult____h388991[26] && - !_theResult____h388991[25] && - !_theResult____h388991[24] && - !_theResult____h388991[23] && - !_theResult____h388991[22] && - !_theResult____h388991[21] && - !_theResult____h388991[20] && - !_theResult____h388991[19] && - !_theResult____h388991[18] && - !_theResult____h388991[17] && - !_theResult____h388991[16] && - !_theResult____h388991[15] && - !_theResult____h388991[14] && - !_theResult____h388991[13] && - !_theResult____h388991[12] && - !_theResult____h388991[11] && - !_theResult____h388991[10] && - !_theResult____h388991[9] && - !_theResult____h388991[8] && - !_theResult____h388991[7] && - !_theResult____h388991[6] && - !_theResult____h388991[5] && - !_theResult____h388991[4] && - !_theResult____h388991[3] && - !_theResult____h388991[2] && - !_theResult____h388991[1] && - !_theResult____h388991[0]) ? - _theResult____h388991 : - _theResult___snd__h397140 ; - assign _theResult___snd__h397140 = + assign _theResult___snd__h397114 = { _theResult____h388994[55:0], 1'd0 } ; + assign _theResult___snd__h397125 = + (!_theResult____h388994[56] && _theResult____h388994[55]) ? + _theResult___snd__h397127 : + _theResult___snd__h397137 ; + assign _theResult___snd__h397127 = { _theResult____h388994[54:0], 2'd0 } ; + assign _theResult___snd__h397137 = + (!_theResult____h388994[56] && !_theResult____h388994[55] && + !_theResult____h388994[54] && + !_theResult____h388994[53] && + !_theResult____h388994[52] && + !_theResult____h388994[51] && + !_theResult____h388994[50] && + !_theResult____h388994[49] && + !_theResult____h388994[48] && + !_theResult____h388994[47] && + !_theResult____h388994[46] && + !_theResult____h388994[45] && + !_theResult____h388994[44] && + !_theResult____h388994[43] && + !_theResult____h388994[42] && + !_theResult____h388994[41] && + !_theResult____h388994[40] && + !_theResult____h388994[39] && + !_theResult____h388994[38] && + !_theResult____h388994[37] && + !_theResult____h388994[36] && + !_theResult____h388994[35] && + !_theResult____h388994[34] && + !_theResult____h388994[33] && + !_theResult____h388994[32] && + !_theResult____h388994[31] && + !_theResult____h388994[30] && + !_theResult____h388994[29] && + !_theResult____h388994[28] && + !_theResult____h388994[27] && + !_theResult____h388994[26] && + !_theResult____h388994[25] && + !_theResult____h388994[24] && + !_theResult____h388994[23] && + !_theResult____h388994[22] && + !_theResult____h388994[21] && + !_theResult____h388994[20] && + !_theResult____h388994[19] && + !_theResult____h388994[18] && + !_theResult____h388994[17] && + !_theResult____h388994[16] && + !_theResult____h388994[15] && + !_theResult____h388994[14] && + !_theResult____h388994[13] && + !_theResult____h388994[12] && + !_theResult____h388994[11] && + !_theResult____h388994[10] && + !_theResult____h388994[9] && + !_theResult____h388994[8] && + !_theResult____h388994[7] && + !_theResult____h388994[6] && + !_theResult____h388994[5] && + !_theResult____h388994[4] && + !_theResult____h388994[3] && + !_theResult____h388994[2] && + !_theResult____h388994[1] && + !_theResult____h388994[0]) ? + _theResult____h388994 : + _theResult___snd__h397143 ; + assign _theResult___snd__h397143 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0], 2'd0 } ; - assign _theResult___snd__h397163 = - _theResult____h388991 << + assign _theResult___snd__h397166 = + _theResult____h388994 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ; - assign _theResult___snd__h405707 = + assign _theResult___snd__h405710 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h405716 : - _theResult___snd__h405709 ; - assign _theResult___snd__h405709 = + _theResult___snd__h405719 : + _theResult___snd__h405712 ; + assign _theResult___snd__h405712 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h405716 = + assign _theResult___snd__h405719 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381389 : - _theResult___snd__h405722 ; - assign _theResult___snd__h405722 = + sfd__h381392 : + _theResult___snd__h405725 ; + assign _theResult___snd__h405725 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0], 2'd0 } ; - assign _theResult___snd__h405745 = - sfd__h381389 << + assign _theResult___snd__h405748 = + sfd__h381392 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ; - assign _theResult___snd__h414877 = { _theResult____h406628[55:0], 1'd0 } ; - assign _theResult___snd__h414888 = - (!_theResult____h406628[56] && _theResult____h406628[55]) ? - _theResult___snd__h414890 : - _theResult___snd__h414900 ; - assign _theResult___snd__h414890 = { _theResult____h406628[54:0], 2'd0 } ; - assign _theResult___snd__h414900 = - (!_theResult____h406628[56] && !_theResult____h406628[55] && - !_theResult____h406628[54] && - !_theResult____h406628[53] && - !_theResult____h406628[52] && - !_theResult____h406628[51] && - !_theResult____h406628[50] && - !_theResult____h406628[49] && - !_theResult____h406628[48] && - !_theResult____h406628[47] && - !_theResult____h406628[46] && - !_theResult____h406628[45] && - !_theResult____h406628[44] && - !_theResult____h406628[43] && - !_theResult____h406628[42] && - !_theResult____h406628[41] && - !_theResult____h406628[40] && - !_theResult____h406628[39] && - !_theResult____h406628[38] && - !_theResult____h406628[37] && - !_theResult____h406628[36] && - !_theResult____h406628[35] && - !_theResult____h406628[34] && - !_theResult____h406628[33] && - !_theResult____h406628[32] && - !_theResult____h406628[31] && - !_theResult____h406628[30] && - !_theResult____h406628[29] && - !_theResult____h406628[28] && - !_theResult____h406628[27] && - !_theResult____h406628[26] && - !_theResult____h406628[25] && - !_theResult____h406628[24] && - !_theResult____h406628[23] && - !_theResult____h406628[22] && - !_theResult____h406628[21] && - !_theResult____h406628[20] && - !_theResult____h406628[19] && - !_theResult____h406628[18] && - !_theResult____h406628[17] && - !_theResult____h406628[16] && - !_theResult____h406628[15] && - !_theResult____h406628[14] && - !_theResult____h406628[13] && - !_theResult____h406628[12] && - !_theResult____h406628[11] && - !_theResult____h406628[10] && - !_theResult____h406628[9] && - !_theResult____h406628[8] && - !_theResult____h406628[7] && - !_theResult____h406628[6] && - !_theResult____h406628[5] && - !_theResult____h406628[4] && - !_theResult____h406628[3] && - !_theResult____h406628[2] && - !_theResult____h406628[1] && - !_theResult____h406628[0]) ? - _theResult____h406628 : - _theResult___snd__h414906 ; - assign _theResult___snd__h414906 = + assign _theResult___snd__h414880 = { _theResult____h406631[55:0], 1'd0 } ; + assign _theResult___snd__h414891 = + (!_theResult____h406631[56] && _theResult____h406631[55]) ? + _theResult___snd__h414893 : + _theResult___snd__h414903 ; + assign _theResult___snd__h414893 = { _theResult____h406631[54:0], 2'd0 } ; + assign _theResult___snd__h414903 = + (!_theResult____h406631[56] && !_theResult____h406631[55] && + !_theResult____h406631[54] && + !_theResult____h406631[53] && + !_theResult____h406631[52] && + !_theResult____h406631[51] && + !_theResult____h406631[50] && + !_theResult____h406631[49] && + !_theResult____h406631[48] && + !_theResult____h406631[47] && + !_theResult____h406631[46] && + !_theResult____h406631[45] && + !_theResult____h406631[44] && + !_theResult____h406631[43] && + !_theResult____h406631[42] && + !_theResult____h406631[41] && + !_theResult____h406631[40] && + !_theResult____h406631[39] && + !_theResult____h406631[38] && + !_theResult____h406631[37] && + !_theResult____h406631[36] && + !_theResult____h406631[35] && + !_theResult____h406631[34] && + !_theResult____h406631[33] && + !_theResult____h406631[32] && + !_theResult____h406631[31] && + !_theResult____h406631[30] && + !_theResult____h406631[29] && + !_theResult____h406631[28] && + !_theResult____h406631[27] && + !_theResult____h406631[26] && + !_theResult____h406631[25] && + !_theResult____h406631[24] && + !_theResult____h406631[23] && + !_theResult____h406631[22] && + !_theResult____h406631[21] && + !_theResult____h406631[20] && + !_theResult____h406631[19] && + !_theResult____h406631[18] && + !_theResult____h406631[17] && + !_theResult____h406631[16] && + !_theResult____h406631[15] && + !_theResult____h406631[14] && + !_theResult____h406631[13] && + !_theResult____h406631[12] && + !_theResult____h406631[11] && + !_theResult____h406631[10] && + !_theResult____h406631[9] && + !_theResult____h406631[8] && + !_theResult____h406631[7] && + !_theResult____h406631[6] && + !_theResult____h406631[5] && + !_theResult____h406631[4] && + !_theResult____h406631[3] && + !_theResult____h406631[2] && + !_theResult____h406631[1] && + !_theResult____h406631[0]) ? + _theResult____h406631 : + _theResult___snd__h414909 ; + assign _theResult___snd__h414909 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h414929 = - _theResult____h406628 << + assign _theResult___snd__h414932 = + _theResult____h406631 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ; - assign _theResult___snd__h423497 = + assign _theResult___snd__h423500 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h423511 : - _theResult___snd__h405709 ; - assign _theResult___snd__h423511 = + _theResult___snd__h423514 : + _theResult___snd__h405712 ; + assign _theResult___snd__h423514 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ? - sfd__h381389 : - _theResult___snd__h423517 ; - assign _theResult___snd__h423517 = + sfd__h381392 : + _theResult___snd__h423520 ; + assign _theResult___snd__h423520 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0], 2'd0 } ; - assign _theResult___snd__h423535 = - sfd__h381389 << + assign _theResult___snd__h423538 = + sfd__h381392 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ; - assign _theResult___snd__h442799 = { _theResult____h434679[55:0], 1'd0 } ; - assign _theResult___snd__h442810 = - (!_theResult____h434679[56] && _theResult____h434679[55]) ? - _theResult___snd__h442812 : - _theResult___snd__h442822 ; - assign _theResult___snd__h442812 = { _theResult____h434679[54:0], 2'd0 } ; - assign _theResult___snd__h442822 = - (!_theResult____h434679[56] && !_theResult____h434679[55] && - !_theResult____h434679[54] && - !_theResult____h434679[53] && - !_theResult____h434679[52] && - !_theResult____h434679[51] && - !_theResult____h434679[50] && - !_theResult____h434679[49] && - !_theResult____h434679[48] && - !_theResult____h434679[47] && - !_theResult____h434679[46] && - !_theResult____h434679[45] && - !_theResult____h434679[44] && - !_theResult____h434679[43] && - !_theResult____h434679[42] && - !_theResult____h434679[41] && - !_theResult____h434679[40] && - !_theResult____h434679[39] && - !_theResult____h434679[38] && - !_theResult____h434679[37] && - !_theResult____h434679[36] && - !_theResult____h434679[35] && - !_theResult____h434679[34] && - !_theResult____h434679[33] && - !_theResult____h434679[32] && - !_theResult____h434679[31] && - !_theResult____h434679[30] && - !_theResult____h434679[29] && - !_theResult____h434679[28] && - !_theResult____h434679[27] && - !_theResult____h434679[26] && - !_theResult____h434679[25] && - !_theResult____h434679[24] && - !_theResult____h434679[23] && - !_theResult____h434679[22] && - !_theResult____h434679[21] && - !_theResult____h434679[20] && - !_theResult____h434679[19] && - !_theResult____h434679[18] && - !_theResult____h434679[17] && - !_theResult____h434679[16] && - !_theResult____h434679[15] && - !_theResult____h434679[14] && - !_theResult____h434679[13] && - !_theResult____h434679[12] && - !_theResult____h434679[11] && - !_theResult____h434679[10] && - !_theResult____h434679[9] && - !_theResult____h434679[8] && - !_theResult____h434679[7] && - !_theResult____h434679[6] && - !_theResult____h434679[5] && - !_theResult____h434679[4] && - !_theResult____h434679[3] && - !_theResult____h434679[2] && - !_theResult____h434679[1] && - !_theResult____h434679[0]) ? - _theResult____h434679 : - _theResult___snd__h442828 ; - assign _theResult___snd__h442828 = + assign _theResult___snd__h442802 = { _theResult____h434682[55:0], 1'd0 } ; + assign _theResult___snd__h442813 = + (!_theResult____h434682[56] && _theResult____h434682[55]) ? + _theResult___snd__h442815 : + _theResult___snd__h442825 ; + assign _theResult___snd__h442815 = { _theResult____h434682[54:0], 2'd0 } ; + assign _theResult___snd__h442825 = + (!_theResult____h434682[56] && !_theResult____h434682[55] && + !_theResult____h434682[54] && + !_theResult____h434682[53] && + !_theResult____h434682[52] && + !_theResult____h434682[51] && + !_theResult____h434682[50] && + !_theResult____h434682[49] && + !_theResult____h434682[48] && + !_theResult____h434682[47] && + !_theResult____h434682[46] && + !_theResult____h434682[45] && + !_theResult____h434682[44] && + !_theResult____h434682[43] && + !_theResult____h434682[42] && + !_theResult____h434682[41] && + !_theResult____h434682[40] && + !_theResult____h434682[39] && + !_theResult____h434682[38] && + !_theResult____h434682[37] && + !_theResult____h434682[36] && + !_theResult____h434682[35] && + !_theResult____h434682[34] && + !_theResult____h434682[33] && + !_theResult____h434682[32] && + !_theResult____h434682[31] && + !_theResult____h434682[30] && + !_theResult____h434682[29] && + !_theResult____h434682[28] && + !_theResult____h434682[27] && + !_theResult____h434682[26] && + !_theResult____h434682[25] && + !_theResult____h434682[24] && + !_theResult____h434682[23] && + !_theResult____h434682[22] && + !_theResult____h434682[21] && + !_theResult____h434682[20] && + !_theResult____h434682[19] && + !_theResult____h434682[18] && + !_theResult____h434682[17] && + !_theResult____h434682[16] && + !_theResult____h434682[15] && + !_theResult____h434682[14] && + !_theResult____h434682[13] && + !_theResult____h434682[12] && + !_theResult____h434682[11] && + !_theResult____h434682[10] && + !_theResult____h434682[9] && + !_theResult____h434682[8] && + !_theResult____h434682[7] && + !_theResult____h434682[6] && + !_theResult____h434682[5] && + !_theResult____h434682[4] && + !_theResult____h434682[3] && + !_theResult____h434682[2] && + !_theResult____h434682[1] && + !_theResult____h434682[0]) ? + _theResult____h434682 : + _theResult___snd__h442831 ; + assign _theResult___snd__h442831 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0], 2'd0 } ; - assign _theResult___snd__h442851 = - _theResult____h434679 << + assign _theResult___snd__h442854 = + _theResult____h434682 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ; - assign _theResult___snd__h451395 = + assign _theResult___snd__h451398 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h451404 : - _theResult___snd__h451397 ; - assign _theResult___snd__h451397 = + _theResult___snd__h451407 : + _theResult___snd__h451400 ; + assign _theResult___snd__h451400 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h451404 = + assign _theResult___snd__h451407 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427077 : - _theResult___snd__h451410 ; - assign _theResult___snd__h451410 = + sfd__h427080 : + _theResult___snd__h451413 ; + assign _theResult___snd__h451413 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0], 2'd0 } ; - assign _theResult___snd__h451433 = - sfd__h427077 << + assign _theResult___snd__h451436 = + sfd__h427080 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ; - assign _theResult___snd__h460565 = { _theResult____h452316[55:0], 1'd0 } ; - assign _theResult___snd__h460576 = - (!_theResult____h452316[56] && _theResult____h452316[55]) ? - _theResult___snd__h460578 : - _theResult___snd__h460588 ; - assign _theResult___snd__h460578 = { _theResult____h452316[54:0], 2'd0 } ; - assign _theResult___snd__h460588 = - (!_theResult____h452316[56] && !_theResult____h452316[55] && - !_theResult____h452316[54] && - !_theResult____h452316[53] && - !_theResult____h452316[52] && - !_theResult____h452316[51] && - !_theResult____h452316[50] && - !_theResult____h452316[49] && - !_theResult____h452316[48] && - !_theResult____h452316[47] && - !_theResult____h452316[46] && - !_theResult____h452316[45] && - !_theResult____h452316[44] && - !_theResult____h452316[43] && - !_theResult____h452316[42] && - !_theResult____h452316[41] && - !_theResult____h452316[40] && - !_theResult____h452316[39] && - !_theResult____h452316[38] && - !_theResult____h452316[37] && - !_theResult____h452316[36] && - !_theResult____h452316[35] && - !_theResult____h452316[34] && - !_theResult____h452316[33] && - !_theResult____h452316[32] && - !_theResult____h452316[31] && - !_theResult____h452316[30] && - !_theResult____h452316[29] && - !_theResult____h452316[28] && - !_theResult____h452316[27] && - !_theResult____h452316[26] && - !_theResult____h452316[25] && - !_theResult____h452316[24] && - !_theResult____h452316[23] && - !_theResult____h452316[22] && - !_theResult____h452316[21] && - !_theResult____h452316[20] && - !_theResult____h452316[19] && - !_theResult____h452316[18] && - !_theResult____h452316[17] && - !_theResult____h452316[16] && - !_theResult____h452316[15] && - !_theResult____h452316[14] && - !_theResult____h452316[13] && - !_theResult____h452316[12] && - !_theResult____h452316[11] && - !_theResult____h452316[10] && - !_theResult____h452316[9] && - !_theResult____h452316[8] && - !_theResult____h452316[7] && - !_theResult____h452316[6] && - !_theResult____h452316[5] && - !_theResult____h452316[4] && - !_theResult____h452316[3] && - !_theResult____h452316[2] && - !_theResult____h452316[1] && - !_theResult____h452316[0]) ? - _theResult____h452316 : - _theResult___snd__h460594 ; - assign _theResult___snd__h460594 = + assign _theResult___snd__h460568 = { _theResult____h452319[55:0], 1'd0 } ; + assign _theResult___snd__h460579 = + (!_theResult____h452319[56] && _theResult____h452319[55]) ? + _theResult___snd__h460581 : + _theResult___snd__h460591 ; + assign _theResult___snd__h460581 = { _theResult____h452319[54:0], 2'd0 } ; + assign _theResult___snd__h460591 = + (!_theResult____h452319[56] && !_theResult____h452319[55] && + !_theResult____h452319[54] && + !_theResult____h452319[53] && + !_theResult____h452319[52] && + !_theResult____h452319[51] && + !_theResult____h452319[50] && + !_theResult____h452319[49] && + !_theResult____h452319[48] && + !_theResult____h452319[47] && + !_theResult____h452319[46] && + !_theResult____h452319[45] && + !_theResult____h452319[44] && + !_theResult____h452319[43] && + !_theResult____h452319[42] && + !_theResult____h452319[41] && + !_theResult____h452319[40] && + !_theResult____h452319[39] && + !_theResult____h452319[38] && + !_theResult____h452319[37] && + !_theResult____h452319[36] && + !_theResult____h452319[35] && + !_theResult____h452319[34] && + !_theResult____h452319[33] && + !_theResult____h452319[32] && + !_theResult____h452319[31] && + !_theResult____h452319[30] && + !_theResult____h452319[29] && + !_theResult____h452319[28] && + !_theResult____h452319[27] && + !_theResult____h452319[26] && + !_theResult____h452319[25] && + !_theResult____h452319[24] && + !_theResult____h452319[23] && + !_theResult____h452319[22] && + !_theResult____h452319[21] && + !_theResult____h452319[20] && + !_theResult____h452319[19] && + !_theResult____h452319[18] && + !_theResult____h452319[17] && + !_theResult____h452319[16] && + !_theResult____h452319[15] && + !_theResult____h452319[14] && + !_theResult____h452319[13] && + !_theResult____h452319[12] && + !_theResult____h452319[11] && + !_theResult____h452319[10] && + !_theResult____h452319[9] && + !_theResult____h452319[8] && + !_theResult____h452319[7] && + !_theResult____h452319[6] && + !_theResult____h452319[5] && + !_theResult____h452319[4] && + !_theResult____h452319[3] && + !_theResult____h452319[2] && + !_theResult____h452319[1] && + !_theResult____h452319[0]) ? + _theResult____h452319 : + _theResult___snd__h460597 ; + assign _theResult___snd__h460597 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h460617 = - _theResult____h452316 << + assign _theResult___snd__h460620 = + _theResult____h452319 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ; - assign _theResult___snd__h469185 = + assign _theResult___snd__h469188 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h469199 : - _theResult___snd__h451397 ; - assign _theResult___snd__h469199 = + _theResult___snd__h469202 : + _theResult___snd__h451400 ; + assign _theResult___snd__h469202 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ? - sfd__h427077 : - _theResult___snd__h469205 ; - assign _theResult___snd__h469205 = + sfd__h427080 : + _theResult___snd__h469208 ; + assign _theResult___snd__h469208 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0], 2'd0 } ; - assign _theResult___snd__h469223 = - sfd__h427077 << + assign _theResult___snd__h469226 = + sfd__h427080 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ; - assign _theResult___snd__h498623 = + assign _theResult___snd__h498627 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h498632 : - _theResult___snd__h498625 ; - assign _theResult___snd__h498625 = + _theResult___snd__h498636 : + _theResult___snd__h498629 ; + assign _theResult___snd__h498629 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ; - assign _theResult___snd__h498632 = + assign _theResult___snd__h498636 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479671 : - _theResult___snd__h498638 ; - assign _theResult___snd__h498638 = + sfd__h479675 : + _theResult___snd__h498642 ; + assign _theResult___snd__h498642 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h498661 = - sfd__h479671 << + assign _theResult___snd__h498665 = + sfd__h479675 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8575 ; - assign _theResult___snd__h508260 = { _theResult____h500013[55:0], 1'd0 } ; - assign _theResult___snd__h508271 = - (!_theResult____h500013[56] && _theResult____h500013[55]) ? - _theResult___snd__h508273 : - _theResult___snd__h508283 ; - assign _theResult___snd__h508273 = { _theResult____h500013[54:0], 2'd0 } ; - assign _theResult___snd__h508283 = - (!_theResult____h500013[56] && !_theResult____h500013[55] && - !_theResult____h500013[54] && - !_theResult____h500013[53] && - !_theResult____h500013[52] && - !_theResult____h500013[51] && - !_theResult____h500013[50] && - !_theResult____h500013[49] && - !_theResult____h500013[48] && - !_theResult____h500013[47] && - !_theResult____h500013[46] && - !_theResult____h500013[45] && - !_theResult____h500013[44] && - !_theResult____h500013[43] && - !_theResult____h500013[42] && - !_theResult____h500013[41] && - !_theResult____h500013[40] && - !_theResult____h500013[39] && - !_theResult____h500013[38] && - !_theResult____h500013[37] && - !_theResult____h500013[36] && - !_theResult____h500013[35] && - !_theResult____h500013[34] && - !_theResult____h500013[33] && - !_theResult____h500013[32] && - !_theResult____h500013[31] && - !_theResult____h500013[30] && - !_theResult____h500013[29] && - !_theResult____h500013[28] && - !_theResult____h500013[27] && - !_theResult____h500013[26] && - !_theResult____h500013[25] && - !_theResult____h500013[24] && - !_theResult____h500013[23] && - !_theResult____h500013[22] && - !_theResult____h500013[21] && - !_theResult____h500013[20] && - !_theResult____h500013[19] && - !_theResult____h500013[18] && - !_theResult____h500013[17] && - !_theResult____h500013[16] && - !_theResult____h500013[15] && - !_theResult____h500013[14] && - !_theResult____h500013[13] && - !_theResult____h500013[12] && - !_theResult____h500013[11] && - !_theResult____h500013[10] && - !_theResult____h500013[9] && - !_theResult____h500013[8] && - !_theResult____h500013[7] && - !_theResult____h500013[6] && - !_theResult____h500013[5] && - !_theResult____h500013[4] && - !_theResult____h500013[3] && - !_theResult____h500013[2] && - !_theResult____h500013[1] && - !_theResult____h500013[0]) ? - _theResult____h500013 : - _theResult___snd__h508289 ; - assign _theResult___snd__h508289 = + assign _theResult___snd__h508264 = { _theResult____h500017[55:0], 1'd0 } ; + assign _theResult___snd__h508275 = + (!_theResult____h500017[56] && _theResult____h500017[55]) ? + _theResult___snd__h508277 : + _theResult___snd__h508287 ; + assign _theResult___snd__h508277 = { _theResult____h500017[54:0], 2'd0 } ; + assign _theResult___snd__h508287 = + (!_theResult____h500017[56] && !_theResult____h500017[55] && + !_theResult____h500017[54] && + !_theResult____h500017[53] && + !_theResult____h500017[52] && + !_theResult____h500017[51] && + !_theResult____h500017[50] && + !_theResult____h500017[49] && + !_theResult____h500017[48] && + !_theResult____h500017[47] && + !_theResult____h500017[46] && + !_theResult____h500017[45] && + !_theResult____h500017[44] && + !_theResult____h500017[43] && + !_theResult____h500017[42] && + !_theResult____h500017[41] && + !_theResult____h500017[40] && + !_theResult____h500017[39] && + !_theResult____h500017[38] && + !_theResult____h500017[37] && + !_theResult____h500017[36] && + !_theResult____h500017[35] && + !_theResult____h500017[34] && + !_theResult____h500017[33] && + !_theResult____h500017[32] && + !_theResult____h500017[31] && + !_theResult____h500017[30] && + !_theResult____h500017[29] && + !_theResult____h500017[28] && + !_theResult____h500017[27] && + !_theResult____h500017[26] && + !_theResult____h500017[25] && + !_theResult____h500017[24] && + !_theResult____h500017[23] && + !_theResult____h500017[22] && + !_theResult____h500017[21] && + !_theResult____h500017[20] && + !_theResult____h500017[19] && + !_theResult____h500017[18] && + !_theResult____h500017[17] && + !_theResult____h500017[16] && + !_theResult____h500017[15] && + !_theResult____h500017[14] && + !_theResult____h500017[13] && + !_theResult____h500017[12] && + !_theResult____h500017[11] && + !_theResult____h500017[10] && + !_theResult____h500017[9] && + !_theResult____h500017[8] && + !_theResult____h500017[7] && + !_theResult____h500017[6] && + !_theResult____h500017[5] && + !_theResult____h500017[4] && + !_theResult____h500017[3] && + !_theResult____h500017[2] && + !_theResult____h500017[1] && + !_theResult____h500017[0]) ? + _theResult____h500017 : + _theResult___snd__h508293 ; + assign _theResult___snd__h508293 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h508312 = - _theResult____h500013 << + assign _theResult___snd__h508316 = + _theResult____h500017 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8887 ; - assign _theResult___snd__h517028 = + assign _theResult___snd__h517032 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ? - _theResult___snd__h517042 : - _theResult___snd__h498625 ; - assign _theResult___snd__h517042 = + _theResult___snd__h517046 : + _theResult___snd__h498629 ; + assign _theResult___snd__h517046 = (coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[162] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8548) ? - sfd__h479671 : - _theResult___snd__h517048 ; - assign _theResult___snd__h517048 = + sfd__h479675 : + _theResult___snd__h517052 ; + assign _theResult___snd__h517052 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h517066 = - sfd__h479671 << + assign _theResult___snd__h517070 = + sfd__h479675 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8938 ; - assign _theResult___snd__h537424 = + assign _theResult___snd__h537428 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h537433 : - _theResult___snd__h537426 ; - assign _theResult___snd__h537426 = + _theResult___snd__h537437 : + _theResult___snd__h537430 ; + assign _theResult___snd__h537430 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ; - assign _theResult___snd__h537433 = + assign _theResult___snd__h537437 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518613 : - _theResult___snd__h537439 ; - assign _theResult___snd__h537439 = + sfd__h518617 : + _theResult___snd__h537443 ; + assign _theResult___snd__h537443 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h537462 = - sfd__h518613 << + assign _theResult___snd__h537466 = + sfd__h518617 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10063 ; - assign _theResult___snd__h547061 = { _theResult____h538814[55:0], 1'd0 } ; - assign _theResult___snd__h547072 = - (!_theResult____h538814[56] && _theResult____h538814[55]) ? - _theResult___snd__h547074 : - _theResult___snd__h547084 ; - assign _theResult___snd__h547074 = { _theResult____h538814[54:0], 2'd0 } ; - assign _theResult___snd__h547084 = - (!_theResult____h538814[56] && !_theResult____h538814[55] && - !_theResult____h538814[54] && - !_theResult____h538814[53] && - !_theResult____h538814[52] && - !_theResult____h538814[51] && - !_theResult____h538814[50] && - !_theResult____h538814[49] && - !_theResult____h538814[48] && - !_theResult____h538814[47] && - !_theResult____h538814[46] && - !_theResult____h538814[45] && - !_theResult____h538814[44] && - !_theResult____h538814[43] && - !_theResult____h538814[42] && - !_theResult____h538814[41] && - !_theResult____h538814[40] && - !_theResult____h538814[39] && - !_theResult____h538814[38] && - !_theResult____h538814[37] && - !_theResult____h538814[36] && - !_theResult____h538814[35] && - !_theResult____h538814[34] && - !_theResult____h538814[33] && - !_theResult____h538814[32] && - !_theResult____h538814[31] && - !_theResult____h538814[30] && - !_theResult____h538814[29] && - !_theResult____h538814[28] && - !_theResult____h538814[27] && - !_theResult____h538814[26] && - !_theResult____h538814[25] && - !_theResult____h538814[24] && - !_theResult____h538814[23] && - !_theResult____h538814[22] && - !_theResult____h538814[21] && - !_theResult____h538814[20] && - !_theResult____h538814[19] && - !_theResult____h538814[18] && - !_theResult____h538814[17] && - !_theResult____h538814[16] && - !_theResult____h538814[15] && - !_theResult____h538814[14] && - !_theResult____h538814[13] && - !_theResult____h538814[12] && - !_theResult____h538814[11] && - !_theResult____h538814[10] && - !_theResult____h538814[9] && - !_theResult____h538814[8] && - !_theResult____h538814[7] && - !_theResult____h538814[6] && - !_theResult____h538814[5] && - !_theResult____h538814[4] && - !_theResult____h538814[3] && - !_theResult____h538814[2] && - !_theResult____h538814[1] && - !_theResult____h538814[0]) ? - _theResult____h538814 : - _theResult___snd__h547090 ; - assign _theResult___snd__h547090 = + assign _theResult___snd__h547065 = { _theResult____h538818[55:0], 1'd0 } ; + assign _theResult___snd__h547076 = + (!_theResult____h538818[56] && _theResult____h538818[55]) ? + _theResult___snd__h547078 : + _theResult___snd__h547088 ; + assign _theResult___snd__h547078 = { _theResult____h538818[54:0], 2'd0 } ; + assign _theResult___snd__h547088 = + (!_theResult____h538818[56] && !_theResult____h538818[55] && + !_theResult____h538818[54] && + !_theResult____h538818[53] && + !_theResult____h538818[52] && + !_theResult____h538818[51] && + !_theResult____h538818[50] && + !_theResult____h538818[49] && + !_theResult____h538818[48] && + !_theResult____h538818[47] && + !_theResult____h538818[46] && + !_theResult____h538818[45] && + !_theResult____h538818[44] && + !_theResult____h538818[43] && + !_theResult____h538818[42] && + !_theResult____h538818[41] && + !_theResult____h538818[40] && + !_theResult____h538818[39] && + !_theResult____h538818[38] && + !_theResult____h538818[37] && + !_theResult____h538818[36] && + !_theResult____h538818[35] && + !_theResult____h538818[34] && + !_theResult____h538818[33] && + !_theResult____h538818[32] && + !_theResult____h538818[31] && + !_theResult____h538818[30] && + !_theResult____h538818[29] && + !_theResult____h538818[28] && + !_theResult____h538818[27] && + !_theResult____h538818[26] && + !_theResult____h538818[25] && + !_theResult____h538818[24] && + !_theResult____h538818[23] && + !_theResult____h538818[22] && + !_theResult____h538818[21] && + !_theResult____h538818[20] && + !_theResult____h538818[19] && + !_theResult____h538818[18] && + !_theResult____h538818[17] && + !_theResult____h538818[16] && + !_theResult____h538818[15] && + !_theResult____h538818[14] && + !_theResult____h538818[13] && + !_theResult____h538818[12] && + !_theResult____h538818[11] && + !_theResult____h538818[10] && + !_theResult____h538818[9] && + !_theResult____h538818[8] && + !_theResult____h538818[7] && + !_theResult____h538818[6] && + !_theResult____h538818[5] && + !_theResult____h538818[4] && + !_theResult____h538818[3] && + !_theResult____h538818[2] && + !_theResult____h538818[1] && + !_theResult____h538818[0]) ? + _theResult____h538818 : + _theResult___snd__h547094 ; + assign _theResult___snd__h547094 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h547113 = - _theResult____h538814 << + assign _theResult___snd__h547117 = + _theResult____h538818 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10360 ; - assign _theResult___snd__h555829 = + assign _theResult___snd__h555833 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ? - _theResult___snd__h555843 : - _theResult___snd__h537426 ; - assign _theResult___snd__h555843 = + _theResult___snd__h555847 : + _theResult___snd__h537430 ; + assign _theResult___snd__h555847 = (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[98] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10036) ? - sfd__h518613 : - _theResult___snd__h555849 ; - assign _theResult___snd__h555849 = + sfd__h518617 : + _theResult___snd__h555853 ; + assign _theResult___snd__h555853 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h555867 = - sfd__h518613 << + assign _theResult___snd__h555871 = + sfd__h518617 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10411 ; - assign _theResult___snd__h576625 = + assign _theResult___snd__h576629 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h576634 : - _theResult___snd__h576627 ; - assign _theResult___snd__h576627 = + _theResult___snd__h576638 : + _theResult___snd__h576631 ; + assign _theResult___snd__h576631 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ; - assign _theResult___snd__h576634 = + assign _theResult___snd__h576638 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557814 : - _theResult___snd__h576640 ; - assign _theResult___snd__h576640 = + sfd__h557818 : + _theResult___snd__h576644 ; + assign _theResult___snd__h576644 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h576663 = - sfd__h557814 << + assign _theResult___snd__h576667 = + sfd__h557818 << IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9300 ; - assign _theResult___snd__h586262 = { _theResult____h578015[55:0], 1'd0 } ; - assign _theResult___snd__h586273 = - (!_theResult____h578015[56] && _theResult____h578015[55]) ? - _theResult___snd__h586275 : - _theResult___snd__h586285 ; - assign _theResult___snd__h586275 = { _theResult____h578015[54:0], 2'd0 } ; - assign _theResult___snd__h586285 = - (!_theResult____h578015[56] && !_theResult____h578015[55] && - !_theResult____h578015[54] && - !_theResult____h578015[53] && - !_theResult____h578015[52] && - !_theResult____h578015[51] && - !_theResult____h578015[50] && - !_theResult____h578015[49] && - !_theResult____h578015[48] && - !_theResult____h578015[47] && - !_theResult____h578015[46] && - !_theResult____h578015[45] && - !_theResult____h578015[44] && - !_theResult____h578015[43] && - !_theResult____h578015[42] && - !_theResult____h578015[41] && - !_theResult____h578015[40] && - !_theResult____h578015[39] && - !_theResult____h578015[38] && - !_theResult____h578015[37] && - !_theResult____h578015[36] && - !_theResult____h578015[35] && - !_theResult____h578015[34] && - !_theResult____h578015[33] && - !_theResult____h578015[32] && - !_theResult____h578015[31] && - !_theResult____h578015[30] && - !_theResult____h578015[29] && - !_theResult____h578015[28] && - !_theResult____h578015[27] && - !_theResult____h578015[26] && - !_theResult____h578015[25] && - !_theResult____h578015[24] && - !_theResult____h578015[23] && - !_theResult____h578015[22] && - !_theResult____h578015[21] && - !_theResult____h578015[20] && - !_theResult____h578015[19] && - !_theResult____h578015[18] && - !_theResult____h578015[17] && - !_theResult____h578015[16] && - !_theResult____h578015[15] && - !_theResult____h578015[14] && - !_theResult____h578015[13] && - !_theResult____h578015[12] && - !_theResult____h578015[11] && - !_theResult____h578015[10] && - !_theResult____h578015[9] && - !_theResult____h578015[8] && - !_theResult____h578015[7] && - !_theResult____h578015[6] && - !_theResult____h578015[5] && - !_theResult____h578015[4] && - !_theResult____h578015[3] && - !_theResult____h578015[2] && - !_theResult____h578015[1] && - !_theResult____h578015[0]) ? - _theResult____h578015 : - _theResult___snd__h586291 ; - assign _theResult___snd__h586291 = + assign _theResult___snd__h586266 = { _theResult____h578019[55:0], 1'd0 } ; + assign _theResult___snd__h586277 = + (!_theResult____h578019[56] && _theResult____h578019[55]) ? + _theResult___snd__h586279 : + _theResult___snd__h586289 ; + assign _theResult___snd__h586279 = { _theResult____h578019[54:0], 2'd0 } ; + assign _theResult___snd__h586289 = + (!_theResult____h578019[56] && !_theResult____h578019[55] && + !_theResult____h578019[54] && + !_theResult____h578019[53] && + !_theResult____h578019[52] && + !_theResult____h578019[51] && + !_theResult____h578019[50] && + !_theResult____h578019[49] && + !_theResult____h578019[48] && + !_theResult____h578019[47] && + !_theResult____h578019[46] && + !_theResult____h578019[45] && + !_theResult____h578019[44] && + !_theResult____h578019[43] && + !_theResult____h578019[42] && + !_theResult____h578019[41] && + !_theResult____h578019[40] && + !_theResult____h578019[39] && + !_theResult____h578019[38] && + !_theResult____h578019[37] && + !_theResult____h578019[36] && + !_theResult____h578019[35] && + !_theResult____h578019[34] && + !_theResult____h578019[33] && + !_theResult____h578019[32] && + !_theResult____h578019[31] && + !_theResult____h578019[30] && + !_theResult____h578019[29] && + !_theResult____h578019[28] && + !_theResult____h578019[27] && + !_theResult____h578019[26] && + !_theResult____h578019[25] && + !_theResult____h578019[24] && + !_theResult____h578019[23] && + !_theResult____h578019[22] && + !_theResult____h578019[21] && + !_theResult____h578019[20] && + !_theResult____h578019[19] && + !_theResult____h578019[18] && + !_theResult____h578019[17] && + !_theResult____h578019[16] && + !_theResult____h578019[15] && + !_theResult____h578019[14] && + !_theResult____h578019[13] && + !_theResult____h578019[12] && + !_theResult____h578019[11] && + !_theResult____h578019[10] && + !_theResult____h578019[9] && + !_theResult____h578019[8] && + !_theResult____h578019[7] && + !_theResult____h578019[6] && + !_theResult____h578019[5] && + !_theResult____h578019[4] && + !_theResult____h578019[3] && + !_theResult____h578019[2] && + !_theResult____h578019[1] && + !_theResult____h578019[0]) ? + _theResult____h578019 : + _theResult___snd__h586295 ; + assign _theResult___snd__h586295 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h586314 = - _theResult____h578015 << + assign _theResult___snd__h586318 = + _theResult____h578019 << IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9597 ; - assign _theResult___snd__h595030 = + assign _theResult___snd__h595034 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ? - _theResult___snd__h595044 : - _theResult___snd__h576627 ; - assign _theResult___snd__h595044 = + _theResult___snd__h595048 : + _theResult___snd__h576631 ; + assign _theResult___snd__h595048 = (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 && !coreFix_fpuMulDivExe_0_regToExeQ$first[34] && NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9273) ? - sfd__h557814 : - _theResult___snd__h595050 ; - assign _theResult___snd__h595050 = + sfd__h557818 : + _theResult___snd__h595054 ; + assign _theResult___snd__h595054 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h595068 = - sfd__h557814 << + assign _theResult___snd__h595072 = + sfd__h557818 << IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9648 ; - assign _theResult___snd__h600258 = - b__h599836[63] ? b___1__h600307 : b__h599836 ; - assign _theResult___snd_fst_exp__h360592 = + assign _theResult___snd__h600262 = + b__h599840[63] ? b___1__h600311 : b__h599840 ; + assign _theResult___snd_fst_exp__h360595 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_exp__h352007 : - _theResult___fst_exp__h360589 ; - assign _theResult___snd_fst_exp__h378412 = + _theResult___fst_exp__h352010 : + _theResult___fst_exp__h360592 ; + assign _theResult___snd_fst_exp__h378415 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_exp__h369773 : - _theResult___fst_exp__h378409 ; - assign _theResult___snd_fst_exp__h406282 = + _theResult___fst_exp__h369776 : + _theResult___fst_exp__h378412 ; + assign _theResult___snd_fst_exp__h406285 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_exp__h397697 : - _theResult___fst_exp__h406279 ; - assign _theResult___snd_fst_exp__h424102 = + _theResult___fst_exp__h397700 : + _theResult___fst_exp__h406282 ; + assign _theResult___snd_fst_exp__h424105 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_exp__h415463 : - _theResult___fst_exp__h424099 ; - assign _theResult___snd_fst_exp__h451970 = + _theResult___fst_exp__h415466 : + _theResult___fst_exp__h424102 ; + assign _theResult___snd_fst_exp__h451973 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_exp__h443385 : - _theResult___fst_exp__h451967 ; - assign _theResult___snd_fst_exp__h469790 = + _theResult___fst_exp__h443388 : + _theResult___fst_exp__h451970 ; + assign _theResult___snd_fst_exp__h469793 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_exp__h461151 : - _theResult___fst_exp__h469787 ; - assign _theResult___snd_fst_exp__h499433 = + _theResult___fst_exp__h461154 : + _theResult___fst_exp__h469790 ; + assign _theResult___snd_fst_exp__h499437 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 11'd0 : - _theResult___fst_exp__h499430 ; - assign _theResult___snd_fst_exp__h517868 = + _theResult___fst_exp__h499434 ; + assign _theResult___snd_fst_exp__h517872 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_exp__h509081 : - _theResult___fst_exp__h517865 ; - assign _theResult___snd_fst_exp__h538234 = + _theResult___fst_exp__h509085 : + _theResult___fst_exp__h517869 ; + assign _theResult___snd_fst_exp__h538238 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 11'd0 : - _theResult___fst_exp__h538231 ; - assign _theResult___snd_fst_exp__h556669 = + _theResult___fst_exp__h538235 ; + assign _theResult___snd_fst_exp__h556673 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_exp__h547882 : - _theResult___fst_exp__h556666 ; - assign _theResult___snd_fst_exp__h577435 = + _theResult___fst_exp__h547886 : + _theResult___fst_exp__h556670 ; + assign _theResult___snd_fst_exp__h577439 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 11'd0 : - _theResult___fst_exp__h577432 ; - assign _theResult___snd_fst_exp__h595870 = + _theResult___fst_exp__h577436 ; + assign _theResult___snd_fst_exp__h595874 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_exp__h587083 : - _theResult___fst_exp__h595867 ; - assign _theResult___snd_fst_sfd__h335644 = + _theResult___fst_exp__h587087 : + _theResult___fst_exp__h595871 ; + assign _theResult___snd_fst_sfd__h335647 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h360593 = + assign _theResult___snd_fst_sfd__h360596 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ? - _theResult___fst_sfd__h352008 : - _theResult___fst_sfd__h360590 ; - assign _theResult___snd_fst_sfd__h378413 = + _theResult___fst_sfd__h352011 : + _theResult___fst_sfd__h360593 ; + assign _theResult___snd_fst_sfd__h378416 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ? - _theResult___fst_sfd__h369774 : - _theResult___fst_sfd__h378410 ; - assign _theResult___snd_fst_sfd__h381339 = + _theResult___fst_sfd__h369777 : + _theResult___fst_sfd__h378413 ; + assign _theResult___snd_fst_sfd__h381342 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h406283 = + assign _theResult___snd_fst_sfd__h406286 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ? - _theResult___fst_sfd__h397698 : - _theResult___fst_sfd__h406280 ; - assign _theResult___snd_fst_sfd__h424103 = + _theResult___fst_sfd__h397701 : + _theResult___fst_sfd__h406283 ; + assign _theResult___snd_fst_sfd__h424106 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ? - _theResult___fst_sfd__h415464 : - _theResult___fst_sfd__h424100 ; - assign _theResult___snd_fst_sfd__h427027 = + _theResult___fst_sfd__h415467 : + _theResult___fst_sfd__h424103 ; + assign _theResult___snd_fst_sfd__h427030 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h451971 = + assign _theResult___snd_fst_sfd__h451974 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ? - _theResult___fst_sfd__h443386 : - _theResult___fst_sfd__h451968 ; - assign _theResult___snd_fst_sfd__h469791 = + _theResult___fst_sfd__h443389 : + _theResult___fst_sfd__h451971 ; + assign _theResult___snd_fst_sfd__h469794 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ? - _theResult___fst_sfd__h461152 : - _theResult___fst_sfd__h469788 ; - assign _theResult___snd_fst_sfd__h479625 = + _theResult___fst_sfd__h461155 : + _theResult___fst_sfd__h469791 ; + assign _theResult___snd_fst_sfd__h479629 = (coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h479374 ; - assign _theResult___snd_fst_sfd__h499434 = + out___1_sfd__h479378 ; + assign _theResult___snd_fst_sfd__h499438 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8504 ? 52'd0 : - _theResult___fst_sfd__h499431 ; - assign _theResult___snd_fst_sfd__h517869 = + _theResult___fst_sfd__h499435 ; + assign _theResult___snd_fst_sfd__h517873 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8640 ? - _theResult___fst_sfd__h509082 : - _theResult___fst_sfd__h517866 ; - assign _theResult___snd_fst_sfd__h518567 = + _theResult___fst_sfd__h509086 : + _theResult___fst_sfd__h517870 ; + assign _theResult___snd_fst_sfd__h518571 = (coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h518316 ; - assign _theResult___snd_fst_sfd__h538235 = + out___1_sfd__h518320 ; + assign _theResult___snd_fst_sfd__h538239 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9992 ? 52'd0 : - _theResult___fst_sfd__h538232 ; - assign _theResult___snd_fst_sfd__h556670 = + _theResult___fst_sfd__h538236 ; + assign _theResult___snd_fst_sfd__h556674 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10113 ? - _theResult___fst_sfd__h547883 : - _theResult___fst_sfd__h556667 ; - assign _theResult___snd_fst_sfd__h557768 = + _theResult___fst_sfd__h547887 : + _theResult___fst_sfd__h556671 ; + assign _theResult___snd_fst_sfd__h557772 = (coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h557517 ; - assign _theResult___snd_fst_sfd__h577436 = + out___1_sfd__h557521 ; + assign _theResult___snd_fst_sfd__h577440 = _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9229 ? 52'd0 : - _theResult___fst_sfd__h577433 ; - assign _theResult___snd_fst_sfd__h595871 = + _theResult___fst_sfd__h577437 ; + assign _theResult___snd_fst_sfd__h595875 = SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9350 ? - _theResult___fst_sfd__h587084 : - _theResult___fst_sfd__h595868 ; - assign a___1__h599976 = + _theResult___fst_sfd__h587088 : + _theResult___fst_sfd__h595872 ; + assign a___1__h599980 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ; - assign a___1__h600262 = 64'd0 - a__h599835 ; - assign a__h599835 = + assign a___1__h600266 = 64'd0 - a__h599839 ; + assign a__h599839 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h599976 : + a___1__h599980 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h599977 = + assign b___1__h599981 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h600307 = 64'd0 - b__h599836 ; - assign b__h599836 = + assign b___1__h600311 = 64'd0 - b__h599840 ; + assign b__h599840 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h599977 : + b___1__h599981 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h694782 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h694985 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h692180 = - commitStage_commitTrap[4] ? i__h692355 : i__h692195 ; + assign base__h694791 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h694994 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h692189 = + commitStage_commitTrap[4] ? i__h692364 : i__h692204 ; assign coreFix_aluExe_0_bypassWire_0_wget__2099_BITS__ETC___d12101 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27353,7 +27353,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h252023 ; + y__h252026 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 || @@ -27707,44 +27707,44 @@ module mkCore(CLK, assign csrf_prv_reg_read__2633_ULT_IF_fetchStage_pipe_ETC___d12871 = csrf_prv_reg < IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[9:8] ; - assign data72478_BITS_31_TO_0__q5 = data__h472478[31:0] ; - assign data___1__h472204 = + assign data72481_BITS_31_TO_0__q5 = data__h472481[31:0] ; + assign data___1__h472207 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ; - assign data___1__h473012 = - { {32{data72478_BITS_31_TO_0__q5[31]}}, - data72478_BITS_31_TO_0__q5 } ; - assign data__h472478 = + assign data___1__h473015 = + { {32{data72481_BITS_31_TO_0__q5[31]}}, + data72481_BITS_31_TO_0__q5 } ; + assign data__h472481 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h472392 : - x_remainder__h472393 ; - assign din_inc___2_exp__h378443 = _theResult___fst_exp__h351410 + 8'd1 ; - assign din_inc___2_exp__h378467 = _theResult___fst_exp__h360066 + 8'd1 ; - assign din_inc___2_exp__h378497 = _theResult___fst_exp__h369176 + 8'd1 ; - assign din_inc___2_exp__h378521 = _theResult___fst_exp__h377861 + 8'd1 ; - assign din_inc___2_exp__h424133 = _theResult___fst_exp__h397100 + 8'd1 ; - assign din_inc___2_exp__h424157 = _theResult___fst_exp__h405756 + 8'd1 ; - assign din_inc___2_exp__h424187 = _theResult___fst_exp__h414866 + 8'd1 ; - assign din_inc___2_exp__h424211 = _theResult___fst_exp__h423551 + 8'd1 ; - assign din_inc___2_exp__h469821 = _theResult___fst_exp__h442788 + 8'd1 ; - assign din_inc___2_exp__h469845 = _theResult___fst_exp__h451444 + 8'd1 ; - assign din_inc___2_exp__h469875 = _theResult___fst_exp__h460554 + 8'd1 ; - assign din_inc___2_exp__h469899 = _theResult___fst_exp__h469239 + 8'd1 ; - assign din_inc___2_exp__h517922 = _theResult___fst_exp__h498672 + 11'd1 ; - assign din_inc___2_exp__h517957 = _theResult___fst_exp__h508249 + 11'd1 ; - assign din_inc___2_exp__h517983 = _theResult___fst_exp__h517082 + 11'd1 ; - assign din_inc___2_exp__h556723 = _theResult___fst_exp__h537473 + 11'd1 ; - assign din_inc___2_exp__h556758 = _theResult___fst_exp__h547050 + 11'd1 ; - assign din_inc___2_exp__h556784 = _theResult___fst_exp__h555883 + 11'd1 ; - assign din_inc___2_exp__h595924 = _theResult___fst_exp__h576674 + 11'd1 ; - assign din_inc___2_exp__h595959 = _theResult___fst_exp__h586251 + 11'd1 ; - assign din_inc___2_exp__h595985 = _theResult___fst_exp__h595084 + 11'd1 ; - assign enabled_ints___1__h645886 = pend_ints__h645387 & y__h645898 ; - assign enabled_ints__h645933 = - pend_ints__h645387 & - { r1__read_BITS_12_TO_0___h645909, csrf_mideleg_1_0_reg } ; - assign fcsr_csr__read__h606143 = { 56'd0, x__h608817 } ; + x_quotient__h472395 : + x_remainder__h472396 ; + assign din_inc___2_exp__h378446 = _theResult___fst_exp__h351413 + 8'd1 ; + assign din_inc___2_exp__h378470 = _theResult___fst_exp__h360069 + 8'd1 ; + assign din_inc___2_exp__h378500 = _theResult___fst_exp__h369179 + 8'd1 ; + assign din_inc___2_exp__h378524 = _theResult___fst_exp__h377864 + 8'd1 ; + assign din_inc___2_exp__h424136 = _theResult___fst_exp__h397103 + 8'd1 ; + assign din_inc___2_exp__h424160 = _theResult___fst_exp__h405759 + 8'd1 ; + assign din_inc___2_exp__h424190 = _theResult___fst_exp__h414869 + 8'd1 ; + assign din_inc___2_exp__h424214 = _theResult___fst_exp__h423554 + 8'd1 ; + assign din_inc___2_exp__h469824 = _theResult___fst_exp__h442791 + 8'd1 ; + assign din_inc___2_exp__h469848 = _theResult___fst_exp__h451447 + 8'd1 ; + assign din_inc___2_exp__h469878 = _theResult___fst_exp__h460557 + 8'd1 ; + assign din_inc___2_exp__h469902 = _theResult___fst_exp__h469242 + 8'd1 ; + assign din_inc___2_exp__h517926 = _theResult___fst_exp__h498676 + 11'd1 ; + assign din_inc___2_exp__h517961 = _theResult___fst_exp__h508253 + 11'd1 ; + assign din_inc___2_exp__h517987 = _theResult___fst_exp__h517086 + 11'd1 ; + assign din_inc___2_exp__h556727 = _theResult___fst_exp__h537477 + 11'd1 ; + assign din_inc___2_exp__h556762 = _theResult___fst_exp__h547054 + 11'd1 ; + assign din_inc___2_exp__h556788 = _theResult___fst_exp__h555887 + 11'd1 ; + assign din_inc___2_exp__h595928 = _theResult___fst_exp__h576678 + 11'd1 ; + assign din_inc___2_exp__h595963 = _theResult___fst_exp__h586255 + 11'd1 ; + assign din_inc___2_exp__h595989 = _theResult___fst_exp__h595088 + 11'd1 ; + assign enabled_ints___1__h645895 = pend_ints__h645396 & y__h645907 ; + assign enabled_ints__h645942 = + pend_ints__h645396 & + { r1__read_BITS_12_TO_0___h645918, csrf_mideleg_1_0_reg } ; + assign fcsr_csr__read__h606148 = { 56'd0, x__h608822 } ; assign fetchStage_RDY_pipelines_0_first__2602_AND_NOT_ETC___d13210 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -27841,8 +27841,8 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d12869 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h649444 != 5'd0 || - imm__h649445 != 32'd0) && + rs1__h649453 != 5'd0 || + imm__h649454 != 32'd0) && IF_fetchStage_pipelines_0_first__2605_BIT_173__ETC___d12866[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13502 = @@ -27969,82 +27969,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13709 ; - assign fflags__h705618 = + assign fflags__h705627 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_fst__h705678 : + y_avValue_snd_fst__h705687 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 ; - assign fflags_csr__read__h606118 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h606129 = { 61'd0, csrf_frm_reg } ; - assign guard__h343309 = - { IF_sfdin51404_BIT_33_THEN_2_ELSE_0__q21[1], - { sfdin__h351404[32:0], 23'd0 } != 56'd0 } ; - assign guard__h352018 = - { IF_theResult___snd60017_BIT_33_THEN_2_ELSE_0__q23[1], - { _theResult___snd__h360017[32:0], 23'd0 } != 56'd0 } ; - assign guard__h360948 = - { IF_sfdin69170_BIT_33_THEN_2_ELSE_0__q31[1], - { sfdin__h369170[32:0], 23'd0 } != 56'd0 } ; - assign guard__h361546 = x__h361648 != 57'd0 ; - assign guard__h369784 = - { IF_theResult___snd77807_BIT_33_THEN_2_ELSE_0__q36[1], - { _theResult___snd__h377807[32:0], 23'd0 } != 56'd0 } ; - assign guard__h389001 = - { IF_sfdin97094_BIT_33_THEN_2_ELSE_0__q56[1], - { sfdin__h397094[32:0], 23'd0 } != 56'd0 } ; - assign guard__h397708 = - { IF_theResult___snd05707_BIT_33_THEN_2_ELSE_0__q58[1], - { _theResult___snd__h405707[32:0], 23'd0 } != 56'd0 } ; - assign guard__h406638 = - { IF_sfdin14860_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h414860[32:0], 23'd0 } != 56'd0 } ; - assign guard__h407236 = x__h407338 != 57'd0 ; - assign guard__h415474 = - { IF_theResult___snd23497_BIT_33_THEN_2_ELSE_0__q71[1], - { _theResult___snd__h423497[32:0], 23'd0 } != 56'd0 } ; - assign guard__h434689 = - { IF_sfdin42782_BIT_33_THEN_2_ELSE_0__q91[1], - { sfdin__h442782[32:0], 23'd0 } != 56'd0 } ; - assign guard__h443396 = - { IF_theResult___snd51395_BIT_33_THEN_2_ELSE_0__q93[1], - { _theResult___snd__h451395[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452326 = - { IF_sfdin60548_BIT_33_THEN_2_ELSE_0__q101[1], - { sfdin__h460548[32:0], 23'd0 } != 56'd0 } ; - assign guard__h452924 = x__h453026 != 57'd0 ; - assign guard__h461162 = - { IF_theResult___snd69185_BIT_33_THEN_2_ELSE_0__q106[1], - { _theResult___snd__h469185[32:0], 23'd0 } != 56'd0 } ; - assign guard__h490711 = - { IF_theResult___snd98623_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h498623[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500023 = - { IF_sfdin08243_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h508243[3:0], 52'd0 } != 56'd0 } ; - assign guard__h500621 = x__h500721 != 57'd0 ; - assign guard__h509092 = - { IF_theResult___snd17028_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h517028[3:0], 52'd0 } != 56'd0 } ; - assign guard__h529512 = - { IF_theResult___snd37424_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h537424[3:0], 52'd0 } != 56'd0 } ; - assign guard__h538824 = - { IF_sfdin47044_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h547044[3:0], 52'd0 } != 56'd0 } ; - assign guard__h539422 = x__h539522 != 57'd0 ; - assign guard__h547893 = - { IF_theResult___snd55829_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h555829[3:0], 52'd0 } != 56'd0 } ; - assign guard__h568713 = - { IF_theResult___snd76625_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h576625[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578025 = - { IF_sfdin86245_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h586245[3:0], 52'd0 } != 56'd0 } ; - assign guard__h578623 = x__h578723 != 57'd0 ; - assign guard__h587094 = - { IF_theResult___snd95030_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h595030[3:0], 52'd0 } != 56'd0 } ; - assign idx__h675470 = + assign fflags_csr__read__h606123 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h606134 = { 61'd0, csrf_frm_reg } ; + assign guard__h343312 = + { IF_sfdin51407_BIT_33_THEN_2_ELSE_0__q21[1], + { sfdin__h351407[32:0], 23'd0 } != 56'd0 } ; + assign guard__h352021 = + { IF_theResult___snd60020_BIT_33_THEN_2_ELSE_0__q23[1], + { _theResult___snd__h360020[32:0], 23'd0 } != 56'd0 } ; + assign guard__h360951 = + { IF_sfdin69173_BIT_33_THEN_2_ELSE_0__q31[1], + { sfdin__h369173[32:0], 23'd0 } != 56'd0 } ; + assign guard__h361549 = x__h361651 != 57'd0 ; + assign guard__h369787 = + { IF_theResult___snd77810_BIT_33_THEN_2_ELSE_0__q36[1], + { _theResult___snd__h377810[32:0], 23'd0 } != 56'd0 } ; + assign guard__h389004 = + { IF_sfdin97097_BIT_33_THEN_2_ELSE_0__q56[1], + { sfdin__h397097[32:0], 23'd0 } != 56'd0 } ; + assign guard__h397711 = + { IF_theResult___snd05710_BIT_33_THEN_2_ELSE_0__q58[1], + { _theResult___snd__h405710[32:0], 23'd0 } != 56'd0 } ; + assign guard__h406641 = + { IF_sfdin14863_BIT_33_THEN_2_ELSE_0__q66[1], + { sfdin__h414863[32:0], 23'd0 } != 56'd0 } ; + assign guard__h407239 = x__h407341 != 57'd0 ; + assign guard__h415477 = + { IF_theResult___snd23500_BIT_33_THEN_2_ELSE_0__q71[1], + { _theResult___snd__h423500[32:0], 23'd0 } != 56'd0 } ; + assign guard__h434692 = + { IF_sfdin42785_BIT_33_THEN_2_ELSE_0__q91[1], + { sfdin__h442785[32:0], 23'd0 } != 56'd0 } ; + assign guard__h443399 = + { IF_theResult___snd51398_BIT_33_THEN_2_ELSE_0__q93[1], + { _theResult___snd__h451398[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452329 = + { IF_sfdin60551_BIT_33_THEN_2_ELSE_0__q101[1], + { sfdin__h460551[32:0], 23'd0 } != 56'd0 } ; + assign guard__h452927 = x__h453029 != 57'd0 ; + assign guard__h461165 = + { IF_theResult___snd69188_BIT_33_THEN_2_ELSE_0__q106[1], + { _theResult___snd__h469188[32:0], 23'd0 } != 56'd0 } ; + assign guard__h490715 = + { IF_theResult___snd98627_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h498627[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500027 = + { IF_sfdin08247_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h508247[3:0], 52'd0 } != 56'd0 } ; + assign guard__h500625 = x__h500725 != 57'd0 ; + assign guard__h509096 = + { IF_theResult___snd17032_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h517032[3:0], 52'd0 } != 56'd0 } ; + assign guard__h529516 = + { IF_theResult___snd37428_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h537428[3:0], 52'd0 } != 56'd0 } ; + assign guard__h538828 = + { IF_sfdin47048_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h547048[3:0], 52'd0 } != 56'd0 } ; + assign guard__h539426 = x__h539526 != 57'd0 ; + assign guard__h547897 = + { IF_theResult___snd55833_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h555833[3:0], 52'd0 } != 56'd0 } ; + assign guard__h568717 = + { IF_theResult___snd76629_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h576629[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578029 = + { IF_sfdin86249_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h586249[3:0], 52'd0 } != 56'd0 } ; + assign guard__h578627 = x__h578727 != 57'd0 ; + assign guard__h587098 = + { IF_theResult___snd95034_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h595034[3:0], 52'd0 } != 56'd0 } ; + assign idx__h675479 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28052,26 +28052,26 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13523) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign imm__h649445 = + assign imm__h649454 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h661036 = + assign k__h661045 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3221__ETC___d13223 ; - assign mcause_csr__read__h607790 = - { r1__read__h610357, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h607535 = - { r1__read__h610344, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h607135 = - { r1__read__h610180, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h607230 = - { r1__read__h610197, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h607361 = - { r1__read__h610221, csrf_software_int_en_vec_0 } ; - assign mip_csr__read__h608030 = - { r1__read__h610363, csrf_software_int_pend_vec_0 } ; + assign mcause_csr__read__h607795 = + { r1__read__h610362, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h607540 = + { r1__read__h610349, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h607140 = + { r1__read__h610185, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h607235 = + { r1__read__h610202, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h607366 = + { r1__read__h610226, csrf_software_int_en_vec_0 } ; + assign mip_csr__read__h608035 = + { r1__read__h610368, csrf_software_int_pend_vec_0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28148,40 +28148,40 @@ module mkCore(CLK, !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; assign msip__h75409 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h606987 = { r1__read__h610043, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h607443 = - { r1__read__h610339, csrf_mtvec_mode_low_reg } ; - assign n___1__h195749 = + assign mstatus_csr__read__h606992 = { r1__read__h610048, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h607448 = + { r1__read__h610344, csrf_mtvec_mode_low_reg } ; + assign n___1__h195752 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h194346[63:56], + x__h194349[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h194346[55:48], + x__h194349[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h194346[47:40], + x__h194349[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h194346[39:32], + x__h194349[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h194346[31:24], + x__h194349[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h194346[23:16], + x__h194349[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h194346[15:8], + x__h194349[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h194346[7:0] } ; - assign n__read__h608134 = + x__h194349[7:0] } ; + assign n__read__h608139 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h608325 = + assign n__read__h608330 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -28192,250 +28192,250 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h703190 = + assign n__read__h703199 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h294020 = + assign next_deqP___1__h294022 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h302016 = + assign next_deqP___1__h302018 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h308297 = + assign next_deqP___1__h308299 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h316151 = + assign next_deqP___1__h316153 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h326208 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h329433 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h702533 = + assign next_deqP___1__h326210 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h329435 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h702542 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[282:219] + 64'd4 ; - assign out___1_sfd__h479374 = + assign out___1_sfd__h479378 = { coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ; - assign out___1_sfd__h518316 = + assign out___1_sfd__h518320 = { coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ; - assign out___1_sfd__h557517 = + assign out___1_sfd__h557521 = { coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ; - assign out_exp__h351929 = - sfdin__h351404[34] ? - _theResult___exp__h351926 : - _theResult___fst_exp__h351410 ; - assign out_exp__h360511 = - _theResult___snd__h360017[34] ? - _theResult___exp__h360508 : - _theResult___fst_exp__h360066 ; - assign out_exp__h369695 = - sfdin__h369170[34] ? - _theResult___exp__h369692 : - _theResult___fst_exp__h369176 ; - assign out_exp__h378331 = - _theResult___snd__h377807[34] ? - _theResult___exp__h378328 : - _theResult___fst_exp__h377861 ; - assign out_exp__h397619 = - sfdin__h397094[34] ? - _theResult___exp__h397616 : - _theResult___fst_exp__h397100 ; - assign out_exp__h406201 = - _theResult___snd__h405707[34] ? - _theResult___exp__h406198 : - _theResult___fst_exp__h405756 ; - assign out_exp__h415385 = - sfdin__h414860[34] ? - _theResult___exp__h415382 : - _theResult___fst_exp__h414866 ; - assign out_exp__h424021 = - _theResult___snd__h423497[34] ? - _theResult___exp__h424018 : - _theResult___fst_exp__h423551 ; - assign out_exp__h443307 = - sfdin__h442782[34] ? - _theResult___exp__h443304 : - _theResult___fst_exp__h442788 ; - assign out_exp__h451889 = - _theResult___snd__h451395[34] ? - _theResult___exp__h451886 : - _theResult___fst_exp__h451444 ; - assign out_exp__h461073 = - sfdin__h460548[34] ? - _theResult___exp__h461070 : - _theResult___fst_exp__h460554 ; - assign out_exp__h469709 = - _theResult___snd__h469185[34] ? - _theResult___exp__h469706 : - _theResult___fst_exp__h469239 ; - assign out_exp__h499330 = - _theResult___snd__h498623[5] ? - _theResult___exp__h499327 : - _theResult___fst_exp__h498672 ; - assign out_exp__h508981 = - sfdin__h508243[5] ? - _theResult___exp__h508978 : - _theResult___fst_exp__h508249 ; - assign out_exp__h517765 = - _theResult___snd__h517028[5] ? - _theResult___exp__h517762 : - _theResult___fst_exp__h517082 ; - assign out_exp__h538131 = - _theResult___snd__h537424[5] ? - _theResult___exp__h538128 : - _theResult___fst_exp__h537473 ; - assign out_exp__h547782 = - sfdin__h547044[5] ? - _theResult___exp__h547779 : - _theResult___fst_exp__h547050 ; - assign out_exp__h556566 = - _theResult___snd__h555829[5] ? - _theResult___exp__h556563 : - _theResult___fst_exp__h555883 ; - assign out_exp__h577332 = - _theResult___snd__h576625[5] ? - _theResult___exp__h577329 : - _theResult___fst_exp__h576674 ; - assign out_exp__h586983 = - sfdin__h586245[5] ? - _theResult___exp__h586980 : - _theResult___fst_exp__h586251 ; - assign out_exp__h595767 = - _theResult___snd__h595030[5] ? - _theResult___exp__h595764 : - _theResult___fst_exp__h595084 ; - assign out_f_exp__h378707 = - (_theResult___exp__h378430 == 8'd255 && - _theResult___sfd__h378431 != 23'd0 || + assign out_exp__h351932 = + sfdin__h351407[34] ? + _theResult___exp__h351929 : + _theResult___fst_exp__h351413 ; + assign out_exp__h360514 = + _theResult___snd__h360020[34] ? + _theResult___exp__h360511 : + _theResult___fst_exp__h360069 ; + assign out_exp__h369698 = + sfdin__h369173[34] ? + _theResult___exp__h369695 : + _theResult___fst_exp__h369179 ; + assign out_exp__h378334 = + _theResult___snd__h377810[34] ? + _theResult___exp__h378331 : + _theResult___fst_exp__h377864 ; + assign out_exp__h397622 = + sfdin__h397097[34] ? + _theResult___exp__h397619 : + _theResult___fst_exp__h397103 ; + assign out_exp__h406204 = + _theResult___snd__h405710[34] ? + _theResult___exp__h406201 : + _theResult___fst_exp__h405759 ; + assign out_exp__h415388 = + sfdin__h414863[34] ? + _theResult___exp__h415385 : + _theResult___fst_exp__h414869 ; + assign out_exp__h424024 = + _theResult___snd__h423500[34] ? + _theResult___exp__h424021 : + _theResult___fst_exp__h423554 ; + assign out_exp__h443310 = + sfdin__h442785[34] ? + _theResult___exp__h443307 : + _theResult___fst_exp__h442791 ; + assign out_exp__h451892 = + _theResult___snd__h451398[34] ? + _theResult___exp__h451889 : + _theResult___fst_exp__h451447 ; + assign out_exp__h461076 = + sfdin__h460551[34] ? + _theResult___exp__h461073 : + _theResult___fst_exp__h460557 ; + assign out_exp__h469712 = + _theResult___snd__h469188[34] ? + _theResult___exp__h469709 : + _theResult___fst_exp__h469242 ; + assign out_exp__h499334 = + _theResult___snd__h498627[5] ? + _theResult___exp__h499331 : + _theResult___fst_exp__h498676 ; + assign out_exp__h508985 = + sfdin__h508247[5] ? + _theResult___exp__h508982 : + _theResult___fst_exp__h508253 ; + assign out_exp__h517769 = + _theResult___snd__h517032[5] ? + _theResult___exp__h517766 : + _theResult___fst_exp__h517086 ; + assign out_exp__h538135 = + _theResult___snd__h537428[5] ? + _theResult___exp__h538132 : + _theResult___fst_exp__h537477 ; + assign out_exp__h547786 = + sfdin__h547048[5] ? + _theResult___exp__h547783 : + _theResult___fst_exp__h547054 ; + assign out_exp__h556570 = + _theResult___snd__h555833[5] ? + _theResult___exp__h556567 : + _theResult___fst_exp__h555887 ; + assign out_exp__h577336 = + _theResult___snd__h576629[5] ? + _theResult___exp__h577333 : + _theResult___fst_exp__h576678 ; + assign out_exp__h586987 = + sfdin__h586249[5] ? + _theResult___exp__h586984 : + _theResult___fst_exp__h586255 ; + assign out_exp__h595771 = + _theResult___snd__h595034[5] ? + _theResult___exp__h595768 : + _theResult___fst_exp__h595088 ; + assign out_f_exp__h378710 = + (_theResult___exp__h378433 == 8'd255 && + _theResult___sfd__h378434 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h378421 ; - assign out_f_exp__h424397 = - (_theResult___exp__h424120 == 8'd255 && - _theResult___sfd__h424121 != 23'd0 || + _theResult___fst_exp__h378424 ; + assign out_f_exp__h424400 = + (_theResult___exp__h424123 == 8'd255 && + _theResult___sfd__h424124 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h424111 ; - assign out_f_exp__h470085 = - (_theResult___exp__h469808 == 8'd255 && - _theResult___sfd__h469809 != 23'd0 || + _theResult___fst_exp__h424114 ; + assign out_f_exp__h470088 = + (_theResult___exp__h469811 == 8'd255 && + _theResult___sfd__h469812 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h469799 ; - assign out_f_sfd__h378708 = - (_theResult___exp__h378430 == 8'd255 && - _theResult___sfd__h378431 != 23'd0) ? + _theResult___fst_exp__h469802 ; + assign out_f_sfd__h378711 = + (_theResult___exp__h378433 == 8'd255 && + _theResult___sfd__h378434 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h378431 ; - assign out_f_sfd__h424398 = - (_theResult___exp__h424120 == 8'd255 && - _theResult___sfd__h424121 != 23'd0) ? + _theResult___sfd__h378434 ; + assign out_f_sfd__h424401 = + (_theResult___exp__h424123 == 8'd255 && + _theResult___sfd__h424124 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h424121 ; - assign out_f_sfd__h470086 = - (_theResult___exp__h469808 == 8'd255 && - _theResult___sfd__h469809 != 23'd0) ? + _theResult___sfd__h424124 ; + assign out_f_sfd__h470089 = + (_theResult___exp__h469811 == 8'd255 && + _theResult___sfd__h469812 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h469809 ; - assign out_sfd__h351930 = - sfdin__h351404[34] ? - _theResult___sfd__h351927 : - sfdin__h351404[56:34] ; - assign out_sfd__h360512 = - _theResult___snd__h360017[34] ? - _theResult___sfd__h360509 : - _theResult___snd__h360017[56:34] ; - assign out_sfd__h369696 = - sfdin__h369170[34] ? - _theResult___sfd__h369693 : - sfdin__h369170[56:34] ; - assign out_sfd__h378332 = - _theResult___snd__h377807[34] ? - _theResult___sfd__h378329 : - _theResult___snd__h377807[56:34] ; - assign out_sfd__h397620 = - sfdin__h397094[34] ? - _theResult___sfd__h397617 : - sfdin__h397094[56:34] ; - assign out_sfd__h406202 = - _theResult___snd__h405707[34] ? - _theResult___sfd__h406199 : - _theResult___snd__h405707[56:34] ; - assign out_sfd__h415386 = - sfdin__h414860[34] ? - _theResult___sfd__h415383 : - sfdin__h414860[56:34] ; - assign out_sfd__h424022 = - _theResult___snd__h423497[34] ? - _theResult___sfd__h424019 : - _theResult___snd__h423497[56:34] ; - assign out_sfd__h443308 = - sfdin__h442782[34] ? - _theResult___sfd__h443305 : - sfdin__h442782[56:34] ; - assign out_sfd__h451890 = - _theResult___snd__h451395[34] ? - _theResult___sfd__h451887 : - _theResult___snd__h451395[56:34] ; - assign out_sfd__h461074 = - sfdin__h460548[34] ? - _theResult___sfd__h461071 : - sfdin__h460548[56:34] ; - assign out_sfd__h469710 = - _theResult___snd__h469185[34] ? - _theResult___sfd__h469707 : - _theResult___snd__h469185[56:34] ; - assign out_sfd__h499331 = - _theResult___snd__h498623[5] ? - _theResult___sfd__h499328 : - _theResult___snd__h498623[56:5] ; - assign out_sfd__h508982 = - sfdin__h508243[5] ? - _theResult___sfd__h508979 : - sfdin__h508243[56:5] ; - assign out_sfd__h517766 = - _theResult___snd__h517028[5] ? - _theResult___sfd__h517763 : - _theResult___snd__h517028[56:5] ; - assign out_sfd__h538132 = - _theResult___snd__h537424[5] ? - _theResult___sfd__h538129 : - _theResult___snd__h537424[56:5] ; - assign out_sfd__h547783 = - sfdin__h547044[5] ? - _theResult___sfd__h547780 : - sfdin__h547044[56:5] ; - assign out_sfd__h556567 = - _theResult___snd__h555829[5] ? - _theResult___sfd__h556564 : - _theResult___snd__h555829[56:5] ; - assign out_sfd__h577333 = - _theResult___snd__h576625[5] ? - _theResult___sfd__h577330 : - _theResult___snd__h576625[56:5] ; - assign out_sfd__h586984 = - sfdin__h586245[5] ? - _theResult___sfd__h586981 : - sfdin__h586245[56:5] ; - assign out_sfd__h595768 = - _theResult___snd__h595030[5] ? - _theResult___sfd__h595765 : - _theResult___snd__h595030[56:5] ; - assign pend_ints__h645387 = + _theResult___sfd__h469812 ; + assign out_sfd__h351933 = + sfdin__h351407[34] ? + _theResult___sfd__h351930 : + sfdin__h351407[56:34] ; + assign out_sfd__h360515 = + _theResult___snd__h360020[34] ? + _theResult___sfd__h360512 : + _theResult___snd__h360020[56:34] ; + assign out_sfd__h369699 = + sfdin__h369173[34] ? + _theResult___sfd__h369696 : + sfdin__h369173[56:34] ; + assign out_sfd__h378335 = + _theResult___snd__h377810[34] ? + _theResult___sfd__h378332 : + _theResult___snd__h377810[56:34] ; + assign out_sfd__h397623 = + sfdin__h397097[34] ? + _theResult___sfd__h397620 : + sfdin__h397097[56:34] ; + assign out_sfd__h406205 = + _theResult___snd__h405710[34] ? + _theResult___sfd__h406202 : + _theResult___snd__h405710[56:34] ; + assign out_sfd__h415389 = + sfdin__h414863[34] ? + _theResult___sfd__h415386 : + sfdin__h414863[56:34] ; + assign out_sfd__h424025 = + _theResult___snd__h423500[34] ? + _theResult___sfd__h424022 : + _theResult___snd__h423500[56:34] ; + assign out_sfd__h443311 = + sfdin__h442785[34] ? + _theResult___sfd__h443308 : + sfdin__h442785[56:34] ; + assign out_sfd__h451893 = + _theResult___snd__h451398[34] ? + _theResult___sfd__h451890 : + _theResult___snd__h451398[56:34] ; + assign out_sfd__h461077 = + sfdin__h460551[34] ? + _theResult___sfd__h461074 : + sfdin__h460551[56:34] ; + assign out_sfd__h469713 = + _theResult___snd__h469188[34] ? + _theResult___sfd__h469710 : + _theResult___snd__h469188[56:34] ; + assign out_sfd__h499335 = + _theResult___snd__h498627[5] ? + _theResult___sfd__h499332 : + _theResult___snd__h498627[56:5] ; + assign out_sfd__h508986 = + sfdin__h508247[5] ? + _theResult___sfd__h508983 : + sfdin__h508247[56:5] ; + assign out_sfd__h517770 = + _theResult___snd__h517032[5] ? + _theResult___sfd__h517767 : + _theResult___snd__h517032[56:5] ; + assign out_sfd__h538136 = + _theResult___snd__h537428[5] ? + _theResult___sfd__h538133 : + _theResult___snd__h537428[56:5] ; + assign out_sfd__h547787 = + sfdin__h547048[5] ? + _theResult___sfd__h547784 : + sfdin__h547048[56:5] ; + assign out_sfd__h556571 = + _theResult___snd__h555833[5] ? + _theResult___sfd__h556568 : + _theResult___snd__h555833[56:5] ; + assign out_sfd__h577337 = + _theResult___snd__h576629[5] ? + _theResult___sfd__h577334 : + _theResult___snd__h576629[56:5] ; + assign out_sfd__h586988 = + sfdin__h586249[5] ? + _theResult___sfd__h586985 : + sfdin__h586249[56:5] ; + assign out_sfd__h595772 = + _theResult___snd__h595034[5] ? + _theResult___sfd__h595769 : + _theResult___snd__h595034[56:5] ; + assign pend_ints__h645396 = { csrf_debug_int_pend_read__1649_CONCAT_0b0_2637_ETC___d12647, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ; - assign prv__h707133 = csrf_prv_reg ; - assign prv__h707177 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h473077 = + assign prv__h707142 = csrf_prv_reg ; + assign prv__h707186 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h473080 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_12_TO_0___h645909 = + assign r1__read_BITS_12_TO_0___h645918 = { 3'd0, csrf_mideleg_11_reg, 1'b0, @@ -28443,126 +28443,126 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h649313 = csrf_fs_reg ; - assign r1__read_BIT_20___h649941 = csrf_tw_reg ; - assign r1__read__h608832 = { r1__read__h608834, csrf_ie_vec_1 } ; - assign r1__read__h608834 = { r1__read__h608836, 2'b0 } ; - assign r1__read__h608836 = { r1__read__h608838, csrf_prev_ie_vec_0 } ; - assign r1__read__h608838 = { r1__read__h608840, csrf_prev_ie_vec_1 } ; - assign r1__read__h608840 = { r1__read__h608842, 2'b0 } ; - assign r1__read__h608842 = { r1__read__h608844, csrf_spp_reg } ; - assign r1__read__h608844 = { r1__read__h608846, 4'b0 } ; - assign r1__read__h608846 = { r1__read__h608848, csrf_fs_reg } ; - assign r1__read__h608848 = { r1__read__h608850, 2'd0 } ; - assign r1__read__h608850 = { r1__read__h608852, 1'b0 } ; - assign r1__read__h608852 = { r1__read__h608854, csrf_sum_reg } ; - assign r1__read__h608854 = { r1__read__h608856, csrf_mxr_reg } ; - assign r1__read__h608856 = { r1__read__h608858, 12'b0 } ; - assign r1__read__h608858 = { r1__read__h608860, 2'b10 } ; - assign r1__read__h608860 = { r__h608864, 29'b0 } ; - assign r1__read__h609236 = - { r1__read__h609238, csrf_software_int_en_vec_1 } ; - assign r1__read__h609238 = { r1__read__h609240, 2'b0 } ; - assign r1__read__h609240 = { r1__read__h609242, csrf_timer_int_en_vec_0 } ; - assign r1__read__h609242 = { r1__read__h609244, csrf_timer_int_en_vec_1 } ; - assign r1__read__h609244 = { r1__read__h609246, 2'b0 } ; - assign r1__read__h609246 = - { r1__read__h609248, csrf_external_int_en_vec_0 } ; - assign r1__read__h609248 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h609766 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h609771 = { r1__read__h609773, csrf_scounteren_tm_reg } ; - assign r1__read__h609773 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h609784 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h609790 = - { r1__read__h609792, csrf_software_int_pend_vec_1 } ; - assign r1__read__h609792 = { r1__read__h609794, 2'b0 } ; - assign r1__read__h609794 = - { r1__read__h609796, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h609796 = - { r1__read__h609798, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h609798 = { r1__read__h609800, 2'b0 } ; - assign r1__read__h609800 = - { r1__read__h609802, csrf_external_int_pend_vec_0 } ; - assign r1__read__h609802 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610020 = { vm_mode_reg__read__h610026, 16'd0 } ; - assign r1__read__h610043 = { r1__read__h610045, csrf_ie_vec_1 } ; - assign r1__read__h610045 = { r1__read__h610047, 1'b0 } ; - assign r1__read__h610047 = { r1__read__h610049, csrf_ie_vec_3 } ; - assign r1__read__h610049 = { r1__read__h610051, csrf_prev_ie_vec_0 } ; - assign r1__read__h610051 = { r1__read__h610053, csrf_prev_ie_vec_1 } ; - assign r1__read__h610053 = { r1__read__h610055, 1'b0 } ; - assign r1__read__h610055 = { r1__read__h610057, csrf_prev_ie_vec_3 } ; - assign r1__read__h610057 = { r1__read__h610059, csrf_spp_reg } ; - assign r1__read__h610059 = { r1__read__h610061, 2'b0 } ; - assign r1__read__h610061 = { r1__read__h610063, csrf_mpp_reg } ; - assign r1__read__h610063 = { r1__read__h610065, csrf_fs_reg } ; - assign r1__read__h610065 = { r1__read__h610067, 2'd0 } ; - assign r1__read__h610067 = { r1__read__h610069, csrf_mprv_reg } ; - assign r1__read__h610069 = { r1__read__h610071, csrf_sum_reg } ; - assign r1__read__h610071 = { r1__read__h610073, csrf_mxr_reg } ; - assign r1__read__h610073 = { r1__read__h610075, csrf_tvm_reg } ; - assign r1__read__h610075 = { r1__read__h610077, csrf_tw_reg } ; - assign r1__read__h610077 = { r1__read__h610079, csrf_tsr_reg } ; - assign r1__read__h610079 = { r1__read__h610081, 9'b0 } ; - assign r1__read__h610081 = { r1__read__h610083, 2'b10 } ; - assign r1__read__h610083 = { r1__read__h610085, 2'b10 } ; - assign r1__read__h610085 = { r__h608864, 27'b0 } ; - assign r1__read__h610180 = { r1__read__h610182, 1'b0 } ; - assign r1__read__h610182 = { r1__read__h610184, csrf_medeleg_13_11_reg } ; - assign r1__read__h610184 = { r1__read__h610186, 1'b0 } ; - assign r1__read__h610186 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h610197 = { r1__read__h610199, 1'b0 } ; - assign r1__read__h610199 = { r1__read__h610201, csrf_mideleg_5_3_reg } ; - assign r1__read__h610201 = { r1__read__h610203, 1'b0 } ; - assign r1__read__h610203 = { r1__read__h610205, csrf_mideleg_9_7_reg } ; - assign r1__read__h610205 = { r1__read__h610207, 1'b0 } ; - assign r1__read__h610207 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h610221 = - { r1__read__h610223, csrf_software_int_en_vec_1 } ; - assign r1__read__h610223 = { r1__read__h610225, 1'b0 } ; - assign r1__read__h610225 = - { r1__read__h610227, csrf_software_int_en_vec_3 } ; - assign r1__read__h610227 = { r1__read__h610229, csrf_timer_int_en_vec_0 } ; - assign r1__read__h610229 = { r1__read__h610231, csrf_timer_int_en_vec_1 } ; - assign r1__read__h610231 = { r1__read__h610233, 1'b0 } ; - assign r1__read__h610233 = { r1__read__h610235, csrf_timer_int_en_vec_3 } ; - assign r1__read__h610235 = - { r1__read__h610237, csrf_external_int_en_vec_0 } ; - assign r1__read__h610237 = - { r1__read__h610239, csrf_external_int_en_vec_1 } ; - assign r1__read__h610239 = { r1__read__h610241, 1'b0 } ; - assign r1__read__h610241 = { 52'd4, csrf_external_int_en_vec_3 } ; - assign r1__read__h610339 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h610344 = { r1__read__h610346, csrf_mcounteren_tm_reg } ; - assign r1__read__h610346 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h610357 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h610363 = - { r1__read__h610365, csrf_software_int_pend_vec_1 } ; - assign r1__read__h610365 = { r1__read__h610367, 1'b0 } ; - assign r1__read__h610367 = - { r1__read__h610369, csrf_software_int_pend_vec_3 } ; - assign r1__read__h610369 = - { r1__read__h610371, csrf_timer_int_pend_vec_0 } ; - assign r1__read__h610371 = - { r1__read__h610373, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h610373 = { r1__read__h610375, 1'b0 } ; - assign r1__read__h610375 = - { r1__read__h610377, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h610377 = - { r1__read__h610379, csrf_external_int_pend_vec_0 } ; - assign r1__read__h610379 = - { r1__read__h610381, csrf_external_int_pend_vec_1 } ; - assign r1__read__h610381 = { r1__read__h610383, 1'b0 } ; - assign r1__read__h610383 = - { r1__read__h610385, csrf_external_int_pend_vec_3 } ; - assign r1__read__h610385 = { r1__read__h610387, 2'b0 } ; - assign r1__read__h610387 = { 49'b0, csrf_debug_int_pend } ; - assign rVal1__h478957 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h478958 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h473103 = + assign r1__read_BITS_13_TO_12___h649322 = csrf_fs_reg ; + assign r1__read_BIT_20___h649950 = csrf_tw_reg ; + assign r1__read__h608837 = { r1__read__h608839, csrf_ie_vec_1 } ; + assign r1__read__h608839 = { r1__read__h608841, 2'b0 } ; + assign r1__read__h608841 = { r1__read__h608843, csrf_prev_ie_vec_0 } ; + assign r1__read__h608843 = { r1__read__h608845, csrf_prev_ie_vec_1 } ; + assign r1__read__h608845 = { r1__read__h608847, 2'b0 } ; + assign r1__read__h608847 = { r1__read__h608849, csrf_spp_reg } ; + assign r1__read__h608849 = { r1__read__h608851, 4'b0 } ; + assign r1__read__h608851 = { r1__read__h608853, csrf_fs_reg } ; + assign r1__read__h608853 = { r1__read__h608855, 2'd0 } ; + assign r1__read__h608855 = { r1__read__h608857, 1'b0 } ; + assign r1__read__h608857 = { r1__read__h608859, csrf_sum_reg } ; + assign r1__read__h608859 = { r1__read__h608861, csrf_mxr_reg } ; + assign r1__read__h608861 = { r1__read__h608863, 12'b0 } ; + assign r1__read__h608863 = { r1__read__h608865, 2'b10 } ; + assign r1__read__h608865 = { r__h608869, 29'b0 } ; + assign r1__read__h609241 = + { r1__read__h609243, csrf_software_int_en_vec_1 } ; + assign r1__read__h609243 = { r1__read__h609245, 2'b0 } ; + assign r1__read__h609245 = { r1__read__h609247, csrf_timer_int_en_vec_0 } ; + assign r1__read__h609247 = { r1__read__h609249, csrf_timer_int_en_vec_1 } ; + assign r1__read__h609249 = { r1__read__h609251, 2'b0 } ; + assign r1__read__h609251 = + { r1__read__h609253, csrf_external_int_en_vec_0 } ; + assign r1__read__h609253 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h609771 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h609776 = { r1__read__h609778, csrf_scounteren_tm_reg } ; + assign r1__read__h609778 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h609789 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h609795 = + { r1__read__h609797, csrf_software_int_pend_vec_1 } ; + assign r1__read__h609797 = { r1__read__h609799, 2'b0 } ; + assign r1__read__h609799 = + { r1__read__h609801, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h609801 = + { r1__read__h609803, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h609803 = { r1__read__h609805, 2'b0 } ; + assign r1__read__h609805 = + { r1__read__h609807, csrf_external_int_pend_vec_0 } ; + assign r1__read__h609807 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610025 = { vm_mode_reg__read__h610031, 16'd0 } ; + assign r1__read__h610048 = { r1__read__h610050, csrf_ie_vec_1 } ; + assign r1__read__h610050 = { r1__read__h610052, 1'b0 } ; + assign r1__read__h610052 = { r1__read__h610054, csrf_ie_vec_3 } ; + assign r1__read__h610054 = { r1__read__h610056, csrf_prev_ie_vec_0 } ; + assign r1__read__h610056 = { r1__read__h610058, csrf_prev_ie_vec_1 } ; + assign r1__read__h610058 = { r1__read__h610060, 1'b0 } ; + assign r1__read__h610060 = { r1__read__h610062, csrf_prev_ie_vec_3 } ; + assign r1__read__h610062 = { r1__read__h610064, csrf_spp_reg } ; + assign r1__read__h610064 = { r1__read__h610066, 2'b0 } ; + assign r1__read__h610066 = { r1__read__h610068, csrf_mpp_reg } ; + assign r1__read__h610068 = { r1__read__h610070, csrf_fs_reg } ; + assign r1__read__h610070 = { r1__read__h610072, 2'd0 } ; + assign r1__read__h610072 = { r1__read__h610074, csrf_mprv_reg } ; + assign r1__read__h610074 = { r1__read__h610076, csrf_sum_reg } ; + assign r1__read__h610076 = { r1__read__h610078, csrf_mxr_reg } ; + assign r1__read__h610078 = { r1__read__h610080, csrf_tvm_reg } ; + assign r1__read__h610080 = { r1__read__h610082, csrf_tw_reg } ; + assign r1__read__h610082 = { r1__read__h610084, csrf_tsr_reg } ; + assign r1__read__h610084 = { r1__read__h610086, 9'b0 } ; + assign r1__read__h610086 = { r1__read__h610088, 2'b10 } ; + assign r1__read__h610088 = { r1__read__h610090, 2'b10 } ; + assign r1__read__h610090 = { r__h608869, 27'b0 } ; + assign r1__read__h610185 = { r1__read__h610187, 1'b0 } ; + assign r1__read__h610187 = { r1__read__h610189, csrf_medeleg_13_11_reg } ; + assign r1__read__h610189 = { r1__read__h610191, 1'b0 } ; + assign r1__read__h610191 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h610202 = { r1__read__h610204, 1'b0 } ; + assign r1__read__h610204 = { r1__read__h610206, csrf_mideleg_5_3_reg } ; + assign r1__read__h610206 = { r1__read__h610208, 1'b0 } ; + assign r1__read__h610208 = { r1__read__h610210, csrf_mideleg_9_7_reg } ; + assign r1__read__h610210 = { r1__read__h610212, 1'b0 } ; + assign r1__read__h610212 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h610226 = + { r1__read__h610228, csrf_software_int_en_vec_1 } ; + assign r1__read__h610228 = { r1__read__h610230, 1'b0 } ; + assign r1__read__h610230 = + { r1__read__h610232, csrf_software_int_en_vec_3 } ; + assign r1__read__h610232 = { r1__read__h610234, csrf_timer_int_en_vec_0 } ; + assign r1__read__h610234 = { r1__read__h610236, csrf_timer_int_en_vec_1 } ; + assign r1__read__h610236 = { r1__read__h610238, 1'b0 } ; + assign r1__read__h610238 = { r1__read__h610240, csrf_timer_int_en_vec_3 } ; + assign r1__read__h610240 = + { r1__read__h610242, csrf_external_int_en_vec_0 } ; + assign r1__read__h610242 = + { r1__read__h610244, csrf_external_int_en_vec_1 } ; + assign r1__read__h610244 = { r1__read__h610246, 1'b0 } ; + assign r1__read__h610246 = { 52'd4, csrf_external_int_en_vec_3 } ; + assign r1__read__h610344 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h610349 = { r1__read__h610351, csrf_mcounteren_tm_reg } ; + assign r1__read__h610351 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h610362 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h610368 = + { r1__read__h610370, csrf_software_int_pend_vec_1 } ; + assign r1__read__h610370 = { r1__read__h610372, 1'b0 } ; + assign r1__read__h610372 = + { r1__read__h610374, csrf_software_int_pend_vec_3 } ; + assign r1__read__h610374 = + { r1__read__h610376, csrf_timer_int_pend_vec_0 } ; + assign r1__read__h610376 = + { r1__read__h610378, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h610378 = { r1__read__h610380, 1'b0 } ; + assign r1__read__h610380 = + { r1__read__h610382, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h610382 = + { r1__read__h610384, csrf_external_int_pend_vec_0 } ; + assign r1__read__h610384 = + { r1__read__h610386, csrf_external_int_pend_vec_1 } ; + assign r1__read__h610386 = { r1__read__h610388, 1'b0 } ; + assign r1__read__h610388 = + { r1__read__h610390, csrf_external_int_pend_vec_3 } ; + assign r1__read__h610390 = { r1__read__h610392, 2'b0 } ; + assign r1__read__h610392 = { 49'b0, csrf_debug_int_pend } ; + assign rVal1__h478961 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h478962 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h473106 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h608864 = csrf_fs_reg == 2'b11 ; + assign r__h608869 = csrf_fs_reg == 2'b11 ; assign regRenamingTable_RDY_rename_0_getRename__3087__ETC___d13688 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && @@ -28662,12 +28662,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd3 && fetchStage$pipelines_0_first[194:192] != 3'd4) && coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ; - assign renaming_spec_bits__h675339 = + assign renaming_spec_bits__h675348 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h672105 : + y_avValue_snd_fst__h672114 : specTagManager$currentSpecBits ; - assign res_data__h335086 = { 32'd0, x__h335098 } ; - assign res_data__h335091 = + assign res_data__h335089 = { 32'd0, x__h335101 } ; + assign res_data__h335094 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -28680,8 +28680,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h380781 = { 32'd0, x__h380793 } ; - assign res_data__h380786 = + assign res_data__h380784 = { 32'd0, x__h380796 } ; + assign res_data__h380789 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -28694,8 +28694,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h426469 = { 32'd0, x__h426481 } ; - assign res_data__h426474 = + assign res_data__h426472 = { 32'd0, x__h426484 } ; + assign res_data__h426477 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -28708,7 +28708,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h335087 = + assign res_fflags__h335090 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -28776,7 +28776,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ; - assign res_fflags__h380782 = + assign res_fflags__h380785 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -28844,7 +28844,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ; - assign res_fflags__h426470 = + assign res_fflags__h426473 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -28912,35 +28912,35 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ; - assign resp_addr__h289190 = + assign resp_addr__h289193 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h361551 = + assign result__h361554 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] | - guard__h361546 } ; - assign result__h407241 = + guard__h361549 } ; + assign result__h407244 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] | - guard__h407236 } ; - assign result__h452929 = + guard__h407239 } ; + assign result__h452932 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] | - guard__h452924 } ; - assign result__h500626 = + guard__h452927 } ; + assign result__h500630 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8645[0] | - guard__h500621 } ; - assign result__h539427 = + guard__h500625 } ; + assign result__h539431 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10118[0] | - guard__h539422 } ; - assign result__h578628 = + guard__h539426 } ; + assign result__h578632 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9355[0] | - guard__h578623 } ; - assign result__h641096 = w__h641091 & y__h641125 ; - assign result__h641147 = ~x__h641146 ; + guard__h578627 } ; + assign result__h641105 = w__h641100 & y__h641134 ; + assign result__h641156 = ~x__h641155 ; assign rob_RDY_enqPort_0_enq__2627_AND_regRenamingTab_ETC___d13095 = rob$RDY_enqPort_0_enq && regRenamingTable$RDY_rename_0_claimRename && @@ -28972,12 +28972,12 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13639) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q261 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h649444 = + assign rs1__h649453 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h606844 = { r1__read__h610020, csrf_ppn_reg } ; + assign satp_csr__read__h606849 = { r1__read__h610025, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 && @@ -28997,298 +28997,298 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 && IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ; - assign sbIdx__h156309 = + assign sbIdx__h156310 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h606642 = - { r1__read__h609784, csrf_scause_code_reg } ; - assign scounteren_csr__read__h606504 = - { r1__read__h609771, csrf_scounteren_cy_reg } ; - assign sfd__h335694 = { value__h343921, 3'd0 } ; - assign sfd__h351502 = + assign scause_csr__read__h606647 = + { r1__read__h609789, csrf_scause_code_reg } ; + assign scounteren_csr__read__h606509 = + { r1__read__h609776, csrf_scounteren_cy_reg } ; + assign sfd__h335697 = { value__h343924, 3'd0 } ; + assign sfd__h351505 = { 1'b0, - _theResult___fst_exp__h351410 != 8'd0, - sfdin__h351404[56:34] } + + _theResult___fst_exp__h351413 != 8'd0, + sfdin__h351407[56:34] } + 25'd1 ; - assign sfd__h360084 = + assign sfd__h360087 = { 1'b0, - _theResult___fst_exp__h360066 != 8'd0, - _theResult___snd__h360017[56:34] } + + _theResult___fst_exp__h360069 != 8'd0, + _theResult___snd__h360020[56:34] } + 25'd1 ; - assign sfd__h369268 = + assign sfd__h369271 = { 1'b0, - _theResult___fst_exp__h369176 != 8'd0, - sfdin__h369170[56:34] } + + _theResult___fst_exp__h369179 != 8'd0, + sfdin__h369173[56:34] } + 25'd1 ; - assign sfd__h377880 = + assign sfd__h377883 = { 1'b0, - _theResult___fst_exp__h377861 != 8'd0, - _theResult___snd__h377807[56:34] } + + _theResult___fst_exp__h377864 != 8'd0, + _theResult___snd__h377810[56:34] } + 25'd1 ; - assign sfd__h381389 = { value__h389611, 3'd0 } ; - assign sfd__h397192 = + assign sfd__h381392 = { value__h389614, 3'd0 } ; + assign sfd__h397195 = { 1'b0, - _theResult___fst_exp__h397100 != 8'd0, - sfdin__h397094[56:34] } + + _theResult___fst_exp__h397103 != 8'd0, + sfdin__h397097[56:34] } + 25'd1 ; - assign sfd__h405774 = + assign sfd__h405777 = { 1'b0, - _theResult___fst_exp__h405756 != 8'd0, - _theResult___snd__h405707[56:34] } + + _theResult___fst_exp__h405759 != 8'd0, + _theResult___snd__h405710[56:34] } + 25'd1 ; - assign sfd__h414958 = + assign sfd__h414961 = { 1'b0, - _theResult___fst_exp__h414866 != 8'd0, - sfdin__h414860[56:34] } + + _theResult___fst_exp__h414869 != 8'd0, + sfdin__h414863[56:34] } + 25'd1 ; - assign sfd__h423570 = + assign sfd__h423573 = { 1'b0, - _theResult___fst_exp__h423551 != 8'd0, - _theResult___snd__h423497[56:34] } + + _theResult___fst_exp__h423554 != 8'd0, + _theResult___snd__h423500[56:34] } + 25'd1 ; - assign sfd__h427077 = { value__h435299, 3'd0 } ; - assign sfd__h442880 = + assign sfd__h427080 = { value__h435302, 3'd0 } ; + assign sfd__h442883 = { 1'b0, - _theResult___fst_exp__h442788 != 8'd0, - sfdin__h442782[56:34] } + + _theResult___fst_exp__h442791 != 8'd0, + sfdin__h442785[56:34] } + 25'd1 ; - assign sfd__h451462 = + assign sfd__h451465 = { 1'b0, - _theResult___fst_exp__h451444 != 8'd0, - _theResult___snd__h451395[56:34] } + + _theResult___fst_exp__h451447 != 8'd0, + _theResult___snd__h451398[56:34] } + 25'd1 ; - assign sfd__h460646 = + assign sfd__h460649 = { 1'b0, - _theResult___fst_exp__h460554 != 8'd0, - sfdin__h460548[56:34] } + + _theResult___fst_exp__h460557 != 8'd0, + sfdin__h460551[56:34] } + 25'd1 ; - assign sfd__h469258 = + assign sfd__h469261 = { 1'b0, - _theResult___fst_exp__h469239 != 8'd0, - _theResult___snd__h469185[56:34] } + + _theResult___fst_exp__h469242 != 8'd0, + _theResult___snd__h469188[56:34] } + 25'd1 ; - assign sfd__h479671 = { value__h484229, 32'd0 } ; - assign sfd__h498690 = + assign sfd__h479675 = { value__h484233, 32'd0 } ; + assign sfd__h498694 = { 1'b0, - _theResult___fst_exp__h498672 != 11'd0, - _theResult___snd__h498623[56:5] } + + _theResult___fst_exp__h498676 != 11'd0, + _theResult___snd__h498627[56:5] } + 54'd1 ; - assign sfd__h508341 = + assign sfd__h508345 = { 1'b0, - _theResult___fst_exp__h508249 != 11'd0, - sfdin__h508243[56:5] } + + _theResult___fst_exp__h508253 != 11'd0, + sfdin__h508247[56:5] } + 54'd1 ; - assign sfd__h517101 = + assign sfd__h517105 = { 1'b0, - _theResult___fst_exp__h517082 != 11'd0, - _theResult___snd__h517028[56:5] } + + _theResult___fst_exp__h517086 != 11'd0, + _theResult___snd__h517032[56:5] } + 54'd1 ; - assign sfd__h518613 = { value__h523030, 32'd0 } ; - assign sfd__h537491 = + assign sfd__h518617 = { value__h523034, 32'd0 } ; + assign sfd__h537495 = { 1'b0, - _theResult___fst_exp__h537473 != 11'd0, - _theResult___snd__h537424[56:5] } + + _theResult___fst_exp__h537477 != 11'd0, + _theResult___snd__h537428[56:5] } + 54'd1 ; - assign sfd__h547142 = + assign sfd__h547146 = { 1'b0, - _theResult___fst_exp__h547050 != 11'd0, - sfdin__h547044[56:5] } + + _theResult___fst_exp__h547054 != 11'd0, + sfdin__h547048[56:5] } + 54'd1 ; - assign sfd__h555902 = + assign sfd__h555906 = { 1'b0, - _theResult___fst_exp__h555883 != 11'd0, - _theResult___snd__h555829[56:5] } + + _theResult___fst_exp__h555887 != 11'd0, + _theResult___snd__h555833[56:5] } + 54'd1 ; - assign sfd__h557814 = { value__h562231, 32'd0 } ; - assign sfd__h576692 = + assign sfd__h557818 = { value__h562235, 32'd0 } ; + assign sfd__h576696 = { 1'b0, - _theResult___fst_exp__h576674 != 11'd0, - _theResult___snd__h576625[56:5] } + + _theResult___fst_exp__h576678 != 11'd0, + _theResult___snd__h576629[56:5] } + 54'd1 ; - assign sfd__h586343 = + assign sfd__h586347 = { 1'b0, - _theResult___fst_exp__h586251 != 11'd0, - sfdin__h586245[56:5] } + + _theResult___fst_exp__h586255 != 11'd0, + sfdin__h586249[56:5] } + 54'd1 ; - assign sfd__h595103 = + assign sfd__h595107 = { 1'b0, - _theResult___fst_exp__h595084 != 11'd0, - _theResult___snd__h595030[56:5] } + + _theResult___fst_exp__h595088 != 11'd0, + _theResult___snd__h595034[56:5] } + 54'd1 ; - assign sfdin__h351404 = - _theResult____h343299[56] ? - _theResult___snd__h351421 : - _theResult___snd__h351432 ; - assign sfdin__h369170 = - _theResult____h360938[56] ? - _theResult___snd__h369187 : - _theResult___snd__h369198 ; - assign sfdin__h397094 = - _theResult____h388991[56] ? - _theResult___snd__h397111 : - _theResult___snd__h397122 ; - assign sfdin__h414860 = - _theResult____h406628[56] ? - _theResult___snd__h414877 : - _theResult___snd__h414888 ; - assign sfdin__h442782 = - _theResult____h434679[56] ? - _theResult___snd__h442799 : - _theResult___snd__h442810 ; - assign sfdin__h460548 = - _theResult____h452316[56] ? - _theResult___snd__h460565 : - _theResult___snd__h460576 ; - assign sfdin__h508243 = - _theResult____h500013[56] ? - _theResult___snd__h508260 : - _theResult___snd__h508271 ; - assign sfdin__h547044 = - _theResult____h538814[56] ? - _theResult___snd__h547061 : - _theResult___snd__h547072 ; - assign sfdin__h586245 = - _theResult____h578015[56] ? - _theResult___snd__h586262 : - _theResult___snd__h586273 ; - assign shiftData__h180513 = - coreFix_memExe_regToExeQ$first[75:12] << x__h180645 ; - assign sie_csr__read__h606408 = - { r1__read__h609236, csrf_software_int_en_vec_0 } ; - assign sip_csr__read__h606781 = - { r1__read__h609790, csrf_software_int_pend_vec_0 } ; - assign spec_bits__h678434 = specTagManager$currentSpecBits | y__h678447 ; - assign sstatus_csr__read__h606339 = { r1__read__h608832, csrf_ie_vec_0 } ; - assign stvec_csr__read__h606451 = - { r1__read__h609766, csrf_stvec_mode_low_reg } ; + assign sfdin__h351407 = + _theResult____h343302[56] ? + _theResult___snd__h351424 : + _theResult___snd__h351435 ; + assign sfdin__h369173 = + _theResult____h360941[56] ? + _theResult___snd__h369190 : + _theResult___snd__h369201 ; + assign sfdin__h397097 = + _theResult____h388994[56] ? + _theResult___snd__h397114 : + _theResult___snd__h397125 ; + assign sfdin__h414863 = + _theResult____h406631[56] ? + _theResult___snd__h414880 : + _theResult___snd__h414891 ; + assign sfdin__h442785 = + _theResult____h434682[56] ? + _theResult___snd__h442802 : + _theResult___snd__h442813 ; + assign sfdin__h460551 = + _theResult____h452319[56] ? + _theResult___snd__h460568 : + _theResult___snd__h460579 ; + assign sfdin__h508247 = + _theResult____h500017[56] ? + _theResult___snd__h508264 : + _theResult___snd__h508275 ; + assign sfdin__h547048 = + _theResult____h538818[56] ? + _theResult___snd__h547065 : + _theResult___snd__h547076 ; + assign sfdin__h586249 = + _theResult____h578019[56] ? + _theResult___snd__h586266 : + _theResult___snd__h586277 ; + assign shiftData__h180516 = + coreFix_memExe_regToExeQ$first[75:12] << x__h180648 ; + assign sie_csr__read__h606413 = + { r1__read__h609241, csrf_software_int_en_vec_0 } ; + assign sip_csr__read__h606786 = + { r1__read__h609795, csrf_software_int_pend_vec_0 } ; + assign spec_bits__h678443 = specTagManager$currentSpecBits | y__h678456 ; + assign sstatus_csr__read__h606344 = { r1__read__h608837, csrf_ie_vec_0 } ; + assign stvec_csr__read__h606456 = + { r1__read__h609771, csrf_stvec_mode_low_reg } ; assign upd__h3639 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; assign upd__h4956 = n__read__h6134 + 64'd1 ; - assign v__h293161 = + assign v__h293163 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ? - v__h293392 : + v__h293394 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h293392 = + assign v__h293394 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h296506 = + assign v__h296508 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ? - v__h297024 : + v__h297026 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h297024 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h307020 = + assign v__h297026 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h307022 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ? - v__h307251 : + v__h307253 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h307251 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h310896 = + assign v__h307253 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h310898 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ? - v__h311127 : + v__h311129 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h311127 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h325497 = + assign v__h311129 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h325499 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ? - v__h325728 : + v__h325730 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h325728 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h328722 = + assign v__h325730 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h328724 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ? - v__h328953 : + v__h328955 : coreFix_memExe_forwardQ_enqP ; - assign v__h328953 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h600770 = + assign v__h328955 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h600774 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h600780 : + v__h600784 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h600780 = + assign v__h600784 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h601415 = v__h600770 - 2'd1 ; - assign v__h604750 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605655 ; - assign v__h628436 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629189 ; - assign vaddr__h180508 = + assign v__h601419 = v__h600774 - 2'd1 ; + assign v__h604754 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605660 ; + assign v__h628444 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h629197 ; + assign vaddr__h180511 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ; - assign value__h343921 = + assign value__h343924 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h389611 = + assign value__h389614 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h435299 = + assign value__h435302 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h484229 = + assign value__h484233 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ; - assign value__h523030 = + assign value__h523034 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ; - assign value__h562231 = + assign value__h562235 = { 1'b0, coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ; - assign vm_mode_reg__read__h610026 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h641091 = + assign vm_mode_reg__read__h610031 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h641100 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h641147 : + result__h641156 : 12'd4095 ; - assign x__h152883 = + assign x__h152884 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h152889 = + assign x__h152890 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h156430 = { 3'd0, sbIdx__h156309 } ; - assign x__h156436 = + assign x__h156431 = { 3'd0, sbIdx__h156310 } ; + assign x__h156437 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h159246 = + assign x__h159247 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h159250 = + assign x__h159251 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161098 = + assign x__h161099 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : @@ -29298,130 +29298,130 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h180422 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179510 ; - assign x__h180423 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180116 ; - assign x__h180645 = { vaddr__h180508[2:0], 3'b0 } ; - assign x__h190899 = + assign x__h180425 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179513 ; + assign x__h180426 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180119 ; + assign x__h180648 = { vaddr__h180511[2:0], 3'b0 } ; + assign x__h190902 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h190136[63:32] : - curData__h190136[31:0] ; + curData__h190139[63:32] : + curData__h190139[31:0] ; assign x__h20210 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h284498 = + assign x__h284501 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h284510 = + assign x__h284513 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h286364 = + assign x__h286367 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h299371 = + assign x__h299373 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h335098 = - { (_theResult___exp__h378430 != 8'd255 || - _theResult___sfd__h378431 == 23'd0) && + assign x__h335101 = + { (_theResult___exp__h378433 != 8'd255 || + _theResult___sfd__h378434 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136, - out_f_exp__h378707, - out_f_sfd__h378708 } ; - assign x__h361648 = - sfd__h335694 << (x__h361681[11] ? 12'hAAA : x__h361681) ; - assign x__h361681 = + out_f_exp__h378710, + out_f_sfd__h378711 } ; + assign x__h361651 = + sfd__h335697 << (x__h361684[11] ? 12'hAAA : x__h361684) ; + assign x__h361684 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ; - assign x__h380793 = - { (_theResult___exp__h424120 != 8'd255 || - _theResult___sfd__h424121 == 23'd0) && + assign x__h380796 = + { (_theResult___exp__h424123 != 8'd255 || + _theResult___sfd__h424124 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528, - out_f_exp__h424397, - out_f_sfd__h424398 } ; - assign x__h407338 = - sfd__h381389 << (x__h407371[11] ? 12'hAAA : x__h407371) ; - assign x__h407371 = + out_f_exp__h424400, + out_f_sfd__h424401 } ; + assign x__h407341 = + sfd__h381392 << (x__h407374[11] ? 12'hAAA : x__h407374) ; + assign x__h407374 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ; - assign x__h426481 = - { (_theResult___exp__h469808 != 8'd255 || - _theResult___sfd__h469809 == 23'd0) && + assign x__h426484 = + { (_theResult___exp__h469811 != 8'd255 || + _theResult___sfd__h469812 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920, - out_f_exp__h470085, - out_f_sfd__h470086 } ; - assign x__h453026 = - sfd__h427077 << (x__h453059[11] ? 12'hAAA : x__h453059) ; - assign x__h453059 = + out_f_exp__h470088, + out_f_sfd__h470089 } ; + assign x__h453029 = + sfd__h427080 << (x__h453062[11] ? 12'hAAA : x__h453062) ; + assign x__h453062 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ; assign x__h45579 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h478866 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476002 ; - assign x__h478867 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476610 ; - assign x__h478868 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477212 ; + assign x__h478870 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476006 ; + assign x__h478871 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476614 ; + assign x__h478872 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477216 ; assign x__h48115 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h500721 = sfd__h479671 << x__h500754 ; - assign x__h500754 = + assign x__h500725 = sfd__h479675 << x__h500758 ; + assign x__h500758 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8641 ; - assign x__h539522 = sfd__h518613 << x__h539555 ; - assign x__h539555 = + assign x__h539526 = sfd__h518617 << x__h539559 ; + assign x__h539559 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10114 ; - assign x__h578723 = sfd__h557814 << x__h578756 ; - assign x__h578756 = + assign x__h578727 = sfd__h557818 << x__h578760 ; + assign x__h578760 = 12'd57 - _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9351 ; - assign x__h600271 = a__h599835[63] ^ b__h599836[63] ; - assign x__h608817 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h613028 = + assign x__h600275 = a__h599839[63] ^ b__h599840[63] ; + assign x__h608822 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h613033 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h605865 : - v__h604750 ; - assign x__h613029 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610917 ; - assign x__h634247 = + rVal1__h605870 : + v__h604754 ; + assign x__h613034 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610922 ; + assign x__h634256 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h629397 : - v__h628436 ; - assign x__h634248 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632146 ; - assign x__h641095 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h641146 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h688716 = + rVal1__h629405 : + v__h628444 ; + assign x__h634257 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h632155 ; + assign x__h641104 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h641155 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h688725 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h694797 = { cause_code__h692180, 2'b0 } ; - assign x__h702593 = { 1'b0, csrf_spp_reg } ; - assign x__h705866 = + assign x__h694806 = { cause_code__h692189, 2'b0 } ; + assign x__h702602 = { 1'b0, csrf_spp_reg } ; + assign x__h705875 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_fst__h705688 : + y_avValue_snd_snd_snd_fst__h705697 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 ; assign x__h75524 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h311294 = + assign x_addr__h311296 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; @@ -29429,29 +29429,29 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h667940 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h682683 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h649128 = csrf_frm_reg ; - assign x_quotient__h472392 = + assign x_data_imm__h667949 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h682692 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h649137 = csrf_frm_reg ; + assign x_quotient__h472395 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h473077 : + q___1__h473080 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h606248 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h472393 = + assign x_reg_ifc__read__h606253 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h472396 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h473103 : + r___1__h473106 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h252023 = + assign y__h252026 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h641125 = ~x__h641095 ; - assign y__h645898 = + assign y__h641134 = ~x__h641104 ; + assign y__h645907 = { 3'd7, ~csrf_mideleg_11_reg, 1'd1, @@ -29460,71 +29460,71 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h678447 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h705641 = + assign y__h678456 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h705650 = NOT_rob_deqPort_0_canDeq__4555_4556_OR_rob_deq_ETC___d14742 ? - y_avValue_snd_snd_snd_snd_snd__h705694 : + y_avValue_snd_snd_snd_snd_snd__h705703 : IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 ; - assign y_avValue__h179510 = + assign y_avValue__h179513 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ; - assign y_avValue__h180116 = + assign y_avValue__h180119 = NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ; - assign y_avValue__h476002 = + assign y_avValue__h476006 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ; - assign y_avValue__h476610 = + assign y_avValue__h476614 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ; - assign y_avValue__h477212 = + assign y_avValue__h477216 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ; - assign y_avValue__h605655 = + assign y_avValue__h605660 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11330 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11708 ; - assign y_avValue__h610917 = + assign y_avValue__h610922 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1303_1_ETC___d11358 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__130_ETC___d11720 ; - assign y_avValue__h629189 = + assign y_avValue__h629197 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12125 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12317 ; - assign y_avValue__h632146 = + assign y_avValue__h632155 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2098_2_ETC___d12153 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12329 ; - assign y_avValue__h693058 = + assign y_avValue__h693067 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694782 + { 58'd0, x__h694797 } : - base__h694782 ; - assign y_avValue__h694819 = + base__h694791 + { 58'd0, x__h694806 } : + base__h694791 ; + assign y_avValue__h694828 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ? - base__h694985 + { 58'd0, x__h694797 } : - base__h694985 ; - assign y_avValue_fst__h671831 = + base__h694994 + { 58'd0, x__h694806 } : + base__h694994 ; + assign y_avValue_fst__h671840 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h678434 : + spec_bits__h678443 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672105 = + assign y_avValue_snd_fst__h672114 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13207) ? - y_avValue_snd_fst__h672140 : + y_avValue_snd_fst__h672149 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h672140 = + assign y_avValue_snd_fst__h672149 = IF_fetchStage_pipelines_0_first__2605_BITS_194_ETC___d13268 ? - y_avValue_fst__h671831 : + y_avValue_fst__h671840 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h705125 = + assign y_avValue_snd_fst__h705134 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29538,7 +29538,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h705678 = + assign y_avValue_snd_fst__h705687 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29551,11 +29551,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 : - y_avValue_snd_fst__h705707 ; - assign y_avValue_snd_fst__h705707 = + y_avValue_snd_fst__h705716 ; + assign y_avValue_snd_fst__h705716 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14749 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_snd_snd_fst__h705135 = + assign y_avValue_snd_snd_snd_fst__h705144 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29569,7 +29569,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h705688 = + assign y_avValue_snd_snd_snd_fst__h705697 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29582,11 +29582,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 : - y_avValue_snd_snd_snd_fst__h705717 ; - assign y_avValue_snd_snd_snd_fst__h705717 = + y_avValue_snd_snd_snd_fst__h705726 ; + assign y_avValue_snd_snd_snd_fst__h705726 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14771 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705141 = + assign y_avValue_snd_snd_snd_snd_snd__h705150 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[186:182] == 5'd0 || @@ -29600,7 +29600,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[186:182] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h705694 = + assign y_avValue_snd_snd_snd_snd_snd__h705703 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[186:182] == 5'd0 || @@ -29613,8 +29613,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[186:182] == 5'd19 || rob$deqPort_1_deq_data[186:182] == 5'd20) ? IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 : - y_avValue_snd_snd_snd_snd_snd__h705723 ; - assign y_avValue_snd_snd_snd_snd_snd__h705723 = + y_avValue_snd_snd_snd_snd_snd__h705732 ; + assign y_avValue_snd_snd_snd_snd_snd__h705732 = IF_rob_deqPort_0_canDeq__4555_THEN_IF_NOT_rob__ETC___d14663 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -29633,28 +29633,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h194346 = + x__h194349 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -29670,28 +29670,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h283065 = + x__h283068 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -29701,10 +29701,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h287286 = + addr__h287289 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h287286 = + addr__h287289 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -29713,36 +29713,36 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h190136 = + curData__h190139 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) - 4'd0, 4'd3: trap_val__h693211 = commitStage_commitTrap[132:69]; - default: trap_val__h693211 = + 4'd0, 4'd3: trap_val__h693220 = commitStage_commitTrap[132:69]; + default: trap_val__h693220 = (commitStage_commitTrap[3:0] != 4'd2 && commitStage_commitTrap[3:0] != 4'd8 && commitStage_commitTrap[3:0] != 4'd9 && @@ -29757,247 +29757,247 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h288835 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h288835 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h288838 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h606118 or - frm_csr__read__h606129 or - fcsr_csr__read__h606143 or - sstatus_csr__read__h606339 or - sie_csr__read__h606408 or - stvec_csr__read__h606451 or - scounteren_csr__read__h606504 or + fflags_csr__read__h606123 or + frm_csr__read__h606134 or + fcsr_csr__read__h606148 or + sstatus_csr__read__h606344 or + sie_csr__read__h606413 or + stvec_csr__read__h606456 or + scounteren_csr__read__h606509 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606642 or + scause_csr__read__h606647 or csrf_stval_csr or - sip_csr__read__h606781 or - satp_csr__read__h606844 or - mstatus_csr__read__h606987 or - medeleg_csr__read__h607135 or - mideleg_csr__read__h607230 or - mie_csr__read__h607361 or - mtvec_csr__read__h607443 or - mcounteren_csr__read__h607535 or + sip_csr__read__h606786 or + satp_csr__read__h606849 or + mstatus_csr__read__h606992 or + medeleg_csr__read__h607140 or + mideleg_csr__read__h607235 or + mie_csr__read__h607366 or + mtvec_csr__read__h607448 or + mcounteren_csr__read__h607540 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607790 or + mcause_csr__read__h607795 or csrf_mtval_csr or - mip_csr__read__h608030 or - x_reg_ifc__read__h606248 or - n__read__h608134 or n__read__h608325 or csrf_time_reg) + mip_csr__read__h608035 or + x_reg_ifc__read__h606253 or + n__read__h608139 or n__read__h608330 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h605865 = fflags_csr__read__h606118; - 12'd2: rVal1__h605865 = frm_csr__read__h606129; - 12'd3: rVal1__h605865 = fcsr_csr__read__h606143; - 12'd256: rVal1__h605865 = sstatus_csr__read__h606339; - 12'd260: rVal1__h605865 = sie_csr__read__h606408; - 12'd261: rVal1__h605865 = stvec_csr__read__h606451; - 12'd262: rVal1__h605865 = scounteren_csr__read__h606504; - 12'd320: rVal1__h605865 = csrf_sscratch_csr; - 12'd321: rVal1__h605865 = csrf_sepc_csr; - 12'd322: rVal1__h605865 = scause_csr__read__h606642; - 12'd323: rVal1__h605865 = csrf_stval_csr; - 12'd324: rVal1__h605865 = sip_csr__read__h606781; - 12'd384: rVal1__h605865 = satp_csr__read__h606844; - 12'd768: rVal1__h605865 = mstatus_csr__read__h606987; - 12'd769: rVal1__h605865 = 64'h8000000000141129; - 12'd770: rVal1__h605865 = medeleg_csr__read__h607135; - 12'd771: rVal1__h605865 = mideleg_csr__read__h607230; - 12'd772: rVal1__h605865 = mie_csr__read__h607361; - 12'd773: rVal1__h605865 = mtvec_csr__read__h607443; - 12'd774: rVal1__h605865 = mcounteren_csr__read__h607535; - 12'd832: rVal1__h605865 = csrf_mscratch_csr; - 12'd833: rVal1__h605865 = csrf_mepc_csr; - 12'd834: rVal1__h605865 = mcause_csr__read__h607790; - 12'd835: rVal1__h605865 = csrf_mtval_csr; - 12'd836: rVal1__h605865 = mip_csr__read__h608030; - 12'd2048: rVal1__h605865 = 64'd0; - 12'd2049: rVal1__h605865 = x_reg_ifc__read__h606248; - 12'd2816, 12'd3072: rVal1__h605865 = n__read__h608134; - 12'd2818, 12'd3074: rVal1__h605865 = n__read__h608325; - 12'd3073: rVal1__h605865 = csrf_time_reg; - default: rVal1__h605865 = 64'd0; + 12'd1: rVal1__h605870 = fflags_csr__read__h606123; + 12'd2: rVal1__h605870 = frm_csr__read__h606134; + 12'd3: rVal1__h605870 = fcsr_csr__read__h606148; + 12'd256: rVal1__h605870 = sstatus_csr__read__h606344; + 12'd260: rVal1__h605870 = sie_csr__read__h606413; + 12'd261: rVal1__h605870 = stvec_csr__read__h606456; + 12'd262: rVal1__h605870 = scounteren_csr__read__h606509; + 12'd320: rVal1__h605870 = csrf_sscratch_csr; + 12'd321: rVal1__h605870 = csrf_sepc_csr; + 12'd322: rVal1__h605870 = scause_csr__read__h606647; + 12'd323: rVal1__h605870 = csrf_stval_csr; + 12'd324: rVal1__h605870 = sip_csr__read__h606786; + 12'd384: rVal1__h605870 = satp_csr__read__h606849; + 12'd768: rVal1__h605870 = mstatus_csr__read__h606992; + 12'd769: rVal1__h605870 = 64'h8000000000141129; + 12'd770: rVal1__h605870 = medeleg_csr__read__h607140; + 12'd771: rVal1__h605870 = mideleg_csr__read__h607235; + 12'd772: rVal1__h605870 = mie_csr__read__h607366; + 12'd773: rVal1__h605870 = mtvec_csr__read__h607448; + 12'd774: rVal1__h605870 = mcounteren_csr__read__h607540; + 12'd832: rVal1__h605870 = csrf_mscratch_csr; + 12'd833: rVal1__h605870 = csrf_mepc_csr; + 12'd834: rVal1__h605870 = mcause_csr__read__h607795; + 12'd835: rVal1__h605870 = csrf_mtval_csr; + 12'd836: rVal1__h605870 = mip_csr__read__h608035; + 12'd2048: rVal1__h605870 = 64'd0; + 12'd2049: rVal1__h605870 = x_reg_ifc__read__h606253; + 12'd2816, 12'd3072: rVal1__h605870 = n__read__h608139; + 12'd2818, 12'd3074: rVal1__h605870 = n__read__h608330; + 12'd3073: rVal1__h605870 = csrf_time_reg; + default: rVal1__h605870 = 64'd0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h606118 or - frm_csr__read__h606129 or - fcsr_csr__read__h606143 or - sstatus_csr__read__h606339 or - sie_csr__read__h606408 or - stvec_csr__read__h606451 or - scounteren_csr__read__h606504 or + fflags_csr__read__h606123 or + frm_csr__read__h606134 or + fcsr_csr__read__h606148 or + sstatus_csr__read__h606344 or + sie_csr__read__h606413 or + stvec_csr__read__h606456 or + scounteren_csr__read__h606509 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h606642 or + scause_csr__read__h606647 or csrf_stval_csr or - sip_csr__read__h606781 or - satp_csr__read__h606844 or - mstatus_csr__read__h606987 or - medeleg_csr__read__h607135 or - mideleg_csr__read__h607230 or - mie_csr__read__h607361 or - mtvec_csr__read__h607443 or - mcounteren_csr__read__h607535 or + sip_csr__read__h606786 or + satp_csr__read__h606849 or + mstatus_csr__read__h606992 or + medeleg_csr__read__h607140 or + mideleg_csr__read__h607235 or + mie_csr__read__h607366 or + mtvec_csr__read__h607448 or + mcounteren_csr__read__h607540 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h607790 or + mcause_csr__read__h607795 or csrf_mtval_csr or - mip_csr__read__h608030 or - x_reg_ifc__read__h606248 or - n__read__h608134 or n__read__h608325 or csrf_time_reg) + mip_csr__read__h608035 or + x_reg_ifc__read__h606253 or + n__read__h608139 or n__read__h608330 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h629397 = fflags_csr__read__h606118; - 12'd2: rVal1__h629397 = frm_csr__read__h606129; - 12'd3: rVal1__h629397 = fcsr_csr__read__h606143; - 12'd256: rVal1__h629397 = sstatus_csr__read__h606339; - 12'd260: rVal1__h629397 = sie_csr__read__h606408; - 12'd261: rVal1__h629397 = stvec_csr__read__h606451; - 12'd262: rVal1__h629397 = scounteren_csr__read__h606504; - 12'd320: rVal1__h629397 = csrf_sscratch_csr; - 12'd321: rVal1__h629397 = csrf_sepc_csr; - 12'd322: rVal1__h629397 = scause_csr__read__h606642; - 12'd323: rVal1__h629397 = csrf_stval_csr; - 12'd324: rVal1__h629397 = sip_csr__read__h606781; - 12'd384: rVal1__h629397 = satp_csr__read__h606844; - 12'd768: rVal1__h629397 = mstatus_csr__read__h606987; - 12'd769: rVal1__h629397 = 64'h8000000000141129; - 12'd770: rVal1__h629397 = medeleg_csr__read__h607135; - 12'd771: rVal1__h629397 = mideleg_csr__read__h607230; - 12'd772: rVal1__h629397 = mie_csr__read__h607361; - 12'd773: rVal1__h629397 = mtvec_csr__read__h607443; - 12'd774: rVal1__h629397 = mcounteren_csr__read__h607535; - 12'd832: rVal1__h629397 = csrf_mscratch_csr; - 12'd833: rVal1__h629397 = csrf_mepc_csr; - 12'd834: rVal1__h629397 = mcause_csr__read__h607790; - 12'd835: rVal1__h629397 = csrf_mtval_csr; - 12'd836: rVal1__h629397 = mip_csr__read__h608030; - 12'd2048: rVal1__h629397 = 64'd0; - 12'd2049: rVal1__h629397 = x_reg_ifc__read__h606248; - 12'd2816, 12'd3072: rVal1__h629397 = n__read__h608134; - 12'd2818, 12'd3074: rVal1__h629397 = n__read__h608325; - 12'd3073: rVal1__h629397 = csrf_time_reg; - default: rVal1__h629397 = 64'd0; + 12'd1: rVal1__h629405 = fflags_csr__read__h606123; + 12'd2: rVal1__h629405 = frm_csr__read__h606134; + 12'd3: rVal1__h629405 = fcsr_csr__read__h606148; + 12'd256: rVal1__h629405 = sstatus_csr__read__h606344; + 12'd260: rVal1__h629405 = sie_csr__read__h606413; + 12'd261: rVal1__h629405 = stvec_csr__read__h606456; + 12'd262: rVal1__h629405 = scounteren_csr__read__h606509; + 12'd320: rVal1__h629405 = csrf_sscratch_csr; + 12'd321: rVal1__h629405 = csrf_sepc_csr; + 12'd322: rVal1__h629405 = scause_csr__read__h606647; + 12'd323: rVal1__h629405 = csrf_stval_csr; + 12'd324: rVal1__h629405 = sip_csr__read__h606786; + 12'd384: rVal1__h629405 = satp_csr__read__h606849; + 12'd768: rVal1__h629405 = mstatus_csr__read__h606992; + 12'd769: rVal1__h629405 = 64'h8000000000141129; + 12'd770: rVal1__h629405 = medeleg_csr__read__h607140; + 12'd771: rVal1__h629405 = mideleg_csr__read__h607235; + 12'd772: rVal1__h629405 = mie_csr__read__h607366; + 12'd773: rVal1__h629405 = mtvec_csr__read__h607448; + 12'd774: rVal1__h629405 = mcounteren_csr__read__h607540; + 12'd832: rVal1__h629405 = csrf_mscratch_csr; + 12'd833: rVal1__h629405 = csrf_mepc_csr; + 12'd834: rVal1__h629405 = mcause_csr__read__h607795; + 12'd835: rVal1__h629405 = csrf_mtval_csr; + 12'd836: rVal1__h629405 = mip_csr__read__h608035; + 12'd2048: rVal1__h629405 = 64'd0; + 12'd2049: rVal1__h629405 = x_reg_ifc__read__h606253; + 12'd2816, 12'd3072: rVal1__h629405 = n__read__h608139; + 12'd2818, 12'd3074: rVal1__h629405 = n__read__h608330; + 12'd3073: rVal1__h629405 = csrf_time_reg; + default: rVal1__h629405 = 64'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h388973 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h388976 = 8'd255; 3'd2: - _theResult___fst_exp__h388973 = + _theResult___fst_exp__h388976 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h388973 = + _theResult___fst_exp__h388976 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h388973 = 8'd254; - default: _theResult___fst_exp__h388973 = 8'd0; + 3'd4: _theResult___fst_exp__h388976 = 8'd254; + default: _theResult___fst_exp__h388976 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h343281 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h343284 = 8'd255; 3'd2: - _theResult___fst_exp__h343281 = + _theResult___fst_exp__h343284 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h343281 = + _theResult___fst_exp__h343284 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h343281 = 8'd254; - default: _theResult___fst_exp__h343281 = 8'd0; + 3'd4: _theResult___fst_exp__h343284 = 8'd254; + default: _theResult___fst_exp__h343284 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h343282 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h343285 = 23'd0; 3'd2: - _theResult___fst_sfd__h343282 = + _theResult___fst_sfd__h343285 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h343282 = + _theResult___fst_sfd__h343285 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h343282 = 23'd8388607; - default: _theResult___fst_sfd__h343282 = 23'd0; + 3'd4: _theResult___fst_sfd__h343285 = 23'd8388607; + default: _theResult___fst_sfd__h343285 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h388974 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h388977 = 23'd0; 3'd2: - _theResult___fst_sfd__h388974 = + _theResult___fst_sfd__h388977 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h388974 = + _theResult___fst_sfd__h388977 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h388974 = 23'd8388607; - default: _theResult___fst_sfd__h388974 = 23'd0; + 3'd4: _theResult___fst_sfd__h388977 = 23'd8388607; + default: _theResult___fst_sfd__h388977 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h434661 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h434664 = 8'd255; 3'd2: - _theResult___fst_exp__h434661 = + _theResult___fst_exp__h434664 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h434661 = + _theResult___fst_exp__h434664 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h434661 = 8'd254; - default: _theResult___fst_exp__h434661 = 8'd0; + 3'd4: _theResult___fst_exp__h434664 = 8'd254; + default: _theResult___fst_exp__h434664 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h434662 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h434665 = 23'd0; 3'd2: - _theResult___fst_sfd__h434662 = + _theResult___fst_sfd__h434665 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h434662 = + _theResult___fst_sfd__h434665 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h434662 = 23'd8388607; - default: _theResult___fst_sfd__h434662 = 23'd0; + 3'd4: _theResult___fst_sfd__h434665 = 23'd8388607; + default: _theResult___fst_sfd__h434665 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30124,16 +30124,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h692195 = commitStage_commitTrap[3:0]; - default: i__h692195 = 4'd15; + i__h692204 = commitStage_commitTrap[3:0]; + default: i__h692204 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[3:0]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11: - i__h692355 = commitStage_commitTrap[3:0]; - default: i__h692355 = 4'd14; + i__h692364 = commitStage_commitTrap[3:0]; + default: i__h692364 = 4'd14; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -30374,446 +30374,446 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352018 or - _theResult___fst_exp__h360066 or - out_exp__h360511 or _theResult___exp__h360508) + always@(guard__h352021 or + _theResult___fst_exp__h360069 or + out_exp__h360514 or _theResult___exp__h360511) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 = - _theResult___fst_exp__h360066; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = + _theResult___fst_exp__h360069; 2'b10: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 = - out_exp__h360511; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = + out_exp__h360514; 2'b11: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 = - _theResult___exp__h360508; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 = + _theResult___exp__h360511; endcase end - always@(guard__h352018 or - _theResult___fst_exp__h360066 or _theResult___exp__h360508) + always@(guard__h352021 or + _theResult___fst_exp__h360069 or _theResult___exp__h360511) begin - case (guard__h352018) + case (guard__h352021) 2'b0: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25 = - _theResult___fst_exp__h360066; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = + _theResult___fst_exp__h360069; 2'b01, 2'b10, 2'b11: - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25 = - _theResult___exp__h360508; + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 = + _theResult___exp__h360511; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24 or - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25 or + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24 or + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or - _theResult___fst_exp__h360066) + _theResult___fst_exp__h360069) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h360586 = - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q24; + _theResult___fst_exp__h360589 = + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q24; 3'd1: - _theResult___fst_exp__h360586 = - CASE_guard52018_0b0_theResult___fst_exp60066_0_ETC__q25; + _theResult___fst_exp__h360589 = + CASE_guard52021_0b0_theResult___fst_exp60069_0_ETC__q25; 3'd2: - _theResult___fst_exp__h360586 = + _theResult___fst_exp__h360589 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528; 3'd3: - _theResult___fst_exp__h360586 = + _theResult___fst_exp__h360589 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530; - 3'd4: _theResult___fst_exp__h360586 = _theResult___fst_exp__h360066; - default: _theResult___fst_exp__h360586 = 8'd0; + 3'd4: _theResult___fst_exp__h360589 = _theResult___fst_exp__h360069; + default: _theResult___fst_exp__h360589 = 8'd0; endcase end - always@(guard__h343309 or - _theResult___fst_exp__h351410 or - out_exp__h351929 or _theResult___exp__h351926) + always@(guard__h343312 or + _theResult___fst_exp__h351413 or + out_exp__h351932 or _theResult___exp__h351929) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 = - _theResult___fst_exp__h351410; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = + _theResult___fst_exp__h351413; 2'b10: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 = - out_exp__h351929; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = + out_exp__h351932; 2'b11: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 = - _theResult___exp__h351926; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 = + _theResult___exp__h351929; endcase end - always@(guard__h343309 or - _theResult___fst_exp__h351410 or _theResult___exp__h351926) + always@(guard__h343312 or + _theResult___fst_exp__h351413 or _theResult___exp__h351929) begin - case (guard__h343309) + case (guard__h343312) 2'b0: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27 = - _theResult___fst_exp__h351410; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = + _theResult___fst_exp__h351413; 2'b01, 2'b10, 2'b11: - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27 = - _theResult___exp__h351926; + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 = + _theResult___exp__h351929; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26 or - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27 or + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26 or + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or - _theResult___fst_exp__h351410) + _theResult___fst_exp__h351413) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h352004 = - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q26; + _theResult___fst_exp__h352007 = + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q26; 3'd1: - _theResult___fst_exp__h352004 = - CASE_guard43309_0b0_theResult___fst_exp51410_0_ETC__q27; + _theResult___fst_exp__h352007 = + CASE_guard43312_0b0_theResult___fst_exp51413_0_ETC__q27; 3'd2: - _theResult___fst_exp__h352004 = + _theResult___fst_exp__h352007 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306; 3'd3: - _theResult___fst_exp__h352004 = + _theResult___fst_exp__h352007 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309; - 3'd4: _theResult___fst_exp__h352004 = _theResult___fst_exp__h351410; - default: _theResult___fst_exp__h352004 = 8'd0; + 3'd4: _theResult___fst_exp__h352007 = _theResult___fst_exp__h351413; + default: _theResult___fst_exp__h352007 = 8'd0; endcase end - always@(guard__h360948 or - _theResult___fst_exp__h369176 or - out_exp__h369695 or _theResult___exp__h369692) + always@(guard__h360951 or + _theResult___fst_exp__h369179 or + out_exp__h369698 or _theResult___exp__h369695) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 = - _theResult___fst_exp__h369176; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = + _theResult___fst_exp__h369179; 2'b10: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 = - out_exp__h369695; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = + out_exp__h369698; 2'b11: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 = - _theResult___exp__h369692; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 = + _theResult___exp__h369695; endcase end - always@(guard__h360948 or - _theResult___fst_exp__h369176 or _theResult___exp__h369692) + always@(guard__h360951 or + _theResult___fst_exp__h369179 or _theResult___exp__h369695) begin - case (guard__h360948) + case (guard__h360951) 2'b0: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33 = - _theResult___fst_exp__h369176; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = + _theResult___fst_exp__h369179; 2'b01, 2'b10, 2'b11: - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33 = - _theResult___exp__h369692; + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 = + _theResult___exp__h369695; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32 or - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33 or + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32 or + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or - _theResult___fst_exp__h369176) + _theResult___fst_exp__h369179) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h369770 = - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q32; + _theResult___fst_exp__h369773 = + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q32; 3'd1: - _theResult___fst_exp__h369770 = - CASE_guard60948_0b0_theResult___fst_exp69176_0_ETC__q33; + _theResult___fst_exp__h369773 = + CASE_guard60951_0b0_theResult___fst_exp69179_0_ETC__q33; 3'd2: - _theResult___fst_exp__h369770 = + _theResult___fst_exp__h369773 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853; 3'd3: - _theResult___fst_exp__h369770 = + _theResult___fst_exp__h369773 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855; - 3'd4: _theResult___fst_exp__h369770 = _theResult___fst_exp__h369176; - default: _theResult___fst_exp__h369770 = 8'd0; + 3'd4: _theResult___fst_exp__h369773 = _theResult___fst_exp__h369179; + default: _theResult___fst_exp__h369773 = 8'd0; endcase end - always@(guard__h369784 or - _theResult___fst_exp__h377861 or - out_exp__h378331 or _theResult___exp__h378328) + always@(guard__h369787 or + _theResult___fst_exp__h377864 or + out_exp__h378334 or _theResult___exp__h378331) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 = - _theResult___fst_exp__h377861; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = + _theResult___fst_exp__h377864; 2'b10: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 = - out_exp__h378331; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = + out_exp__h378334; 2'b11: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 = - _theResult___exp__h378328; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 = + _theResult___exp__h378331; endcase end - always@(guard__h369784 or - _theResult___fst_exp__h377861 or _theResult___exp__h378328) + always@(guard__h369787 or + _theResult___fst_exp__h377864 or _theResult___exp__h378331) begin - case (guard__h369784) + case (guard__h369787) 2'b0: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38 = - _theResult___fst_exp__h377861; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = + _theResult___fst_exp__h377864; 2'b01, 2'b10, 2'b11: - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38 = - _theResult___exp__h378328; + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 = + _theResult___exp__h378331; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37 or - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38 or + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37 or + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or - _theResult___fst_exp__h377861) + _theResult___fst_exp__h377864) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h378406 = - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q37; + _theResult___fst_exp__h378409 = + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q37; 3'd1: - _theResult___fst_exp__h378406 = - CASE_guard69784_0b0_theResult___fst_exp77861_0_ETC__q38; + _theResult___fst_exp__h378409 = + CASE_guard69787_0b0_theResult___fst_exp77864_0_ETC__q38; 3'd2: - _theResult___fst_exp__h378406 = + _theResult___fst_exp__h378409 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922; 3'd3: - _theResult___fst_exp__h378406 = + _theResult___fst_exp__h378409 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924; - 3'd4: _theResult___fst_exp__h378406 = _theResult___fst_exp__h377861; - default: _theResult___fst_exp__h378406 = 8'd0; + 3'd4: _theResult___fst_exp__h378409 = _theResult___fst_exp__h377864; + default: _theResult___fst_exp__h378409 = 8'd0; endcase end - always@(guard__h352018 or - _theResult___snd__h360017 or - out_sfd__h360512 or _theResult___sfd__h360509) + always@(guard__h352021 or + _theResult___snd__h360020 or + out_sfd__h360515 or _theResult___sfd__h360512) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 = - _theResult___snd__h360017[56:34]; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = + _theResult___snd__h360020[56:34]; 2'b10: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 = - out_sfd__h360512; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = + out_sfd__h360515; 2'b11: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 = - _theResult___sfd__h360509; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 = + _theResult___sfd__h360512; endcase end - always@(guard__h352018 or - _theResult___snd__h360017 or _theResult___sfd__h360509) + always@(guard__h352021 or + _theResult___snd__h360020 or _theResult___sfd__h360512) begin - case (guard__h352018) + case (guard__h352021) 2'b0: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40 = - _theResult___snd__h360017[56:34]; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = + _theResult___snd__h360020[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40 = - _theResult___sfd__h360509; + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 = + _theResult___sfd__h360512; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39 or - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40 or + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39 or + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or - _theResult___snd__h360017) + _theResult___snd__h360020) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h360587 = - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q39; + _theResult___fst_sfd__h360590 = + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q39; 3'd1: - _theResult___fst_sfd__h360587 = - CASE_guard52018_0b0_theResult___snd60017_BITS__ETC__q40; + _theResult___fst_sfd__h360590 = + CASE_guard52021_0b0_theResult___snd60020_BITS__ETC__q40; 3'd2: - _theResult___fst_sfd__h360587 = + _theResult___fst_sfd__h360590 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972; 3'd3: - _theResult___fst_sfd__h360587 = + _theResult___fst_sfd__h360590 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974; - 3'd4: _theResult___fst_sfd__h360587 = _theResult___snd__h360017[56:34]; - default: _theResult___fst_sfd__h360587 = 23'd0; + 3'd4: _theResult___fst_sfd__h360590 = _theResult___snd__h360020[56:34]; + default: _theResult___fst_sfd__h360590 = 23'd0; endcase end - always@(guard__h343309 or - sfdin__h351404 or out_sfd__h351930 or _theResult___sfd__h351927) + always@(guard__h343312 or + sfdin__h351407 or out_sfd__h351933 or _theResult___sfd__h351930) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 = - sfdin__h351404[56:34]; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = + sfdin__h351407[56:34]; 2'b10: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 = - out_sfd__h351930; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = + out_sfd__h351933; 2'b11: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 = - _theResult___sfd__h351927; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 = + _theResult___sfd__h351930; endcase end - always@(guard__h343309 or sfdin__h351404 or _theResult___sfd__h351927) + always@(guard__h343312 or sfdin__h351407 or _theResult___sfd__h351930) begin - case (guard__h343309) + case (guard__h343312) 2'b0: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42 = - sfdin__h351404[56:34]; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = + sfdin__h351407[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h351927; + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h351930; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41 or - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42 or + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41 or + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or - sfdin__h351404) + sfdin__h351407) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h352005 = - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q41; + _theResult___fst_sfd__h352008 = + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q41; 3'd1: - _theResult___fst_sfd__h352005 = - CASE_guard43309_0b0_sfdin51404_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h352008 = + CASE_guard43312_0b0_sfdin51407_BITS_56_TO_34_0_ETC__q42; 3'd2: - _theResult___fst_sfd__h352005 = + _theResult___fst_sfd__h352008 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953; 3'd3: - _theResult___fst_sfd__h352005 = + _theResult___fst_sfd__h352008 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955; - 3'd4: _theResult___fst_sfd__h352005 = sfdin__h351404[56:34]; - default: _theResult___fst_sfd__h352005 = 23'd0; + 3'd4: _theResult___fst_sfd__h352008 = sfdin__h351407[56:34]; + default: _theResult___fst_sfd__h352008 = 23'd0; endcase end - always@(guard__h360948 or - sfdin__h369170 or out_sfd__h369696 or _theResult___sfd__h369693) + always@(guard__h360951 or + sfdin__h369173 or out_sfd__h369699 or _theResult___sfd__h369696) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 = - sfdin__h369170[56:34]; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = + sfdin__h369173[56:34]; 2'b10: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 = - out_sfd__h369696; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = + out_sfd__h369699; 2'b11: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h369693; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h369696; endcase end - always@(guard__h360948 or sfdin__h369170 or _theResult___sfd__h369693) + always@(guard__h360951 or sfdin__h369173 or _theResult___sfd__h369696) begin - case (guard__h360948) + case (guard__h360951) 2'b0: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44 = - sfdin__h369170[56:34]; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = + sfdin__h369173[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h369693; + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h369696; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43 or - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44 or + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43 or + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or - sfdin__h369170) + sfdin__h369173) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h369771 = - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h369774 = + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q43; 3'd1: - _theResult___fst_sfd__h369771 = - CASE_guard60948_0b0_sfdin69170_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h369774 = + CASE_guard60951_0b0_sfdin69173_BITS_56_TO_34_0_ETC__q44; 3'd2: - _theResult___fst_sfd__h369771 = + _theResult___fst_sfd__h369774 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999; 3'd3: - _theResult___fst_sfd__h369771 = + _theResult___fst_sfd__h369774 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001; - 3'd4: _theResult___fst_sfd__h369771 = sfdin__h369170[56:34]; - default: _theResult___fst_sfd__h369771 = 23'd0; + 3'd4: _theResult___fst_sfd__h369774 = sfdin__h369173[56:34]; + default: _theResult___fst_sfd__h369774 = 23'd0; endcase end - always@(guard__h369784 or - _theResult___snd__h377807 or - out_sfd__h378332 or _theResult___sfd__h378329) + always@(guard__h369787 or + _theResult___snd__h377810 or + out_sfd__h378335 or _theResult___sfd__h378332) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 = - _theResult___snd__h377807[56:34]; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = + _theResult___snd__h377810[56:34]; 2'b10: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 = - out_sfd__h378332; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = + out_sfd__h378335; 2'b11: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 = - _theResult___sfd__h378329; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 = + _theResult___sfd__h378332; endcase end - always@(guard__h369784 or - _theResult___snd__h377807 or _theResult___sfd__h378329) + always@(guard__h369787 or + _theResult___snd__h377810 or _theResult___sfd__h378332) begin - case (guard__h369784) + case (guard__h369787) 2'b0: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46 = - _theResult___snd__h377807[56:34]; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = + _theResult___snd__h377810[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46 = - _theResult___sfd__h378329; + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 = + _theResult___sfd__h378332; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45 or - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46 or + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45 or + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or - _theResult___snd__h377807) + _theResult___snd__h377810) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h378407 = - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q45; + _theResult___fst_sfd__h378410 = + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q45; 3'd1: - _theResult___fst_sfd__h378407 = - CASE_guard69784_0b0_theResult___snd77807_BITS__ETC__q46; + _theResult___fst_sfd__h378410 = + CASE_guard69787_0b0_theResult___snd77810_BITS__ETC__q46; 3'd2: - _theResult___fst_sfd__h378407 = + _theResult___fst_sfd__h378410 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018; 3'd3: - _theResult___fst_sfd__h378407 = + _theResult___fst_sfd__h378410 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020; - 3'd4: _theResult___fst_sfd__h378407 = _theResult___snd__h377807[56:34]; - default: _theResult___fst_sfd__h378407 = 23'd0; + 3'd4: _theResult___fst_sfd__h378410 = _theResult___snd__h377810[56:34]; + default: _theResult___fst_sfd__h378410 = 23'd0; endcase end - always@(guard__h343309 or + always@(guard__h343312 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01, 2'b10: - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = - guard__h343309 == 2'b11 && + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 = + guard__h343312 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or - guard__h343309) + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or + guard__h343312) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - CASE_guard43309_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; + CASE_guard43312_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = - (guard__h343309 == 2'b0) ? + (guard__h343312 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h343309 == 2'b01 || guard__h343309 == 2'b10 || - guard__h343309 == 2'b11) && + (guard__h343312 == 2'b01 || guard__h343312 == 2'b10 || + guard__h343312 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 = @@ -30824,34 +30824,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352018 or + always@(guard__h352021 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01, 2'b10: - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h352018 == 2'b11 && + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h352021 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h352018) + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h352021) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - CASE_guard52018_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard52021_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = - (guard__h352018 == 2'b0) ? + (guard__h352021 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h352018 == 2'b01 || guard__h352018 == 2'b10 || - guard__h352018 == 2'b11) && + (guard__h352021 == 2'b01 || guard__h352021 == 2'b10 || + guard__h352021 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 = @@ -30862,34 +30862,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h343309 or + always@(guard__h343312 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h343309) + case (guard__h343312) 2'b0, 2'b01, 2'b10: - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h343309 != 2'b11 || + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h343312 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h343309) + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h343312) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - CASE_guard43309_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard43312_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = - (guard__h343309 == 2'b0) ? + (guard__h343312 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h343309 != 2'b01 && guard__h343309 != 2'b10 && - guard__h343309 != 2'b11 || + guard__h343312 != 2'b01 && guard__h343312 != 2'b10 && + guard__h343312 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 = @@ -30900,34 +30900,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h352018 or + always@(guard__h352021 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h352018) + case (guard__h352021) 2'b0, 2'b01, 2'b10: - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = - guard__h352018 != 2'b11 || + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 = + guard__h352021 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or - guard__h352018) + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or + guard__h352021) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - CASE_guard52018_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; + CASE_guard52021_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = - (guard__h352018 == 2'b0) ? + (guard__h352021 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h352018 != 2'b01 && guard__h352018 != 2'b10 && - guard__h352018 != 2'b11 || + guard__h352021 != 2'b01 && guard__h352021 != 2'b10 && + guard__h352021 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 = @@ -30938,34 +30938,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360948 or + always@(guard__h360951 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01, 2'b10: - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = - guard__h360948 == 2'b11 && + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 = + guard__h360951 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or - guard__h360948) + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or + guard__h360951) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - CASE_guard60948_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; + CASE_guard60951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = - (guard__h360948 == 2'b0) ? + (guard__h360951 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h360948 == 2'b01 || guard__h360948 == 2'b10 || - guard__h360948 == 2'b11) && + (guard__h360951 == 2'b01 || guard__h360951 == 2'b10 || + guard__h360951 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 = @@ -30976,34 +30976,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369784 or + always@(guard__h369787 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01, 2'b10: - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h369784 == 2'b11 && + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h369787 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h369784) + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h369787) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - CASE_guard69784_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard69787_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = - (guard__h369784 == 2'b0) ? + (guard__h369787 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h369784 == 2'b01 || guard__h369784 == 2'b10 || - guard__h369784 == 2'b11) && + (guard__h369787 == 2'b01 || guard__h369787 == 2'b10 || + guard__h369787 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 = @@ -31014,34 +31014,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h360948 or + always@(guard__h360951 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h360948) + case (guard__h360951) 2'b0, 2'b01, 2'b10: - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h360948 != 2'b11 || + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h360951 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h360948) + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h360951) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - CASE_guard60948_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard60951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = - (guard__h360948 == 2'b0) ? + (guard__h360951 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h360948 != 2'b01 && guard__h360948 != 2'b10 && - guard__h360948 != 2'b11 || + guard__h360951 != 2'b01 && guard__h360951 != 2'b10 && + guard__h360951 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 = @@ -31052,34 +31052,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h369784 or + always@(guard__h369787 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h369784) + case (guard__h369787) 2'b0, 2'b01, 2'b10: - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = - guard__h369784 != 2'b11 || + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 = + guard__h369787 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or - guard__h369784) + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or + guard__h369787) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - CASE_guard69784_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; + CASE_guard69787_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = - (guard__h369784 == 2'b0) ? + (guard__h369787 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h369784 != 2'b01 && guard__h369784 != 2'b10 && - guard__h369784 != 2'b11 || + guard__h369787 != 2'b01 && guard__h369787 != 2'b10 && + guard__h369787 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 = @@ -31103,446 +31103,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h397708 or - _theResult___fst_exp__h405756 or - out_exp__h406201 or _theResult___exp__h406198) + always@(guard__h397711 or + _theResult___fst_exp__h405759 or + out_exp__h406204 or _theResult___exp__h406201) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 = - _theResult___fst_exp__h405756; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = + _theResult___fst_exp__h405759; 2'b10: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 = - out_exp__h406201; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = + out_exp__h406204; 2'b11: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 = - _theResult___exp__h406198; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 = + _theResult___exp__h406201; endcase end - always@(guard__h397708 or - _theResult___fst_exp__h405756 or _theResult___exp__h406198) + always@(guard__h397711 or + _theResult___fst_exp__h405759 or _theResult___exp__h406201) begin - case (guard__h397708) + case (guard__h397711) 2'b0: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60 = - _theResult___fst_exp__h405756; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = + _theResult___fst_exp__h405759; 2'b01, 2'b10, 2'b11: - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60 = - _theResult___exp__h406198; + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 = + _theResult___exp__h406201; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59 or - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60 or + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59 or + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or - _theResult___fst_exp__h405756) + _theResult___fst_exp__h405759) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h406276 = - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q59; + _theResult___fst_exp__h406279 = + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q59; 3'd1: - _theResult___fst_exp__h406276 = - CASE_guard97708_0b0_theResult___fst_exp05756_0_ETC__q60; + _theResult___fst_exp__h406279 = + CASE_guard97711_0b0_theResult___fst_exp05759_0_ETC__q60; 3'd2: - _theResult___fst_exp__h406276 = + _theResult___fst_exp__h406279 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920; 3'd3: - _theResult___fst_exp__h406276 = + _theResult___fst_exp__h406279 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922; - 3'd4: _theResult___fst_exp__h406276 = _theResult___fst_exp__h405756; - default: _theResult___fst_exp__h406276 = 8'd0; + 3'd4: _theResult___fst_exp__h406279 = _theResult___fst_exp__h405759; + default: _theResult___fst_exp__h406279 = 8'd0; endcase end - always@(guard__h389001 or - _theResult___fst_exp__h397100 or - out_exp__h397619 or _theResult___exp__h397616) + always@(guard__h389004 or + _theResult___fst_exp__h397103 or + out_exp__h397622 or _theResult___exp__h397619) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 = - _theResult___fst_exp__h397100; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = + _theResult___fst_exp__h397103; 2'b10: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 = - out_exp__h397619; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = + out_exp__h397622; 2'b11: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 = - _theResult___exp__h397616; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 = + _theResult___exp__h397619; endcase end - always@(guard__h389001 or - _theResult___fst_exp__h397100 or _theResult___exp__h397616) + always@(guard__h389004 or + _theResult___fst_exp__h397103 or _theResult___exp__h397619) begin - case (guard__h389001) + case (guard__h389004) 2'b0: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62 = - _theResult___fst_exp__h397100; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = + _theResult___fst_exp__h397103; 2'b01, 2'b10, 2'b11: - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62 = - _theResult___exp__h397616; + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 = + _theResult___exp__h397619; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61 or - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62 or + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61 or + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or - _theResult___fst_exp__h397100) + _theResult___fst_exp__h397103) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h397694 = - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q61; + _theResult___fst_exp__h397697 = + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q61; 3'd1: - _theResult___fst_exp__h397694 = - CASE_guard89001_0b0_theResult___fst_exp97100_0_ETC__q62; + _theResult___fst_exp__h397697 = + CASE_guard89004_0b0_theResult___fst_exp97103_0_ETC__q62; 3'd2: - _theResult___fst_exp__h397694 = + _theResult___fst_exp__h397697 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698; 3'd3: - _theResult___fst_exp__h397694 = + _theResult___fst_exp__h397697 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701; - 3'd4: _theResult___fst_exp__h397694 = _theResult___fst_exp__h397100; - default: _theResult___fst_exp__h397694 = 8'd0; + 3'd4: _theResult___fst_exp__h397697 = _theResult___fst_exp__h397103; + default: _theResult___fst_exp__h397697 = 8'd0; endcase end - always@(guard__h406638 or - _theResult___fst_exp__h414866 or - out_exp__h415385 or _theResult___exp__h415382) + always@(guard__h406641 or + _theResult___fst_exp__h414869 or + out_exp__h415388 or _theResult___exp__h415385) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 = - _theResult___fst_exp__h414866; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = + _theResult___fst_exp__h414869; 2'b10: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 = - out_exp__h415385; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = + out_exp__h415388; 2'b11: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 = - _theResult___exp__h415382; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 = + _theResult___exp__h415385; endcase end - always@(guard__h406638 or - _theResult___fst_exp__h414866 or _theResult___exp__h415382) + always@(guard__h406641 or + _theResult___fst_exp__h414869 or _theResult___exp__h415385) begin - case (guard__h406638) + case (guard__h406641) 2'b0: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68 = - _theResult___fst_exp__h414866; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = + _theResult___fst_exp__h414869; 2'b01, 2'b10, 2'b11: - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68 = - _theResult___exp__h415382; + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 = + _theResult___exp__h415385; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67 or - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68 or + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67 or + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or - _theResult___fst_exp__h414866) + _theResult___fst_exp__h414869) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h415460 = - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q67; + _theResult___fst_exp__h415463 = + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q67; 3'd1: - _theResult___fst_exp__h415460 = - CASE_guard06638_0b0_theResult___fst_exp14866_0_ETC__q68; + _theResult___fst_exp__h415463 = + CASE_guard06641_0b0_theResult___fst_exp14869_0_ETC__q68; 3'd2: - _theResult___fst_exp__h415460 = + _theResult___fst_exp__h415463 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245; 3'd3: - _theResult___fst_exp__h415460 = + _theResult___fst_exp__h415463 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247; - 3'd4: _theResult___fst_exp__h415460 = _theResult___fst_exp__h414866; - default: _theResult___fst_exp__h415460 = 8'd0; + 3'd4: _theResult___fst_exp__h415463 = _theResult___fst_exp__h414869; + default: _theResult___fst_exp__h415463 = 8'd0; endcase end - always@(guard__h415474 or - _theResult___fst_exp__h423551 or - out_exp__h424021 or _theResult___exp__h424018) + always@(guard__h415477 or + _theResult___fst_exp__h423554 or + out_exp__h424024 or _theResult___exp__h424021) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 = - _theResult___fst_exp__h423551; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = + _theResult___fst_exp__h423554; 2'b10: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 = - out_exp__h424021; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = + out_exp__h424024; 2'b11: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 = - _theResult___exp__h424018; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 = + _theResult___exp__h424021; endcase end - always@(guard__h415474 or - _theResult___fst_exp__h423551 or _theResult___exp__h424018) + always@(guard__h415477 or + _theResult___fst_exp__h423554 or _theResult___exp__h424021) begin - case (guard__h415474) + case (guard__h415477) 2'b0: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73 = - _theResult___fst_exp__h423551; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = + _theResult___fst_exp__h423554; 2'b01, 2'b10, 2'b11: - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73 = - _theResult___exp__h424018; + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 = + _theResult___exp__h424021; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72 or - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73 or + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72 or + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or - _theResult___fst_exp__h423551) + _theResult___fst_exp__h423554) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h424096 = - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q72; + _theResult___fst_exp__h424099 = + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q72; 3'd1: - _theResult___fst_exp__h424096 = - CASE_guard15474_0b0_theResult___fst_exp23551_0_ETC__q73; + _theResult___fst_exp__h424099 = + CASE_guard15477_0b0_theResult___fst_exp23554_0_ETC__q73; 3'd2: - _theResult___fst_exp__h424096 = + _theResult___fst_exp__h424099 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314; 3'd3: - _theResult___fst_exp__h424096 = + _theResult___fst_exp__h424099 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316; - 3'd4: _theResult___fst_exp__h424096 = _theResult___fst_exp__h423551; - default: _theResult___fst_exp__h424096 = 8'd0; + 3'd4: _theResult___fst_exp__h424099 = _theResult___fst_exp__h423554; + default: _theResult___fst_exp__h424099 = 8'd0; endcase end - always@(guard__h397708 or - _theResult___snd__h405707 or - out_sfd__h406202 or _theResult___sfd__h406199) + always@(guard__h397711 or + _theResult___snd__h405710 or + out_sfd__h406205 or _theResult___sfd__h406202) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 = - _theResult___snd__h405707[56:34]; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = + _theResult___snd__h405710[56:34]; 2'b10: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 = - out_sfd__h406202; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = + out_sfd__h406205; 2'b11: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 = - _theResult___sfd__h406199; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 = + _theResult___sfd__h406202; endcase end - always@(guard__h397708 or - _theResult___snd__h405707 or _theResult___sfd__h406199) + always@(guard__h397711 or + _theResult___snd__h405710 or _theResult___sfd__h406202) begin - case (guard__h397708) + case (guard__h397711) 2'b0: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75 = - _theResult___snd__h405707[56:34]; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = + _theResult___snd__h405710[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75 = - _theResult___sfd__h406199; + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 = + _theResult___sfd__h406202; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74 or - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75 or + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74 or + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or - _theResult___snd__h405707) + _theResult___snd__h405710) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h406277 = - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q74; + _theResult___fst_sfd__h406280 = + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q74; 3'd1: - _theResult___fst_sfd__h406277 = - CASE_guard97708_0b0_theResult___snd05707_BITS__ETC__q75; + _theResult___fst_sfd__h406280 = + CASE_guard97711_0b0_theResult___snd05710_BITS__ETC__q75; 3'd2: - _theResult___fst_sfd__h406277 = + _theResult___fst_sfd__h406280 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364; 3'd3: - _theResult___fst_sfd__h406277 = + _theResult___fst_sfd__h406280 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366; - 3'd4: _theResult___fst_sfd__h406277 = _theResult___snd__h405707[56:34]; - default: _theResult___fst_sfd__h406277 = 23'd0; + 3'd4: _theResult___fst_sfd__h406280 = _theResult___snd__h405710[56:34]; + default: _theResult___fst_sfd__h406280 = 23'd0; endcase end - always@(guard__h389001 or - sfdin__h397094 or out_sfd__h397620 or _theResult___sfd__h397617) + always@(guard__h389004 or + sfdin__h397097 or out_sfd__h397623 or _theResult___sfd__h397620) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 = - sfdin__h397094[56:34]; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = + sfdin__h397097[56:34]; 2'b10: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 = - out_sfd__h397620; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = + out_sfd__h397623; 2'b11: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 = - _theResult___sfd__h397617; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 = + _theResult___sfd__h397620; endcase end - always@(guard__h389001 or sfdin__h397094 or _theResult___sfd__h397617) + always@(guard__h389004 or sfdin__h397097 or _theResult___sfd__h397620) begin - case (guard__h389001) + case (guard__h389004) 2'b0: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77 = - sfdin__h397094[56:34]; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = + sfdin__h397097[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h397617; + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h397620; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76 or - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77 or + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76 or + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or - sfdin__h397094) + sfdin__h397097) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h397695 = - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q76; + _theResult___fst_sfd__h397698 = + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q76; 3'd1: - _theResult___fst_sfd__h397695 = - CASE_guard89001_0b0_sfdin97094_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h397698 = + CASE_guard89004_0b0_sfdin97097_BITS_56_TO_34_0_ETC__q77; 3'd2: - _theResult___fst_sfd__h397695 = + _theResult___fst_sfd__h397698 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345; 3'd3: - _theResult___fst_sfd__h397695 = + _theResult___fst_sfd__h397698 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347; - 3'd4: _theResult___fst_sfd__h397695 = sfdin__h397094[56:34]; - default: _theResult___fst_sfd__h397695 = 23'd0; + 3'd4: _theResult___fst_sfd__h397698 = sfdin__h397097[56:34]; + default: _theResult___fst_sfd__h397698 = 23'd0; endcase end - always@(guard__h406638 or - sfdin__h414860 or out_sfd__h415386 or _theResult___sfd__h415383) + always@(guard__h406641 or + sfdin__h414863 or out_sfd__h415389 or _theResult___sfd__h415386) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 = - sfdin__h414860[56:34]; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = + sfdin__h414863[56:34]; 2'b10: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 = - out_sfd__h415386; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = + out_sfd__h415389; 2'b11: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h415383; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h415386; endcase end - always@(guard__h406638 or sfdin__h414860 or _theResult___sfd__h415383) + always@(guard__h406641 or sfdin__h414863 or _theResult___sfd__h415386) begin - case (guard__h406638) + case (guard__h406641) 2'b0: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79 = - sfdin__h414860[56:34]; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = + sfdin__h414863[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h415383; + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h415386; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78 or - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79 or + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78 or + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or - sfdin__h414860) + sfdin__h414863) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h415461 = - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h415464 = + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q78; 3'd1: - _theResult___fst_sfd__h415461 = - CASE_guard06638_0b0_sfdin14860_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h415464 = + CASE_guard06641_0b0_sfdin14863_BITS_56_TO_34_0_ETC__q79; 3'd2: - _theResult___fst_sfd__h415461 = + _theResult___fst_sfd__h415464 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391; 3'd3: - _theResult___fst_sfd__h415461 = + _theResult___fst_sfd__h415464 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393; - 3'd4: _theResult___fst_sfd__h415461 = sfdin__h414860[56:34]; - default: _theResult___fst_sfd__h415461 = 23'd0; + 3'd4: _theResult___fst_sfd__h415464 = sfdin__h414863[56:34]; + default: _theResult___fst_sfd__h415464 = 23'd0; endcase end - always@(guard__h415474 or - _theResult___snd__h423497 or - out_sfd__h424022 or _theResult___sfd__h424019) + always@(guard__h415477 or + _theResult___snd__h423500 or + out_sfd__h424025 or _theResult___sfd__h424022) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 = - _theResult___snd__h423497[56:34]; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = + _theResult___snd__h423500[56:34]; 2'b10: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 = - out_sfd__h424022; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = + out_sfd__h424025; 2'b11: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 = - _theResult___sfd__h424019; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 = + _theResult___sfd__h424022; endcase end - always@(guard__h415474 or - _theResult___snd__h423497 or _theResult___sfd__h424019) + always@(guard__h415477 or + _theResult___snd__h423500 or _theResult___sfd__h424022) begin - case (guard__h415474) + case (guard__h415477) 2'b0: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81 = - _theResult___snd__h423497[56:34]; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = + _theResult___snd__h423500[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81 = - _theResult___sfd__h424019; + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 = + _theResult___sfd__h424022; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80 or - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81 or + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80 or + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or - _theResult___snd__h423497) + _theResult___snd__h423500) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h424097 = - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q80; + _theResult___fst_sfd__h424100 = + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q80; 3'd1: - _theResult___fst_sfd__h424097 = - CASE_guard15474_0b0_theResult___snd23497_BITS__ETC__q81; + _theResult___fst_sfd__h424100 = + CASE_guard15477_0b0_theResult___snd23500_BITS__ETC__q81; 3'd2: - _theResult___fst_sfd__h424097 = + _theResult___fst_sfd__h424100 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410; 3'd3: - _theResult___fst_sfd__h424097 = + _theResult___fst_sfd__h424100 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412; - 3'd4: _theResult___fst_sfd__h424097 = _theResult___snd__h423497[56:34]; - default: _theResult___fst_sfd__h424097 = 23'd0; + 3'd4: _theResult___fst_sfd__h424100 = _theResult___snd__h423500[56:34]; + default: _theResult___fst_sfd__h424100 = 23'd0; endcase end - always@(guard__h389001 or + always@(guard__h389004 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01, 2'b10: - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = - guard__h389001 == 2'b11 && + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 = + guard__h389004 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or - guard__h389001) + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or + guard__h389004) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - CASE_guard89001_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; + CASE_guard89004_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = - (guard__h389001 == 2'b0) ? + (guard__h389004 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h389001 == 2'b01 || guard__h389001 == 2'b10 || - guard__h389001 == 2'b11) && + (guard__h389004 == 2'b01 || guard__h389004 == 2'b10 || + guard__h389004 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 = @@ -31553,34 +31553,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h389001 or + always@(guard__h389004 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h389001) + case (guard__h389004) 2'b0, 2'b01, 2'b10: - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = - guard__h389001 != 2'b11 || + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 = + guard__h389004 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or - guard__h389001) + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or + guard__h389004) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - CASE_guard89001_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; + CASE_guard89004_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = - (guard__h389001 == 2'b0) ? + (guard__h389004 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h389001 != 2'b01 && guard__h389001 != 2'b10 && - guard__h389001 != 2'b11 || + guard__h389004 != 2'b01 && guard__h389004 != 2'b10 && + guard__h389004 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 = @@ -31591,34 +31591,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397708 or + always@(guard__h397711 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01, 2'b10: - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = - guard__h397708 == 2'b11 && + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 = + guard__h397711 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or - guard__h397708) + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or + guard__h397711) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - CASE_guard97708_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; + CASE_guard97711_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = - (guard__h397708 == 2'b0) ? + (guard__h397711 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h397708 == 2'b01 || guard__h397708 == 2'b10 || - guard__h397708 == 2'b11) && + (guard__h397711 == 2'b01 || guard__h397711 == 2'b10 || + guard__h397711 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 = @@ -31629,34 +31629,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h397708 or + always@(guard__h397711 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h397708) + case (guard__h397711) 2'b0, 2'b01, 2'b10: - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = - guard__h397708 != 2'b11 || + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 = + guard__h397711 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or - guard__h397708) + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or + guard__h397711) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - CASE_guard97708_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; + CASE_guard97711_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = - (guard__h397708 == 2'b0) ? + (guard__h397711 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h397708 != 2'b01 && guard__h397708 != 2'b10 && - guard__h397708 != 2'b11 || + guard__h397711 != 2'b01 && guard__h397711 != 2'b10 && + guard__h397711 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 = @@ -31667,34 +31667,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406638 or + always@(guard__h406641 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01, 2'b10: - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = - guard__h406638 == 2'b11 && + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 = + guard__h406641 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or - guard__h406638) + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or + guard__h406641) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - CASE_guard06638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; + CASE_guard06641_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = - (guard__h406638 == 2'b0) ? + (guard__h406641 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h406638 == 2'b01 || guard__h406638 == 2'b10 || - guard__h406638 == 2'b11) && + (guard__h406641 == 2'b01 || guard__h406641 == 2'b10 || + guard__h406641 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 = @@ -31705,34 +31705,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h406638 or + always@(guard__h406641 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h406638) + case (guard__h406641) 2'b0, 2'b01, 2'b10: - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = - guard__h406638 != 2'b11 || + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 = + guard__h406641 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or - guard__h406638) + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or + guard__h406641) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - CASE_guard06638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; + CASE_guard06641_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = - (guard__h406638 == 2'b0) ? + (guard__h406641 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h406638 != 2'b01 && guard__h406638 != 2'b10 && - guard__h406638 != 2'b11 || + guard__h406641 != 2'b01 && guard__h406641 != 2'b10 && + guard__h406641 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 = @@ -31743,34 +31743,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415474 or + always@(guard__h415477 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01, 2'b10: - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = - guard__h415474 == 2'b11 && + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 = + guard__h415477 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or - guard__h415474) + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or + guard__h415477) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - CASE_guard15474_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; + CASE_guard15477_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = - (guard__h415474 == 2'b0) ? + (guard__h415477 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h415474 == 2'b01 || guard__h415474 == 2'b10 || - guard__h415474 == 2'b11) && + (guard__h415477 == 2'b01 || guard__h415477 == 2'b10 || + guard__h415477 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 = @@ -31781,34 +31781,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h415474 or + always@(guard__h415477 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h415474) + case (guard__h415477) 2'b0, 2'b01, 2'b10: - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = - guard__h415474 != 2'b11 || + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 = + guard__h415477 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or - guard__h415474) + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or + guard__h415477) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - CASE_guard15474_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; + CASE_guard15477_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = - (guard__h415474 == 2'b0) ? + (guard__h415477 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h415474 != 2'b01 && guard__h415474 != 2'b10 && - guard__h415474 != 2'b11 || + guard__h415477 != 2'b01 && guard__h415477 != 2'b10 && + guard__h415477 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 = @@ -31845,446 +31845,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h443396 or - _theResult___fst_exp__h451444 or - out_exp__h451889 or _theResult___exp__h451886) + always@(guard__h443399 or + _theResult___fst_exp__h451447 or + out_exp__h451892 or _theResult___exp__h451889) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 = - _theResult___fst_exp__h451444; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = + _theResult___fst_exp__h451447; 2'b10: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 = - out_exp__h451889; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = + out_exp__h451892; 2'b11: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 = - _theResult___exp__h451886; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 = + _theResult___exp__h451889; endcase end - always@(guard__h443396 or - _theResult___fst_exp__h451444 or _theResult___exp__h451886) + always@(guard__h443399 or + _theResult___fst_exp__h451447 or _theResult___exp__h451889) begin - case (guard__h443396) + case (guard__h443399) 2'b0: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95 = - _theResult___fst_exp__h451444; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = + _theResult___fst_exp__h451447; 2'b01, 2'b10, 2'b11: - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95 = - _theResult___exp__h451886; + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 = + _theResult___exp__h451889; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94 or - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95 or + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94 or + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or - _theResult___fst_exp__h451444) + _theResult___fst_exp__h451447) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h451964 = - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q94; + _theResult___fst_exp__h451967 = + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q94; 3'd1: - _theResult___fst_exp__h451964 = - CASE_guard43396_0b0_theResult___fst_exp51444_0_ETC__q95; + _theResult___fst_exp__h451967 = + CASE_guard43399_0b0_theResult___fst_exp51447_0_ETC__q95; 3'd2: - _theResult___fst_exp__h451964 = + _theResult___fst_exp__h451967 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312; 3'd3: - _theResult___fst_exp__h451964 = + _theResult___fst_exp__h451967 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314; - 3'd4: _theResult___fst_exp__h451964 = _theResult___fst_exp__h451444; - default: _theResult___fst_exp__h451964 = 8'd0; + 3'd4: _theResult___fst_exp__h451967 = _theResult___fst_exp__h451447; + default: _theResult___fst_exp__h451967 = 8'd0; endcase end - always@(guard__h434689 or - _theResult___fst_exp__h442788 or - out_exp__h443307 or _theResult___exp__h443304) + always@(guard__h434692 or + _theResult___fst_exp__h442791 or + out_exp__h443310 or _theResult___exp__h443307) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 = - _theResult___fst_exp__h442788; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = + _theResult___fst_exp__h442791; 2'b10: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 = - out_exp__h443307; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = + out_exp__h443310; 2'b11: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 = - _theResult___exp__h443304; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 = + _theResult___exp__h443307; endcase end - always@(guard__h434689 or - _theResult___fst_exp__h442788 or _theResult___exp__h443304) + always@(guard__h434692 or + _theResult___fst_exp__h442791 or _theResult___exp__h443307) begin - case (guard__h434689) + case (guard__h434692) 2'b0: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97 = - _theResult___fst_exp__h442788; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = + _theResult___fst_exp__h442791; 2'b01, 2'b10, 2'b11: - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97 = - _theResult___exp__h443304; + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 = + _theResult___exp__h443307; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96 or - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97 or + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96 or + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or - _theResult___fst_exp__h442788) + _theResult___fst_exp__h442791) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h443382 = - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q96; + _theResult___fst_exp__h443385 = + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q96; 3'd1: - _theResult___fst_exp__h443382 = - CASE_guard34689_0b0_theResult___fst_exp42788_0_ETC__q97; + _theResult___fst_exp__h443385 = + CASE_guard34692_0b0_theResult___fst_exp42791_0_ETC__q97; 3'd2: - _theResult___fst_exp__h443382 = + _theResult___fst_exp__h443385 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090; 3'd3: - _theResult___fst_exp__h443382 = + _theResult___fst_exp__h443385 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093; - 3'd4: _theResult___fst_exp__h443382 = _theResult___fst_exp__h442788; - default: _theResult___fst_exp__h443382 = 8'd0; + 3'd4: _theResult___fst_exp__h443385 = _theResult___fst_exp__h442791; + default: _theResult___fst_exp__h443385 = 8'd0; endcase end - always@(guard__h452326 or - _theResult___fst_exp__h460554 or - out_exp__h461073 or _theResult___exp__h461070) + always@(guard__h452329 or + _theResult___fst_exp__h460557 or + out_exp__h461076 or _theResult___exp__h461073) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 = - _theResult___fst_exp__h460554; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = + _theResult___fst_exp__h460557; 2'b10: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 = - out_exp__h461073; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = + out_exp__h461076; 2'b11: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 = - _theResult___exp__h461070; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 = + _theResult___exp__h461073; endcase end - always@(guard__h452326 or - _theResult___fst_exp__h460554 or _theResult___exp__h461070) + always@(guard__h452329 or + _theResult___fst_exp__h460557 or _theResult___exp__h461073) begin - case (guard__h452326) + case (guard__h452329) 2'b0: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103 = - _theResult___fst_exp__h460554; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = + _theResult___fst_exp__h460557; 2'b01, 2'b10, 2'b11: - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103 = - _theResult___exp__h461070; + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 = + _theResult___exp__h461073; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102 or - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103 or + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102 or + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or - _theResult___fst_exp__h460554) + _theResult___fst_exp__h460557) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h461148 = - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q102; + _theResult___fst_exp__h461151 = + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q102; 3'd1: - _theResult___fst_exp__h461148 = - CASE_guard52326_0b0_theResult___fst_exp60554_0_ETC__q103; + _theResult___fst_exp__h461151 = + CASE_guard52329_0b0_theResult___fst_exp60557_0_ETC__q103; 3'd2: - _theResult___fst_exp__h461148 = + _theResult___fst_exp__h461151 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637; 3'd3: - _theResult___fst_exp__h461148 = + _theResult___fst_exp__h461151 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639; - 3'd4: _theResult___fst_exp__h461148 = _theResult___fst_exp__h460554; - default: _theResult___fst_exp__h461148 = 8'd0; + 3'd4: _theResult___fst_exp__h461151 = _theResult___fst_exp__h460557; + default: _theResult___fst_exp__h461151 = 8'd0; endcase end - always@(guard__h461162 or - _theResult___fst_exp__h469239 or - out_exp__h469709 or _theResult___exp__h469706) + always@(guard__h461165 or + _theResult___fst_exp__h469242 or + out_exp__h469712 or _theResult___exp__h469709) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 = - _theResult___fst_exp__h469239; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = + _theResult___fst_exp__h469242; 2'b10: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 = - out_exp__h469709; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = + out_exp__h469712; 2'b11: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 = - _theResult___exp__h469706; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 = + _theResult___exp__h469709; endcase end - always@(guard__h461162 or - _theResult___fst_exp__h469239 or _theResult___exp__h469706) + always@(guard__h461165 or + _theResult___fst_exp__h469242 or _theResult___exp__h469709) begin - case (guard__h461162) + case (guard__h461165) 2'b0: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108 = - _theResult___fst_exp__h469239; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = + _theResult___fst_exp__h469242; 2'b01, 2'b10, 2'b11: - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108 = - _theResult___exp__h469706; + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 = + _theResult___exp__h469709; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107 or - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108 or + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107 or + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or - _theResult___fst_exp__h469239) + _theResult___fst_exp__h469242) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h469784 = - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q107; + _theResult___fst_exp__h469787 = + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q107; 3'd1: - _theResult___fst_exp__h469784 = - CASE_guard61162_0b0_theResult___fst_exp69239_0_ETC__q108; + _theResult___fst_exp__h469787 = + CASE_guard61165_0b0_theResult___fst_exp69242_0_ETC__q108; 3'd2: - _theResult___fst_exp__h469784 = + _theResult___fst_exp__h469787 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706; 3'd3: - _theResult___fst_exp__h469784 = + _theResult___fst_exp__h469787 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708; - 3'd4: _theResult___fst_exp__h469784 = _theResult___fst_exp__h469239; - default: _theResult___fst_exp__h469784 = 8'd0; + 3'd4: _theResult___fst_exp__h469787 = _theResult___fst_exp__h469242; + default: _theResult___fst_exp__h469787 = 8'd0; endcase end - always@(guard__h443396 or - _theResult___snd__h451395 or - out_sfd__h451890 or _theResult___sfd__h451887) + always@(guard__h443399 or + _theResult___snd__h451398 or + out_sfd__h451893 or _theResult___sfd__h451890) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 = - _theResult___snd__h451395[56:34]; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = + _theResult___snd__h451398[56:34]; 2'b10: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 = - out_sfd__h451890; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = + out_sfd__h451893; 2'b11: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 = - _theResult___sfd__h451887; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 = + _theResult___sfd__h451890; endcase end - always@(guard__h443396 or - _theResult___snd__h451395 or _theResult___sfd__h451887) + always@(guard__h443399 or + _theResult___snd__h451398 or _theResult___sfd__h451890) begin - case (guard__h443396) + case (guard__h443399) 2'b0: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110 = - _theResult___snd__h451395[56:34]; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = + _theResult___snd__h451398[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110 = - _theResult___sfd__h451887; + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 = + _theResult___sfd__h451890; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109 or - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110 or + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109 or + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or - _theResult___snd__h451395) + _theResult___snd__h451398) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h451965 = - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q109; + _theResult___fst_sfd__h451968 = + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q109; 3'd1: - _theResult___fst_sfd__h451965 = - CASE_guard43396_0b0_theResult___snd51395_BITS__ETC__q110; + _theResult___fst_sfd__h451968 = + CASE_guard43399_0b0_theResult___snd51398_BITS__ETC__q110; 3'd2: - _theResult___fst_sfd__h451965 = + _theResult___fst_sfd__h451968 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756; 3'd3: - _theResult___fst_sfd__h451965 = + _theResult___fst_sfd__h451968 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758; - 3'd4: _theResult___fst_sfd__h451965 = _theResult___snd__h451395[56:34]; - default: _theResult___fst_sfd__h451965 = 23'd0; + 3'd4: _theResult___fst_sfd__h451968 = _theResult___snd__h451398[56:34]; + default: _theResult___fst_sfd__h451968 = 23'd0; endcase end - always@(guard__h434689 or - sfdin__h442782 or out_sfd__h443308 or _theResult___sfd__h443305) + always@(guard__h434692 or + sfdin__h442785 or out_sfd__h443311 or _theResult___sfd__h443308) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 = - sfdin__h442782[56:34]; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = + sfdin__h442785[56:34]; 2'b10: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 = - out_sfd__h443308; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = + out_sfd__h443311; 2'b11: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 = - _theResult___sfd__h443305; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 = + _theResult___sfd__h443308; endcase end - always@(guard__h434689 or sfdin__h442782 or _theResult___sfd__h443305) + always@(guard__h434692 or sfdin__h442785 or _theResult___sfd__h443308) begin - case (guard__h434689) + case (guard__h434692) 2'b0: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112 = - sfdin__h442782[56:34]; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = + sfdin__h442785[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h443305; + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h443308; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111 or - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112 or + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111 or + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or - sfdin__h442782) + sfdin__h442785) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h443383 = - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q111; + _theResult___fst_sfd__h443386 = + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q111; 3'd1: - _theResult___fst_sfd__h443383 = - CASE_guard34689_0b0_sfdin42782_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h443386 = + CASE_guard34692_0b0_sfdin42785_BITS_56_TO_34_0_ETC__q112; 3'd2: - _theResult___fst_sfd__h443383 = + _theResult___fst_sfd__h443386 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737; 3'd3: - _theResult___fst_sfd__h443383 = + _theResult___fst_sfd__h443386 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739; - 3'd4: _theResult___fst_sfd__h443383 = sfdin__h442782[56:34]; - default: _theResult___fst_sfd__h443383 = 23'd0; + 3'd4: _theResult___fst_sfd__h443386 = sfdin__h442785[56:34]; + default: _theResult___fst_sfd__h443386 = 23'd0; endcase end - always@(guard__h452326 or - sfdin__h460548 or out_sfd__h461074 or _theResult___sfd__h461071) + always@(guard__h452329 or + sfdin__h460551 or out_sfd__h461077 or _theResult___sfd__h461074) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 = - sfdin__h460548[56:34]; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = + sfdin__h460551[56:34]; 2'b10: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 = - out_sfd__h461074; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = + out_sfd__h461077; 2'b11: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h461071; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h461074; endcase end - always@(guard__h452326 or sfdin__h460548 or _theResult___sfd__h461071) + always@(guard__h452329 or sfdin__h460551 or _theResult___sfd__h461074) begin - case (guard__h452326) + case (guard__h452329) 2'b0: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114 = - sfdin__h460548[56:34]; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = + sfdin__h460551[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h461071; + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h461074; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113 or - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114 or + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113 or + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or - sfdin__h460548) + sfdin__h460551) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h461149 = - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h461152 = + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q113; 3'd1: - _theResult___fst_sfd__h461149 = - CASE_guard52326_0b0_sfdin60548_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h461152 = + CASE_guard52329_0b0_sfdin60551_BITS_56_TO_34_0_ETC__q114; 3'd2: - _theResult___fst_sfd__h461149 = + _theResult___fst_sfd__h461152 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783; 3'd3: - _theResult___fst_sfd__h461149 = + _theResult___fst_sfd__h461152 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785; - 3'd4: _theResult___fst_sfd__h461149 = sfdin__h460548[56:34]; - default: _theResult___fst_sfd__h461149 = 23'd0; + 3'd4: _theResult___fst_sfd__h461152 = sfdin__h460551[56:34]; + default: _theResult___fst_sfd__h461152 = 23'd0; endcase end - always@(guard__h461162 or - _theResult___snd__h469185 or - out_sfd__h469710 or _theResult___sfd__h469707) + always@(guard__h461165 or + _theResult___snd__h469188 or + out_sfd__h469713 or _theResult___sfd__h469710) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 = - _theResult___snd__h469185[56:34]; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = + _theResult___snd__h469188[56:34]; 2'b10: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 = - out_sfd__h469710; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = + out_sfd__h469713; 2'b11: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 = - _theResult___sfd__h469707; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 = + _theResult___sfd__h469710; endcase end - always@(guard__h461162 or - _theResult___snd__h469185 or _theResult___sfd__h469707) + always@(guard__h461165 or + _theResult___snd__h469188 or _theResult___sfd__h469710) begin - case (guard__h461162) + case (guard__h461165) 2'b0: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116 = - _theResult___snd__h469185[56:34]; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = + _theResult___snd__h469188[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116 = - _theResult___sfd__h469707; + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 = + _theResult___sfd__h469710; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115 or - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116 or + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115 or + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or - _theResult___snd__h469185) + _theResult___snd__h469188) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h469785 = - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q115; + _theResult___fst_sfd__h469788 = + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q115; 3'd1: - _theResult___fst_sfd__h469785 = - CASE_guard61162_0b0_theResult___snd69185_BITS__ETC__q116; + _theResult___fst_sfd__h469788 = + CASE_guard61165_0b0_theResult___snd69188_BITS__ETC__q116; 3'd2: - _theResult___fst_sfd__h469785 = + _theResult___fst_sfd__h469788 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802; 3'd3: - _theResult___fst_sfd__h469785 = + _theResult___fst_sfd__h469788 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804; - 3'd4: _theResult___fst_sfd__h469785 = _theResult___snd__h469185[56:34]; - default: _theResult___fst_sfd__h469785 = 23'd0; + 3'd4: _theResult___fst_sfd__h469788 = _theResult___snd__h469188[56:34]; + default: _theResult___fst_sfd__h469788 = 23'd0; endcase end - always@(guard__h434689 or + always@(guard__h434692 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01, 2'b10: - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = - guard__h434689 == 2'b11 && + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 = + guard__h434692 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or - guard__h434689) + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or + guard__h434692) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - CASE_guard34689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; + CASE_guard34692_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = - (guard__h434689 == 2'b0) ? + (guard__h434692 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h434689 == 2'b01 || guard__h434689 == 2'b10 || - guard__h434689 == 2'b11) && + (guard__h434692 == 2'b01 || guard__h434692 == 2'b10 || + guard__h434692 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 = @@ -32295,34 +32295,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h434689 or + always@(guard__h434692 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h434689) + case (guard__h434692) 2'b0, 2'b01, 2'b10: - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = - guard__h434689 != 2'b11 || + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 = + guard__h434692 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or - guard__h434689) + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or + guard__h434692) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - CASE_guard34689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; + CASE_guard34692_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = - (guard__h434689 == 2'b0) ? + (guard__h434692 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h434689 != 2'b01 && guard__h434689 != 2'b10 && - guard__h434689 != 2'b11 || + guard__h434692 != 2'b01 && guard__h434692 != 2'b10 && + guard__h434692 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 = @@ -32333,34 +32333,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443396 or + always@(guard__h443399 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01, 2'b10: - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = - guard__h443396 == 2'b11 && + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h443399 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or - guard__h443396) + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h443399) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - CASE_guard43396_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard43399_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = - (guard__h443396 == 2'b0) ? + (guard__h443399 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h443396 == 2'b01 || guard__h443396 == 2'b10 || - guard__h443396 == 2'b11) && + (guard__h443399 == 2'b01 || guard__h443399 == 2'b10 || + guard__h443399 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 = @@ -32371,34 +32371,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h443396 or + always@(guard__h443399 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h443396) + case (guard__h443399) 2'b0, 2'b01, 2'b10: - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h443396 != 2'b11 || + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h443399 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h443396) + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h443399) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - CASE_guard43396_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + CASE_guard43399_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = - (guard__h443396 == 2'b0) ? + (guard__h443399 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h443396 != 2'b01 && guard__h443396 != 2'b10 && - guard__h443396 != 2'b11 || + guard__h443399 != 2'b01 && guard__h443399 != 2'b10 && + guard__h443399 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 = @@ -32409,34 +32409,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452326 or + always@(guard__h452329 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01, 2'b10: - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = - guard__h452326 == 2'b11 && + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 = + guard__h452329 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or - guard__h452326) + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or + guard__h452329) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - CASE_guard52326_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; + CASE_guard52329_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = - (guard__h452326 == 2'b0) ? + (guard__h452329 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h452326 == 2'b01 || guard__h452326 == 2'b10 || - guard__h452326 == 2'b11) && + (guard__h452329 == 2'b01 || guard__h452329 == 2'b10 || + guard__h452329 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 = @@ -32447,34 +32447,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h452326 or + always@(guard__h452329 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h452326) + case (guard__h452329) 2'b0, 2'b01, 2'b10: - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = - guard__h452326 != 2'b11 || + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 = + guard__h452329 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or - guard__h452326) + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or + guard__h452329) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - CASE_guard52326_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; + CASE_guard52329_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = - (guard__h452326 == 2'b0) ? + (guard__h452329 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h452326 != 2'b01 && guard__h452326 != 2'b10 && - guard__h452326 != 2'b11 || + guard__h452329 != 2'b01 && guard__h452329 != 2'b10 && + guard__h452329 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 = @@ -32485,34 +32485,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461162 or + always@(guard__h461165 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01, 2'b10: - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h461162 == 2'b11 && + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + guard__h461165 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h461162) + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or + guard__h461165) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - CASE_guard61162_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + CASE_guard61165_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = - (guard__h461162 == 2'b0) ? + (guard__h461165 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h461162 == 2'b01 || guard__h461162 == 2'b10 || - guard__h461162 == 2'b11) && + (guard__h461165 == 2'b01 || guard__h461165 == 2'b10 || + guard__h461165 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 = @@ -32523,34 +32523,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h461162 or + always@(guard__h461165 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h461162) + case (guard__h461165) 2'b0, 2'b01, 2'b10: - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = - guard__h461162 != 2'b11 || + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 = + guard__h461165 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or - guard__h461162) + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or + guard__h461165) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - CASE_guard61162_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; + CASE_guard61165_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = - (guard__h461162 == 2'b0) ? + (guard__h461165 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h461162 != 2'b01 && guard__h461162 != 2'b10 && - guard__h461162 != 2'b11 || + guard__h461165 != 2'b01 && guard__h461165 != 2'b10 && + guard__h461165 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 = @@ -32607,28 +32607,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h490711 or - _theResult___fst_exp__h498672 or _theResult___exp__h499327) + always@(guard__h490715 or + _theResult___fst_exp__h498676 or _theResult___exp__h499331) begin - case (guard__h490711) + case (guard__h490715) 2'b0: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135 = - _theResult___fst_exp__h498672; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = + _theResult___fst_exp__h498676; 2'b01, 2'b10, 2'b11: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135 = - _theResult___exp__h499327; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135 = + _theResult___exp__h499331; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h498672 or + _theResult___fst_exp__h498676 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005 or - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135) + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - _theResult___fst_exp__h498672; + _theResult___fst_exp__h498676; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9007; @@ -32637,40 +32637,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9005; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q135; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9011 = 11'd0; endcase end - always@(guard__h490711 or - _theResult___fst_exp__h498672 or - out_exp__h499330 or _theResult___exp__h499327) + always@(guard__h490715 or + _theResult___fst_exp__h498676 or + out_exp__h499334 or _theResult___exp__h499331) begin - case (guard__h490711) + case (guard__h490715) 2'b0, 2'b01: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 = - _theResult___fst_exp__h498672; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = + _theResult___fst_exp__h498676; 2'b10: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 = - out_exp__h499330; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = + out_exp__h499334; 2'b11: - CASE_guard90711_0b0_theResult___fst_exp98672_0_ETC__q136 = - _theResult___exp__h499327; + CASE_guard90715_0b0_theResult___fst_exp98676_0_ETC__q136 = + _theResult___exp__h499331; endcase end - always@(guard__h490711 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h490715 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h490711) + case (guard__h490715) 2'b0, 2'b01, 2'b10: - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard90711_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h490711 == 2'b11 && + CASE_guard90715_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h490715 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490711) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490715) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32678,29 +32678,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h490711 == 2'b0) ? + (guard__h490715 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h490711 == 2'b01 || guard__h490711 == 2'b10 || - guard__h490711 == 2'b11) && + (guard__h490715 == 2'b01 || guard__h490715 == 2'b10 || + guard__h490715 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h500023 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h500027 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h500023) + case (guard__h500027) 2'b0, 2'b01, 2'b10: - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard00023_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h500023 == 2'b11 && + CASE_guard00027_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h500027 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500023) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500027) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32708,29 +32708,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h500023 == 2'b0) ? + (guard__h500027 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h500023 == 2'b01 || guard__h500023 == 2'b10 || - guard__h500023 == 2'b11) && + (guard__h500027 == 2'b01 || guard__h500027 == 2'b10 || + guard__h500027 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h509092 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h509096 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h509092) + case (guard__h509096) 2'b0, 2'b01, 2'b10: - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard09092_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h509092 == 2'b11 && + CASE_guard09096_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h509096 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509092) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509096) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32738,38 +32738,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h509092 == 2'b0) ? + (guard__h509096 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h509092 == 2'b01 || guard__h509092 == 2'b10 || - guard__h509092 == 2'b11) && + (guard__h509096 == 2'b01 || guard__h509096 == 2'b10 || + guard__h509096 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h568713 or - _theResult___fst_exp__h576674 or _theResult___exp__h577329) + always@(guard__h568717 or + _theResult___fst_exp__h576678 or _theResult___exp__h577333) begin - case (guard__h568713) + case (guard__h568717) 2'b0: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152 = - _theResult___fst_exp__h576674; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = + _theResult___fst_exp__h576678; 2'b01, 2'b10, 2'b11: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152 = - _theResult___exp__h577329; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152 = + _theResult___exp__h577333; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h576674 or + _theResult___fst_exp__h576678 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715 or - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152) + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - _theResult___fst_exp__h576674; + _theResult___fst_exp__h576678; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9717; @@ -32778,40 +32778,40 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9715; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q152; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9721 = 11'd0; endcase end - always@(guard__h568713 or - _theResult___fst_exp__h576674 or - out_exp__h577332 or _theResult___exp__h577329) + always@(guard__h568717 or + _theResult___fst_exp__h576678 or + out_exp__h577336 or _theResult___exp__h577333) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 = - _theResult___fst_exp__h576674; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = + _theResult___fst_exp__h576678; 2'b10: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 = - out_exp__h577332; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = + out_exp__h577336; 2'b11: - CASE_guard68713_0b0_theResult___fst_exp76674_0_ETC__q153 = - _theResult___exp__h577329; + CASE_guard68717_0b0_theResult___fst_exp76678_0_ETC__q153 = + _theResult___exp__h577333; endcase end - always@(guard__h568713 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01, 2'b10: - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68713_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h568713 == 2'b11 && + CASE_guard68717_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h568717 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568713) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32819,29 +32819,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h568713 == 2'b0) ? + (guard__h568717 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h568713 == 2'b01 || guard__h568713 == 2'b10 || - guard__h568713 == 2'b11) && + (guard__h568717 == 2'b01 || guard__h568717 == 2'b10 || + guard__h568717 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578025 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01, 2'b10: - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78025_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h578025 == 2'b11 && + CASE_guard78029_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h578029 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578025) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32849,29 +32849,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h578025 == 2'b0) ? + (guard__h578029 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h578025 == 2'b01 || guard__h578025 == 2'b10 || - guard__h578025 == 2'b11) && + (guard__h578029 == 2'b01 || guard__h578029 == 2'b10 || + guard__h578029 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587094 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01, 2'b10: - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87094_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h587094 == 2'b11 && + CASE_guard87098_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h587098 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587094) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32879,29 +32879,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h587094 == 2'b0) ? + (guard__h587098 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h587094 == 2'b01 || guard__h587094 == 2'b10 || - guard__h587094 == 2'b11) && + (guard__h587098 == 2'b01 || guard__h587098 == 2'b10 || + guard__h587098 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h578025 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h578029 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01, 2'b10: - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard78025_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h578025 != 2'b11 || + CASE_guard78029_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h578029 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578025) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578029) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32909,29 +32909,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h578025 == 2'b0) ? + (guard__h578029 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h578025 != 2'b01 && guard__h578025 != 2'b10 && - guard__h578025 != 2'b11 || + guard__h578029 != 2'b01 && guard__h578029 != 2'b10 && + guard__h578029 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h587094 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h587098 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01, 2'b10: - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard87094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h587094 != 2'b11 || + CASE_guard87098_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h587098 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587094) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587098) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32939,29 +32939,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h587094 == 2'b0) ? + (guard__h587098 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h587094 != 2'b01 && guard__h587094 != 2'b10 && - guard__h587094 != 2'b11 || + guard__h587098 != 2'b01 && guard__h587098 != 2'b10 && + guard__h587098 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h568713 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h568717 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01, 2'b10: - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard68713_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h568713 != 2'b11 || + CASE_guard68717_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h568717 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568713) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568717) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -32969,38 +32969,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h568713 == 2'b0) ? + (guard__h568717 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h568713 != 2'b01 && guard__h568713 != 2'b10 && - guard__h568713 != 2'b11 || + guard__h568717 != 2'b01 && guard__h568717 != 2'b10 && + guard__h568717 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h529512 or - _theResult___fst_exp__h537473 or _theResult___exp__h538128) + always@(guard__h529516 or + _theResult___fst_exp__h537477 or _theResult___exp__h538132) begin - case (guard__h529512) + case (guard__h529516) 2'b0: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175 = - _theResult___fst_exp__h537473; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = + _theResult___fst_exp__h537477; 2'b01, 2'b10, 2'b11: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175 = - _theResult___exp__h538128; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175 = + _theResult___exp__h538132; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h537473 or + _theResult___fst_exp__h537477 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478 or - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175) + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - _theResult___fst_exp__h537473; + _theResult___fst_exp__h537477; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10480; @@ -33009,49 +33009,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10478; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q175; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10484 = 11'd0; endcase end - always@(guard__h529512 or - _theResult___fst_exp__h537473 or - out_exp__h538131 or _theResult___exp__h538128) + always@(guard__h529516 or + _theResult___fst_exp__h537477 or + out_exp__h538135 or _theResult___exp__h538132) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 = - _theResult___fst_exp__h537473; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = + _theResult___fst_exp__h537477; 2'b10: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 = - out_exp__h538131; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = + out_exp__h538135; 2'b11: - CASE_guard29512_0b0_theResult___fst_exp37473_0_ETC__q176 = - _theResult___exp__h538128; + CASE_guard29516_0b0_theResult___fst_exp37477_0_ETC__q176 = + _theResult___exp__h538132; endcase end - always@(guard__h538824 or - _theResult___fst_exp__h547050 or _theResult___exp__h547779) + always@(guard__h538828 or + _theResult___fst_exp__h547054 or _theResult___exp__h547783) begin - case (guard__h538824) + case (guard__h538828) 2'b0: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177 = - _theResult___fst_exp__h547050; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = + _theResult___fst_exp__h547054; 2'b01, 2'b10, 2'b11: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177 = - _theResult___exp__h547779; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177 = + _theResult___exp__h547783; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h547050 or + _theResult___fst_exp__h547054 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516 or - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177) + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - _theResult___fst_exp__h547050; + _theResult___fst_exp__h547054; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10518; @@ -33060,49 +33060,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10516; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q177; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10522 = 11'd0; endcase end - always@(guard__h538824 or - _theResult___fst_exp__h547050 or - out_exp__h547782 or _theResult___exp__h547779) + always@(guard__h538828 or + _theResult___fst_exp__h547054 or + out_exp__h547786 or _theResult___exp__h547783) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 = - _theResult___fst_exp__h547050; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = + _theResult___fst_exp__h547054; 2'b10: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 = - out_exp__h547782; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = + out_exp__h547786; 2'b11: - CASE_guard38824_0b0_theResult___fst_exp47050_0_ETC__q178 = - _theResult___exp__h547779; + CASE_guard38828_0b0_theResult___fst_exp47054_0_ETC__q178 = + _theResult___exp__h547783; endcase end - always@(guard__h547893 or - _theResult___fst_exp__h555883 or _theResult___exp__h556563) + always@(guard__h547897 or + _theResult___fst_exp__h555887 or _theResult___exp__h556567) begin - case (guard__h547893) + case (guard__h547897) 2'b0: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179 = - _theResult___fst_exp__h555883; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = + _theResult___fst_exp__h555887; 2'b01, 2'b10, 2'b11: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179 = - _theResult___exp__h556563; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179 = + _theResult___exp__h556567; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555883 or + _theResult___fst_exp__h555887 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547 or - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179) + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - _theResult___fst_exp__h555883; + _theResult___fst_exp__h555887; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10549; @@ -33111,49 +33111,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10547; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q179; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10553 = 11'd0; endcase end - always@(guard__h547893 or - _theResult___fst_exp__h555883 or - out_exp__h556566 or _theResult___exp__h556563) + always@(guard__h547897 or + _theResult___fst_exp__h555887 or + out_exp__h556570 or _theResult___exp__h556567) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 = - _theResult___fst_exp__h555883; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = + _theResult___fst_exp__h555887; 2'b10: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 = - out_exp__h556566; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = + out_exp__h556570; 2'b11: - CASE_guard47893_0b0_theResult___fst_exp55883_0_ETC__q180 = - _theResult___exp__h556563; + CASE_guard47897_0b0_theResult___fst_exp55887_0_ETC__q180 = + _theResult___exp__h556567; endcase end - always@(guard__h587094 or - _theResult___fst_exp__h595084 or _theResult___exp__h595764) + always@(guard__h587098 or + _theResult___fst_exp__h595088 or _theResult___exp__h595768) begin - case (guard__h587094) + case (guard__h587098) 2'b0: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181 = - _theResult___fst_exp__h595084; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = + _theResult___fst_exp__h595088; 2'b01, 2'b10, 2'b11: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181 = - _theResult___exp__h595764; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181 = + _theResult___exp__h595768; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h595084 or + _theResult___fst_exp__h595088 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784 or - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181) + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - _theResult___fst_exp__h595084; + _theResult___fst_exp__h595088; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9786; @@ -33162,49 +33162,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9784; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q181; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9790 = 11'd0; endcase end - always@(guard__h587094 or - _theResult___fst_exp__h595084 or - out_exp__h595767 or _theResult___exp__h595764) + always@(guard__h587098 or + _theResult___fst_exp__h595088 or + out_exp__h595771 or _theResult___exp__h595768) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 = - _theResult___fst_exp__h595084; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = + _theResult___fst_exp__h595088; 2'b10: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 = - out_exp__h595767; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = + out_exp__h595771; 2'b11: - CASE_guard87094_0b0_theResult___fst_exp95084_0_ETC__q182 = - _theResult___exp__h595764; + CASE_guard87098_0b0_theResult___fst_exp95088_0_ETC__q182 = + _theResult___exp__h595768; endcase end - always@(guard__h578025 or - _theResult___fst_exp__h586251 or _theResult___exp__h586980) + always@(guard__h578029 or + _theResult___fst_exp__h586255 or _theResult___exp__h586984) begin - case (guard__h578025) + case (guard__h578029) 2'b0: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183 = - _theResult___fst_exp__h586251; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = + _theResult___fst_exp__h586255; 2'b01, 2'b10, 2'b11: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183 = - _theResult___exp__h586980; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183 = + _theResult___exp__h586984; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h586251 or + _theResult___fst_exp__h586255 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753 or - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183) + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - _theResult___fst_exp__h586251; + _theResult___fst_exp__h586255; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9755; @@ -33213,40 +33213,40 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9753; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q183; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9759 = 11'd0; endcase end - always@(guard__h578025 or - _theResult___fst_exp__h586251 or - out_exp__h586983 or _theResult___exp__h586980) + always@(guard__h578029 or + _theResult___fst_exp__h586255 or + out_exp__h586987 or _theResult___exp__h586984) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 = - _theResult___fst_exp__h586251; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = + _theResult___fst_exp__h586255; 2'b10: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 = - out_exp__h586983; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = + out_exp__h586987; 2'b11: - CASE_guard78025_0b0_theResult___fst_exp86251_0_ETC__q184 = - _theResult___exp__h586980; + CASE_guard78029_0b0_theResult___fst_exp86255_0_ETC__q184 = + _theResult___exp__h586984; endcase end - always@(guard__h529512 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01, 2'b10: - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29512_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h529512 == 2'b11 && + CASE_guard29516_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h529516 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529512) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33254,29 +33254,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h529512 == 2'b0) ? + (guard__h529516 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h529512 == 2'b01 || guard__h529512 == 2'b10 || - guard__h529512 == 2'b11) && + (guard__h529516 == 2'b01 || guard__h529516 == 2'b10 || + guard__h529516 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538824 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01, 2'b10: - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38824_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h538824 == 2'b11 && + CASE_guard38828_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h538828 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538824) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33284,29 +33284,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h538824 == 2'b0) ? + (guard__h538828 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h538824 == 2'b01 || guard__h538824 == 2'b10 || - guard__h538824 == 2'b11) && + (guard__h538828 == 2'b01 || guard__h538828 == 2'b10 || + guard__h538828 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547893 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01, 2'b10: - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h547893 == 2'b11 && + CASE_guard47897_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h547897 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547893) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33314,29 +33314,29 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h547893 == 2'b0) ? + (guard__h547897 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547893 == 2'b01 || guard__h547893 == 2'b10 || - guard__h547893 == 2'b11) && + (guard__h547897 == 2'b01 || guard__h547897 == 2'b10 || + guard__h547897 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h538824 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h538828 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01, 2'b10: - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard38824_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h538824 != 2'b11 || + CASE_guard38828_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h538828 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538824) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538828) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33344,29 +33344,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h538824 == 2'b0) ? + (guard__h538828 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h538824 != 2'b01 && guard__h538824 != 2'b10 && - guard__h538824 != 2'b11 || + guard__h538828 != 2'b01 && guard__h538828 != 2'b10 && + guard__h538828 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547893 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547897 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01, 2'b10: - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47893_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h547893 != 2'b11 || + CASE_guard47897_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h547897 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547893) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547897) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33374,29 +33374,29 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h547893 == 2'b0) ? + (guard__h547897 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547893 != 2'b01 && guard__h547893 != 2'b10 && - guard__h547893 != 2'b11 || + guard__h547897 != 2'b01 && guard__h547897 != 2'b10 && + guard__h547897 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529512 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h529516 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01, 2'b10: - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard29512_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h529512 != 2'b11 || + CASE_guard29516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h529516 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529512) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529516) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33404,38 +33404,38 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h529512 == 2'b0) ? + (guard__h529516 == 2'b0) ? !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h529512 != 2'b01 && guard__h529512 != 2'b10 && - guard__h529512 != 2'b11 || + guard__h529516 != 2'b01 && guard__h529516 != 2'b10 && + guard__h529516 != 2'b11 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h529512 or - _theResult___snd__h537424 or _theResult___sfd__h538129) + always@(guard__h529516 or + _theResult___snd__h537428 or _theResult___sfd__h538133) begin - case (guard__h529512) + case (guard__h529516) 2'b0: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197 = - _theResult___snd__h537424[56:5]; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = + _theResult___snd__h537428[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197 = - _theResult___sfd__h538129; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197 = + _theResult___sfd__h538133; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h537424 or + _theResult___snd__h537428 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573 or - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197) + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - _theResult___snd__h537424[56:5]; + _theResult___snd__h537428[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10575; @@ -33444,48 +33444,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10573; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q197; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10579 = 52'd0; endcase end - always@(guard__h529512 or - _theResult___snd__h537424 or - out_sfd__h538132 or _theResult___sfd__h538129) + always@(guard__h529516 or + _theResult___snd__h537428 or + out_sfd__h538136 or _theResult___sfd__h538133) begin - case (guard__h529512) + case (guard__h529516) 2'b0, 2'b01: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 = - _theResult___snd__h537424[56:5]; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = + _theResult___snd__h537428[56:5]; 2'b10: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 = - out_sfd__h538132; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = + out_sfd__h538136; 2'b11: - CASE_guard29512_0b0_theResult___snd37424_BITS__ETC__q198 = - _theResult___sfd__h538129; + CASE_guard29516_0b0_theResult___snd37428_BITS__ETC__q198 = + _theResult___sfd__h538133; endcase end - always@(guard__h538824 or sfdin__h547044 or _theResult___sfd__h547780) + always@(guard__h538828 or sfdin__h547048 or _theResult___sfd__h547784) begin - case (guard__h538824) + case (guard__h538828) 2'b0: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h547044[56:5]; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h547048[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h547780; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h547784; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h547044 or + sfdin__h547048 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599 or - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199) + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - sfdin__h547044[56:5]; + sfdin__h547048[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10601; @@ -33494,48 +33494,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10599; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q199; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10605 = 52'd0; endcase end - always@(guard__h538824 or - sfdin__h547044 or out_sfd__h547783 or _theResult___sfd__h547780) + always@(guard__h538828 or + sfdin__h547048 or out_sfd__h547787 or _theResult___sfd__h547784) begin - case (guard__h538824) + case (guard__h538828) 2'b0, 2'b01: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h547044[56:5]; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h547048[56:5]; 2'b10: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h547783; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h547787; 2'b11: - CASE_guard38824_0b0_sfdin47044_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h547780; + CASE_guard38828_0b0_sfdin47048_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h547784; endcase end - always@(guard__h547893 or - _theResult___snd__h555829 or _theResult___sfd__h556564) + always@(guard__h547897 or + _theResult___snd__h555833 or _theResult___sfd__h556568) begin - case (guard__h547893) + case (guard__h547897) 2'b0: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201 = - _theResult___snd__h555829[56:5]; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = + _theResult___snd__h555833[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201 = - _theResult___sfd__h556564; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201 = + _theResult___sfd__h556568; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h555829 or + _theResult___snd__h555833 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618 or - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201) + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - _theResult___snd__h555829[56:5]; + _theResult___snd__h555833[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10620; @@ -33544,49 +33544,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10618; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q201; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10624 = 52'd0; endcase end - always@(guard__h547893 or - _theResult___snd__h555829 or - out_sfd__h556567 or _theResult___sfd__h556564) + always@(guard__h547897 or + _theResult___snd__h555833 or + out_sfd__h556571 or _theResult___sfd__h556568) begin - case (guard__h547893) + case (guard__h547897) 2'b0, 2'b01: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 = - _theResult___snd__h555829[56:5]; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = + _theResult___snd__h555833[56:5]; 2'b10: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 = - out_sfd__h556567; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = + out_sfd__h556571; 2'b11: - CASE_guard47893_0b0_theResult___snd55829_BITS__ETC__q202 = - _theResult___sfd__h556564; + CASE_guard47897_0b0_theResult___snd55833_BITS__ETC__q202 = + _theResult___sfd__h556568; endcase end - always@(guard__h500023 or - _theResult___fst_exp__h508249 or _theResult___exp__h508978) + always@(guard__h500027 or + _theResult___fst_exp__h508253 or _theResult___exp__h508982) begin - case (guard__h500023) + case (guard__h500027) 2'b0: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203 = - _theResult___fst_exp__h508249; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = + _theResult___fst_exp__h508253; 2'b01, 2'b10, 2'b11: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203 = - _theResult___exp__h508978; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203 = + _theResult___exp__h508982; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h508249 or + _theResult___fst_exp__h508253 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048 or - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203) + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - _theResult___fst_exp__h508249; + _theResult___fst_exp__h508253; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9050; @@ -33595,49 +33595,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9048; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q203; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9054 = 11'd0; endcase end - always@(guard__h500023 or - _theResult___fst_exp__h508249 or - out_exp__h508981 or _theResult___exp__h508978) + always@(guard__h500027 or + _theResult___fst_exp__h508253 or + out_exp__h508985 or _theResult___exp__h508982) begin - case (guard__h500023) + case (guard__h500027) 2'b0, 2'b01: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 = - _theResult___fst_exp__h508249; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = + _theResult___fst_exp__h508253; 2'b10: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 = - out_exp__h508981; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = + out_exp__h508985; 2'b11: - CASE_guard00023_0b0_theResult___fst_exp08249_0_ETC__q204 = - _theResult___exp__h508978; + CASE_guard00027_0b0_theResult___fst_exp08253_0_ETC__q204 = + _theResult___exp__h508982; endcase end - always@(guard__h509092 or - _theResult___fst_exp__h517082 or _theResult___exp__h517762) + always@(guard__h509096 or + _theResult___fst_exp__h517086 or _theResult___exp__h517766) begin - case (guard__h509092) + case (guard__h509096) 2'b0: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205 = - _theResult___fst_exp__h517082; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = + _theResult___fst_exp__h517086; 2'b01, 2'b10, 2'b11: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205 = - _theResult___exp__h517762; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205 = + _theResult___exp__h517766; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h517082 or + _theResult___fst_exp__h517086 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079 or - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205) + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - _theResult___fst_exp__h517082; + _theResult___fst_exp__h517086; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9081; @@ -33646,49 +33646,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9079; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q205; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9085 = 11'd0; endcase end - always@(guard__h509092 or - _theResult___fst_exp__h517082 or - out_exp__h517765 or _theResult___exp__h517762) + always@(guard__h509096 or + _theResult___fst_exp__h517086 or + out_exp__h517769 or _theResult___exp__h517766) begin - case (guard__h509092) + case (guard__h509096) 2'b0, 2'b01: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 = - _theResult___fst_exp__h517082; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = + _theResult___fst_exp__h517086; 2'b10: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 = - out_exp__h517765; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = + out_exp__h517769; 2'b11: - CASE_guard09092_0b0_theResult___fst_exp17082_0_ETC__q206 = - _theResult___exp__h517762; + CASE_guard09096_0b0_theResult___fst_exp17086_0_ETC__q206 = + _theResult___exp__h517766; endcase end - always@(guard__h490711 or - _theResult___snd__h498623 or _theResult___sfd__h499328) + always@(guard__h490715 or + _theResult___snd__h498627 or _theResult___sfd__h499332) begin - case (guard__h490711) + case (guard__h490715) 2'b0: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207 = - _theResult___snd__h498623[56:5]; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = + _theResult___snd__h498627[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207 = - _theResult___sfd__h499328; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207 = + _theResult___sfd__h499332; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h498623 or + _theResult___snd__h498627 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105 or - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207) + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - _theResult___snd__h498623[56:5]; + _theResult___snd__h498627[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9107; @@ -33697,49 +33697,49 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9105; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q207; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9111 = 52'd0; endcase end - always@(guard__h490711 or - _theResult___snd__h498623 or - out_sfd__h499331 or _theResult___sfd__h499328) + always@(guard__h490715 or + _theResult___snd__h498627 or + out_sfd__h499335 or _theResult___sfd__h499332) begin - case (guard__h490711) + case (guard__h490715) 2'b0, 2'b01: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 = - _theResult___snd__h498623[56:5]; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = + _theResult___snd__h498627[56:5]; 2'b10: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 = - out_sfd__h499331; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = + out_sfd__h499335; 2'b11: - CASE_guard90711_0b0_theResult___snd98623_BITS__ETC__q208 = - _theResult___sfd__h499328; + CASE_guard90715_0b0_theResult___snd98627_BITS__ETC__q208 = + _theResult___sfd__h499332; endcase end - always@(guard__h509092 or - _theResult___snd__h517028 or _theResult___sfd__h517763) + always@(guard__h509096 or + _theResult___snd__h517032 or _theResult___sfd__h517767) begin - case (guard__h509092) + case (guard__h509096) 2'b0: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209 = - _theResult___snd__h517028[56:5]; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = + _theResult___snd__h517032[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209 = - _theResult___sfd__h517763; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209 = + _theResult___sfd__h517767; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h517028 or + _theResult___snd__h517032 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151 or - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209) + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - _theResult___snd__h517028[56:5]; + _theResult___snd__h517032[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9153; @@ -33748,48 +33748,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9151; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q209; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9157 = 52'd0; endcase end - always@(guard__h509092 or - _theResult___snd__h517028 or - out_sfd__h517766 or _theResult___sfd__h517763) + always@(guard__h509096 or + _theResult___snd__h517032 or + out_sfd__h517770 or _theResult___sfd__h517767) begin - case (guard__h509092) + case (guard__h509096) 2'b0, 2'b01: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 = - _theResult___snd__h517028[56:5]; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = + _theResult___snd__h517032[56:5]; 2'b10: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 = - out_sfd__h517766; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = + out_sfd__h517770; 2'b11: - CASE_guard09092_0b0_theResult___snd17028_BITS__ETC__q210 = - _theResult___sfd__h517763; + CASE_guard09096_0b0_theResult___snd17032_BITS__ETC__q210 = + _theResult___sfd__h517767; endcase end - always@(guard__h500023 or sfdin__h508243 or _theResult___sfd__h508979) + always@(guard__h500027 or sfdin__h508247 or _theResult___sfd__h508983) begin - case (guard__h500023) + case (guard__h500027) 2'b0: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211 = - sfdin__h508243[56:5]; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = + sfdin__h508247[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211 = - _theResult___sfd__h508979; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211 = + _theResult___sfd__h508983; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h508243 or + sfdin__h508247 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132 or - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211) + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - sfdin__h508243[56:5]; + sfdin__h508247[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9134; @@ -33798,48 +33798,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9132; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q211; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9138 = 52'd0; endcase end - always@(guard__h500023 or - sfdin__h508243 or out_sfd__h508982 or _theResult___sfd__h508979) + always@(guard__h500027 or + sfdin__h508247 or out_sfd__h508986 or _theResult___sfd__h508983) begin - case (guard__h500023) + case (guard__h500027) 2'b0, 2'b01: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 = - sfdin__h508243[56:5]; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = + sfdin__h508247[56:5]; 2'b10: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 = - out_sfd__h508982; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = + out_sfd__h508986; 2'b11: - CASE_guard00023_0b0_sfdin08243_BITS_56_TO_5_0b_ETC__q212 = - _theResult___sfd__h508979; + CASE_guard00027_0b0_sfdin08247_BITS_56_TO_5_0b_ETC__q212 = + _theResult___sfd__h508983; endcase end - always@(guard__h568713 or - _theResult___snd__h576625 or _theResult___sfd__h577330) + always@(guard__h568717 or + _theResult___snd__h576629 or _theResult___sfd__h577334) begin - case (guard__h568713) + case (guard__h568717) 2'b0: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213 = - _theResult___snd__h576625[56:5]; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = + _theResult___snd__h576629[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213 = - _theResult___sfd__h577330; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213 = + _theResult___sfd__h577334; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h576625 or + _theResult___snd__h576629 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810 or - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213) + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - _theResult___snd__h576625[56:5]; + _theResult___snd__h576629[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9812; @@ -33848,48 +33848,48 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9810; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q213; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9816 = 52'd0; endcase end - always@(guard__h568713 or - _theResult___snd__h576625 or - out_sfd__h577333 or _theResult___sfd__h577330) + always@(guard__h568717 or + _theResult___snd__h576629 or + out_sfd__h577337 or _theResult___sfd__h577334) begin - case (guard__h568713) + case (guard__h568717) 2'b0, 2'b01: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 = - _theResult___snd__h576625[56:5]; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = + _theResult___snd__h576629[56:5]; 2'b10: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 = - out_sfd__h577333; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = + out_sfd__h577337; 2'b11: - CASE_guard68713_0b0_theResult___snd76625_BITS__ETC__q214 = - _theResult___sfd__h577330; + CASE_guard68717_0b0_theResult___snd76629_BITS__ETC__q214 = + _theResult___sfd__h577334; endcase end - always@(guard__h578025 or sfdin__h586245 or _theResult___sfd__h586981) + always@(guard__h578029 or sfdin__h586249 or _theResult___sfd__h586985) begin - case (guard__h578025) + case (guard__h578029) 2'b0: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h586245[56:5]; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h586249[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h586981; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h586985; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h586245 or + sfdin__h586249 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838 or IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836 or - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215) + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - sfdin__h586245[56:5]; + sfdin__h586249[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9838; @@ -33898,24 +33898,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9836; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q215; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9842 = 52'd0; endcase end - always@(guard__h578025 or - sfdin__h586245 or out_sfd__h586984 or _theResult___sfd__h586981) + always@(guard__h578029 or + sfdin__h586249 or out_sfd__h586988 or _theResult___sfd__h586985) begin - case (guard__h578025) + case (guard__h578029) 2'b0, 2'b01: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h586245[56:5]; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h586249[56:5]; 2'b10: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h586984; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h586988; 2'b11: - CASE_guard78025_0b0_sfdin86245_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h586981; + CASE_guard78029_0b0_sfdin86249_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h586985; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -33950,28 +33950,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10830; endcase end - always@(guard__h587094 or - _theResult___snd__h595030 or _theResult___sfd__h595765) + always@(guard__h587098 or + _theResult___snd__h595034 or _theResult___sfd__h595769) begin - case (guard__h587094) + case (guard__h587098) 2'b0: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217 = - _theResult___snd__h595030[56:5]; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = + _theResult___snd__h595034[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217 = - _theResult___sfd__h595765; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217 = + _theResult___sfd__h595769; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h595030 or + _theResult___snd__h595034 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857 or IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855 or - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217) + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - _theResult___snd__h595030[56:5]; + _theResult___snd__h595034[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9857; @@ -33980,25 +33980,25 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9855; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q217; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9861 = 52'd0; endcase end - always@(guard__h587094 or - _theResult___snd__h595030 or - out_sfd__h595768 or _theResult___sfd__h595765) + always@(guard__h587098 or + _theResult___snd__h595034 or + out_sfd__h595772 or _theResult___sfd__h595769) begin - case (guard__h587094) + case (guard__h587098) 2'b0, 2'b01: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 = - _theResult___snd__h595030[56:5]; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = + _theResult___snd__h595034[56:5]; 2'b10: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 = - out_sfd__h595768; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = + out_sfd__h595772; 2'b11: - CASE_guard87094_0b0_theResult___snd95030_BITS__ETC__q218 = - _theResult___sfd__h595765; + CASE_guard87098_0b0_theResult___snd95034_BITS__ETC__q218 = + _theResult___sfd__h595769; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34311,10 +34311,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h661036 or + always@(k__h661045 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661036) + case (k__h661045) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3217_co_ETC___d13227 = coreFix_aluExe_0_rsAlu$canEnq; @@ -34353,10 +34353,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(k__h661036 or + always@(k__h661045 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h661036) + case (k__h661045) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__321_ETC___d13261 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -34498,14 +34498,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h675470 or + always@(idx__h675479 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13503 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2605_BITS_19_ETC___d13509 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675470) + case (idx__h675479) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2603_AN_ETC___d13528 = fetchStage$pipelines_0_canDeq && @@ -34641,15 +34641,15 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2614_BITS_19_ETC___d13494; endcase end - always@(k__h661036 or + always@(k__h661045 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h661036) + case (k__h661045) 1'd0: - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k61036_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k61045_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -34752,14 +34752,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2605_BITS_191_ETC___d13240; endcase end - always@(idx__h675470 or + always@(idx__h675479 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13731 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2605_BITS_194_TO_ETC___d13738 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h675470) + case (idx__h675479) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__260_ETC___d13742 = (!fetchStage$pipelines_0_canDeq || @@ -35668,28 +35668,6 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -35706,9 +35684,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q263 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = 4'd15; endcase end @@ -37751,7 +37751,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h600770 == 2'd0) + v__h600774 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index 1035e97..8a98286 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -1530,10 +1530,10 @@ module mkCoreW(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5048; + reg [31 : 0] v__h5014; reg [31 : 0] v__h4855; reg [31 : 0] v__h4849; - reg [31 : 0] v__h5042; + reg [31 : 0] v__h5008; // synopsys translate_on // action method set_verbosity @@ -2580,9 +2580,9 @@ module mkCoreW(CLK, // rule RL_rl_hart0_server_reset assign CAN_FIRE_RL_rl_hart0_server_reset = - proc$RDY_hart0_server_reset_response_get ; + proc$RDY_start && proc$RDY_hart0_server_reset_response_get ; assign WILL_FIRE_RL_rl_hart0_server_reset = - proc$RDY_hart0_server_reset_response_get ; + CAN_FIRE_RL_rl_hart0_server_reset ; // rule RL_rl_hart0_server_run_halt assign CAN_FIRE_RL_rl_hart0_server_run_halt = 1'd1 ; @@ -2600,20 +2600,20 @@ module mkCoreW(CLK, // rule RL_rl_gpr assign CAN_FIRE_RL_rl_gpr = - debug_module$RDY_hart0_gpr_mem_client_request_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; + debug_module$RDY_hart0_gpr_mem_client_response_put && + debug_module$RDY_hart0_gpr_mem_client_request_get ; assign WILL_FIRE_RL_rl_gpr = CAN_FIRE_RL_rl_gpr ; // rule RL_rl_fpr assign CAN_FIRE_RL_rl_fpr = - debug_module$RDY_hart0_fpr_mem_client_request_get && - debug_module$RDY_hart0_fpr_mem_client_response_put ; + debug_module$RDY_hart0_fpr_mem_client_response_put && + debug_module$RDY_hart0_fpr_mem_client_request_get ; assign WILL_FIRE_RL_rl_fpr = CAN_FIRE_RL_rl_fpr ; // rule RL_rl_csr assign CAN_FIRE_RL_rl_csr = - debug_module$RDY_hart0_csr_mem_client_request_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + debug_module$RDY_hart0_csr_mem_client_request_get ; assign WILL_FIRE_RL_rl_csr = CAN_FIRE_RL_rl_csr ; // rule RL_rl_cpu_hart0_reset_from_dm_complete @@ -2743,8 +2743,7 @@ module mkCoreW(CLK, // rule RL_rl_cpu_hart0_reset_complete assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - plic$RDY_server_reset_response_get && proc$RDY_start && - f_reset_rsps$FULL_N && + plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N && !cpu_reset$ASSERT_OUT ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; @@ -2904,8 +2903,7 @@ module mkCoreW(CLK, // submodule f_reset_rsps assign f_reset_rsps$ENQ = - plic$RDY_server_reset_response_get && proc$RDY_start && - f_reset_rsps$FULL_N && + plic$RDY_server_reset_response_get && f_reset_rsps$FULL_N && !cpu_reset$ASSERT_OUT ; assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -3131,8 +3129,8 @@ module mkCoreW(CLK, assign proc$start_tohostAddr = rg_tohost_addr ; assign proc$EN_hart0_server_reset_request_put = CAN_FIRE_RL_rl_once ; assign proc$EN_hart0_server_reset_response_get = - proc$RDY_hart0_server_reset_response_get ; - assign proc$EN_start = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + CAN_FIRE_RL_rl_hart0_server_reset ; + assign proc$EN_start = CAN_FIRE_RL_rl_hart0_server_reset ; assign proc$EN_set_verbosity = EN_set_verbosity ; assign proc$EN_trace_data_out_get = CAN_FIRE_RL_merge_cpu_trace_data ; assign proc$EN_hart0_server_run_halt_request_put = 1'b0 ; @@ -3205,18 +3203,16 @@ module mkCoreW(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (cpu_reset_either$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h5048 = $stime; - #0; - end - v__h5042 = v__h5048 / 32'd10; + if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) + begin + v__h5014 = $stime; + #0; + end + v__h5008 = v__h5014 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (cpu_reset_either$RST_OUT != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", - v__h5042); + if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) + $display("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", + v__h5008); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v index 681bff9..1a41e81 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v index 62280a6..935f2d7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v index 659476b..f6ead5f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v index 16f6afa..2843207 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v index b30df25..9f748f7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v index 0d6421c..32b8295 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v index 7eb91a4..1a3ba20 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v index d7ed640..8f7dfb4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v index 053bf66..e885e7d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -7,15 +7,16 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 -// RDY_response_get O 1 +// response_get O 69 reg +// RDY_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// request_put I 131 +// request_put I 131 reg // EN_request_put I 1 // EN_response_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// EN_response_get -> RDY_request_put // // @@ -59,44 +60,4031 @@ module mkDoubleDiv(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu - wire [130 : 0] fpu$request_put; - wire [68 : 0] fpu$response_get; - wire fpu$EN_request_put, - fpu$EN_response_get, - fpu$RDY_request_put, - fpu$RDY_response_get; + // ports of submodule fpu_fOperands_S0 + wire [130 : 0] fpu_fOperands_S0$D_IN, fpu_fOperands_S0$D_OUT; + wire fpu_fOperands_S0$CLR, + fpu_fOperands_S0$DEQ, + fpu_fOperands_S0$EMPTY_N, + fpu_fOperands_S0$ENQ, + fpu_fOperands_S0$FULL_N; + + // ports of submodule fpu_fResult_S5 + wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; + wire fpu_fResult_S5$CLR, + fpu_fResult_S5$DEQ, + fpu_fResult_S5$EMPTY_N, + fpu_fResult_S5$ENQ, + fpu_fResult_S5$FULL_N; + + // ports of submodule fpu_fState_S1 + wire [318 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; + wire fpu_fState_S1$CLR, + fpu_fState_S1$DEQ, + fpu_fState_S1$EMPTY_N, + fpu_fState_S1$ENQ, + fpu_fState_S1$FULL_N; + + // ports of submodule fpu_fState_S2 + wire [147 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; + wire fpu_fState_S2$CLR, + fpu_fState_S2$DEQ, + fpu_fState_S2$EMPTY_N, + fpu_fState_S2$ENQ, + fpu_fState_S2$FULL_N; + + // ports of submodule fpu_fState_S3 + wire [194 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; + wire fpu_fState_S3$CLR, + fpu_fState_S3$DEQ, + fpu_fState_S3$EMPTY_N, + fpu_fState_S3$ENQ, + fpu_fState_S3$FULL_N; + + // ports of submodule fpu_fState_S4 + wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; + wire fpu_fState_S4$CLR, + fpu_fState_S4$DEQ, + fpu_fState_S4$EMPTY_N, + fpu_fState_S4$ENQ, + fpu_fState_S4$FULL_N; + + // ports of submodule int_div_fFirst + wire [231 : 0] int_div_fFirst$D_IN, int_div_fFirst$D_OUT; + wire int_div_fFirst$CLR, + int_div_fFirst$DEQ, + int_div_fFirst$EMPTY_N, + int_div_fFirst$ENQ, + int_div_fFirst$FULL_N; + + // ports of submodule int_div_fNext_0 + wire [231 : 0] int_div_fNext_0$D_IN, int_div_fNext_0$D_OUT; + wire int_div_fNext_0$CLR, + int_div_fNext_0$DEQ, + int_div_fNext_0$EMPTY_N, + int_div_fNext_0$ENQ, + int_div_fNext_0$FULL_N; + + // ports of submodule int_div_fNext_1 + wire [231 : 0] int_div_fNext_1$D_IN, int_div_fNext_1$D_OUT; + wire int_div_fNext_1$CLR, + int_div_fNext_1$DEQ, + int_div_fNext_1$EMPTY_N, + int_div_fNext_1$ENQ, + int_div_fNext_1$FULL_N; + + // ports of submodule int_div_fNext_10 + wire [231 : 0] int_div_fNext_10$D_IN, int_div_fNext_10$D_OUT; + wire int_div_fNext_10$CLR, + int_div_fNext_10$DEQ, + int_div_fNext_10$EMPTY_N, + int_div_fNext_10$ENQ, + int_div_fNext_10$FULL_N; + + // ports of submodule int_div_fNext_11 + wire [231 : 0] int_div_fNext_11$D_IN, int_div_fNext_11$D_OUT; + wire int_div_fNext_11$CLR, + int_div_fNext_11$DEQ, + int_div_fNext_11$EMPTY_N, + int_div_fNext_11$ENQ, + int_div_fNext_11$FULL_N; + + // ports of submodule int_div_fNext_12 + wire [231 : 0] int_div_fNext_12$D_IN, int_div_fNext_12$D_OUT; + wire int_div_fNext_12$CLR, + int_div_fNext_12$DEQ, + int_div_fNext_12$EMPTY_N, + int_div_fNext_12$ENQ, + int_div_fNext_12$FULL_N; + + // ports of submodule int_div_fNext_13 + wire [231 : 0] int_div_fNext_13$D_IN, int_div_fNext_13$D_OUT; + wire int_div_fNext_13$CLR, + int_div_fNext_13$DEQ, + int_div_fNext_13$EMPTY_N, + int_div_fNext_13$ENQ, + int_div_fNext_13$FULL_N; + + // ports of submodule int_div_fNext_14 + wire [231 : 0] int_div_fNext_14$D_IN, int_div_fNext_14$D_OUT; + wire int_div_fNext_14$CLR, + int_div_fNext_14$DEQ, + int_div_fNext_14$EMPTY_N, + int_div_fNext_14$ENQ, + int_div_fNext_14$FULL_N; + + // ports of submodule int_div_fNext_15 + wire [231 : 0] int_div_fNext_15$D_IN, int_div_fNext_15$D_OUT; + wire int_div_fNext_15$CLR, + int_div_fNext_15$DEQ, + int_div_fNext_15$EMPTY_N, + int_div_fNext_15$ENQ, + int_div_fNext_15$FULL_N; + + // ports of submodule int_div_fNext_16 + wire [231 : 0] int_div_fNext_16$D_IN, int_div_fNext_16$D_OUT; + wire int_div_fNext_16$CLR, + int_div_fNext_16$DEQ, + int_div_fNext_16$EMPTY_N, + int_div_fNext_16$ENQ, + int_div_fNext_16$FULL_N; + + // ports of submodule int_div_fNext_17 + wire [231 : 0] int_div_fNext_17$D_IN, int_div_fNext_17$D_OUT; + wire int_div_fNext_17$CLR, + int_div_fNext_17$DEQ, + int_div_fNext_17$EMPTY_N, + int_div_fNext_17$ENQ, + int_div_fNext_17$FULL_N; + + // ports of submodule int_div_fNext_18 + wire [231 : 0] int_div_fNext_18$D_IN, int_div_fNext_18$D_OUT; + wire int_div_fNext_18$CLR, + int_div_fNext_18$DEQ, + int_div_fNext_18$EMPTY_N, + int_div_fNext_18$ENQ, + int_div_fNext_18$FULL_N; + + // ports of submodule int_div_fNext_19 + wire [231 : 0] int_div_fNext_19$D_IN, int_div_fNext_19$D_OUT; + wire int_div_fNext_19$CLR, + int_div_fNext_19$DEQ, + int_div_fNext_19$EMPTY_N, + int_div_fNext_19$ENQ, + int_div_fNext_19$FULL_N; + + // ports of submodule int_div_fNext_2 + wire [231 : 0] int_div_fNext_2$D_IN, int_div_fNext_2$D_OUT; + wire int_div_fNext_2$CLR, + int_div_fNext_2$DEQ, + int_div_fNext_2$EMPTY_N, + int_div_fNext_2$ENQ, + int_div_fNext_2$FULL_N; + + // ports of submodule int_div_fNext_20 + wire [231 : 0] int_div_fNext_20$D_IN, int_div_fNext_20$D_OUT; + wire int_div_fNext_20$CLR, + int_div_fNext_20$DEQ, + int_div_fNext_20$EMPTY_N, + int_div_fNext_20$ENQ, + int_div_fNext_20$FULL_N; + + // ports of submodule int_div_fNext_21 + wire [231 : 0] int_div_fNext_21$D_IN, int_div_fNext_21$D_OUT; + wire int_div_fNext_21$CLR, + int_div_fNext_21$DEQ, + int_div_fNext_21$EMPTY_N, + int_div_fNext_21$ENQ, + int_div_fNext_21$FULL_N; + + // ports of submodule int_div_fNext_22 + wire [231 : 0] int_div_fNext_22$D_IN, int_div_fNext_22$D_OUT; + wire int_div_fNext_22$CLR, + int_div_fNext_22$DEQ, + int_div_fNext_22$EMPTY_N, + int_div_fNext_22$ENQ, + int_div_fNext_22$FULL_N; + + // ports of submodule int_div_fNext_23 + wire [231 : 0] int_div_fNext_23$D_IN, int_div_fNext_23$D_OUT; + wire int_div_fNext_23$CLR, + int_div_fNext_23$DEQ, + int_div_fNext_23$EMPTY_N, + int_div_fNext_23$ENQ, + int_div_fNext_23$FULL_N; + + // ports of submodule int_div_fNext_24 + wire [231 : 0] int_div_fNext_24$D_IN, int_div_fNext_24$D_OUT; + wire int_div_fNext_24$CLR, + int_div_fNext_24$DEQ, + int_div_fNext_24$EMPTY_N, + int_div_fNext_24$ENQ, + int_div_fNext_24$FULL_N; + + // ports of submodule int_div_fNext_25 + wire [231 : 0] int_div_fNext_25$D_IN, int_div_fNext_25$D_OUT; + wire int_div_fNext_25$CLR, + int_div_fNext_25$DEQ, + int_div_fNext_25$EMPTY_N, + int_div_fNext_25$ENQ, + int_div_fNext_25$FULL_N; + + // ports of submodule int_div_fNext_26 + wire [231 : 0] int_div_fNext_26$D_IN, int_div_fNext_26$D_OUT; + wire int_div_fNext_26$CLR, + int_div_fNext_26$DEQ, + int_div_fNext_26$EMPTY_N, + int_div_fNext_26$ENQ, + int_div_fNext_26$FULL_N; + + // ports of submodule int_div_fNext_27 + wire [231 : 0] int_div_fNext_27$D_IN, int_div_fNext_27$D_OUT; + wire int_div_fNext_27$CLR, + int_div_fNext_27$DEQ, + int_div_fNext_27$EMPTY_N, + int_div_fNext_27$ENQ, + int_div_fNext_27$FULL_N; + + // ports of submodule int_div_fNext_28 + wire [231 : 0] int_div_fNext_28$D_IN, int_div_fNext_28$D_OUT; + wire int_div_fNext_28$CLR, + int_div_fNext_28$DEQ, + int_div_fNext_28$EMPTY_N, + int_div_fNext_28$ENQ, + int_div_fNext_28$FULL_N; + + // ports of submodule int_div_fNext_29 + wire [231 : 0] int_div_fNext_29$D_IN, int_div_fNext_29$D_OUT; + wire int_div_fNext_29$CLR, + int_div_fNext_29$DEQ, + int_div_fNext_29$EMPTY_N, + int_div_fNext_29$ENQ, + int_div_fNext_29$FULL_N; + + // ports of submodule int_div_fNext_3 + wire [231 : 0] int_div_fNext_3$D_IN, int_div_fNext_3$D_OUT; + wire int_div_fNext_3$CLR, + int_div_fNext_3$DEQ, + int_div_fNext_3$EMPTY_N, + int_div_fNext_3$ENQ, + int_div_fNext_3$FULL_N; + + // ports of submodule int_div_fNext_30 + wire [231 : 0] int_div_fNext_30$D_IN, int_div_fNext_30$D_OUT; + wire int_div_fNext_30$CLR, + int_div_fNext_30$DEQ, + int_div_fNext_30$EMPTY_N, + int_div_fNext_30$ENQ, + int_div_fNext_30$FULL_N; + + // ports of submodule int_div_fNext_31 + wire [231 : 0] int_div_fNext_31$D_IN, int_div_fNext_31$D_OUT; + wire int_div_fNext_31$CLR, + int_div_fNext_31$DEQ, + int_div_fNext_31$EMPTY_N, + int_div_fNext_31$ENQ, + int_div_fNext_31$FULL_N; + + // ports of submodule int_div_fNext_32 + wire [231 : 0] int_div_fNext_32$D_IN, int_div_fNext_32$D_OUT; + wire int_div_fNext_32$CLR, + int_div_fNext_32$DEQ, + int_div_fNext_32$EMPTY_N, + int_div_fNext_32$ENQ, + int_div_fNext_32$FULL_N; + + // ports of submodule int_div_fNext_33 + wire [231 : 0] int_div_fNext_33$D_IN, int_div_fNext_33$D_OUT; + wire int_div_fNext_33$CLR, + int_div_fNext_33$DEQ, + int_div_fNext_33$EMPTY_N, + int_div_fNext_33$ENQ, + int_div_fNext_33$FULL_N; + + // ports of submodule int_div_fNext_34 + wire [231 : 0] int_div_fNext_34$D_IN, int_div_fNext_34$D_OUT; + wire int_div_fNext_34$CLR, + int_div_fNext_34$DEQ, + int_div_fNext_34$EMPTY_N, + int_div_fNext_34$ENQ, + int_div_fNext_34$FULL_N; + + // ports of submodule int_div_fNext_35 + wire [231 : 0] int_div_fNext_35$D_IN, int_div_fNext_35$D_OUT; + wire int_div_fNext_35$CLR, + int_div_fNext_35$DEQ, + int_div_fNext_35$EMPTY_N, + int_div_fNext_35$ENQ, + int_div_fNext_35$FULL_N; + + // ports of submodule int_div_fNext_36 + wire [231 : 0] int_div_fNext_36$D_IN, int_div_fNext_36$D_OUT; + wire int_div_fNext_36$CLR, + int_div_fNext_36$DEQ, + int_div_fNext_36$EMPTY_N, + int_div_fNext_36$ENQ, + int_div_fNext_36$FULL_N; + + // ports of submodule int_div_fNext_37 + wire [231 : 0] int_div_fNext_37$D_IN, int_div_fNext_37$D_OUT; + wire int_div_fNext_37$CLR, + int_div_fNext_37$DEQ, + int_div_fNext_37$EMPTY_N, + int_div_fNext_37$ENQ, + int_div_fNext_37$FULL_N; + + // ports of submodule int_div_fNext_38 + wire [231 : 0] int_div_fNext_38$D_IN, int_div_fNext_38$D_OUT; + wire int_div_fNext_38$CLR, + int_div_fNext_38$DEQ, + int_div_fNext_38$EMPTY_N, + int_div_fNext_38$ENQ, + int_div_fNext_38$FULL_N; + + // ports of submodule int_div_fNext_39 + wire [231 : 0] int_div_fNext_39$D_IN, int_div_fNext_39$D_OUT; + wire int_div_fNext_39$CLR, + int_div_fNext_39$DEQ, + int_div_fNext_39$EMPTY_N, + int_div_fNext_39$ENQ, + int_div_fNext_39$FULL_N; + + // ports of submodule int_div_fNext_4 + wire [231 : 0] int_div_fNext_4$D_IN, int_div_fNext_4$D_OUT; + wire int_div_fNext_4$CLR, + int_div_fNext_4$DEQ, + int_div_fNext_4$EMPTY_N, + int_div_fNext_4$ENQ, + int_div_fNext_4$FULL_N; + + // ports of submodule int_div_fNext_40 + wire [231 : 0] int_div_fNext_40$D_IN, int_div_fNext_40$D_OUT; + wire int_div_fNext_40$CLR, + int_div_fNext_40$DEQ, + int_div_fNext_40$EMPTY_N, + int_div_fNext_40$ENQ, + int_div_fNext_40$FULL_N; + + // ports of submodule int_div_fNext_41 + wire [231 : 0] int_div_fNext_41$D_IN, int_div_fNext_41$D_OUT; + wire int_div_fNext_41$CLR, + int_div_fNext_41$DEQ, + int_div_fNext_41$EMPTY_N, + int_div_fNext_41$ENQ, + int_div_fNext_41$FULL_N; + + // ports of submodule int_div_fNext_42 + wire [231 : 0] int_div_fNext_42$D_IN, int_div_fNext_42$D_OUT; + wire int_div_fNext_42$CLR, + int_div_fNext_42$DEQ, + int_div_fNext_42$EMPTY_N, + int_div_fNext_42$ENQ, + int_div_fNext_42$FULL_N; + + // ports of submodule int_div_fNext_43 + wire [231 : 0] int_div_fNext_43$D_IN, int_div_fNext_43$D_OUT; + wire int_div_fNext_43$CLR, + int_div_fNext_43$DEQ, + int_div_fNext_43$EMPTY_N, + int_div_fNext_43$ENQ, + int_div_fNext_43$FULL_N; + + // ports of submodule int_div_fNext_44 + wire [231 : 0] int_div_fNext_44$D_IN, int_div_fNext_44$D_OUT; + wire int_div_fNext_44$CLR, + int_div_fNext_44$DEQ, + int_div_fNext_44$EMPTY_N, + int_div_fNext_44$ENQ, + int_div_fNext_44$FULL_N; + + // ports of submodule int_div_fNext_45 + wire [231 : 0] int_div_fNext_45$D_IN, int_div_fNext_45$D_OUT; + wire int_div_fNext_45$CLR, + int_div_fNext_45$DEQ, + int_div_fNext_45$EMPTY_N, + int_div_fNext_45$ENQ, + int_div_fNext_45$FULL_N; + + // ports of submodule int_div_fNext_46 + wire [231 : 0] int_div_fNext_46$D_IN, int_div_fNext_46$D_OUT; + wire int_div_fNext_46$CLR, + int_div_fNext_46$DEQ, + int_div_fNext_46$EMPTY_N, + int_div_fNext_46$ENQ, + int_div_fNext_46$FULL_N; + + // ports of submodule int_div_fNext_47 + wire [231 : 0] int_div_fNext_47$D_IN, int_div_fNext_47$D_OUT; + wire int_div_fNext_47$CLR, + int_div_fNext_47$DEQ, + int_div_fNext_47$EMPTY_N, + int_div_fNext_47$ENQ, + int_div_fNext_47$FULL_N; + + // ports of submodule int_div_fNext_48 + wire [231 : 0] int_div_fNext_48$D_IN, int_div_fNext_48$D_OUT; + wire int_div_fNext_48$CLR, + int_div_fNext_48$DEQ, + int_div_fNext_48$EMPTY_N, + int_div_fNext_48$ENQ, + int_div_fNext_48$FULL_N; + + // ports of submodule int_div_fNext_49 + wire [231 : 0] int_div_fNext_49$D_IN, int_div_fNext_49$D_OUT; + wire int_div_fNext_49$CLR, + int_div_fNext_49$DEQ, + int_div_fNext_49$EMPTY_N, + int_div_fNext_49$ENQ, + int_div_fNext_49$FULL_N; + + // ports of submodule int_div_fNext_5 + wire [231 : 0] int_div_fNext_5$D_IN, int_div_fNext_5$D_OUT; + wire int_div_fNext_5$CLR, + int_div_fNext_5$DEQ, + int_div_fNext_5$EMPTY_N, + int_div_fNext_5$ENQ, + int_div_fNext_5$FULL_N; + + // ports of submodule int_div_fNext_50 + wire [231 : 0] int_div_fNext_50$D_IN, int_div_fNext_50$D_OUT; + wire int_div_fNext_50$CLR, + int_div_fNext_50$DEQ, + int_div_fNext_50$EMPTY_N, + int_div_fNext_50$ENQ, + int_div_fNext_50$FULL_N; + + // ports of submodule int_div_fNext_51 + wire [231 : 0] int_div_fNext_51$D_IN, int_div_fNext_51$D_OUT; + wire int_div_fNext_51$CLR, + int_div_fNext_51$DEQ, + int_div_fNext_51$EMPTY_N, + int_div_fNext_51$ENQ, + int_div_fNext_51$FULL_N; + + // ports of submodule int_div_fNext_52 + wire [231 : 0] int_div_fNext_52$D_IN, int_div_fNext_52$D_OUT; + wire int_div_fNext_52$CLR, + int_div_fNext_52$DEQ, + int_div_fNext_52$EMPTY_N, + int_div_fNext_52$ENQ, + int_div_fNext_52$FULL_N; + + // ports of submodule int_div_fNext_53 + wire [231 : 0] int_div_fNext_53$D_IN, int_div_fNext_53$D_OUT; + wire int_div_fNext_53$CLR, + int_div_fNext_53$DEQ, + int_div_fNext_53$EMPTY_N, + int_div_fNext_53$ENQ, + int_div_fNext_53$FULL_N; + + // ports of submodule int_div_fNext_54 + wire [231 : 0] int_div_fNext_54$D_IN, int_div_fNext_54$D_OUT; + wire int_div_fNext_54$CLR, + int_div_fNext_54$DEQ, + int_div_fNext_54$EMPTY_N, + int_div_fNext_54$ENQ, + int_div_fNext_54$FULL_N; + + // ports of submodule int_div_fNext_55 + wire [231 : 0] int_div_fNext_55$D_IN, int_div_fNext_55$D_OUT; + wire int_div_fNext_55$CLR, + int_div_fNext_55$DEQ, + int_div_fNext_55$EMPTY_N, + int_div_fNext_55$ENQ, + int_div_fNext_55$FULL_N; + + // ports of submodule int_div_fNext_56 + wire [231 : 0] int_div_fNext_56$D_IN, int_div_fNext_56$D_OUT; + wire int_div_fNext_56$CLR, + int_div_fNext_56$DEQ, + int_div_fNext_56$EMPTY_N, + int_div_fNext_56$ENQ, + int_div_fNext_56$FULL_N; + + // ports of submodule int_div_fNext_57 + wire [231 : 0] int_div_fNext_57$D_IN, int_div_fNext_57$D_OUT; + wire int_div_fNext_57$CLR, + int_div_fNext_57$DEQ, + int_div_fNext_57$EMPTY_N, + int_div_fNext_57$ENQ, + int_div_fNext_57$FULL_N; + + // ports of submodule int_div_fNext_6 + wire [231 : 0] int_div_fNext_6$D_IN, int_div_fNext_6$D_OUT; + wire int_div_fNext_6$CLR, + int_div_fNext_6$DEQ, + int_div_fNext_6$EMPTY_N, + int_div_fNext_6$ENQ, + int_div_fNext_6$FULL_N; + + // ports of submodule int_div_fNext_7 + wire [231 : 0] int_div_fNext_7$D_IN, int_div_fNext_7$D_OUT; + wire int_div_fNext_7$CLR, + int_div_fNext_7$DEQ, + int_div_fNext_7$EMPTY_N, + int_div_fNext_7$ENQ, + int_div_fNext_7$FULL_N; + + // ports of submodule int_div_fNext_8 + wire [231 : 0] int_div_fNext_8$D_IN, int_div_fNext_8$D_OUT; + wire int_div_fNext_8$CLR, + int_div_fNext_8$DEQ, + int_div_fNext_8$EMPTY_N, + int_div_fNext_8$ENQ, + int_div_fNext_8$FULL_N; + + // ports of submodule int_div_fNext_9 + wire [231 : 0] int_div_fNext_9$D_IN, int_div_fNext_9$D_OUT; + wire int_div_fNext_9$CLR, + int_div_fNext_9$DEQ, + int_div_fNext_9$EMPTY_N, + int_div_fNext_9$ENQ, + int_div_fNext_9$FULL_N; + + // ports of submodule int_div_fRequest + wire [170 : 0] int_div_fRequest$D_IN, int_div_fRequest$D_OUT; + wire int_div_fRequest$CLR, + int_div_fRequest$DEQ, + int_div_fRequest$EMPTY_N, + int_div_fRequest$ENQ, + int_div_fRequest$FULL_N; + + // ports of submodule int_div_fResponse + wire [113 : 0] int_div_fResponse$D_IN, int_div_fResponse$D_OUT; + wire int_div_fResponse$CLR, + int_div_fResponse$DEQ, + int_div_fResponse$EMPTY_N, + int_div_fResponse$ENQ, + int_div_fResponse$FULL_N; // rule scheduling signals - wire CAN_FIRE_request_put, + wire CAN_FIRE_RL_fpu_s1_stage, + CAN_FIRE_RL_fpu_s2_stage, + CAN_FIRE_RL_fpu_s3_stage, + CAN_FIRE_RL_fpu_s4_stage, + CAN_FIRE_RL_fpu_s5_stage, + CAN_FIRE_RL_int_div_finish, + CAN_FIRE_RL_int_div_start, + CAN_FIRE_RL_int_div_work, + CAN_FIRE_RL_int_div_work_1, + CAN_FIRE_RL_int_div_work_10, + CAN_FIRE_RL_int_div_work_11, + CAN_FIRE_RL_int_div_work_12, + CAN_FIRE_RL_int_div_work_13, + CAN_FIRE_RL_int_div_work_14, + CAN_FIRE_RL_int_div_work_15, + CAN_FIRE_RL_int_div_work_16, + CAN_FIRE_RL_int_div_work_17, + CAN_FIRE_RL_int_div_work_18, + CAN_FIRE_RL_int_div_work_19, + CAN_FIRE_RL_int_div_work_2, + CAN_FIRE_RL_int_div_work_20, + CAN_FIRE_RL_int_div_work_21, + CAN_FIRE_RL_int_div_work_22, + CAN_FIRE_RL_int_div_work_23, + CAN_FIRE_RL_int_div_work_24, + CAN_FIRE_RL_int_div_work_25, + CAN_FIRE_RL_int_div_work_26, + CAN_FIRE_RL_int_div_work_27, + CAN_FIRE_RL_int_div_work_28, + CAN_FIRE_RL_int_div_work_29, + CAN_FIRE_RL_int_div_work_3, + CAN_FIRE_RL_int_div_work_30, + CAN_FIRE_RL_int_div_work_31, + CAN_FIRE_RL_int_div_work_32, + CAN_FIRE_RL_int_div_work_33, + CAN_FIRE_RL_int_div_work_34, + CAN_FIRE_RL_int_div_work_35, + CAN_FIRE_RL_int_div_work_36, + CAN_FIRE_RL_int_div_work_37, + CAN_FIRE_RL_int_div_work_38, + CAN_FIRE_RL_int_div_work_39, + CAN_FIRE_RL_int_div_work_4, + CAN_FIRE_RL_int_div_work_40, + CAN_FIRE_RL_int_div_work_41, + CAN_FIRE_RL_int_div_work_42, + CAN_FIRE_RL_int_div_work_43, + CAN_FIRE_RL_int_div_work_44, + CAN_FIRE_RL_int_div_work_45, + CAN_FIRE_RL_int_div_work_46, + CAN_FIRE_RL_int_div_work_47, + CAN_FIRE_RL_int_div_work_48, + CAN_FIRE_RL_int_div_work_49, + CAN_FIRE_RL_int_div_work_5, + CAN_FIRE_RL_int_div_work_50, + CAN_FIRE_RL_int_div_work_51, + CAN_FIRE_RL_int_div_work_52, + CAN_FIRE_RL_int_div_work_53, + CAN_FIRE_RL_int_div_work_54, + CAN_FIRE_RL_int_div_work_55, + CAN_FIRE_RL_int_div_work_56, + CAN_FIRE_RL_int_div_work_57, + CAN_FIRE_RL_int_div_work_6, + CAN_FIRE_RL_int_div_work_7, + CAN_FIRE_RL_int_div_work_8, + CAN_FIRE_RL_int_div_work_9, + CAN_FIRE_request_put, CAN_FIRE_response_get, + WILL_FIRE_RL_fpu_s1_stage, + WILL_FIRE_RL_fpu_s2_stage, + WILL_FIRE_RL_fpu_s3_stage, + WILL_FIRE_RL_fpu_s4_stage, + WILL_FIRE_RL_fpu_s5_stage, + WILL_FIRE_RL_int_div_finish, + WILL_FIRE_RL_int_div_start, + WILL_FIRE_RL_int_div_work, + WILL_FIRE_RL_int_div_work_1, + WILL_FIRE_RL_int_div_work_10, + WILL_FIRE_RL_int_div_work_11, + WILL_FIRE_RL_int_div_work_12, + WILL_FIRE_RL_int_div_work_13, + WILL_FIRE_RL_int_div_work_14, + WILL_FIRE_RL_int_div_work_15, + WILL_FIRE_RL_int_div_work_16, + WILL_FIRE_RL_int_div_work_17, + WILL_FIRE_RL_int_div_work_18, + WILL_FIRE_RL_int_div_work_19, + WILL_FIRE_RL_int_div_work_2, + WILL_FIRE_RL_int_div_work_20, + WILL_FIRE_RL_int_div_work_21, + WILL_FIRE_RL_int_div_work_22, + WILL_FIRE_RL_int_div_work_23, + WILL_FIRE_RL_int_div_work_24, + WILL_FIRE_RL_int_div_work_25, + WILL_FIRE_RL_int_div_work_26, + WILL_FIRE_RL_int_div_work_27, + WILL_FIRE_RL_int_div_work_28, + WILL_FIRE_RL_int_div_work_29, + WILL_FIRE_RL_int_div_work_3, + WILL_FIRE_RL_int_div_work_30, + WILL_FIRE_RL_int_div_work_31, + WILL_FIRE_RL_int_div_work_32, + WILL_FIRE_RL_int_div_work_33, + WILL_FIRE_RL_int_div_work_34, + WILL_FIRE_RL_int_div_work_35, + WILL_FIRE_RL_int_div_work_36, + WILL_FIRE_RL_int_div_work_37, + WILL_FIRE_RL_int_div_work_38, + WILL_FIRE_RL_int_div_work_39, + WILL_FIRE_RL_int_div_work_4, + WILL_FIRE_RL_int_div_work_40, + WILL_FIRE_RL_int_div_work_41, + WILL_FIRE_RL_int_div_work_42, + WILL_FIRE_RL_int_div_work_43, + WILL_FIRE_RL_int_div_work_44, + WILL_FIRE_RL_int_div_work_45, + WILL_FIRE_RL_int_div_work_46, + WILL_FIRE_RL_int_div_work_47, + WILL_FIRE_RL_int_div_work_48, + WILL_FIRE_RL_int_div_work_49, + WILL_FIRE_RL_int_div_work_5, + WILL_FIRE_RL_int_div_work_50, + WILL_FIRE_RL_int_div_work_51, + WILL_FIRE_RL_int_div_work_52, + WILL_FIRE_RL_int_div_work_53, + WILL_FIRE_RL_int_div_work_54, + WILL_FIRE_RL_int_div_work_55, + WILL_FIRE_RL_int_div_work_56, + WILL_FIRE_RL_int_div_work_57, + WILL_FIRE_RL_int_div_work_6, + WILL_FIRE_RL_int_div_work_7, + WILL_FIRE_RL_int_div_work_8, + WILL_FIRE_RL_int_div_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; + // remaining internal signals + reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16; + reg [62 : 0] CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12; + reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, + _theResult___fst_sfd__h37218, + _theResult___fst_sfd__h37707, + _theResult___fst_sfd__h60989; + reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9, + _theResult___fst_exp__h37217, + _theResult___fst_exp__h60988; + reg CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5, + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11; + wire [115 : 0] b__h10163, + b__h10487, + b__h10811, + b__h1091, + b__h11135, + b__h11459, + b__h11783, + b__h12107, + b__h12431, + b__h12755, + b__h13079, + b__h13403, + b__h13727, + b__h14051, + b__h1415, + b__h14375, + b__h14699, + b__h15023, + b__h15347, + b__h15671, + b__h15995, + b__h16319, + b__h16643, + b__h16967, + b__h17291, + b__h1739, + b__h17615, + b__h17939, + b__h18263, + b__h18587, + b__h18911, + b__h19235, + b__h19482, + b__h2063, + b__h2387, + b__h2711, + b__h3035, + b__h3359, + b__h3683, + b__h4007, + b__h4331, + b__h4655, + b__h4979, + b__h5303, + b__h5627, + b__h5951, + b__h6275, + b__h6599, + b__h6923, + b__h7247, + b__h7571, + b__h767, + b__h7895, + b__h8219, + b__h8543, + b__h8867, + b__h9191, + b__h9515, + b__h9839, + value__h19447; + wire [113 : 0] x__h49176; + wire [63 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305, + fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780; + wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773; + wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7, + IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19, + _theResult____h50063, + _theResult___snd__h52150, + _theResult___snd__h59785, + _theResult___snd__h59800, + _theResult___snd__h59802, + _theResult___snd__h59815, + _theResult___snd__h59821, + _theResult___snd__h59839, + _theResult___snd__h59844, + _theResult___snd_snd_snd__h51398, + b__h378, + int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945, + result__h50077, + result__h50108, + result__h50258, + sfdin__h51553, + sfdin__h59762, + x__h50197, + x__h50487; + wire [56 : 0] value__h50121, x__h49237; + wire [53 : 0] sfd__h60417, value__h49179; + wire [52 : 0] sfdA__h19785, sfdA__h19789, sfdB__h19786, sfdB__h19791; + wire [51 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303, + _theResult___fst_sfd__h60992, + _theResult___sfd__h60911, + _theResult___snd_fst_sfd__h49112, + out_sfd__h60914, + sfd__h36684, + sfd__h36687; + wire [12 : 0] IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205, + value__h49124, + value__h49300; + wire [11 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726; + wire [10 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, + IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, + _theResult___exp__h60910, + _theResult___fst__h49072, + _theResult___fst_exp__h59719, + _theResult___fst_exp__h59722, + _theResult___fst_exp__h59725, + _theResult___fst_exp__h59768, + _theResult___fst_exp__h59771, + _theResult___fst_exp__h59791, + _theResult___fst_exp__h59807, + _theResult___fst_exp__h59846, + _theResult___fst_exp__h59852, + _theResult___fst_exp__h59855, + _theResult___fst_exp__h60991, + _theResult___snd_fst_exp__h49084, + _theResult___snd_fst_exp__h49087, + _theResult___snd_fst_exp__h49111, + din_inc___2_exp__h61001, + fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3, + fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4, + out_exp__h60913, + theResult___fst_exp9725_MINUS_1023__q6, + x__h49291, + x__h50204; + wire [5 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724, + b__h21789, + b__h29207; + wire [4 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765; + wire [1 : 0] IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8, + _theResult___snd_fst__h59874, + guard__h51381, + x__h60140; + wire IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208, + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352, + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441, + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253, + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, + _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351, + fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212, + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, + sfdlsb__h50103; + // action method request_put - assign RDY_request_put = fpu$RDY_request_put ; - assign CAN_FIRE_request_put = fpu$RDY_request_put ; + assign RDY_request_put = fpu_fOperands_S0$FULL_N ; + assign CAN_FIRE_request_put = fpu_fOperands_S0$FULL_N ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu$response_get ; - assign RDY_response_get = fpu$RDY_response_get ; - assign CAN_FIRE_response_get = fpu$RDY_response_get ; + assign response_get = fpu_fResult_S5$D_OUT ; + assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; + assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu - mkXilinxFpDiv fpu(.CLK(CLK), - .RST_N(RST_N), - .request_put(fpu$request_put), - .EN_request_put(fpu$EN_request_put), - .EN_response_get(fpu$EN_response_get), - .RDY_request_put(fpu$RDY_request_put), - .response_get(fpu$response_get), - .RDY_response_get(fpu$RDY_response_get)); + // submodule fpu_fOperands_S0 + FIFOL1 #(.width(32'd131)) fpu_fOperands_S0(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fOperands_S0$D_IN), + .ENQ(fpu_fOperands_S0$ENQ), + .DEQ(fpu_fOperands_S0$DEQ), + .CLR(fpu_fOperands_S0$CLR), + .D_OUT(fpu_fOperands_S0$D_OUT), + .FULL_N(fpu_fOperands_S0$FULL_N), + .EMPTY_N(fpu_fOperands_S0$EMPTY_N)); - // submodule fpu - assign fpu$request_put = request_put ; - assign fpu$EN_request_put = EN_request_put ; - assign fpu$EN_response_get = EN_response_get ; + // submodule fpu_fResult_S5 + FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fResult_S5$D_IN), + .ENQ(fpu_fResult_S5$ENQ), + .DEQ(fpu_fResult_S5$DEQ), + .CLR(fpu_fResult_S5$CLR), + .D_OUT(fpu_fResult_S5$D_OUT), + .FULL_N(fpu_fResult_S5$FULL_N), + .EMPTY_N(fpu_fResult_S5$EMPTY_N)); + + // submodule fpu_fState_S1 + FIFOL1 #(.width(32'd319)) fpu_fState_S1(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S1$D_IN), + .ENQ(fpu_fState_S1$ENQ), + .DEQ(fpu_fState_S1$DEQ), + .CLR(fpu_fState_S1$CLR), + .D_OUT(fpu_fState_S1$D_OUT), + .FULL_N(fpu_fState_S1$FULL_N), + .EMPTY_N(fpu_fState_S1$EMPTY_N)); + + // submodule fpu_fState_S2 + FIFOL1 #(.width(32'd148)) fpu_fState_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S2$D_IN), + .ENQ(fpu_fState_S2$ENQ), + .DEQ(fpu_fState_S2$DEQ), + .CLR(fpu_fState_S2$CLR), + .D_OUT(fpu_fState_S2$D_OUT), + .FULL_N(fpu_fState_S2$FULL_N), + .EMPTY_N(fpu_fState_S2$EMPTY_N)); + + // submodule fpu_fState_S3 + FIFOL1 #(.width(32'd195)) fpu_fState_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S3$D_IN), + .ENQ(fpu_fState_S3$ENQ), + .DEQ(fpu_fState_S3$DEQ), + .CLR(fpu_fState_S3$CLR), + .D_OUT(fpu_fState_S3$D_OUT), + .FULL_N(fpu_fState_S3$FULL_N), + .EMPTY_N(fpu_fState_S3$EMPTY_N)); + + // submodule fpu_fState_S4 + FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S4$D_IN), + .ENQ(fpu_fState_S4$ENQ), + .DEQ(fpu_fState_S4$DEQ), + .CLR(fpu_fState_S4$CLR), + .D_OUT(fpu_fState_S4$D_OUT), + .FULL_N(fpu_fState_S4$FULL_N), + .EMPTY_N(fpu_fState_S4$EMPTY_N)); + + // submodule int_div_fFirst + FIFOL1 #(.width(32'd232)) int_div_fFirst(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fFirst$D_IN), + .ENQ(int_div_fFirst$ENQ), + .DEQ(int_div_fFirst$DEQ), + .CLR(int_div_fFirst$CLR), + .D_OUT(int_div_fFirst$D_OUT), + .FULL_N(int_div_fFirst$FULL_N), + .EMPTY_N(int_div_fFirst$EMPTY_N)); + + // submodule int_div_fNext_0 + FIFOL1 #(.width(32'd232)) int_div_fNext_0(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_0$D_IN), + .ENQ(int_div_fNext_0$ENQ), + .DEQ(int_div_fNext_0$DEQ), + .CLR(int_div_fNext_0$CLR), + .D_OUT(int_div_fNext_0$D_OUT), + .FULL_N(int_div_fNext_0$FULL_N), + .EMPTY_N(int_div_fNext_0$EMPTY_N)); + + // submodule int_div_fNext_1 + FIFOL1 #(.width(32'd232)) int_div_fNext_1(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_1$D_IN), + .ENQ(int_div_fNext_1$ENQ), + .DEQ(int_div_fNext_1$DEQ), + .CLR(int_div_fNext_1$CLR), + .D_OUT(int_div_fNext_1$D_OUT), + .FULL_N(int_div_fNext_1$FULL_N), + .EMPTY_N(int_div_fNext_1$EMPTY_N)); + + // submodule int_div_fNext_10 + FIFOL1 #(.width(32'd232)) int_div_fNext_10(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_10$D_IN), + .ENQ(int_div_fNext_10$ENQ), + .DEQ(int_div_fNext_10$DEQ), + .CLR(int_div_fNext_10$CLR), + .D_OUT(int_div_fNext_10$D_OUT), + .FULL_N(int_div_fNext_10$FULL_N), + .EMPTY_N(int_div_fNext_10$EMPTY_N)); + + // submodule int_div_fNext_11 + FIFOL1 #(.width(32'd232)) int_div_fNext_11(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_11$D_IN), + .ENQ(int_div_fNext_11$ENQ), + .DEQ(int_div_fNext_11$DEQ), + .CLR(int_div_fNext_11$CLR), + .D_OUT(int_div_fNext_11$D_OUT), + .FULL_N(int_div_fNext_11$FULL_N), + .EMPTY_N(int_div_fNext_11$EMPTY_N)); + + // submodule int_div_fNext_12 + FIFOL1 #(.width(32'd232)) int_div_fNext_12(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_12$D_IN), + .ENQ(int_div_fNext_12$ENQ), + .DEQ(int_div_fNext_12$DEQ), + .CLR(int_div_fNext_12$CLR), + .D_OUT(int_div_fNext_12$D_OUT), + .FULL_N(int_div_fNext_12$FULL_N), + .EMPTY_N(int_div_fNext_12$EMPTY_N)); + + // submodule int_div_fNext_13 + FIFOL1 #(.width(32'd232)) int_div_fNext_13(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_13$D_IN), + .ENQ(int_div_fNext_13$ENQ), + .DEQ(int_div_fNext_13$DEQ), + .CLR(int_div_fNext_13$CLR), + .D_OUT(int_div_fNext_13$D_OUT), + .FULL_N(int_div_fNext_13$FULL_N), + .EMPTY_N(int_div_fNext_13$EMPTY_N)); + + // submodule int_div_fNext_14 + FIFOL1 #(.width(32'd232)) int_div_fNext_14(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_14$D_IN), + .ENQ(int_div_fNext_14$ENQ), + .DEQ(int_div_fNext_14$DEQ), + .CLR(int_div_fNext_14$CLR), + .D_OUT(int_div_fNext_14$D_OUT), + .FULL_N(int_div_fNext_14$FULL_N), + .EMPTY_N(int_div_fNext_14$EMPTY_N)); + + // submodule int_div_fNext_15 + FIFOL1 #(.width(32'd232)) int_div_fNext_15(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_15$D_IN), + .ENQ(int_div_fNext_15$ENQ), + .DEQ(int_div_fNext_15$DEQ), + .CLR(int_div_fNext_15$CLR), + .D_OUT(int_div_fNext_15$D_OUT), + .FULL_N(int_div_fNext_15$FULL_N), + .EMPTY_N(int_div_fNext_15$EMPTY_N)); + + // submodule int_div_fNext_16 + FIFOL1 #(.width(32'd232)) int_div_fNext_16(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_16$D_IN), + .ENQ(int_div_fNext_16$ENQ), + .DEQ(int_div_fNext_16$DEQ), + .CLR(int_div_fNext_16$CLR), + .D_OUT(int_div_fNext_16$D_OUT), + .FULL_N(int_div_fNext_16$FULL_N), + .EMPTY_N(int_div_fNext_16$EMPTY_N)); + + // submodule int_div_fNext_17 + FIFOL1 #(.width(32'd232)) int_div_fNext_17(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_17$D_IN), + .ENQ(int_div_fNext_17$ENQ), + .DEQ(int_div_fNext_17$DEQ), + .CLR(int_div_fNext_17$CLR), + .D_OUT(int_div_fNext_17$D_OUT), + .FULL_N(int_div_fNext_17$FULL_N), + .EMPTY_N(int_div_fNext_17$EMPTY_N)); + + // submodule int_div_fNext_18 + FIFOL1 #(.width(32'd232)) int_div_fNext_18(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_18$D_IN), + .ENQ(int_div_fNext_18$ENQ), + .DEQ(int_div_fNext_18$DEQ), + .CLR(int_div_fNext_18$CLR), + .D_OUT(int_div_fNext_18$D_OUT), + .FULL_N(int_div_fNext_18$FULL_N), + .EMPTY_N(int_div_fNext_18$EMPTY_N)); + + // submodule int_div_fNext_19 + FIFOL1 #(.width(32'd232)) int_div_fNext_19(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_19$D_IN), + .ENQ(int_div_fNext_19$ENQ), + .DEQ(int_div_fNext_19$DEQ), + .CLR(int_div_fNext_19$CLR), + .D_OUT(int_div_fNext_19$D_OUT), + .FULL_N(int_div_fNext_19$FULL_N), + .EMPTY_N(int_div_fNext_19$EMPTY_N)); + + // submodule int_div_fNext_2 + FIFOL1 #(.width(32'd232)) int_div_fNext_2(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_2$D_IN), + .ENQ(int_div_fNext_2$ENQ), + .DEQ(int_div_fNext_2$DEQ), + .CLR(int_div_fNext_2$CLR), + .D_OUT(int_div_fNext_2$D_OUT), + .FULL_N(int_div_fNext_2$FULL_N), + .EMPTY_N(int_div_fNext_2$EMPTY_N)); + + // submodule int_div_fNext_20 + FIFOL1 #(.width(32'd232)) int_div_fNext_20(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_20$D_IN), + .ENQ(int_div_fNext_20$ENQ), + .DEQ(int_div_fNext_20$DEQ), + .CLR(int_div_fNext_20$CLR), + .D_OUT(int_div_fNext_20$D_OUT), + .FULL_N(int_div_fNext_20$FULL_N), + .EMPTY_N(int_div_fNext_20$EMPTY_N)); + + // submodule int_div_fNext_21 + FIFOL1 #(.width(32'd232)) int_div_fNext_21(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_21$D_IN), + .ENQ(int_div_fNext_21$ENQ), + .DEQ(int_div_fNext_21$DEQ), + .CLR(int_div_fNext_21$CLR), + .D_OUT(int_div_fNext_21$D_OUT), + .FULL_N(int_div_fNext_21$FULL_N), + .EMPTY_N(int_div_fNext_21$EMPTY_N)); + + // submodule int_div_fNext_22 + FIFOL1 #(.width(32'd232)) int_div_fNext_22(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_22$D_IN), + .ENQ(int_div_fNext_22$ENQ), + .DEQ(int_div_fNext_22$DEQ), + .CLR(int_div_fNext_22$CLR), + .D_OUT(int_div_fNext_22$D_OUT), + .FULL_N(int_div_fNext_22$FULL_N), + .EMPTY_N(int_div_fNext_22$EMPTY_N)); + + // submodule int_div_fNext_23 + FIFOL1 #(.width(32'd232)) int_div_fNext_23(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_23$D_IN), + .ENQ(int_div_fNext_23$ENQ), + .DEQ(int_div_fNext_23$DEQ), + .CLR(int_div_fNext_23$CLR), + .D_OUT(int_div_fNext_23$D_OUT), + .FULL_N(int_div_fNext_23$FULL_N), + .EMPTY_N(int_div_fNext_23$EMPTY_N)); + + // submodule int_div_fNext_24 + FIFOL1 #(.width(32'd232)) int_div_fNext_24(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_24$D_IN), + .ENQ(int_div_fNext_24$ENQ), + .DEQ(int_div_fNext_24$DEQ), + .CLR(int_div_fNext_24$CLR), + .D_OUT(int_div_fNext_24$D_OUT), + .FULL_N(int_div_fNext_24$FULL_N), + .EMPTY_N(int_div_fNext_24$EMPTY_N)); + + // submodule int_div_fNext_25 + FIFOL1 #(.width(32'd232)) int_div_fNext_25(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_25$D_IN), + .ENQ(int_div_fNext_25$ENQ), + .DEQ(int_div_fNext_25$DEQ), + .CLR(int_div_fNext_25$CLR), + .D_OUT(int_div_fNext_25$D_OUT), + .FULL_N(int_div_fNext_25$FULL_N), + .EMPTY_N(int_div_fNext_25$EMPTY_N)); + + // submodule int_div_fNext_26 + FIFOL1 #(.width(32'd232)) int_div_fNext_26(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_26$D_IN), + .ENQ(int_div_fNext_26$ENQ), + .DEQ(int_div_fNext_26$DEQ), + .CLR(int_div_fNext_26$CLR), + .D_OUT(int_div_fNext_26$D_OUT), + .FULL_N(int_div_fNext_26$FULL_N), + .EMPTY_N(int_div_fNext_26$EMPTY_N)); + + // submodule int_div_fNext_27 + FIFOL1 #(.width(32'd232)) int_div_fNext_27(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_27$D_IN), + .ENQ(int_div_fNext_27$ENQ), + .DEQ(int_div_fNext_27$DEQ), + .CLR(int_div_fNext_27$CLR), + .D_OUT(int_div_fNext_27$D_OUT), + .FULL_N(int_div_fNext_27$FULL_N), + .EMPTY_N(int_div_fNext_27$EMPTY_N)); + + // submodule int_div_fNext_28 + FIFOL1 #(.width(32'd232)) int_div_fNext_28(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_28$D_IN), + .ENQ(int_div_fNext_28$ENQ), + .DEQ(int_div_fNext_28$DEQ), + .CLR(int_div_fNext_28$CLR), + .D_OUT(int_div_fNext_28$D_OUT), + .FULL_N(int_div_fNext_28$FULL_N), + .EMPTY_N(int_div_fNext_28$EMPTY_N)); + + // submodule int_div_fNext_29 + FIFOL1 #(.width(32'd232)) int_div_fNext_29(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_29$D_IN), + .ENQ(int_div_fNext_29$ENQ), + .DEQ(int_div_fNext_29$DEQ), + .CLR(int_div_fNext_29$CLR), + .D_OUT(int_div_fNext_29$D_OUT), + .FULL_N(int_div_fNext_29$FULL_N), + .EMPTY_N(int_div_fNext_29$EMPTY_N)); + + // submodule int_div_fNext_3 + FIFOL1 #(.width(32'd232)) int_div_fNext_3(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_3$D_IN), + .ENQ(int_div_fNext_3$ENQ), + .DEQ(int_div_fNext_3$DEQ), + .CLR(int_div_fNext_3$CLR), + .D_OUT(int_div_fNext_3$D_OUT), + .FULL_N(int_div_fNext_3$FULL_N), + .EMPTY_N(int_div_fNext_3$EMPTY_N)); + + // submodule int_div_fNext_30 + FIFOL1 #(.width(32'd232)) int_div_fNext_30(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_30$D_IN), + .ENQ(int_div_fNext_30$ENQ), + .DEQ(int_div_fNext_30$DEQ), + .CLR(int_div_fNext_30$CLR), + .D_OUT(int_div_fNext_30$D_OUT), + .FULL_N(int_div_fNext_30$FULL_N), + .EMPTY_N(int_div_fNext_30$EMPTY_N)); + + // submodule int_div_fNext_31 + FIFOL1 #(.width(32'd232)) int_div_fNext_31(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_31$D_IN), + .ENQ(int_div_fNext_31$ENQ), + .DEQ(int_div_fNext_31$DEQ), + .CLR(int_div_fNext_31$CLR), + .D_OUT(int_div_fNext_31$D_OUT), + .FULL_N(int_div_fNext_31$FULL_N), + .EMPTY_N(int_div_fNext_31$EMPTY_N)); + + // submodule int_div_fNext_32 + FIFOL1 #(.width(32'd232)) int_div_fNext_32(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_32$D_IN), + .ENQ(int_div_fNext_32$ENQ), + .DEQ(int_div_fNext_32$DEQ), + .CLR(int_div_fNext_32$CLR), + .D_OUT(int_div_fNext_32$D_OUT), + .FULL_N(int_div_fNext_32$FULL_N), + .EMPTY_N(int_div_fNext_32$EMPTY_N)); + + // submodule int_div_fNext_33 + FIFOL1 #(.width(32'd232)) int_div_fNext_33(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_33$D_IN), + .ENQ(int_div_fNext_33$ENQ), + .DEQ(int_div_fNext_33$DEQ), + .CLR(int_div_fNext_33$CLR), + .D_OUT(int_div_fNext_33$D_OUT), + .FULL_N(int_div_fNext_33$FULL_N), + .EMPTY_N(int_div_fNext_33$EMPTY_N)); + + // submodule int_div_fNext_34 + FIFOL1 #(.width(32'd232)) int_div_fNext_34(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_34$D_IN), + .ENQ(int_div_fNext_34$ENQ), + .DEQ(int_div_fNext_34$DEQ), + .CLR(int_div_fNext_34$CLR), + .D_OUT(int_div_fNext_34$D_OUT), + .FULL_N(int_div_fNext_34$FULL_N), + .EMPTY_N(int_div_fNext_34$EMPTY_N)); + + // submodule int_div_fNext_35 + FIFOL1 #(.width(32'd232)) int_div_fNext_35(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_35$D_IN), + .ENQ(int_div_fNext_35$ENQ), + .DEQ(int_div_fNext_35$DEQ), + .CLR(int_div_fNext_35$CLR), + .D_OUT(int_div_fNext_35$D_OUT), + .FULL_N(int_div_fNext_35$FULL_N), + .EMPTY_N(int_div_fNext_35$EMPTY_N)); + + // submodule int_div_fNext_36 + FIFOL1 #(.width(32'd232)) int_div_fNext_36(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_36$D_IN), + .ENQ(int_div_fNext_36$ENQ), + .DEQ(int_div_fNext_36$DEQ), + .CLR(int_div_fNext_36$CLR), + .D_OUT(int_div_fNext_36$D_OUT), + .FULL_N(int_div_fNext_36$FULL_N), + .EMPTY_N(int_div_fNext_36$EMPTY_N)); + + // submodule int_div_fNext_37 + FIFOL1 #(.width(32'd232)) int_div_fNext_37(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_37$D_IN), + .ENQ(int_div_fNext_37$ENQ), + .DEQ(int_div_fNext_37$DEQ), + .CLR(int_div_fNext_37$CLR), + .D_OUT(int_div_fNext_37$D_OUT), + .FULL_N(int_div_fNext_37$FULL_N), + .EMPTY_N(int_div_fNext_37$EMPTY_N)); + + // submodule int_div_fNext_38 + FIFOL1 #(.width(32'd232)) int_div_fNext_38(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_38$D_IN), + .ENQ(int_div_fNext_38$ENQ), + .DEQ(int_div_fNext_38$DEQ), + .CLR(int_div_fNext_38$CLR), + .D_OUT(int_div_fNext_38$D_OUT), + .FULL_N(int_div_fNext_38$FULL_N), + .EMPTY_N(int_div_fNext_38$EMPTY_N)); + + // submodule int_div_fNext_39 + FIFOL1 #(.width(32'd232)) int_div_fNext_39(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_39$D_IN), + .ENQ(int_div_fNext_39$ENQ), + .DEQ(int_div_fNext_39$DEQ), + .CLR(int_div_fNext_39$CLR), + .D_OUT(int_div_fNext_39$D_OUT), + .FULL_N(int_div_fNext_39$FULL_N), + .EMPTY_N(int_div_fNext_39$EMPTY_N)); + + // submodule int_div_fNext_4 + FIFOL1 #(.width(32'd232)) int_div_fNext_4(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_4$D_IN), + .ENQ(int_div_fNext_4$ENQ), + .DEQ(int_div_fNext_4$DEQ), + .CLR(int_div_fNext_4$CLR), + .D_OUT(int_div_fNext_4$D_OUT), + .FULL_N(int_div_fNext_4$FULL_N), + .EMPTY_N(int_div_fNext_4$EMPTY_N)); + + // submodule int_div_fNext_40 + FIFOL1 #(.width(32'd232)) int_div_fNext_40(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_40$D_IN), + .ENQ(int_div_fNext_40$ENQ), + .DEQ(int_div_fNext_40$DEQ), + .CLR(int_div_fNext_40$CLR), + .D_OUT(int_div_fNext_40$D_OUT), + .FULL_N(int_div_fNext_40$FULL_N), + .EMPTY_N(int_div_fNext_40$EMPTY_N)); + + // submodule int_div_fNext_41 + FIFOL1 #(.width(32'd232)) int_div_fNext_41(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_41$D_IN), + .ENQ(int_div_fNext_41$ENQ), + .DEQ(int_div_fNext_41$DEQ), + .CLR(int_div_fNext_41$CLR), + .D_OUT(int_div_fNext_41$D_OUT), + .FULL_N(int_div_fNext_41$FULL_N), + .EMPTY_N(int_div_fNext_41$EMPTY_N)); + + // submodule int_div_fNext_42 + FIFOL1 #(.width(32'd232)) int_div_fNext_42(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_42$D_IN), + .ENQ(int_div_fNext_42$ENQ), + .DEQ(int_div_fNext_42$DEQ), + .CLR(int_div_fNext_42$CLR), + .D_OUT(int_div_fNext_42$D_OUT), + .FULL_N(int_div_fNext_42$FULL_N), + .EMPTY_N(int_div_fNext_42$EMPTY_N)); + + // submodule int_div_fNext_43 + FIFOL1 #(.width(32'd232)) int_div_fNext_43(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_43$D_IN), + .ENQ(int_div_fNext_43$ENQ), + .DEQ(int_div_fNext_43$DEQ), + .CLR(int_div_fNext_43$CLR), + .D_OUT(int_div_fNext_43$D_OUT), + .FULL_N(int_div_fNext_43$FULL_N), + .EMPTY_N(int_div_fNext_43$EMPTY_N)); + + // submodule int_div_fNext_44 + FIFOL1 #(.width(32'd232)) int_div_fNext_44(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_44$D_IN), + .ENQ(int_div_fNext_44$ENQ), + .DEQ(int_div_fNext_44$DEQ), + .CLR(int_div_fNext_44$CLR), + .D_OUT(int_div_fNext_44$D_OUT), + .FULL_N(int_div_fNext_44$FULL_N), + .EMPTY_N(int_div_fNext_44$EMPTY_N)); + + // submodule int_div_fNext_45 + FIFOL1 #(.width(32'd232)) int_div_fNext_45(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_45$D_IN), + .ENQ(int_div_fNext_45$ENQ), + .DEQ(int_div_fNext_45$DEQ), + .CLR(int_div_fNext_45$CLR), + .D_OUT(int_div_fNext_45$D_OUT), + .FULL_N(int_div_fNext_45$FULL_N), + .EMPTY_N(int_div_fNext_45$EMPTY_N)); + + // submodule int_div_fNext_46 + FIFOL1 #(.width(32'd232)) int_div_fNext_46(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_46$D_IN), + .ENQ(int_div_fNext_46$ENQ), + .DEQ(int_div_fNext_46$DEQ), + .CLR(int_div_fNext_46$CLR), + .D_OUT(int_div_fNext_46$D_OUT), + .FULL_N(int_div_fNext_46$FULL_N), + .EMPTY_N(int_div_fNext_46$EMPTY_N)); + + // submodule int_div_fNext_47 + FIFOL1 #(.width(32'd232)) int_div_fNext_47(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_47$D_IN), + .ENQ(int_div_fNext_47$ENQ), + .DEQ(int_div_fNext_47$DEQ), + .CLR(int_div_fNext_47$CLR), + .D_OUT(int_div_fNext_47$D_OUT), + .FULL_N(int_div_fNext_47$FULL_N), + .EMPTY_N(int_div_fNext_47$EMPTY_N)); + + // submodule int_div_fNext_48 + FIFOL1 #(.width(32'd232)) int_div_fNext_48(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_48$D_IN), + .ENQ(int_div_fNext_48$ENQ), + .DEQ(int_div_fNext_48$DEQ), + .CLR(int_div_fNext_48$CLR), + .D_OUT(int_div_fNext_48$D_OUT), + .FULL_N(int_div_fNext_48$FULL_N), + .EMPTY_N(int_div_fNext_48$EMPTY_N)); + + // submodule int_div_fNext_49 + FIFOL1 #(.width(32'd232)) int_div_fNext_49(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_49$D_IN), + .ENQ(int_div_fNext_49$ENQ), + .DEQ(int_div_fNext_49$DEQ), + .CLR(int_div_fNext_49$CLR), + .D_OUT(int_div_fNext_49$D_OUT), + .FULL_N(int_div_fNext_49$FULL_N), + .EMPTY_N(int_div_fNext_49$EMPTY_N)); + + // submodule int_div_fNext_5 + FIFOL1 #(.width(32'd232)) int_div_fNext_5(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_5$D_IN), + .ENQ(int_div_fNext_5$ENQ), + .DEQ(int_div_fNext_5$DEQ), + .CLR(int_div_fNext_5$CLR), + .D_OUT(int_div_fNext_5$D_OUT), + .FULL_N(int_div_fNext_5$FULL_N), + .EMPTY_N(int_div_fNext_5$EMPTY_N)); + + // submodule int_div_fNext_50 + FIFOL1 #(.width(32'd232)) int_div_fNext_50(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_50$D_IN), + .ENQ(int_div_fNext_50$ENQ), + .DEQ(int_div_fNext_50$DEQ), + .CLR(int_div_fNext_50$CLR), + .D_OUT(int_div_fNext_50$D_OUT), + .FULL_N(int_div_fNext_50$FULL_N), + .EMPTY_N(int_div_fNext_50$EMPTY_N)); + + // submodule int_div_fNext_51 + FIFOL1 #(.width(32'd232)) int_div_fNext_51(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_51$D_IN), + .ENQ(int_div_fNext_51$ENQ), + .DEQ(int_div_fNext_51$DEQ), + .CLR(int_div_fNext_51$CLR), + .D_OUT(int_div_fNext_51$D_OUT), + .FULL_N(int_div_fNext_51$FULL_N), + .EMPTY_N(int_div_fNext_51$EMPTY_N)); + + // submodule int_div_fNext_52 + FIFOL1 #(.width(32'd232)) int_div_fNext_52(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_52$D_IN), + .ENQ(int_div_fNext_52$ENQ), + .DEQ(int_div_fNext_52$DEQ), + .CLR(int_div_fNext_52$CLR), + .D_OUT(int_div_fNext_52$D_OUT), + .FULL_N(int_div_fNext_52$FULL_N), + .EMPTY_N(int_div_fNext_52$EMPTY_N)); + + // submodule int_div_fNext_53 + FIFOL1 #(.width(32'd232)) int_div_fNext_53(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_53$D_IN), + .ENQ(int_div_fNext_53$ENQ), + .DEQ(int_div_fNext_53$DEQ), + .CLR(int_div_fNext_53$CLR), + .D_OUT(int_div_fNext_53$D_OUT), + .FULL_N(int_div_fNext_53$FULL_N), + .EMPTY_N(int_div_fNext_53$EMPTY_N)); + + // submodule int_div_fNext_54 + FIFOL1 #(.width(32'd232)) int_div_fNext_54(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_54$D_IN), + .ENQ(int_div_fNext_54$ENQ), + .DEQ(int_div_fNext_54$DEQ), + .CLR(int_div_fNext_54$CLR), + .D_OUT(int_div_fNext_54$D_OUT), + .FULL_N(int_div_fNext_54$FULL_N), + .EMPTY_N(int_div_fNext_54$EMPTY_N)); + + // submodule int_div_fNext_55 + FIFOL1 #(.width(32'd232)) int_div_fNext_55(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_55$D_IN), + .ENQ(int_div_fNext_55$ENQ), + .DEQ(int_div_fNext_55$DEQ), + .CLR(int_div_fNext_55$CLR), + .D_OUT(int_div_fNext_55$D_OUT), + .FULL_N(int_div_fNext_55$FULL_N), + .EMPTY_N(int_div_fNext_55$EMPTY_N)); + + // submodule int_div_fNext_56 + FIFOL1 #(.width(32'd232)) int_div_fNext_56(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_56$D_IN), + .ENQ(int_div_fNext_56$ENQ), + .DEQ(int_div_fNext_56$DEQ), + .CLR(int_div_fNext_56$CLR), + .D_OUT(int_div_fNext_56$D_OUT), + .FULL_N(int_div_fNext_56$FULL_N), + .EMPTY_N(int_div_fNext_56$EMPTY_N)); + + // submodule int_div_fNext_57 + FIFOL1 #(.width(32'd232)) int_div_fNext_57(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_57$D_IN), + .ENQ(int_div_fNext_57$ENQ), + .DEQ(int_div_fNext_57$DEQ), + .CLR(int_div_fNext_57$CLR), + .D_OUT(int_div_fNext_57$D_OUT), + .FULL_N(int_div_fNext_57$FULL_N), + .EMPTY_N(int_div_fNext_57$EMPTY_N)); + + // submodule int_div_fNext_6 + FIFOL1 #(.width(32'd232)) int_div_fNext_6(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_6$D_IN), + .ENQ(int_div_fNext_6$ENQ), + .DEQ(int_div_fNext_6$DEQ), + .CLR(int_div_fNext_6$CLR), + .D_OUT(int_div_fNext_6$D_OUT), + .FULL_N(int_div_fNext_6$FULL_N), + .EMPTY_N(int_div_fNext_6$EMPTY_N)); + + // submodule int_div_fNext_7 + FIFOL1 #(.width(32'd232)) int_div_fNext_7(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_7$D_IN), + .ENQ(int_div_fNext_7$ENQ), + .DEQ(int_div_fNext_7$DEQ), + .CLR(int_div_fNext_7$CLR), + .D_OUT(int_div_fNext_7$D_OUT), + .FULL_N(int_div_fNext_7$FULL_N), + .EMPTY_N(int_div_fNext_7$EMPTY_N)); + + // submodule int_div_fNext_8 + FIFOL1 #(.width(32'd232)) int_div_fNext_8(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_8$D_IN), + .ENQ(int_div_fNext_8$ENQ), + .DEQ(int_div_fNext_8$DEQ), + .CLR(int_div_fNext_8$CLR), + .D_OUT(int_div_fNext_8$D_OUT), + .FULL_N(int_div_fNext_8$FULL_N), + .EMPTY_N(int_div_fNext_8$EMPTY_N)); + + // submodule int_div_fNext_9 + FIFOL1 #(.width(32'd232)) int_div_fNext_9(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fNext_9$D_IN), + .ENQ(int_div_fNext_9$ENQ), + .DEQ(int_div_fNext_9$DEQ), + .CLR(int_div_fNext_9$CLR), + .D_OUT(int_div_fNext_9$D_OUT), + .FULL_N(int_div_fNext_9$FULL_N), + .EMPTY_N(int_div_fNext_9$EMPTY_N)); + + // submodule int_div_fRequest + FIFOL1 #(.width(32'd171)) int_div_fRequest(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fRequest$D_IN), + .ENQ(int_div_fRequest$ENQ), + .DEQ(int_div_fRequest$DEQ), + .CLR(int_div_fRequest$CLR), + .D_OUT(int_div_fRequest$D_OUT), + .FULL_N(int_div_fRequest$FULL_N), + .EMPTY_N(int_div_fRequest$EMPTY_N)); + + // submodule int_div_fResponse + FIFOL1 #(.width(32'd114)) int_div_fResponse(.RST(RST_N), + .CLK(CLK), + .D_IN(int_div_fResponse$D_IN), + .ENQ(int_div_fResponse$ENQ), + .DEQ(int_div_fResponse$DEQ), + .CLR(int_div_fResponse$CLR), + .D_OUT(int_div_fResponse$D_OUT), + .FULL_N(int_div_fResponse$FULL_N), + .EMPTY_N(int_div_fResponse$EMPTY_N)); + + // rule RL_fpu_s5_stage + assign CAN_FIRE_RL_fpu_s5_stage = + fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; + assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; + + // rule RL_fpu_s4_stage + assign CAN_FIRE_RL_fpu_s4_stage = + fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; + assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; + + // rule RL_fpu_s3_stage + assign CAN_FIRE_RL_fpu_s3_stage = + fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && + (fpu_fState_S2$D_OUT[147] || int_div_fResponse$EMPTY_N) ; + assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; + + // rule RL_int_div_finish + assign CAN_FIRE_RL_int_div_finish = + int_div_fNext_57$EMPTY_N && int_div_fResponse$FULL_N ; + assign WILL_FIRE_RL_int_div_finish = CAN_FIRE_RL_int_div_finish ; + + // rule RL_int_div_work_57 + assign CAN_FIRE_RL_int_div_work_57 = + int_div_fNext_56$EMPTY_N && int_div_fNext_57$FULL_N ; + assign WILL_FIRE_RL_int_div_work_57 = CAN_FIRE_RL_int_div_work_57 ; + + // rule RL_int_div_work_56 + assign CAN_FIRE_RL_int_div_work_56 = + int_div_fNext_55$EMPTY_N && int_div_fNext_56$FULL_N ; + assign WILL_FIRE_RL_int_div_work_56 = CAN_FIRE_RL_int_div_work_56 ; + + // rule RL_int_div_work_55 + assign CAN_FIRE_RL_int_div_work_55 = + int_div_fNext_54$EMPTY_N && int_div_fNext_55$FULL_N ; + assign WILL_FIRE_RL_int_div_work_55 = CAN_FIRE_RL_int_div_work_55 ; + + // rule RL_int_div_work_54 + assign CAN_FIRE_RL_int_div_work_54 = + int_div_fNext_53$EMPTY_N && int_div_fNext_54$FULL_N ; + assign WILL_FIRE_RL_int_div_work_54 = CAN_FIRE_RL_int_div_work_54 ; + + // rule RL_int_div_work_53 + assign CAN_FIRE_RL_int_div_work_53 = + int_div_fNext_52$EMPTY_N && int_div_fNext_53$FULL_N ; + assign WILL_FIRE_RL_int_div_work_53 = CAN_FIRE_RL_int_div_work_53 ; + + // rule RL_int_div_work_52 + assign CAN_FIRE_RL_int_div_work_52 = + int_div_fNext_51$EMPTY_N && int_div_fNext_52$FULL_N ; + assign WILL_FIRE_RL_int_div_work_52 = CAN_FIRE_RL_int_div_work_52 ; + + // rule RL_int_div_work_51 + assign CAN_FIRE_RL_int_div_work_51 = + int_div_fNext_50$EMPTY_N && int_div_fNext_51$FULL_N ; + assign WILL_FIRE_RL_int_div_work_51 = CAN_FIRE_RL_int_div_work_51 ; + + // rule RL_int_div_work_50 + assign CAN_FIRE_RL_int_div_work_50 = + int_div_fNext_49$EMPTY_N && int_div_fNext_50$FULL_N ; + assign WILL_FIRE_RL_int_div_work_50 = CAN_FIRE_RL_int_div_work_50 ; + + // rule RL_int_div_work_49 + assign CAN_FIRE_RL_int_div_work_49 = + int_div_fNext_48$EMPTY_N && int_div_fNext_49$FULL_N ; + assign WILL_FIRE_RL_int_div_work_49 = CAN_FIRE_RL_int_div_work_49 ; + + // rule RL_int_div_work_48 + assign CAN_FIRE_RL_int_div_work_48 = + int_div_fNext_47$EMPTY_N && int_div_fNext_48$FULL_N ; + assign WILL_FIRE_RL_int_div_work_48 = CAN_FIRE_RL_int_div_work_48 ; + + // rule RL_int_div_work_47 + assign CAN_FIRE_RL_int_div_work_47 = + int_div_fNext_46$EMPTY_N && int_div_fNext_47$FULL_N ; + assign WILL_FIRE_RL_int_div_work_47 = CAN_FIRE_RL_int_div_work_47 ; + + // rule RL_int_div_work_46 + assign CAN_FIRE_RL_int_div_work_46 = + int_div_fNext_45$EMPTY_N && int_div_fNext_46$FULL_N ; + assign WILL_FIRE_RL_int_div_work_46 = CAN_FIRE_RL_int_div_work_46 ; + + // rule RL_int_div_work_45 + assign CAN_FIRE_RL_int_div_work_45 = + int_div_fNext_44$EMPTY_N && int_div_fNext_45$FULL_N ; + assign WILL_FIRE_RL_int_div_work_45 = CAN_FIRE_RL_int_div_work_45 ; + + // rule RL_int_div_work_44 + assign CAN_FIRE_RL_int_div_work_44 = + int_div_fNext_43$EMPTY_N && int_div_fNext_44$FULL_N ; + assign WILL_FIRE_RL_int_div_work_44 = CAN_FIRE_RL_int_div_work_44 ; + + // rule RL_int_div_work_43 + assign CAN_FIRE_RL_int_div_work_43 = + int_div_fNext_42$EMPTY_N && int_div_fNext_43$FULL_N ; + assign WILL_FIRE_RL_int_div_work_43 = CAN_FIRE_RL_int_div_work_43 ; + + // rule RL_int_div_work_42 + assign CAN_FIRE_RL_int_div_work_42 = + int_div_fNext_41$EMPTY_N && int_div_fNext_42$FULL_N ; + assign WILL_FIRE_RL_int_div_work_42 = CAN_FIRE_RL_int_div_work_42 ; + + // rule RL_int_div_work_41 + assign CAN_FIRE_RL_int_div_work_41 = + int_div_fNext_40$EMPTY_N && int_div_fNext_41$FULL_N ; + assign WILL_FIRE_RL_int_div_work_41 = CAN_FIRE_RL_int_div_work_41 ; + + // rule RL_int_div_work_40 + assign CAN_FIRE_RL_int_div_work_40 = + int_div_fNext_39$EMPTY_N && int_div_fNext_40$FULL_N ; + assign WILL_FIRE_RL_int_div_work_40 = CAN_FIRE_RL_int_div_work_40 ; + + // rule RL_int_div_work_39 + assign CAN_FIRE_RL_int_div_work_39 = + int_div_fNext_38$EMPTY_N && int_div_fNext_39$FULL_N ; + assign WILL_FIRE_RL_int_div_work_39 = CAN_FIRE_RL_int_div_work_39 ; + + // rule RL_int_div_work_38 + assign CAN_FIRE_RL_int_div_work_38 = + int_div_fNext_37$EMPTY_N && int_div_fNext_38$FULL_N ; + assign WILL_FIRE_RL_int_div_work_38 = CAN_FIRE_RL_int_div_work_38 ; + + // rule RL_int_div_work_37 + assign CAN_FIRE_RL_int_div_work_37 = + int_div_fNext_36$EMPTY_N && int_div_fNext_37$FULL_N ; + assign WILL_FIRE_RL_int_div_work_37 = CAN_FIRE_RL_int_div_work_37 ; + + // rule RL_int_div_work_36 + assign CAN_FIRE_RL_int_div_work_36 = + int_div_fNext_35$EMPTY_N && int_div_fNext_36$FULL_N ; + assign WILL_FIRE_RL_int_div_work_36 = CAN_FIRE_RL_int_div_work_36 ; + + // rule RL_int_div_work_35 + assign CAN_FIRE_RL_int_div_work_35 = + int_div_fNext_34$EMPTY_N && int_div_fNext_35$FULL_N ; + assign WILL_FIRE_RL_int_div_work_35 = CAN_FIRE_RL_int_div_work_35 ; + + // rule RL_int_div_work_34 + assign CAN_FIRE_RL_int_div_work_34 = + int_div_fNext_33$EMPTY_N && int_div_fNext_34$FULL_N ; + assign WILL_FIRE_RL_int_div_work_34 = CAN_FIRE_RL_int_div_work_34 ; + + // rule RL_int_div_work_33 + assign CAN_FIRE_RL_int_div_work_33 = + int_div_fNext_32$EMPTY_N && int_div_fNext_33$FULL_N ; + assign WILL_FIRE_RL_int_div_work_33 = CAN_FIRE_RL_int_div_work_33 ; + + // rule RL_int_div_work_32 + assign CAN_FIRE_RL_int_div_work_32 = + int_div_fNext_31$EMPTY_N && int_div_fNext_32$FULL_N ; + assign WILL_FIRE_RL_int_div_work_32 = CAN_FIRE_RL_int_div_work_32 ; + + // rule RL_int_div_work_31 + assign CAN_FIRE_RL_int_div_work_31 = + int_div_fNext_30$EMPTY_N && int_div_fNext_31$FULL_N ; + assign WILL_FIRE_RL_int_div_work_31 = CAN_FIRE_RL_int_div_work_31 ; + + // rule RL_int_div_work_30 + assign CAN_FIRE_RL_int_div_work_30 = + int_div_fNext_29$EMPTY_N && int_div_fNext_30$FULL_N ; + assign WILL_FIRE_RL_int_div_work_30 = CAN_FIRE_RL_int_div_work_30 ; + + // rule RL_int_div_work_29 + assign CAN_FIRE_RL_int_div_work_29 = + int_div_fNext_28$EMPTY_N && int_div_fNext_29$FULL_N ; + assign WILL_FIRE_RL_int_div_work_29 = CAN_FIRE_RL_int_div_work_29 ; + + // rule RL_int_div_work_28 + assign CAN_FIRE_RL_int_div_work_28 = + int_div_fNext_27$EMPTY_N && int_div_fNext_28$FULL_N ; + assign WILL_FIRE_RL_int_div_work_28 = CAN_FIRE_RL_int_div_work_28 ; + + // rule RL_int_div_work_27 + assign CAN_FIRE_RL_int_div_work_27 = + int_div_fNext_26$EMPTY_N && int_div_fNext_27$FULL_N ; + assign WILL_FIRE_RL_int_div_work_27 = CAN_FIRE_RL_int_div_work_27 ; + + // rule RL_int_div_work_26 + assign CAN_FIRE_RL_int_div_work_26 = + int_div_fNext_25$EMPTY_N && int_div_fNext_26$FULL_N ; + assign WILL_FIRE_RL_int_div_work_26 = CAN_FIRE_RL_int_div_work_26 ; + + // rule RL_int_div_work_25 + assign CAN_FIRE_RL_int_div_work_25 = + int_div_fNext_24$EMPTY_N && int_div_fNext_25$FULL_N ; + assign WILL_FIRE_RL_int_div_work_25 = CAN_FIRE_RL_int_div_work_25 ; + + // rule RL_int_div_work_24 + assign CAN_FIRE_RL_int_div_work_24 = + int_div_fNext_23$EMPTY_N && int_div_fNext_24$FULL_N ; + assign WILL_FIRE_RL_int_div_work_24 = CAN_FIRE_RL_int_div_work_24 ; + + // rule RL_int_div_work_23 + assign CAN_FIRE_RL_int_div_work_23 = + int_div_fNext_22$EMPTY_N && int_div_fNext_23$FULL_N ; + assign WILL_FIRE_RL_int_div_work_23 = CAN_FIRE_RL_int_div_work_23 ; + + // rule RL_int_div_work_22 + assign CAN_FIRE_RL_int_div_work_22 = + int_div_fNext_21$EMPTY_N && int_div_fNext_22$FULL_N ; + assign WILL_FIRE_RL_int_div_work_22 = CAN_FIRE_RL_int_div_work_22 ; + + // rule RL_int_div_work_21 + assign CAN_FIRE_RL_int_div_work_21 = + int_div_fNext_20$EMPTY_N && int_div_fNext_21$FULL_N ; + assign WILL_FIRE_RL_int_div_work_21 = CAN_FIRE_RL_int_div_work_21 ; + + // rule RL_int_div_work_20 + assign CAN_FIRE_RL_int_div_work_20 = + int_div_fNext_19$EMPTY_N && int_div_fNext_20$FULL_N ; + assign WILL_FIRE_RL_int_div_work_20 = CAN_FIRE_RL_int_div_work_20 ; + + // rule RL_int_div_work_19 + assign CAN_FIRE_RL_int_div_work_19 = + int_div_fNext_18$EMPTY_N && int_div_fNext_19$FULL_N ; + assign WILL_FIRE_RL_int_div_work_19 = CAN_FIRE_RL_int_div_work_19 ; + + // rule RL_int_div_work_18 + assign CAN_FIRE_RL_int_div_work_18 = + int_div_fNext_17$EMPTY_N && int_div_fNext_18$FULL_N ; + assign WILL_FIRE_RL_int_div_work_18 = CAN_FIRE_RL_int_div_work_18 ; + + // rule RL_int_div_work_17 + assign CAN_FIRE_RL_int_div_work_17 = + int_div_fNext_16$EMPTY_N && int_div_fNext_17$FULL_N ; + assign WILL_FIRE_RL_int_div_work_17 = CAN_FIRE_RL_int_div_work_17 ; + + // rule RL_int_div_work_16 + assign CAN_FIRE_RL_int_div_work_16 = + int_div_fNext_15$EMPTY_N && int_div_fNext_16$FULL_N ; + assign WILL_FIRE_RL_int_div_work_16 = CAN_FIRE_RL_int_div_work_16 ; + + // rule RL_int_div_work_15 + assign CAN_FIRE_RL_int_div_work_15 = + int_div_fNext_14$EMPTY_N && int_div_fNext_15$FULL_N ; + assign WILL_FIRE_RL_int_div_work_15 = CAN_FIRE_RL_int_div_work_15 ; + + // rule RL_int_div_work_14 + assign CAN_FIRE_RL_int_div_work_14 = + int_div_fNext_13$EMPTY_N && int_div_fNext_14$FULL_N ; + assign WILL_FIRE_RL_int_div_work_14 = CAN_FIRE_RL_int_div_work_14 ; + + // rule RL_int_div_work_13 + assign CAN_FIRE_RL_int_div_work_13 = + int_div_fNext_12$EMPTY_N && int_div_fNext_13$FULL_N ; + assign WILL_FIRE_RL_int_div_work_13 = CAN_FIRE_RL_int_div_work_13 ; + + // rule RL_int_div_work_12 + assign CAN_FIRE_RL_int_div_work_12 = + int_div_fNext_11$EMPTY_N && int_div_fNext_12$FULL_N ; + assign WILL_FIRE_RL_int_div_work_12 = CAN_FIRE_RL_int_div_work_12 ; + + // rule RL_int_div_work_11 + assign CAN_FIRE_RL_int_div_work_11 = + int_div_fNext_10$EMPTY_N && int_div_fNext_11$FULL_N ; + assign WILL_FIRE_RL_int_div_work_11 = CAN_FIRE_RL_int_div_work_11 ; + + // rule RL_int_div_work_10 + assign CAN_FIRE_RL_int_div_work_10 = + int_div_fNext_9$EMPTY_N && int_div_fNext_10$FULL_N ; + assign WILL_FIRE_RL_int_div_work_10 = CAN_FIRE_RL_int_div_work_10 ; + + // rule RL_int_div_work_9 + assign CAN_FIRE_RL_int_div_work_9 = + int_div_fNext_8$EMPTY_N && int_div_fNext_9$FULL_N ; + assign WILL_FIRE_RL_int_div_work_9 = CAN_FIRE_RL_int_div_work_9 ; + + // rule RL_int_div_work_8 + assign CAN_FIRE_RL_int_div_work_8 = + int_div_fNext_7$EMPTY_N && int_div_fNext_8$FULL_N ; + assign WILL_FIRE_RL_int_div_work_8 = CAN_FIRE_RL_int_div_work_8 ; + + // rule RL_int_div_work_7 + assign CAN_FIRE_RL_int_div_work_7 = + int_div_fNext_6$EMPTY_N && int_div_fNext_7$FULL_N ; + assign WILL_FIRE_RL_int_div_work_7 = CAN_FIRE_RL_int_div_work_7 ; + + // rule RL_int_div_work_6 + assign CAN_FIRE_RL_int_div_work_6 = + int_div_fNext_5$EMPTY_N && int_div_fNext_6$FULL_N ; + assign WILL_FIRE_RL_int_div_work_6 = CAN_FIRE_RL_int_div_work_6 ; + + // rule RL_int_div_work_5 + assign CAN_FIRE_RL_int_div_work_5 = + int_div_fNext_4$EMPTY_N && int_div_fNext_5$FULL_N ; + assign WILL_FIRE_RL_int_div_work_5 = CAN_FIRE_RL_int_div_work_5 ; + + // rule RL_int_div_work_4 + assign CAN_FIRE_RL_int_div_work_4 = + int_div_fNext_3$EMPTY_N && int_div_fNext_4$FULL_N ; + assign WILL_FIRE_RL_int_div_work_4 = CAN_FIRE_RL_int_div_work_4 ; + + // rule RL_int_div_work_3 + assign CAN_FIRE_RL_int_div_work_3 = + int_div_fNext_2$EMPTY_N && int_div_fNext_3$FULL_N ; + assign WILL_FIRE_RL_int_div_work_3 = CAN_FIRE_RL_int_div_work_3 ; + + // rule RL_int_div_work_2 + assign CAN_FIRE_RL_int_div_work_2 = + int_div_fNext_1$EMPTY_N && int_div_fNext_2$FULL_N ; + assign WILL_FIRE_RL_int_div_work_2 = CAN_FIRE_RL_int_div_work_2 ; + + // rule RL_int_div_work_1 + assign CAN_FIRE_RL_int_div_work_1 = + int_div_fNext_0$EMPTY_N && int_div_fNext_1$FULL_N ; + assign WILL_FIRE_RL_int_div_work_1 = CAN_FIRE_RL_int_div_work_1 ; + + // rule RL_int_div_work + assign CAN_FIRE_RL_int_div_work = + int_div_fFirst$EMPTY_N && int_div_fNext_0$FULL_N ; + assign WILL_FIRE_RL_int_div_work = CAN_FIRE_RL_int_div_work ; + + // rule RL_int_div_start + assign CAN_FIRE_RL_int_div_start = + int_div_fRequest$EMPTY_N && int_div_fFirst$FULL_N ; + assign WILL_FIRE_RL_int_div_start = CAN_FIRE_RL_int_div_start ; + + // rule RL_fpu_s2_stage + assign CAN_FIRE_RL_fpu_s2_stage = + fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && + (fpu_fState_S1$D_OUT[318] || int_div_fRequest$FULL_N) ; + assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; + + // rule RL_fpu_s1_stage + assign CAN_FIRE_RL_fpu_s1_stage = + fpu_fOperands_S0$EMPTY_N && fpu_fState_S1$FULL_N ; + assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; + + // submodule fpu_fOperands_S0 + assign fpu_fOperands_S0$D_IN = request_put ; + assign fpu_fOperands_S0$ENQ = EN_request_put ; + assign fpu_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fOperands_S0$CLR = 1'b0 ; + + // submodule fpu_fResult_S5 + assign fpu_fResult_S5$D_IN = + fpu_fState_S4$D_OUT[138] ? + fpu_fState_S4$D_OUT[137:69] : + { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[65:2] : + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16, + fpu_fState_S4$D_OUT[73:69] | + { 2'd0, + _theResult___fst_exp__h60991 == 11'd2047 && + _theResult___fst_sfd__h60992 == 52'd0, + 1'd0, + fpu_fState_S4$D_OUT[64:54] != 11'd2047 && + fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; + assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fResult_S5$DEQ = EN_response_get ; + assign fpu_fResult_S5$CLR = 1'b0 ; + + // submodule fpu_fState_S1 + assign fpu_fState_S1$D_IN = + { fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, + (fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118]) ? + { fpu_fOperands_S0$D_OUT[130:119], sfd__h36684 } : + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54] || + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0), + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[54]) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[118]) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperands_S0$D_OUT[54]) && + NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, + fpu_fOperands_S0$D_OUT[2:0], + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, + _theResult___snd_fst_exp__h49111, + _theResult___snd_fst_sfd__h49112, + x__h49176, + x__h49237, + x__h49291 } ; + assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S1$CLR = 1'b0 ; + + // submodule fpu_fState_S2 + assign fpu_fState_S2$D_IN = + { fpu_fState_S1$D_OUT[318:182], fpu_fState_S1$D_OUT[10:0] } ; + assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S2$CLR = 1'b0 ; + + // submodule fpu_fState_S3 + assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT[147:11], x__h50487 } ; + assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S3$CLR = 1'b0 ; + + // submodule fpu_fState_S4 + assign fpu_fState_S4$D_IN = + { (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[194] : + fpu_fState_S3$D_OUT[194], + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + fpu_fState_S3$D_OUT[193:130] : + { CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 }) : + fpu_fState_S3$D_OUT[193:130], + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, + fpu_fState_S3$D_OUT[124:122], + fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780, + x__h60140 } ; + assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S4$CLR = 1'b0 ; + + // submodule int_div_fFirst + assign int_div_fFirst$D_IN = + { b__h378, 60'd0, int_div_fRequest$D_OUT[170:57] } ; + assign int_div_fFirst$ENQ = CAN_FIRE_RL_int_div_start ; + assign int_div_fFirst$DEQ = CAN_FIRE_RL_int_div_work ; + assign int_div_fFirst$CLR = 1'b0 ; + + // submodule int_div_fNext_0 + assign int_div_fNext_0$D_IN = + { int_div_fFirst$D_OUT[231:174], + int_div_fFirst$D_OUT[172:116], + !int_div_fFirst$D_OUT[115], + int_div_fFirst$D_OUT[115] ? + { int_div_fFirst$D_OUT[114:0], 1'd0 } + b__h767 : + { int_div_fFirst$D_OUT[114:0], 1'd0 } - b__h767 } ; + assign int_div_fNext_0$ENQ = CAN_FIRE_RL_int_div_work ; + assign int_div_fNext_0$DEQ = CAN_FIRE_RL_int_div_work_1 ; + assign int_div_fNext_0$CLR = 1'b0 ; + + // submodule int_div_fNext_1 + assign int_div_fNext_1$D_IN = + { int_div_fNext_0$D_OUT[231:174], + int_div_fNext_0$D_OUT[172:116], + !int_div_fNext_0$D_OUT[115], + int_div_fNext_0$D_OUT[115] ? + { int_div_fNext_0$D_OUT[114:0], 1'd0 } + b__h1091 : + { int_div_fNext_0$D_OUT[114:0], 1'd0 } - b__h1091 } ; + assign int_div_fNext_1$ENQ = CAN_FIRE_RL_int_div_work_1 ; + assign int_div_fNext_1$DEQ = CAN_FIRE_RL_int_div_work_2 ; + assign int_div_fNext_1$CLR = 1'b0 ; + + // submodule int_div_fNext_10 + assign int_div_fNext_10$D_IN = + { int_div_fNext_9$D_OUT[231:174], + int_div_fNext_9$D_OUT[172:116], + !int_div_fNext_9$D_OUT[115], + int_div_fNext_9$D_OUT[115] ? + { int_div_fNext_9$D_OUT[114:0], 1'd0 } + b__h4007 : + { int_div_fNext_9$D_OUT[114:0], 1'd0 } - b__h4007 } ; + assign int_div_fNext_10$ENQ = CAN_FIRE_RL_int_div_work_10 ; + assign int_div_fNext_10$DEQ = CAN_FIRE_RL_int_div_work_11 ; + assign int_div_fNext_10$CLR = 1'b0 ; + + // submodule int_div_fNext_11 + assign int_div_fNext_11$D_IN = + { int_div_fNext_10$D_OUT[231:174], + int_div_fNext_10$D_OUT[172:116], + !int_div_fNext_10$D_OUT[115], + int_div_fNext_10$D_OUT[115] ? + { int_div_fNext_10$D_OUT[114:0], 1'd0 } + b__h4331 : + { int_div_fNext_10$D_OUT[114:0], 1'd0 } - b__h4331 } ; + assign int_div_fNext_11$ENQ = CAN_FIRE_RL_int_div_work_11 ; + assign int_div_fNext_11$DEQ = CAN_FIRE_RL_int_div_work_12 ; + assign int_div_fNext_11$CLR = 1'b0 ; + + // submodule int_div_fNext_12 + assign int_div_fNext_12$D_IN = + { int_div_fNext_11$D_OUT[231:174], + int_div_fNext_11$D_OUT[172:116], + !int_div_fNext_11$D_OUT[115], + int_div_fNext_11$D_OUT[115] ? + { int_div_fNext_11$D_OUT[114:0], 1'd0 } + b__h4655 : + { int_div_fNext_11$D_OUT[114:0], 1'd0 } - b__h4655 } ; + assign int_div_fNext_12$ENQ = CAN_FIRE_RL_int_div_work_12 ; + assign int_div_fNext_12$DEQ = CAN_FIRE_RL_int_div_work_13 ; + assign int_div_fNext_12$CLR = 1'b0 ; + + // submodule int_div_fNext_13 + assign int_div_fNext_13$D_IN = + { int_div_fNext_12$D_OUT[231:174], + int_div_fNext_12$D_OUT[172:116], + !int_div_fNext_12$D_OUT[115], + int_div_fNext_12$D_OUT[115] ? + { int_div_fNext_12$D_OUT[114:0], 1'd0 } + b__h4979 : + { int_div_fNext_12$D_OUT[114:0], 1'd0 } - b__h4979 } ; + assign int_div_fNext_13$ENQ = CAN_FIRE_RL_int_div_work_13 ; + assign int_div_fNext_13$DEQ = CAN_FIRE_RL_int_div_work_14 ; + assign int_div_fNext_13$CLR = 1'b0 ; + + // submodule int_div_fNext_14 + assign int_div_fNext_14$D_IN = + { int_div_fNext_13$D_OUT[231:174], + int_div_fNext_13$D_OUT[172:116], + !int_div_fNext_13$D_OUT[115], + int_div_fNext_13$D_OUT[115] ? + { int_div_fNext_13$D_OUT[114:0], 1'd0 } + b__h5303 : + { int_div_fNext_13$D_OUT[114:0], 1'd0 } - b__h5303 } ; + assign int_div_fNext_14$ENQ = CAN_FIRE_RL_int_div_work_14 ; + assign int_div_fNext_14$DEQ = CAN_FIRE_RL_int_div_work_15 ; + assign int_div_fNext_14$CLR = 1'b0 ; + + // submodule int_div_fNext_15 + assign int_div_fNext_15$D_IN = + { int_div_fNext_14$D_OUT[231:174], + int_div_fNext_14$D_OUT[172:116], + !int_div_fNext_14$D_OUT[115], + int_div_fNext_14$D_OUT[115] ? + { int_div_fNext_14$D_OUT[114:0], 1'd0 } + b__h5627 : + { int_div_fNext_14$D_OUT[114:0], 1'd0 } - b__h5627 } ; + assign int_div_fNext_15$ENQ = CAN_FIRE_RL_int_div_work_15 ; + assign int_div_fNext_15$DEQ = CAN_FIRE_RL_int_div_work_16 ; + assign int_div_fNext_15$CLR = 1'b0 ; + + // submodule int_div_fNext_16 + assign int_div_fNext_16$D_IN = + { int_div_fNext_15$D_OUT[231:174], + int_div_fNext_15$D_OUT[172:116], + !int_div_fNext_15$D_OUT[115], + int_div_fNext_15$D_OUT[115] ? + { int_div_fNext_15$D_OUT[114:0], 1'd0 } + b__h5951 : + { int_div_fNext_15$D_OUT[114:0], 1'd0 } - b__h5951 } ; + assign int_div_fNext_16$ENQ = CAN_FIRE_RL_int_div_work_16 ; + assign int_div_fNext_16$DEQ = CAN_FIRE_RL_int_div_work_17 ; + assign int_div_fNext_16$CLR = 1'b0 ; + + // submodule int_div_fNext_17 + assign int_div_fNext_17$D_IN = + { int_div_fNext_16$D_OUT[231:174], + int_div_fNext_16$D_OUT[172:116], + !int_div_fNext_16$D_OUT[115], + int_div_fNext_16$D_OUT[115] ? + { int_div_fNext_16$D_OUT[114:0], 1'd0 } + b__h6275 : + { int_div_fNext_16$D_OUT[114:0], 1'd0 } - b__h6275 } ; + assign int_div_fNext_17$ENQ = CAN_FIRE_RL_int_div_work_17 ; + assign int_div_fNext_17$DEQ = CAN_FIRE_RL_int_div_work_18 ; + assign int_div_fNext_17$CLR = 1'b0 ; + + // submodule int_div_fNext_18 + assign int_div_fNext_18$D_IN = + { int_div_fNext_17$D_OUT[231:174], + int_div_fNext_17$D_OUT[172:116], + !int_div_fNext_17$D_OUT[115], + int_div_fNext_17$D_OUT[115] ? + { int_div_fNext_17$D_OUT[114:0], 1'd0 } + b__h6599 : + { int_div_fNext_17$D_OUT[114:0], 1'd0 } - b__h6599 } ; + assign int_div_fNext_18$ENQ = CAN_FIRE_RL_int_div_work_18 ; + assign int_div_fNext_18$DEQ = CAN_FIRE_RL_int_div_work_19 ; + assign int_div_fNext_18$CLR = 1'b0 ; + + // submodule int_div_fNext_19 + assign int_div_fNext_19$D_IN = + { int_div_fNext_18$D_OUT[231:174], + int_div_fNext_18$D_OUT[172:116], + !int_div_fNext_18$D_OUT[115], + int_div_fNext_18$D_OUT[115] ? + { int_div_fNext_18$D_OUT[114:0], 1'd0 } + b__h6923 : + { int_div_fNext_18$D_OUT[114:0], 1'd0 } - b__h6923 } ; + assign int_div_fNext_19$ENQ = CAN_FIRE_RL_int_div_work_19 ; + assign int_div_fNext_19$DEQ = CAN_FIRE_RL_int_div_work_20 ; + assign int_div_fNext_19$CLR = 1'b0 ; + + // submodule int_div_fNext_2 + assign int_div_fNext_2$D_IN = + { int_div_fNext_1$D_OUT[231:174], + int_div_fNext_1$D_OUT[172:116], + !int_div_fNext_1$D_OUT[115], + int_div_fNext_1$D_OUT[115] ? + { int_div_fNext_1$D_OUT[114:0], 1'd0 } + b__h1415 : + { int_div_fNext_1$D_OUT[114:0], 1'd0 } - b__h1415 } ; + assign int_div_fNext_2$ENQ = CAN_FIRE_RL_int_div_work_2 ; + assign int_div_fNext_2$DEQ = CAN_FIRE_RL_int_div_work_3 ; + assign int_div_fNext_2$CLR = 1'b0 ; + + // submodule int_div_fNext_20 + assign int_div_fNext_20$D_IN = + { int_div_fNext_19$D_OUT[231:174], + int_div_fNext_19$D_OUT[172:116], + !int_div_fNext_19$D_OUT[115], + int_div_fNext_19$D_OUT[115] ? + { int_div_fNext_19$D_OUT[114:0], 1'd0 } + b__h7247 : + { int_div_fNext_19$D_OUT[114:0], 1'd0 } - b__h7247 } ; + assign int_div_fNext_20$ENQ = CAN_FIRE_RL_int_div_work_20 ; + assign int_div_fNext_20$DEQ = CAN_FIRE_RL_int_div_work_21 ; + assign int_div_fNext_20$CLR = 1'b0 ; + + // submodule int_div_fNext_21 + assign int_div_fNext_21$D_IN = + { int_div_fNext_20$D_OUT[231:174], + int_div_fNext_20$D_OUT[172:116], + !int_div_fNext_20$D_OUT[115], + int_div_fNext_20$D_OUT[115] ? + { int_div_fNext_20$D_OUT[114:0], 1'd0 } + b__h7571 : + { int_div_fNext_20$D_OUT[114:0], 1'd0 } - b__h7571 } ; + assign int_div_fNext_21$ENQ = CAN_FIRE_RL_int_div_work_21 ; + assign int_div_fNext_21$DEQ = CAN_FIRE_RL_int_div_work_22 ; + assign int_div_fNext_21$CLR = 1'b0 ; + + // submodule int_div_fNext_22 + assign int_div_fNext_22$D_IN = + { int_div_fNext_21$D_OUT[231:174], + int_div_fNext_21$D_OUT[172:116], + !int_div_fNext_21$D_OUT[115], + int_div_fNext_21$D_OUT[115] ? + { int_div_fNext_21$D_OUT[114:0], 1'd0 } + b__h7895 : + { int_div_fNext_21$D_OUT[114:0], 1'd0 } - b__h7895 } ; + assign int_div_fNext_22$ENQ = CAN_FIRE_RL_int_div_work_22 ; + assign int_div_fNext_22$DEQ = CAN_FIRE_RL_int_div_work_23 ; + assign int_div_fNext_22$CLR = 1'b0 ; + + // submodule int_div_fNext_23 + assign int_div_fNext_23$D_IN = + { int_div_fNext_22$D_OUT[231:174], + int_div_fNext_22$D_OUT[172:116], + !int_div_fNext_22$D_OUT[115], + int_div_fNext_22$D_OUT[115] ? + { int_div_fNext_22$D_OUT[114:0], 1'd0 } + b__h8219 : + { int_div_fNext_22$D_OUT[114:0], 1'd0 } - b__h8219 } ; + assign int_div_fNext_23$ENQ = CAN_FIRE_RL_int_div_work_23 ; + assign int_div_fNext_23$DEQ = CAN_FIRE_RL_int_div_work_24 ; + assign int_div_fNext_23$CLR = 1'b0 ; + + // submodule int_div_fNext_24 + assign int_div_fNext_24$D_IN = + { int_div_fNext_23$D_OUT[231:174], + int_div_fNext_23$D_OUT[172:116], + !int_div_fNext_23$D_OUT[115], + int_div_fNext_23$D_OUT[115] ? + { int_div_fNext_23$D_OUT[114:0], 1'd0 } + b__h8543 : + { int_div_fNext_23$D_OUT[114:0], 1'd0 } - b__h8543 } ; + assign int_div_fNext_24$ENQ = CAN_FIRE_RL_int_div_work_24 ; + assign int_div_fNext_24$DEQ = CAN_FIRE_RL_int_div_work_25 ; + assign int_div_fNext_24$CLR = 1'b0 ; + + // submodule int_div_fNext_25 + assign int_div_fNext_25$D_IN = + { int_div_fNext_24$D_OUT[231:174], + int_div_fNext_24$D_OUT[172:116], + !int_div_fNext_24$D_OUT[115], + int_div_fNext_24$D_OUT[115] ? + { int_div_fNext_24$D_OUT[114:0], 1'd0 } + b__h8867 : + { int_div_fNext_24$D_OUT[114:0], 1'd0 } - b__h8867 } ; + assign int_div_fNext_25$ENQ = CAN_FIRE_RL_int_div_work_25 ; + assign int_div_fNext_25$DEQ = CAN_FIRE_RL_int_div_work_26 ; + assign int_div_fNext_25$CLR = 1'b0 ; + + // submodule int_div_fNext_26 + assign int_div_fNext_26$D_IN = + { int_div_fNext_25$D_OUT[231:174], + int_div_fNext_25$D_OUT[172:116], + !int_div_fNext_25$D_OUT[115], + int_div_fNext_25$D_OUT[115] ? + { int_div_fNext_25$D_OUT[114:0], 1'd0 } + b__h9191 : + { int_div_fNext_25$D_OUT[114:0], 1'd0 } - b__h9191 } ; + assign int_div_fNext_26$ENQ = CAN_FIRE_RL_int_div_work_26 ; + assign int_div_fNext_26$DEQ = CAN_FIRE_RL_int_div_work_27 ; + assign int_div_fNext_26$CLR = 1'b0 ; + + // submodule int_div_fNext_27 + assign int_div_fNext_27$D_IN = + { int_div_fNext_26$D_OUT[231:174], + int_div_fNext_26$D_OUT[172:116], + !int_div_fNext_26$D_OUT[115], + int_div_fNext_26$D_OUT[115] ? + { int_div_fNext_26$D_OUT[114:0], 1'd0 } + b__h9515 : + { int_div_fNext_26$D_OUT[114:0], 1'd0 } - b__h9515 } ; + assign int_div_fNext_27$ENQ = CAN_FIRE_RL_int_div_work_27 ; + assign int_div_fNext_27$DEQ = CAN_FIRE_RL_int_div_work_28 ; + assign int_div_fNext_27$CLR = 1'b0 ; + + // submodule int_div_fNext_28 + assign int_div_fNext_28$D_IN = + { int_div_fNext_27$D_OUT[231:174], + int_div_fNext_27$D_OUT[172:116], + !int_div_fNext_27$D_OUT[115], + int_div_fNext_27$D_OUT[115] ? + { int_div_fNext_27$D_OUT[114:0], 1'd0 } + b__h9839 : + { int_div_fNext_27$D_OUT[114:0], 1'd0 } - b__h9839 } ; + assign int_div_fNext_28$ENQ = CAN_FIRE_RL_int_div_work_28 ; + assign int_div_fNext_28$DEQ = CAN_FIRE_RL_int_div_work_29 ; + assign int_div_fNext_28$CLR = 1'b0 ; + + // submodule int_div_fNext_29 + assign int_div_fNext_29$D_IN = + { int_div_fNext_28$D_OUT[231:174], + int_div_fNext_28$D_OUT[172:116], + !int_div_fNext_28$D_OUT[115], + int_div_fNext_28$D_OUT[115] ? + { int_div_fNext_28$D_OUT[114:0], 1'd0 } + b__h10163 : + { int_div_fNext_28$D_OUT[114:0], 1'd0 } - b__h10163 } ; + assign int_div_fNext_29$ENQ = CAN_FIRE_RL_int_div_work_29 ; + assign int_div_fNext_29$DEQ = CAN_FIRE_RL_int_div_work_30 ; + assign int_div_fNext_29$CLR = 1'b0 ; + + // submodule int_div_fNext_3 + assign int_div_fNext_3$D_IN = + { int_div_fNext_2$D_OUT[231:174], + int_div_fNext_2$D_OUT[172:116], + !int_div_fNext_2$D_OUT[115], + int_div_fNext_2$D_OUT[115] ? + { int_div_fNext_2$D_OUT[114:0], 1'd0 } + b__h1739 : + { int_div_fNext_2$D_OUT[114:0], 1'd0 } - b__h1739 } ; + assign int_div_fNext_3$ENQ = CAN_FIRE_RL_int_div_work_3 ; + assign int_div_fNext_3$DEQ = CAN_FIRE_RL_int_div_work_4 ; + assign int_div_fNext_3$CLR = 1'b0 ; + + // submodule int_div_fNext_30 + assign int_div_fNext_30$D_IN = + { int_div_fNext_29$D_OUT[231:174], + int_div_fNext_29$D_OUT[172:116], + !int_div_fNext_29$D_OUT[115], + int_div_fNext_29$D_OUT[115] ? + { int_div_fNext_29$D_OUT[114:0], 1'd0 } + b__h10487 : + { int_div_fNext_29$D_OUT[114:0], 1'd0 } - b__h10487 } ; + assign int_div_fNext_30$ENQ = CAN_FIRE_RL_int_div_work_30 ; + assign int_div_fNext_30$DEQ = CAN_FIRE_RL_int_div_work_31 ; + assign int_div_fNext_30$CLR = 1'b0 ; + + // submodule int_div_fNext_31 + assign int_div_fNext_31$D_IN = + { int_div_fNext_30$D_OUT[231:174], + int_div_fNext_30$D_OUT[172:116], + !int_div_fNext_30$D_OUT[115], + int_div_fNext_30$D_OUT[115] ? + { int_div_fNext_30$D_OUT[114:0], 1'd0 } + b__h10811 : + { int_div_fNext_30$D_OUT[114:0], 1'd0 } - b__h10811 } ; + assign int_div_fNext_31$ENQ = CAN_FIRE_RL_int_div_work_31 ; + assign int_div_fNext_31$DEQ = CAN_FIRE_RL_int_div_work_32 ; + assign int_div_fNext_31$CLR = 1'b0 ; + + // submodule int_div_fNext_32 + assign int_div_fNext_32$D_IN = + { int_div_fNext_31$D_OUT[231:174], + int_div_fNext_31$D_OUT[172:116], + !int_div_fNext_31$D_OUT[115], + int_div_fNext_31$D_OUT[115] ? + { int_div_fNext_31$D_OUT[114:0], 1'd0 } + b__h11135 : + { int_div_fNext_31$D_OUT[114:0], 1'd0 } - b__h11135 } ; + assign int_div_fNext_32$ENQ = CAN_FIRE_RL_int_div_work_32 ; + assign int_div_fNext_32$DEQ = CAN_FIRE_RL_int_div_work_33 ; + assign int_div_fNext_32$CLR = 1'b0 ; + + // submodule int_div_fNext_33 + assign int_div_fNext_33$D_IN = + { int_div_fNext_32$D_OUT[231:174], + int_div_fNext_32$D_OUT[172:116], + !int_div_fNext_32$D_OUT[115], + int_div_fNext_32$D_OUT[115] ? + { int_div_fNext_32$D_OUT[114:0], 1'd0 } + b__h11459 : + { int_div_fNext_32$D_OUT[114:0], 1'd0 } - b__h11459 } ; + assign int_div_fNext_33$ENQ = CAN_FIRE_RL_int_div_work_33 ; + assign int_div_fNext_33$DEQ = CAN_FIRE_RL_int_div_work_34 ; + assign int_div_fNext_33$CLR = 1'b0 ; + + // submodule int_div_fNext_34 + assign int_div_fNext_34$D_IN = + { int_div_fNext_33$D_OUT[231:174], + int_div_fNext_33$D_OUT[172:116], + !int_div_fNext_33$D_OUT[115], + int_div_fNext_33$D_OUT[115] ? + { int_div_fNext_33$D_OUT[114:0], 1'd0 } + b__h11783 : + { int_div_fNext_33$D_OUT[114:0], 1'd0 } - b__h11783 } ; + assign int_div_fNext_34$ENQ = CAN_FIRE_RL_int_div_work_34 ; + assign int_div_fNext_34$DEQ = CAN_FIRE_RL_int_div_work_35 ; + assign int_div_fNext_34$CLR = 1'b0 ; + + // submodule int_div_fNext_35 + assign int_div_fNext_35$D_IN = + { int_div_fNext_34$D_OUT[231:174], + int_div_fNext_34$D_OUT[172:116], + !int_div_fNext_34$D_OUT[115], + int_div_fNext_34$D_OUT[115] ? + { int_div_fNext_34$D_OUT[114:0], 1'd0 } + b__h12107 : + { int_div_fNext_34$D_OUT[114:0], 1'd0 } - b__h12107 } ; + assign int_div_fNext_35$ENQ = CAN_FIRE_RL_int_div_work_35 ; + assign int_div_fNext_35$DEQ = CAN_FIRE_RL_int_div_work_36 ; + assign int_div_fNext_35$CLR = 1'b0 ; + + // submodule int_div_fNext_36 + assign int_div_fNext_36$D_IN = + { int_div_fNext_35$D_OUT[231:174], + int_div_fNext_35$D_OUT[172:116], + !int_div_fNext_35$D_OUT[115], + int_div_fNext_35$D_OUT[115] ? + { int_div_fNext_35$D_OUT[114:0], 1'd0 } + b__h12431 : + { int_div_fNext_35$D_OUT[114:0], 1'd0 } - b__h12431 } ; + assign int_div_fNext_36$ENQ = CAN_FIRE_RL_int_div_work_36 ; + assign int_div_fNext_36$DEQ = CAN_FIRE_RL_int_div_work_37 ; + assign int_div_fNext_36$CLR = 1'b0 ; + + // submodule int_div_fNext_37 + assign int_div_fNext_37$D_IN = + { int_div_fNext_36$D_OUT[231:174], + int_div_fNext_36$D_OUT[172:116], + !int_div_fNext_36$D_OUT[115], + int_div_fNext_36$D_OUT[115] ? + { int_div_fNext_36$D_OUT[114:0], 1'd0 } + b__h12755 : + { int_div_fNext_36$D_OUT[114:0], 1'd0 } - b__h12755 } ; + assign int_div_fNext_37$ENQ = CAN_FIRE_RL_int_div_work_37 ; + assign int_div_fNext_37$DEQ = CAN_FIRE_RL_int_div_work_38 ; + assign int_div_fNext_37$CLR = 1'b0 ; + + // submodule int_div_fNext_38 + assign int_div_fNext_38$D_IN = + { int_div_fNext_37$D_OUT[231:174], + int_div_fNext_37$D_OUT[172:116], + !int_div_fNext_37$D_OUT[115], + int_div_fNext_37$D_OUT[115] ? + { int_div_fNext_37$D_OUT[114:0], 1'd0 } + b__h13079 : + { int_div_fNext_37$D_OUT[114:0], 1'd0 } - b__h13079 } ; + assign int_div_fNext_38$ENQ = CAN_FIRE_RL_int_div_work_38 ; + assign int_div_fNext_38$DEQ = CAN_FIRE_RL_int_div_work_39 ; + assign int_div_fNext_38$CLR = 1'b0 ; + + // submodule int_div_fNext_39 + assign int_div_fNext_39$D_IN = + { int_div_fNext_38$D_OUT[231:174], + int_div_fNext_38$D_OUT[172:116], + !int_div_fNext_38$D_OUT[115], + int_div_fNext_38$D_OUT[115] ? + { int_div_fNext_38$D_OUT[114:0], 1'd0 } + b__h13403 : + { int_div_fNext_38$D_OUT[114:0], 1'd0 } - b__h13403 } ; + assign int_div_fNext_39$ENQ = CAN_FIRE_RL_int_div_work_39 ; + assign int_div_fNext_39$DEQ = CAN_FIRE_RL_int_div_work_40 ; + assign int_div_fNext_39$CLR = 1'b0 ; + + // submodule int_div_fNext_4 + assign int_div_fNext_4$D_IN = + { int_div_fNext_3$D_OUT[231:174], + int_div_fNext_3$D_OUT[172:116], + !int_div_fNext_3$D_OUT[115], + int_div_fNext_3$D_OUT[115] ? + { int_div_fNext_3$D_OUT[114:0], 1'd0 } + b__h2063 : + { int_div_fNext_3$D_OUT[114:0], 1'd0 } - b__h2063 } ; + assign int_div_fNext_4$ENQ = CAN_FIRE_RL_int_div_work_4 ; + assign int_div_fNext_4$DEQ = CAN_FIRE_RL_int_div_work_5 ; + assign int_div_fNext_4$CLR = 1'b0 ; + + // submodule int_div_fNext_40 + assign int_div_fNext_40$D_IN = + { int_div_fNext_39$D_OUT[231:174], + int_div_fNext_39$D_OUT[172:116], + !int_div_fNext_39$D_OUT[115], + int_div_fNext_39$D_OUT[115] ? + { int_div_fNext_39$D_OUT[114:0], 1'd0 } + b__h13727 : + { int_div_fNext_39$D_OUT[114:0], 1'd0 } - b__h13727 } ; + assign int_div_fNext_40$ENQ = CAN_FIRE_RL_int_div_work_40 ; + assign int_div_fNext_40$DEQ = CAN_FIRE_RL_int_div_work_41 ; + assign int_div_fNext_40$CLR = 1'b0 ; + + // submodule int_div_fNext_41 + assign int_div_fNext_41$D_IN = + { int_div_fNext_40$D_OUT[231:174], + int_div_fNext_40$D_OUT[172:116], + !int_div_fNext_40$D_OUT[115], + int_div_fNext_40$D_OUT[115] ? + { int_div_fNext_40$D_OUT[114:0], 1'd0 } + b__h14051 : + { int_div_fNext_40$D_OUT[114:0], 1'd0 } - b__h14051 } ; + assign int_div_fNext_41$ENQ = CAN_FIRE_RL_int_div_work_41 ; + assign int_div_fNext_41$DEQ = CAN_FIRE_RL_int_div_work_42 ; + assign int_div_fNext_41$CLR = 1'b0 ; + + // submodule int_div_fNext_42 + assign int_div_fNext_42$D_IN = + { int_div_fNext_41$D_OUT[231:174], + int_div_fNext_41$D_OUT[172:116], + !int_div_fNext_41$D_OUT[115], + int_div_fNext_41$D_OUT[115] ? + { int_div_fNext_41$D_OUT[114:0], 1'd0 } + b__h14375 : + { int_div_fNext_41$D_OUT[114:0], 1'd0 } - b__h14375 } ; + assign int_div_fNext_42$ENQ = CAN_FIRE_RL_int_div_work_42 ; + assign int_div_fNext_42$DEQ = CAN_FIRE_RL_int_div_work_43 ; + assign int_div_fNext_42$CLR = 1'b0 ; + + // submodule int_div_fNext_43 + assign int_div_fNext_43$D_IN = + { int_div_fNext_42$D_OUT[231:174], + int_div_fNext_42$D_OUT[172:116], + !int_div_fNext_42$D_OUT[115], + int_div_fNext_42$D_OUT[115] ? + { int_div_fNext_42$D_OUT[114:0], 1'd0 } + b__h14699 : + { int_div_fNext_42$D_OUT[114:0], 1'd0 } - b__h14699 } ; + assign int_div_fNext_43$ENQ = CAN_FIRE_RL_int_div_work_43 ; + assign int_div_fNext_43$DEQ = CAN_FIRE_RL_int_div_work_44 ; + assign int_div_fNext_43$CLR = 1'b0 ; + + // submodule int_div_fNext_44 + assign int_div_fNext_44$D_IN = + { int_div_fNext_43$D_OUT[231:174], + int_div_fNext_43$D_OUT[172:116], + !int_div_fNext_43$D_OUT[115], + int_div_fNext_43$D_OUT[115] ? + { int_div_fNext_43$D_OUT[114:0], 1'd0 } + b__h15023 : + { int_div_fNext_43$D_OUT[114:0], 1'd0 } - b__h15023 } ; + assign int_div_fNext_44$ENQ = CAN_FIRE_RL_int_div_work_44 ; + assign int_div_fNext_44$DEQ = CAN_FIRE_RL_int_div_work_45 ; + assign int_div_fNext_44$CLR = 1'b0 ; + + // submodule int_div_fNext_45 + assign int_div_fNext_45$D_IN = + { int_div_fNext_44$D_OUT[231:174], + int_div_fNext_44$D_OUT[172:116], + !int_div_fNext_44$D_OUT[115], + int_div_fNext_44$D_OUT[115] ? + { int_div_fNext_44$D_OUT[114:0], 1'd0 } + b__h15347 : + { int_div_fNext_44$D_OUT[114:0], 1'd0 } - b__h15347 } ; + assign int_div_fNext_45$ENQ = CAN_FIRE_RL_int_div_work_45 ; + assign int_div_fNext_45$DEQ = CAN_FIRE_RL_int_div_work_46 ; + assign int_div_fNext_45$CLR = 1'b0 ; + + // submodule int_div_fNext_46 + assign int_div_fNext_46$D_IN = + { int_div_fNext_45$D_OUT[231:174], + int_div_fNext_45$D_OUT[172:116], + !int_div_fNext_45$D_OUT[115], + int_div_fNext_45$D_OUT[115] ? + { int_div_fNext_45$D_OUT[114:0], 1'd0 } + b__h15671 : + { int_div_fNext_45$D_OUT[114:0], 1'd0 } - b__h15671 } ; + assign int_div_fNext_46$ENQ = CAN_FIRE_RL_int_div_work_46 ; + assign int_div_fNext_46$DEQ = CAN_FIRE_RL_int_div_work_47 ; + assign int_div_fNext_46$CLR = 1'b0 ; + + // submodule int_div_fNext_47 + assign int_div_fNext_47$D_IN = + { int_div_fNext_46$D_OUT[231:174], + int_div_fNext_46$D_OUT[172:116], + !int_div_fNext_46$D_OUT[115], + int_div_fNext_46$D_OUT[115] ? + { int_div_fNext_46$D_OUT[114:0], 1'd0 } + b__h15995 : + { int_div_fNext_46$D_OUT[114:0], 1'd0 } - b__h15995 } ; + assign int_div_fNext_47$ENQ = CAN_FIRE_RL_int_div_work_47 ; + assign int_div_fNext_47$DEQ = CAN_FIRE_RL_int_div_work_48 ; + assign int_div_fNext_47$CLR = 1'b0 ; + + // submodule int_div_fNext_48 + assign int_div_fNext_48$D_IN = + { int_div_fNext_47$D_OUT[231:174], + int_div_fNext_47$D_OUT[172:116], + !int_div_fNext_47$D_OUT[115], + int_div_fNext_47$D_OUT[115] ? + { int_div_fNext_47$D_OUT[114:0], 1'd0 } + b__h16319 : + { int_div_fNext_47$D_OUT[114:0], 1'd0 } - b__h16319 } ; + assign int_div_fNext_48$ENQ = CAN_FIRE_RL_int_div_work_48 ; + assign int_div_fNext_48$DEQ = CAN_FIRE_RL_int_div_work_49 ; + assign int_div_fNext_48$CLR = 1'b0 ; + + // submodule int_div_fNext_49 + assign int_div_fNext_49$D_IN = + { int_div_fNext_48$D_OUT[231:174], + int_div_fNext_48$D_OUT[172:116], + !int_div_fNext_48$D_OUT[115], + int_div_fNext_48$D_OUT[115] ? + { int_div_fNext_48$D_OUT[114:0], 1'd0 } + b__h16643 : + { int_div_fNext_48$D_OUT[114:0], 1'd0 } - b__h16643 } ; + assign int_div_fNext_49$ENQ = CAN_FIRE_RL_int_div_work_49 ; + assign int_div_fNext_49$DEQ = CAN_FIRE_RL_int_div_work_50 ; + assign int_div_fNext_49$CLR = 1'b0 ; + + // submodule int_div_fNext_5 + assign int_div_fNext_5$D_IN = + { int_div_fNext_4$D_OUT[231:174], + int_div_fNext_4$D_OUT[172:116], + !int_div_fNext_4$D_OUT[115], + int_div_fNext_4$D_OUT[115] ? + { int_div_fNext_4$D_OUT[114:0], 1'd0 } + b__h2387 : + { int_div_fNext_4$D_OUT[114:0], 1'd0 } - b__h2387 } ; + assign int_div_fNext_5$ENQ = CAN_FIRE_RL_int_div_work_5 ; + assign int_div_fNext_5$DEQ = CAN_FIRE_RL_int_div_work_6 ; + assign int_div_fNext_5$CLR = 1'b0 ; + + // submodule int_div_fNext_50 + assign int_div_fNext_50$D_IN = + { int_div_fNext_49$D_OUT[231:174], + int_div_fNext_49$D_OUT[172:116], + !int_div_fNext_49$D_OUT[115], + int_div_fNext_49$D_OUT[115] ? + { int_div_fNext_49$D_OUT[114:0], 1'd0 } + b__h16967 : + { int_div_fNext_49$D_OUT[114:0], 1'd0 } - b__h16967 } ; + assign int_div_fNext_50$ENQ = CAN_FIRE_RL_int_div_work_50 ; + assign int_div_fNext_50$DEQ = CAN_FIRE_RL_int_div_work_51 ; + assign int_div_fNext_50$CLR = 1'b0 ; + + // submodule int_div_fNext_51 + assign int_div_fNext_51$D_IN = + { int_div_fNext_50$D_OUT[231:174], + int_div_fNext_50$D_OUT[172:116], + !int_div_fNext_50$D_OUT[115], + int_div_fNext_50$D_OUT[115] ? + { int_div_fNext_50$D_OUT[114:0], 1'd0 } + b__h17291 : + { int_div_fNext_50$D_OUT[114:0], 1'd0 } - b__h17291 } ; + assign int_div_fNext_51$ENQ = CAN_FIRE_RL_int_div_work_51 ; + assign int_div_fNext_51$DEQ = CAN_FIRE_RL_int_div_work_52 ; + assign int_div_fNext_51$CLR = 1'b0 ; + + // submodule int_div_fNext_52 + assign int_div_fNext_52$D_IN = + { int_div_fNext_51$D_OUT[231:174], + int_div_fNext_51$D_OUT[172:116], + !int_div_fNext_51$D_OUT[115], + int_div_fNext_51$D_OUT[115] ? + { int_div_fNext_51$D_OUT[114:0], 1'd0 } + b__h17615 : + { int_div_fNext_51$D_OUT[114:0], 1'd0 } - b__h17615 } ; + assign int_div_fNext_52$ENQ = CAN_FIRE_RL_int_div_work_52 ; + assign int_div_fNext_52$DEQ = CAN_FIRE_RL_int_div_work_53 ; + assign int_div_fNext_52$CLR = 1'b0 ; + + // submodule int_div_fNext_53 + assign int_div_fNext_53$D_IN = + { int_div_fNext_52$D_OUT[231:174], + int_div_fNext_52$D_OUT[172:116], + !int_div_fNext_52$D_OUT[115], + int_div_fNext_52$D_OUT[115] ? + { int_div_fNext_52$D_OUT[114:0], 1'd0 } + b__h17939 : + { int_div_fNext_52$D_OUT[114:0], 1'd0 } - b__h17939 } ; + assign int_div_fNext_53$ENQ = CAN_FIRE_RL_int_div_work_53 ; + assign int_div_fNext_53$DEQ = CAN_FIRE_RL_int_div_work_54 ; + assign int_div_fNext_53$CLR = 1'b0 ; + + // submodule int_div_fNext_54 + assign int_div_fNext_54$D_IN = + { int_div_fNext_53$D_OUT[231:174], + int_div_fNext_53$D_OUT[172:116], + !int_div_fNext_53$D_OUT[115], + int_div_fNext_53$D_OUT[115] ? + { int_div_fNext_53$D_OUT[114:0], 1'd0 } + b__h18263 : + { int_div_fNext_53$D_OUT[114:0], 1'd0 } - b__h18263 } ; + assign int_div_fNext_54$ENQ = CAN_FIRE_RL_int_div_work_54 ; + assign int_div_fNext_54$DEQ = CAN_FIRE_RL_int_div_work_55 ; + assign int_div_fNext_54$CLR = 1'b0 ; + + // submodule int_div_fNext_55 + assign int_div_fNext_55$D_IN = + { int_div_fNext_54$D_OUT[231:174], + int_div_fNext_54$D_OUT[172:116], + !int_div_fNext_54$D_OUT[115], + int_div_fNext_54$D_OUT[115] ? + { int_div_fNext_54$D_OUT[114:0], 1'd0 } + b__h18587 : + { int_div_fNext_54$D_OUT[114:0], 1'd0 } - b__h18587 } ; + assign int_div_fNext_55$ENQ = CAN_FIRE_RL_int_div_work_55 ; + assign int_div_fNext_55$DEQ = CAN_FIRE_RL_int_div_work_56 ; + assign int_div_fNext_55$CLR = 1'b0 ; + + // submodule int_div_fNext_56 + assign int_div_fNext_56$D_IN = + { int_div_fNext_55$D_OUT[231:174], + int_div_fNext_55$D_OUT[172:116], + !int_div_fNext_55$D_OUT[115], + int_div_fNext_55$D_OUT[115] ? + { int_div_fNext_55$D_OUT[114:0], 1'd0 } + b__h18911 : + { int_div_fNext_55$D_OUT[114:0], 1'd0 } - b__h18911 } ; + assign int_div_fNext_56$ENQ = CAN_FIRE_RL_int_div_work_56 ; + assign int_div_fNext_56$DEQ = CAN_FIRE_RL_int_div_work_57 ; + assign int_div_fNext_56$CLR = 1'b0 ; + + // submodule int_div_fNext_57 + assign int_div_fNext_57$D_IN = + { int_div_fNext_56$D_OUT[231:174], + int_div_fNext_56$D_OUT[172:116], + !int_div_fNext_56$D_OUT[115], + int_div_fNext_56$D_OUT[115] ? + { int_div_fNext_56$D_OUT[114:0], 1'd0 } + b__h19235 : + { int_div_fNext_56$D_OUT[114:0], 1'd0 } - b__h19235 } ; + assign int_div_fNext_57$ENQ = CAN_FIRE_RL_int_div_work_57 ; + assign int_div_fNext_57$DEQ = CAN_FIRE_RL_int_div_finish ; + assign int_div_fNext_57$CLR = 1'b0 ; + + // submodule int_div_fNext_6 + assign int_div_fNext_6$D_IN = + { int_div_fNext_5$D_OUT[231:174], + int_div_fNext_5$D_OUT[172:116], + !int_div_fNext_5$D_OUT[115], + int_div_fNext_5$D_OUT[115] ? + { int_div_fNext_5$D_OUT[114:0], 1'd0 } + b__h2711 : + { int_div_fNext_5$D_OUT[114:0], 1'd0 } - b__h2711 } ; + assign int_div_fNext_6$ENQ = CAN_FIRE_RL_int_div_work_6 ; + assign int_div_fNext_6$DEQ = CAN_FIRE_RL_int_div_work_7 ; + assign int_div_fNext_6$CLR = 1'b0 ; + + // submodule int_div_fNext_7 + assign int_div_fNext_7$D_IN = + { int_div_fNext_6$D_OUT[231:174], + int_div_fNext_6$D_OUT[172:116], + !int_div_fNext_6$D_OUT[115], + int_div_fNext_6$D_OUT[115] ? + { int_div_fNext_6$D_OUT[114:0], 1'd0 } + b__h3035 : + { int_div_fNext_6$D_OUT[114:0], 1'd0 } - b__h3035 } ; + assign int_div_fNext_7$ENQ = CAN_FIRE_RL_int_div_work_7 ; + assign int_div_fNext_7$DEQ = CAN_FIRE_RL_int_div_work_8 ; + assign int_div_fNext_7$CLR = 1'b0 ; + + // submodule int_div_fNext_8 + assign int_div_fNext_8$D_IN = + { int_div_fNext_7$D_OUT[231:174], + int_div_fNext_7$D_OUT[172:116], + !int_div_fNext_7$D_OUT[115], + int_div_fNext_7$D_OUT[115] ? + { int_div_fNext_7$D_OUT[114:0], 1'd0 } + b__h3359 : + { int_div_fNext_7$D_OUT[114:0], 1'd0 } - b__h3359 } ; + assign int_div_fNext_8$ENQ = CAN_FIRE_RL_int_div_work_8 ; + assign int_div_fNext_8$DEQ = CAN_FIRE_RL_int_div_work_9 ; + assign int_div_fNext_8$CLR = 1'b0 ; + + // submodule int_div_fNext_9 + assign int_div_fNext_9$D_IN = + { int_div_fNext_8$D_OUT[231:174], + int_div_fNext_8$D_OUT[172:116], + !int_div_fNext_8$D_OUT[115], + int_div_fNext_8$D_OUT[115] ? + { int_div_fNext_8$D_OUT[114:0], 1'd0 } + b__h3683 : + { int_div_fNext_8$D_OUT[114:0], 1'd0 } - b__h3683 } ; + assign int_div_fNext_9$ENQ = CAN_FIRE_RL_int_div_work_9 ; + assign int_div_fNext_9$DEQ = CAN_FIRE_RL_int_div_work_10 ; + assign int_div_fNext_9$CLR = 1'b0 ; + + // submodule int_div_fRequest + assign int_div_fRequest$D_IN = fpu_fState_S1$D_OUT[181:11] ; + assign int_div_fRequest$ENQ = + WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[318] ; + assign int_div_fRequest$DEQ = CAN_FIRE_RL_int_div_start ; + assign int_div_fRequest$CLR = 1'b0 ; + + // submodule int_div_fResponse + assign int_div_fResponse$D_IN = + { IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19[56:0], + value__h19447[114:58] } ; + assign int_div_fResponse$ENQ = CAN_FIRE_RL_int_div_finish ; + assign int_div_fResponse$DEQ = + WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[147] ; + assign int_div_fResponse$CLR = 1'b0 ; + + // remaining internal signals + assign IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7 = + _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 ? + _theResult___snd__h59844 : + _theResult___snd__h59839 ; + assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 = + sfd__h60417[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 63'h7FF0000000000000 : + { din_inc___2_exp__h61001, sfd__h60417[52:1] }) : + { IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, + sfd__h60417[51:0] } ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 = + (_theResult___fst_exp__h59725 == 11'd0) ? + 12'd3074 : + { theResult___fst_exp9725_MINUS_1023__q6[10], + theResult___fst_exp9725_MINUS_1023__q6 } ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 = + (sfdin__h51553[57] ? + 6'd0 : + (sfdin__h51553[56] ? + 6'd1 : + (sfdin__h51553[55] ? + 6'd2 : + (sfdin__h51553[54] ? + 6'd3 : + (sfdin__h51553[53] ? + 6'd4 : + (sfdin__h51553[52] ? + 6'd5 : + (sfdin__h51553[51] ? + 6'd6 : + (sfdin__h51553[50] ? + 6'd7 : + (sfdin__h51553[49] ? + 6'd8 : + (sfdin__h51553[48] ? + 6'd9 : + (sfdin__h51553[47] ? + 6'd10 : + (sfdin__h51553[46] ? + 6'd11 : + (sfdin__h51553[45] ? + 6'd12 : + (sfdin__h51553[44] ? + 6'd13 : + (sfdin__h51553[43] ? + 6'd14 : + (sfdin__h51553[42] ? + 6'd15 : + (sfdin__h51553[41] ? + 6'd16 : + (sfdin__h51553[40] ? + 6'd17 : + (sfdin__h51553[39] ? + 6'd18 : + (sfdin__h51553[38] ? + 6'd19 : + (sfdin__h51553[37] ? + 6'd20 : + (sfdin__h51553[36] ? + 6'd21 : + (sfdin__h51553[35] ? + 6'd22 : + (sfdin__h51553[34] ? + 6'd23 : + (sfdin__h51553[33] ? + 6'd24 : + (sfdin__h51553[32] ? + 6'd25 : + (sfdin__h51553[31] ? + 6'd26 : + (sfdin__h51553[30] ? + 6'd27 : + (sfdin__h51553[29] ? + 6'd28 : + (sfdin__h51553[28] ? + 6'd29 : + (sfdin__h51553[27] ? + 6'd30 : + (sfdin__h51553[26] ? + 6'd31 : + (sfdin__h51553[25] ? + 6'd32 : + (sfdin__h51553[24] ? + 6'd33 : + (sfdin__h51553[23] ? + 6'd34 : + (sfdin__h51553[22] ? + 6'd35 : + (sfdin__h51553[21] ? + 6'd36 : + (sfdin__h51553[20] ? + 6'd37 : + (sfdin__h51553[19] ? + 6'd38 : + (sfdin__h51553[18] ? + 6'd39 : + (sfdin__h51553[17] ? + 6'd40 : + (sfdin__h51553[16] ? + 6'd41 : + (sfdin__h51553[15] ? + 6'd42 : + (sfdin__h51553[14] ? + 6'd43 : + (sfdin__h51553[13] ? + 6'd44 : + (sfdin__h51553[12] ? + 6'd45 : + (sfdin__h51553[11] ? + 6'd46 : + (sfdin__h51553[10] ? + 6'd47 : + (sfdin__h51553[9] ? + 6'd48 : + (sfdin__h51553[8] ? + 6'd49 : + (sfdin__h51553[7] ? + 6'd50 : + (sfdin__h51553[6] ? + 6'd51 : + (sfdin__h51553[5] ? + 6'd52 : + (sfdin__h51553[4] ? + 6'd53 : + (sfdin__h51553[3] ? + 6'd54 : + (sfdin__h51553[2] ? + 6'd55 : + (sfdin__h51553[1] ? + 6'd56 : + (sfdin__h51553[0] ? + 6'd57 : + 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 6'd1 ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 = + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 - + 12'd3074 ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770 = + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 : + { fpu_fState_S3$D_OUT[129:128], + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[127] : + fpu_fState_S3$D_OUT[127], + fpu_fState_S3$D_OUT[126], + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[125] : + fpu_fState_S3$D_OUT[125] } ; + assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 = + (sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h59768, sfdin__h59762[57:6] } ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 = + (((fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3[10]}}, + fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 }) - + { 7'd0, b__h21789 }) - + (((fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4[10]}}, + fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 }) - + { 7'd0, b__h29207 }) ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ + 13'h1000) <= + 13'd5120 ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ + 13'h1000) < + 13'd3020 ; + assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ + 13'h1000) < + 13'd3074 ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 : + CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0) ? + 11'd2047 : + ((fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? + 11'd0 : + _theResult___fst_exp__h37217) ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? + 52'd0 : + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? + _theResult___fst_sfd__h37707 : + _theResult___fst_sfd__h37218) ; + assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54]) ? + { fpu_fOperands_S0$D_OUT[66:55], sfd__h36687 } : + ((fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118]) ? + fpu_fOperands_S0$D_OUT[130:67] : + ((fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54]) ? + fpu_fOperands_S0$D_OUT[66:3] : + NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305)) ; + assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 = + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + fpu_fState_S3$D_OUT[57:56] == 2'b0 && + !fpu_fState_S3$D_OUT[194] : + !fpu_fState_S3$D_OUT[194] ; + assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 = + ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + { fpu_fState_S3$D_OUT[129:128], + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[127], + fpu_fState_S3$D_OUT[126], + fpu_fState_S3$D_OUT[57:56] != 2'b0 || + fpu_fState_S3$D_OUT[125] } : + fpu_fState_S3$D_OUT[129:125]) | + { 2'd0, + sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023, + _theResult___fst_exp__h59771 == 11'd0 && guard__h51381 != 2'd0, + sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023 } ; + assign IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 = + (fpu_fState_S4$D_OUT[64:54] == 11'd0 && + sfd__h60417[53:52] == 2'b01) ? + 11'd1 : + fpu_fState_S4$D_OUT[64:54] ; + assign IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19 = + int_div_fNext_57$D_OUT[115] ? + int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 - + 58'd1 : + int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 ; + assign IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8 = + sfdin__h59762[5] ? 2'd2 : 2'd0 ; + assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 = + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) ; + assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305 = + { NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 ? + 52'h8000000000000 : + IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 } ; + assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334 = + (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 && + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; + assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341 = + (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && + (!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208) ; + assign _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 = + ({ 6'd0, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ^ + 12'h800) <= + (IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ^ + 12'h800) ; + assign _theResult____h50063 = + (fpu_fState_S2$D_OUT[10:0] < 11'd58) ? + result__h50108 : + result__h50258 ; + assign _theResult___exp__h60910 = + sfd__h60417[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 11'd2047 : + din_inc___2_exp__h61001) : + IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 ; + assign _theResult___fst__h49072 = + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 ? + value__h49300[10:0] : + 11'd0 ; + assign _theResult___fst_exp__h59719 = fpu_fState_S3$D_OUT[120:110] - 11'd1 ; + assign _theResult___fst_exp__h59722 = + (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + _theResult___fst_exp__h59719 : + 11'd2046 ; + assign _theResult___fst_exp__h59725 = + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + _theResult___fst_exp__h59722 : + fpu_fState_S3$D_OUT[120:110] ; + assign _theResult___fst_exp__h59768 = + sfdin__h51553[57] ? + _theResult___fst_exp__h59791 : + _theResult___fst_exp__h59855 ; + assign _theResult___fst_exp__h59771 = + (sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h59768 ; + assign _theResult___fst_exp__h59791 = + (_theResult___fst_exp__h59725 == 11'd0) ? + 11'd2 : + _theResult___fst_exp__h59725 + 11'd1 ; + assign _theResult___fst_exp__h59807 = + (_theResult___fst_exp__h59725 == 11'd0) ? + 11'd1 : + _theResult___fst_exp__h59725 ; + assign _theResult___fst_exp__h59846 = + _theResult___fst_exp__h59725 - + { 5'd0, + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ; + assign _theResult___fst_exp__h59852 = + (!sfdin__h51553[57] && !sfdin__h51553[56] && + !sfdin__h51553[55] && + !sfdin__h51553[54] && + !sfdin__h51553[53] && + !sfdin__h51553[52] && + !sfdin__h51553[51] && + !sfdin__h51553[50] && + !sfdin__h51553[49] && + !sfdin__h51553[48] && + !sfdin__h51553[47] && + !sfdin__h51553[46] && + !sfdin__h51553[45] && + !sfdin__h51553[44] && + !sfdin__h51553[43] && + !sfdin__h51553[42] && + !sfdin__h51553[41] && + !sfdin__h51553[40] && + !sfdin__h51553[39] && + !sfdin__h51553[38] && + !sfdin__h51553[37] && + !sfdin__h51553[36] && + !sfdin__h51553[35] && + !sfdin__h51553[34] && + !sfdin__h51553[33] && + !sfdin__h51553[32] && + !sfdin__h51553[31] && + !sfdin__h51553[30] && + !sfdin__h51553[29] && + !sfdin__h51553[28] && + !sfdin__h51553[27] && + !sfdin__h51553[26] && + !sfdin__h51553[25] && + !sfdin__h51553[24] && + !sfdin__h51553[23] && + !sfdin__h51553[22] && + !sfdin__h51553[21] && + !sfdin__h51553[20] && + !sfdin__h51553[19] && + !sfdin__h51553[18] && + !sfdin__h51553[17] && + !sfdin__h51553[16] && + !sfdin__h51553[15] && + !sfdin__h51553[14] && + !sfdin__h51553[13] && + !sfdin__h51553[12] && + !sfdin__h51553[11] && + !sfdin__h51553[10] && + !sfdin__h51553[9] && + !sfdin__h51553[8] && + !sfdin__h51553[7] && + !sfdin__h51553[6] && + !sfdin__h51553[5] && + !sfdin__h51553[4] && + !sfdin__h51553[3] && + !sfdin__h51553[2] && + !sfdin__h51553[1] && + !sfdin__h51553[0] || + !_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727) ? + 11'd0 : + _theResult___fst_exp__h59846 ; + assign _theResult___fst_exp__h59855 = + (!sfdin__h51553[57] && sfdin__h51553[56]) ? + _theResult___fst_exp__h59807 : + _theResult___fst_exp__h59852 ; + assign _theResult___fst_exp__h60991 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___fst_exp__h60988 ; + assign _theResult___fst_sfd__h60992 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___fst_sfd__h60989 ; + assign _theResult___sfd__h60911 = + sfd__h60417[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 52'd0 : + sfd__h60417[52:1]) : + sfd__h60417[51:0] ; + assign _theResult___snd__h52150 = { fpu_fState_S3$D_OUT[56:0], 1'd0 } ; + assign _theResult___snd__h59785 = { sfdin__h51553[56:0], 1'd0 } ; + assign _theResult___snd__h59800 = + (!sfdin__h51553[57] && sfdin__h51553[56]) ? + _theResult___snd__h59802 : + _theResult___snd__h59815 ; + assign _theResult___snd__h59802 = { sfdin__h51553[55:0], 2'd0 } ; + assign _theResult___snd__h59815 = + (!sfdin__h51553[57] && !sfdin__h51553[56] && + !sfdin__h51553[55] && + !sfdin__h51553[54] && + !sfdin__h51553[53] && + !sfdin__h51553[52] && + !sfdin__h51553[51] && + !sfdin__h51553[50] && + !sfdin__h51553[49] && + !sfdin__h51553[48] && + !sfdin__h51553[47] && + !sfdin__h51553[46] && + !sfdin__h51553[45] && + !sfdin__h51553[44] && + !sfdin__h51553[43] && + !sfdin__h51553[42] && + !sfdin__h51553[41] && + !sfdin__h51553[40] && + !sfdin__h51553[39] && + !sfdin__h51553[38] && + !sfdin__h51553[37] && + !sfdin__h51553[36] && + !sfdin__h51553[35] && + !sfdin__h51553[34] && + !sfdin__h51553[33] && + !sfdin__h51553[32] && + !sfdin__h51553[31] && + !sfdin__h51553[30] && + !sfdin__h51553[29] && + !sfdin__h51553[28] && + !sfdin__h51553[27] && + !sfdin__h51553[26] && + !sfdin__h51553[25] && + !sfdin__h51553[24] && + !sfdin__h51553[23] && + !sfdin__h51553[22] && + !sfdin__h51553[21] && + !sfdin__h51553[20] && + !sfdin__h51553[19] && + !sfdin__h51553[18] && + !sfdin__h51553[17] && + !sfdin__h51553[16] && + !sfdin__h51553[15] && + !sfdin__h51553[14] && + !sfdin__h51553[13] && + !sfdin__h51553[12] && + !sfdin__h51553[11] && + !sfdin__h51553[10] && + !sfdin__h51553[9] && + !sfdin__h51553[8] && + !sfdin__h51553[7] && + !sfdin__h51553[6] && + !sfdin__h51553[5] && + !sfdin__h51553[4] && + !sfdin__h51553[3] && + !sfdin__h51553[2] && + !sfdin__h51553[1] && + !sfdin__h51553[0]) ? + sfdin__h51553 : + _theResult___snd__h59821 ; + assign _theResult___snd__h59821 = + { IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7[55:0], + 2'd0 } ; + assign _theResult___snd__h59839 = + sfdin__h51553 << + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ; + assign _theResult___snd__h59844 = + sfdin__h51553 << + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 ; + assign _theResult___snd_fst__h59874 = + { IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8[1], + { sfdin__h59762[4:0], 52'd0 } != 57'd0 } ; + assign _theResult___snd_fst_exp__h49084 = + (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352) ? + 11'd0 : + value__h49124[10:0] ; + assign _theResult___snd_fst_exp__h49087 = + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? + _theResult___snd_fst_exp__h49084 : + 11'd2046 ; + assign _theResult___snd_fst_exp__h49111 = + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 ? + 11'd0 : + _theResult___snd_fst_exp__h49087 ; + assign _theResult___snd_fst_sfd__h49112 = + (fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? + 52'd0 : + 52'hFFFFFFFFFFFFF ; + assign _theResult___snd_snd_snd__h51398 = + (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + _theResult___snd__h52150 : + fpu_fState_S3$D_OUT[57:0] ; + assign b__h10163 = { int_div_fNext_28$D_OUT[231:174], 58'd0 } ; + assign b__h10487 = { int_div_fNext_29$D_OUT[231:174], 58'd0 } ; + assign b__h10811 = { int_div_fNext_30$D_OUT[231:174], 58'd0 } ; + assign b__h1091 = { int_div_fNext_0$D_OUT[231:174], 58'd0 } ; + assign b__h11135 = { int_div_fNext_31$D_OUT[231:174], 58'd0 } ; + assign b__h11459 = { int_div_fNext_32$D_OUT[231:174], 58'd0 } ; + assign b__h11783 = { int_div_fNext_33$D_OUT[231:174], 58'd0 } ; + assign b__h12107 = { int_div_fNext_34$D_OUT[231:174], 58'd0 } ; + assign b__h12431 = { int_div_fNext_35$D_OUT[231:174], 58'd0 } ; + assign b__h12755 = { int_div_fNext_36$D_OUT[231:174], 58'd0 } ; + assign b__h13079 = { int_div_fNext_37$D_OUT[231:174], 58'd0 } ; + assign b__h13403 = { int_div_fNext_38$D_OUT[231:174], 58'd0 } ; + assign b__h13727 = { int_div_fNext_39$D_OUT[231:174], 58'd0 } ; + assign b__h14051 = { int_div_fNext_40$D_OUT[231:174], 58'd0 } ; + assign b__h1415 = { int_div_fNext_1$D_OUT[231:174], 58'd0 } ; + assign b__h14375 = { int_div_fNext_41$D_OUT[231:174], 58'd0 } ; + assign b__h14699 = { int_div_fNext_42$D_OUT[231:174], 58'd0 } ; + assign b__h15023 = { int_div_fNext_43$D_OUT[231:174], 58'd0 } ; + assign b__h15347 = { int_div_fNext_44$D_OUT[231:174], 58'd0 } ; + assign b__h15671 = { int_div_fNext_45$D_OUT[231:174], 58'd0 } ; + assign b__h15995 = { int_div_fNext_46$D_OUT[231:174], 58'd0 } ; + assign b__h16319 = { int_div_fNext_47$D_OUT[231:174], 58'd0 } ; + assign b__h16643 = { int_div_fNext_48$D_OUT[231:174], 58'd0 } ; + assign b__h16967 = { int_div_fNext_49$D_OUT[231:174], 58'd0 } ; + assign b__h17291 = { int_div_fNext_50$D_OUT[231:174], 58'd0 } ; + assign b__h1739 = { int_div_fNext_2$D_OUT[231:174], 58'd0 } ; + assign b__h17615 = { int_div_fNext_51$D_OUT[231:174], 58'd0 } ; + assign b__h17939 = { int_div_fNext_52$D_OUT[231:174], 58'd0 } ; + assign b__h18263 = { int_div_fNext_53$D_OUT[231:174], 58'd0 } ; + assign b__h18587 = { int_div_fNext_54$D_OUT[231:174], 58'd0 } ; + assign b__h18911 = { int_div_fNext_55$D_OUT[231:174], 58'd0 } ; + assign b__h19235 = { int_div_fNext_56$D_OUT[231:174], 58'd0 } ; + assign b__h19482 = { int_div_fNext_57$D_OUT[231:174], 58'd0 } ; + assign b__h2063 = { int_div_fNext_3$D_OUT[231:174], 58'd0 } ; + assign b__h21789 = + (fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? + (fpu_fOperands_S0$D_OUT[118] ? + 6'd1 : + (fpu_fOperands_S0$D_OUT[117] ? + 6'd2 : + (fpu_fOperands_S0$D_OUT[116] ? + 6'd3 : + (fpu_fOperands_S0$D_OUT[115] ? + 6'd4 : + (fpu_fOperands_S0$D_OUT[114] ? + 6'd5 : + (fpu_fOperands_S0$D_OUT[113] ? + 6'd6 : + (fpu_fOperands_S0$D_OUT[112] ? + 6'd7 : + (fpu_fOperands_S0$D_OUT[111] ? + 6'd8 : + (fpu_fOperands_S0$D_OUT[110] ? + 6'd9 : + (fpu_fOperands_S0$D_OUT[109] ? + 6'd10 : + (fpu_fOperands_S0$D_OUT[108] ? + 6'd11 : + (fpu_fOperands_S0$D_OUT[107] ? + 6'd12 : + (fpu_fOperands_S0$D_OUT[106] ? + 6'd13 : + (fpu_fOperands_S0$D_OUT[105] ? + 6'd14 : + (fpu_fOperands_S0$D_OUT[104] ? + 6'd15 : + (fpu_fOperands_S0$D_OUT[103] ? + 6'd16 : + (fpu_fOperands_S0$D_OUT[102] ? + 6'd17 : + (fpu_fOperands_S0$D_OUT[101] ? + 6'd18 : + (fpu_fOperands_S0$D_OUT[100] ? + 6'd19 : + (fpu_fOperands_S0$D_OUT[99] ? + 6'd20 : + (fpu_fOperands_S0$D_OUT[98] ? + 6'd21 : + (fpu_fOperands_S0$D_OUT[97] ? + 6'd22 : + (fpu_fOperands_S0$D_OUT[96] ? + 6'd23 : + (fpu_fOperands_S0$D_OUT[95] ? + 6'd24 : + (fpu_fOperands_S0$D_OUT[94] ? + 6'd25 : + (fpu_fOperands_S0$D_OUT[93] ? + 6'd26 : + (fpu_fOperands_S0$D_OUT[92] ? + 6'd27 : + (fpu_fOperands_S0$D_OUT[91] ? + 6'd28 : + (fpu_fOperands_S0$D_OUT[90] ? + 6'd29 : + (fpu_fOperands_S0$D_OUT[89] ? + 6'd30 : + (fpu_fOperands_S0$D_OUT[88] ? + 6'd31 : + (fpu_fOperands_S0$D_OUT[87] ? + 6'd32 : + (fpu_fOperands_S0$D_OUT[86] ? + 6'd33 : + (fpu_fOperands_S0$D_OUT[85] ? + 6'd34 : + (fpu_fOperands_S0$D_OUT[84] ? + 6'd35 : + (fpu_fOperands_S0$D_OUT[83] ? + 6'd36 : + (fpu_fOperands_S0$D_OUT[82] ? + 6'd37 : + (fpu_fOperands_S0$D_OUT[81] ? + 6'd38 : + (fpu_fOperands_S0$D_OUT[80] ? + 6'd39 : + (fpu_fOperands_S0$D_OUT[79] ? + 6'd40 : + (fpu_fOperands_S0$D_OUT[78] ? + 6'd41 : + (fpu_fOperands_S0$D_OUT[77] ? + 6'd42 : + (fpu_fOperands_S0$D_OUT[76] ? + 6'd43 : + (fpu_fOperands_S0$D_OUT[75] ? + 6'd44 : + (fpu_fOperands_S0$D_OUT[74] ? + 6'd45 : + (fpu_fOperands_S0$D_OUT[73] ? + 6'd46 : + (fpu_fOperands_S0$D_OUT[72] ? + 6'd47 : + (fpu_fOperands_S0$D_OUT[71] ? + 6'd48 : + (fpu_fOperands_S0$D_OUT[70] ? + 6'd49 : + (fpu_fOperands_S0$D_OUT[69] ? + 6'd50 : + (fpu_fOperands_S0$D_OUT[68] ? + 6'd51 : + (fpu_fOperands_S0$D_OUT[67] ? + 6'd52 : + 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : + 6'd0 ; + assign b__h2387 = { int_div_fNext_4$D_OUT[231:174], 58'd0 } ; + assign b__h2711 = { int_div_fNext_5$D_OUT[231:174], 58'd0 } ; + assign b__h29207 = + (fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? + (fpu_fOperands_S0$D_OUT[54] ? + 6'd1 : + (fpu_fOperands_S0$D_OUT[53] ? + 6'd2 : + (fpu_fOperands_S0$D_OUT[52] ? + 6'd3 : + (fpu_fOperands_S0$D_OUT[51] ? + 6'd4 : + (fpu_fOperands_S0$D_OUT[50] ? + 6'd5 : + (fpu_fOperands_S0$D_OUT[49] ? + 6'd6 : + (fpu_fOperands_S0$D_OUT[48] ? + 6'd7 : + (fpu_fOperands_S0$D_OUT[47] ? + 6'd8 : + (fpu_fOperands_S0$D_OUT[46] ? + 6'd9 : + (fpu_fOperands_S0$D_OUT[45] ? + 6'd10 : + (fpu_fOperands_S0$D_OUT[44] ? + 6'd11 : + (fpu_fOperands_S0$D_OUT[43] ? + 6'd12 : + (fpu_fOperands_S0$D_OUT[42] ? + 6'd13 : + (fpu_fOperands_S0$D_OUT[41] ? + 6'd14 : + (fpu_fOperands_S0$D_OUT[40] ? + 6'd15 : + (fpu_fOperands_S0$D_OUT[39] ? + 6'd16 : + (fpu_fOperands_S0$D_OUT[38] ? + 6'd17 : + (fpu_fOperands_S0$D_OUT[37] ? + 6'd18 : + (fpu_fOperands_S0$D_OUT[36] ? + 6'd19 : + (fpu_fOperands_S0$D_OUT[35] ? + 6'd20 : + (fpu_fOperands_S0$D_OUT[34] ? + 6'd21 : + (fpu_fOperands_S0$D_OUT[33] ? + 6'd22 : + (fpu_fOperands_S0$D_OUT[32] ? + 6'd23 : + (fpu_fOperands_S0$D_OUT[31] ? + 6'd24 : + (fpu_fOperands_S0$D_OUT[30] ? + 6'd25 : + (fpu_fOperands_S0$D_OUT[29] ? + 6'd26 : + (fpu_fOperands_S0$D_OUT[28] ? + 6'd27 : + (fpu_fOperands_S0$D_OUT[27] ? + 6'd28 : + (fpu_fOperands_S0$D_OUT[26] ? + 6'd29 : + (fpu_fOperands_S0$D_OUT[25] ? + 6'd30 : + (fpu_fOperands_S0$D_OUT[24] ? + 6'd31 : + (fpu_fOperands_S0$D_OUT[23] ? + 6'd32 : + (fpu_fOperands_S0$D_OUT[22] ? + 6'd33 : + (fpu_fOperands_S0$D_OUT[21] ? + 6'd34 : + (fpu_fOperands_S0$D_OUT[20] ? + 6'd35 : + (fpu_fOperands_S0$D_OUT[19] ? + 6'd36 : + (fpu_fOperands_S0$D_OUT[18] ? + 6'd37 : + (fpu_fOperands_S0$D_OUT[17] ? + 6'd38 : + (fpu_fOperands_S0$D_OUT[16] ? + 6'd39 : + (fpu_fOperands_S0$D_OUT[15] ? + 6'd40 : + (fpu_fOperands_S0$D_OUT[14] ? + 6'd41 : + (fpu_fOperands_S0$D_OUT[13] ? + 6'd42 : + (fpu_fOperands_S0$D_OUT[12] ? + 6'd43 : + (fpu_fOperands_S0$D_OUT[11] ? + 6'd44 : + (fpu_fOperands_S0$D_OUT[10] ? + 6'd45 : + (fpu_fOperands_S0$D_OUT[9] ? + 6'd46 : + (fpu_fOperands_S0$D_OUT[8] ? + 6'd47 : + (fpu_fOperands_S0$D_OUT[7] ? + 6'd48 : + (fpu_fOperands_S0$D_OUT[6] ? + 6'd49 : + (fpu_fOperands_S0$D_OUT[5] ? + 6'd50 : + (fpu_fOperands_S0$D_OUT[4] ? + 6'd51 : + (fpu_fOperands_S0$D_OUT[3] ? + 6'd52 : + 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : + 6'd0 ; + assign b__h3035 = { int_div_fNext_6$D_OUT[231:174], 58'd0 } ; + assign b__h3359 = { int_div_fNext_7$D_OUT[231:174], 58'd0 } ; + assign b__h3683 = { int_div_fNext_8$D_OUT[231:174], 58'd0 } ; + assign b__h378 = { 1'd0, int_div_fRequest$D_OUT[56:0] } ; + assign b__h4007 = { int_div_fNext_9$D_OUT[231:174], 58'd0 } ; + assign b__h4331 = { int_div_fNext_10$D_OUT[231:174], 58'd0 } ; + assign b__h4655 = { int_div_fNext_11$D_OUT[231:174], 58'd0 } ; + assign b__h4979 = { int_div_fNext_12$D_OUT[231:174], 58'd0 } ; + assign b__h5303 = { int_div_fNext_13$D_OUT[231:174], 58'd0 } ; + assign b__h5627 = { int_div_fNext_14$D_OUT[231:174], 58'd0 } ; + assign b__h5951 = { int_div_fNext_15$D_OUT[231:174], 58'd0 } ; + assign b__h6275 = { int_div_fNext_16$D_OUT[231:174], 58'd0 } ; + assign b__h6599 = { int_div_fNext_17$D_OUT[231:174], 58'd0 } ; + assign b__h6923 = { int_div_fNext_18$D_OUT[231:174], 58'd0 } ; + assign b__h7247 = { int_div_fNext_19$D_OUT[231:174], 58'd0 } ; + assign b__h7571 = { int_div_fNext_20$D_OUT[231:174], 58'd0 } ; + assign b__h767 = { int_div_fFirst$D_OUT[231:174], 58'd0 } ; + assign b__h7895 = { int_div_fNext_21$D_OUT[231:174], 58'd0 } ; + assign b__h8219 = { int_div_fNext_22$D_OUT[231:174], 58'd0 } ; + assign b__h8543 = { int_div_fNext_23$D_OUT[231:174], 58'd0 } ; + assign b__h8867 = { int_div_fNext_24$D_OUT[231:174], 58'd0 } ; + assign b__h9191 = { int_div_fNext_25$D_OUT[231:174], 58'd0 } ; + assign b__h9515 = { int_div_fNext_26$D_OUT[231:174], 58'd0 } ; + assign b__h9839 = { int_div_fNext_27$D_OUT[231:174], 58'd0 } ; + assign din_inc___2_exp__h61001 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; + assign fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 = + fpu_fOperands_S0$D_OUT[129:119] - 11'd1023 ; + assign fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 = + fpu_fOperands_S0$D_OUT[65:55] - 11'd1023 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; + assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 = + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54] || + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 ; + assign fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 = + fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || + !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; + assign fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 = + fpu_fOperands_S0$D_OUT[130] == fpu_fOperands_S0$D_OUT[66] ; + assign fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780 = + { fpu_fState_S3$D_OUT[121], + IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 : + ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? + { _theResult___fst_exp__h59719, + fpu_fState_S3$D_OUT[109:58] } : + 63'h7FEFFFFFFFFFFFFF) : + fpu_fState_S3$D_OUT[120:58]) } ; + assign guard__h51381 = x__h60140 ; + assign int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 = + int_div_fNext_57$D_OUT[173:116] + + -(~int_div_fNext_57$D_OUT[173:116]) ; + assign out_exp__h60913 = + fpu_fState_S4$D_OUT[2] ? + _theResult___exp__h60910 : + fpu_fState_S4$D_OUT[64:54] ; + assign out_sfd__h60914 = + fpu_fState_S4$D_OUT[2] ? + _theResult___sfd__h60911 : + fpu_fState_S4$D_OUT[53:2] ; + assign result__h50077 = { _theResult____h50063[57:1], 1'd1 } ; + assign result__h50108 = + { 1'd0, + value__h50121[56:1], + value__h50121[0] | sfdlsb__h50103 } ; + assign result__h50258 = + (int_div_fResponse$D_OUT[113:57] == 57'd0) ? 58'd0 : 58'd1 ; + assign sfdA__h19785 = + { fpu_fOperands_S0$D_OUT[129:119] != 11'd0, + fpu_fOperands_S0$D_OUT[118:67] } ; + assign sfdA__h19789 = sfdA__h19785 << b__h21789 ; + assign sfdB__h19786 = + { fpu_fOperands_S0$D_OUT[65:55] != 11'd0, + fpu_fOperands_S0$D_OUT[54:3] } ; + assign sfdB__h19791 = sfdB__h19786 << b__h29207 ; + assign sfd__h36684 = { 1'd1, fpu_fOperands_S0$D_OUT[117:67] } ; + assign sfd__h36687 = { 1'd1, fpu_fOperands_S0$D_OUT[53:3] } ; + assign sfd__h60417 = + { 1'b0, + fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:2] } + + 54'd1 ; + assign sfdin__h51553 = + (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? + _theResult___snd_snd_snd__h51398 : + fpu_fState_S3$D_OUT[57:0] ; + assign sfdin__h59762 = + sfdin__h51553[57] ? + _theResult___snd__h59785 : + _theResult___snd__h59800 ; + assign sfdlsb__h50103 = x__h50197 != 58'd0 ; + assign theResult___fst_exp9725_MINUS_1023__q6 = + _theResult___fst_exp__h59725 - 11'd1023 ; + assign value__h19447 = + int_div_fNext_57$D_OUT[115] ? + int_div_fNext_57$D_OUT[115:0] + b__h19482 : + int_div_fNext_57$D_OUT[115:0] ; + assign value__h49124 = + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 + + 13'd1023 ; + assign value__h49179 = { 1'b0, sfdA__h19789 } ; + assign value__h49300 = + 13'd7170 - + IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ; + assign value__h50121 = + int_div_fResponse$D_OUT[113:57] >> fpu_fState_S2$D_OUT[10:0] ; + assign x__h49176 = { value__h49179, 60'd0 } ; + assign x__h49237 = { sfdB__h19791, 4'b0 } ; + assign x__h49291 = + fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 ? + 11'd0 : + _theResult___fst__h49072 ; + assign x__h50197 = { 1'd0, int_div_fResponse$D_OUT[113:57] } << x__h50204 ; + assign x__h50204 = 11'd58 - fpu_fState_S2$D_OUT[10:0] ; + assign x__h50487 = + (int_div_fResponse$D_OUT[56:0] == 57'd0) ? + _theResult____h50063 : + result__h50077 ; + assign x__h60140 = + (sfdin__h51553[57] && + IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h59874 ; + always@(fpu_fState_S4$D_OUT or out_sfd__h60914 or _theResult___sfd__h60911) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + fpu_fState_S4$D_OUT[53:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + out_sfd__h60914; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + _theResult___sfd__h60911; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___sfd__h60911) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + fpu_fState_S4$D_OUT[53:2]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + _theResult___sfd__h60911; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or + _theResult___sfd__h60911) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_sfd__h60989 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; + 3'd1: + _theResult___fst_sfd__h60989 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; + 3'd2: + _theResult___fst_sfd__h60989 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___sfd__h60911; + 3'd3: + _theResult___fst_sfd__h60989 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[53:2] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___sfd__h60911 : + fpu_fState_S4$D_OUT[53:2]); + 3'd4: _theResult___fst_sfd__h60989 = fpu_fState_S4$D_OUT[53:2]; + default: _theResult___fst_sfd__h60989 = 52'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0, 3'd1: _theResult___fst_exp__h37217 = 11'd2047; + 3'd2: + _theResult___fst_exp__h37217 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 11'd2047 : + 11'd2046; + 3'd3: + _theResult___fst_exp__h37217 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 11'd2046 : + 11'd2047; + 3'd4: _theResult___fst_exp__h37217 = 11'd2046; + default: _theResult___fst_exp__h37217 = 11'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0, 3'd1: _theResult___fst_sfd__h37218 = 52'd0; + 3'd2: + _theResult___fst_sfd__h37218 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'd0 : + 52'hFFFFFFFFFFFFF; + 3'd3: + _theResult___fst_sfd__h37218 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'hFFFFFFFFFFFFF : + 52'd0; + 3'd4: _theResult___fst_sfd__h37218 = 52'hFFFFFFFFFFFFF; + default: _theResult___fst_sfd__h37218 = 52'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0: _theResult___fst_sfd__h37707 = 52'd0; + 3'd1: _theResult___fst_sfd__h37707 = 52'd1; + 3'd2: + _theResult___fst_sfd__h37707 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'd1 : + 52'd0; + 3'd3: + _theResult___fst_sfd__h37707 = + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? + 52'd0 : + 52'd1; + default: _theResult___fst_sfd__h37707 = 52'd0; + endcase + end + always@(fpu_fOperands_S0$D_OUT or + fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) + begin + case (fpu_fOperands_S0$D_OUT[2:0]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; + default: CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = + fpu_fOperands_S0$D_OUT[2:0] == 3'd4 && + !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; + endcase + end + always@(fpu_fState_S4$D_OUT or out_exp__h60913 or _theResult___exp__h60910) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = + fpu_fState_S4$D_OUT[64:54]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = + out_exp__h60913; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = + _theResult___exp__h60910; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___exp__h60910) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = + fpu_fState_S4$D_OUT[64:54]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = + _theResult___exp__h60910; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 or + _theResult___exp__h60910) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_exp__h60988 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9; + 3'd1: + _theResult___fst_exp__h60988 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10; + 3'd2: + _theResult___fst_exp__h60988 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___exp__h60910; + 3'd3: + _theResult___fst_exp__h60988 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:54] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___exp__h60910 : + fpu_fState_S4$D_OUT[64:54]); + 3'd4: _theResult___fst_exp__h60988 = fpu_fState_S4$D_OUT[64:54]; + default: _theResult___fst_exp__h60988 = 11'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2, 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = + fpu_fState_S4$D_OUT[65]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = + fpu_fState_S4$D_OUT[68:66] == 3'd4 && + fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:2] : + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; + 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:2] : + (fpu_fState_S4$D_OUT[65] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : + fpu_fState_S4$D_OUT[64:2]); + 3'd4: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = + fpu_fState_S4$D_OUT[64:2]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = 63'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01, 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[65]; + 2'd3: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = + fpu_fState_S4$D_OUT[64:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = + fpu_fState_S4$D_OUT[2] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : + fpu_fState_S4$D_OUT[64:2]; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = 63'd0; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = + { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 }; + 3'd1: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[65:2] : + { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || + fpu_fState_S4$D_OUT[1:0] == 2'b10 || + fpu_fState_S4$D_OUT[1:0] == 2'b11) && + fpu_fState_S4$D_OUT[65], + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 }; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = + { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 }; + endcase + end + always@(fpu_fState_S3$D_OUT) + begin + case (fpu_fState_S3$D_OUT[124:122]) + 3'd0, 3'd1, 3'd2, 3'd3: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = + fpu_fState_S3$D_OUT[121]; + default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = + fpu_fState_S3$D_OUT[124:122] == 3'd4 && + fpu_fState_S3$D_OUT[121]; + endcase + end + always@(fpu_fState_S3$D_OUT) + begin + case (fpu_fState_S3$D_OUT[124:122]) + 3'd0, 3'd1: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + 63'h7FF0000000000000; + 3'd2: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + fpu_fState_S3$D_OUT[121] ? + 63'h7FEFFFFFFFFFFFFF : + 63'h7FF0000000000000; + 3'd3: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + fpu_fState_S3$D_OUT[121] ? + 63'h7FF0000000000000 : + 63'h7FEFFFFFFFFFFFFF; + 3'd4: + CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = + 63'h7FEFFFFFFFFFFFFF; + default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = 63'd0; + endcase + end endmodule // mkDoubleDiv diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v index a75a034..de193e3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -7,15 +7,16 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 -// RDY_response_get O 1 +// response_get O 69 reg +// RDY_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// request_put I 196 +// request_put I 196 reg // EN_request_put I 1 // EN_response_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// EN_response_get -> RDY_request_put // // @@ -59,44 +60,2035 @@ module mkDoubleFMA(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu - wire [195 : 0] fpu$request_put; - wire [68 : 0] fpu$response_get; - wire fpu$EN_request_put, - fpu$EN_response_get, - fpu$RDY_request_put, - fpu$RDY_response_get; + // ports of submodule fpu_fOperand_S0 + wire [195 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; + wire fpu_fOperand_S0$CLR, + fpu_fOperand_S0$DEQ, + fpu_fOperand_S0$EMPTY_N, + fpu_fOperand_S0$ENQ, + fpu_fOperand_S0$FULL_N; + + // ports of submodule fpu_fProd_S2 + wire [105 : 0] fpu_fProd_S2$D_IN, fpu_fProd_S2$D_OUT; + wire fpu_fProd_S2$CLR, + fpu_fProd_S2$DEQ, + fpu_fProd_S2$EMPTY_N, + fpu_fProd_S2$ENQ, + fpu_fProd_S2$FULL_N; + + // ports of submodule fpu_fProd_S3 + wire [105 : 0] fpu_fProd_S3$D_IN, fpu_fProd_S3$D_OUT; + wire fpu_fProd_S3$CLR, + fpu_fProd_S3$DEQ, + fpu_fProd_S3$EMPTY_N, + fpu_fProd_S3$ENQ, + fpu_fProd_S3$FULL_N; + + // ports of submodule fpu_fResult_S9 + wire [68 : 0] fpu_fResult_S9$D_IN, fpu_fResult_S9$D_OUT; + wire fpu_fResult_S9$CLR, + fpu_fResult_S9$DEQ, + fpu_fResult_S9$EMPTY_N, + fpu_fResult_S9$ENQ, + fpu_fResult_S9$FULL_N; + + // ports of submodule fpu_fState_S1 + wire [257 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; + wire fpu_fState_S1$CLR, + fpu_fState_S1$DEQ, + fpu_fState_S1$EMPTY_N, + fpu_fState_S1$ENQ, + fpu_fState_S1$FULL_N; + + // ports of submodule fpu_fState_S2 + wire [151 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; + wire fpu_fState_S2$CLR, + fpu_fState_S2$DEQ, + fpu_fState_S2$EMPTY_N, + fpu_fState_S2$ENQ, + fpu_fState_S2$FULL_N; + + // ports of submodule fpu_fState_S3 + wire [151 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; + wire fpu_fState_S3$CLR, + fpu_fState_S3$DEQ, + fpu_fState_S3$EMPTY_N, + fpu_fState_S3$ENQ, + fpu_fState_S3$FULL_N; + + // ports of submodule fpu_fState_S4 + wire [203 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; + wire fpu_fState_S4$CLR, + fpu_fState_S4$DEQ, + fpu_fState_S4$EMPTY_N, + fpu_fState_S4$ENQ, + fpu_fState_S4$FULL_N; + + // ports of submodule fpu_fState_S5 + wire [215 : 0] fpu_fState_S5$D_IN, fpu_fState_S5$D_OUT; + wire fpu_fState_S5$CLR, + fpu_fState_S5$DEQ, + fpu_fState_S5$EMPTY_N, + fpu_fState_S5$ENQ, + fpu_fState_S5$FULL_N; + + // ports of submodule fpu_fState_S6 + wire [202 : 0] fpu_fState_S6$D_IN, fpu_fState_S6$D_OUT; + wire fpu_fState_S6$CLR, + fpu_fState_S6$DEQ, + fpu_fState_S6$EMPTY_N, + fpu_fState_S6$ENQ, + fpu_fState_S6$FULL_N; + + // ports of submodule fpu_fState_S7 + wire [202 : 0] fpu_fState_S7$D_IN, fpu_fState_S7$D_OUT; + wire fpu_fState_S7$CLR, + fpu_fState_S7$DEQ, + fpu_fState_S7$EMPTY_N, + fpu_fState_S7$ENQ, + fpu_fState_S7$FULL_N; + + // ports of submodule fpu_fState_S8 + wire [140 : 0] fpu_fState_S8$D_IN, fpu_fState_S8$D_OUT; + wire fpu_fState_S8$CLR, + fpu_fState_S8$DEQ, + fpu_fState_S8$EMPTY_N, + fpu_fState_S8$ENQ, + fpu_fState_S8$FULL_N; // rule scheduling signals - wire CAN_FIRE_request_put, + wire CAN_FIRE_RL_fpu_s1_stage, + CAN_FIRE_RL_fpu_s2_stage, + CAN_FIRE_RL_fpu_s3_stage, + CAN_FIRE_RL_fpu_s4_stage, + CAN_FIRE_RL_fpu_s5_stage, + CAN_FIRE_RL_fpu_s6_stage, + CAN_FIRE_RL_fpu_s7_stage, + CAN_FIRE_RL_fpu_s8_stage, + CAN_FIRE_RL_fpu_s9_stage, + CAN_FIRE_request_put, CAN_FIRE_response_get, + WILL_FIRE_RL_fpu_s1_stage, + WILL_FIRE_RL_fpu_s2_stage, + WILL_FIRE_RL_fpu_s3_stage, + WILL_FIRE_RL_fpu_s4_stage, + WILL_FIRE_RL_fpu_s5_stage, + WILL_FIRE_RL_fpu_s6_stage, + WILL_FIRE_RL_fpu_s7_stage, + WILL_FIRE_RL_fpu_s8_stage, + WILL_FIRE_RL_fpu_s9_stage, WILL_FIRE_request_put, WILL_FIRE_response_get; + // remaining internal signals + reg [62 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17, + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18, + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19; + reg [51 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1, + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2, + _theResult___fst_sfd__h46438; + reg [10 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11, + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12, + _theResult___fst_exp__h46437; + reg CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14; + wire [139 : 0] IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796; + wire [118 : 0] IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160; + wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4, + _theResult___fst__h20642, + _theResult___snd__h34781, + _theResult___snd__h34795, + _theResult___snd__h34797, + _theResult___snd__h34809, + _theResult___snd__h34815, + _theResult___snd__h34833, + _theResult___snd__h34838, + fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213, + sfdBC__h19477, + sfdin__h34758, + x__h20711; + wire [68 : 0] IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282; + wire [63 : 0] IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137, + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139; + wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735, + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132, + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737; + wire [56 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9, + _theResult___snd__h45207, + _theResult___snd__h45221, + _theResult___snd__h45223, + _theResult___snd__h45235, + _theResult___snd__h45241, + _theResult___snd__h45259, + _theResult___snd__h45264, + fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816, + guard__h36182, + result__h36187, + sfdA__h35392, + sfdBC__h35393, + sfd__h36934, + sfdin__h45184, + x__h35755, + x__h35759, + x__h36174, + x__h36686, + x__h36695; + wire [53 : 0] sfd__h45855; + wire [52 : 0] x__h18058, x__h18070; + wire [51 : 0] _theResult___fst_sfd__h396, + _theResult___sfd__h46360, + out_sfd__h46363, + sfd__h3208, + sfd__h3211, + sfd__h3214; + wire [12 : 0] IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208, + value__h34698, + value__h45122, + x__h20744, + x__h36286; + wire [11 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663, + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104, + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869; + wire [10 : 0] IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212, + _theResult___exp__h46359, + _theResult___fst_exp__h34764, + _theResult___fst_exp__h34767, + _theResult___fst_exp__h34786, + _theResult___fst_exp__h34801, + _theResult___fst_exp__h34840, + _theResult___fst_exp__h34846, + _theResult___fst_exp__h34849, + _theResult___fst_exp__h45190, + _theResult___fst_exp__h45193, + _theResult___fst_exp__h45212, + _theResult___fst_exp__h45227, + _theResult___fst_exp__h45266, + _theResult___fst_exp__h45272, + _theResult___fst_exp__h45275, + din_exp4681_MINUS_1023__q3, + din_exp__h34681, + din_inc___2_exp__h46444, + fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16, + fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7, + fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6, + out_exp__h46362, + value5122_BITS_10_TO_0_MINUS_1023__q8, + x__h327; + wire [6 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661; + wire [5 : 0] IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102; + wire [4 : 0] IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702, + fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, + fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244; + wire [2 : 0] NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724; + wire [1 : 0] IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5, + IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10, + _theResult___snd_fst__h34866, + _theResult___snd_fst__h45292, + _theResult___snd_snd__h35186, + _theResult___snd_snd_snd__h35184, + guardBC__h19481, + guard__h36938, + x__h35221, + x__h45575; + wire IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123, + IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, + IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717, + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722, + IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, + NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147, + NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, + NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785, + _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664, + _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105, + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209, + fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127, + fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58, + fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56, + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203, + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205, + sfdlsb__h20640; + // action method request_put - assign RDY_request_put = fpu$RDY_request_put ; - assign CAN_FIRE_request_put = fpu$RDY_request_put ; + assign RDY_request_put = fpu_fOperand_S0$FULL_N ; + assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu$response_get ; - assign RDY_response_get = fpu$RDY_response_get ; - assign CAN_FIRE_response_get = fpu$RDY_response_get ; + assign response_get = fpu_fResult_S9$D_OUT ; + assign RDY_response_get = fpu_fResult_S9$EMPTY_N ; + assign CAN_FIRE_response_get = fpu_fResult_S9$EMPTY_N ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu - mkXilinxFpFma fpu(.CLK(CLK), - .RST_N(RST_N), - .request_put(fpu$request_put), - .EN_request_put(fpu$EN_request_put), - .EN_response_get(fpu$EN_response_get), - .RDY_request_put(fpu$RDY_request_put), - .response_get(fpu$response_get), - .RDY_response_get(fpu$RDY_response_get)); + // submodule fpu_fOperand_S0 + FIFOL1 #(.width(32'd196)) fpu_fOperand_S0(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fOperand_S0$D_IN), + .ENQ(fpu_fOperand_S0$ENQ), + .DEQ(fpu_fOperand_S0$DEQ), + .CLR(fpu_fOperand_S0$CLR), + .D_OUT(fpu_fOperand_S0$D_OUT), + .FULL_N(fpu_fOperand_S0$FULL_N), + .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); - // submodule fpu - assign fpu$request_put = request_put ; - assign fpu$EN_request_put = EN_request_put ; - assign fpu$EN_response_get = EN_response_get ; + // submodule fpu_fProd_S2 + FIFOL1 #(.width(32'd106)) fpu_fProd_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fProd_S2$D_IN), + .ENQ(fpu_fProd_S2$ENQ), + .DEQ(fpu_fProd_S2$DEQ), + .CLR(fpu_fProd_S2$CLR), + .D_OUT(fpu_fProd_S2$D_OUT), + .FULL_N(fpu_fProd_S2$FULL_N), + .EMPTY_N(fpu_fProd_S2$EMPTY_N)); + + // submodule fpu_fProd_S3 + FIFOL1 #(.width(32'd106)) fpu_fProd_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fProd_S3$D_IN), + .ENQ(fpu_fProd_S3$ENQ), + .DEQ(fpu_fProd_S3$DEQ), + .CLR(fpu_fProd_S3$CLR), + .D_OUT(fpu_fProd_S3$D_OUT), + .FULL_N(fpu_fProd_S3$FULL_N), + .EMPTY_N(fpu_fProd_S3$EMPTY_N)); + + // submodule fpu_fResult_S9 + FIFOL1 #(.width(32'd69)) fpu_fResult_S9(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fResult_S9$D_IN), + .ENQ(fpu_fResult_S9$ENQ), + .DEQ(fpu_fResult_S9$DEQ), + .CLR(fpu_fResult_S9$CLR), + .D_OUT(fpu_fResult_S9$D_OUT), + .FULL_N(fpu_fResult_S9$FULL_N), + .EMPTY_N(fpu_fResult_S9$EMPTY_N)); + + // submodule fpu_fState_S1 + FIFOL1 #(.width(32'd258)) fpu_fState_S1(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S1$D_IN), + .ENQ(fpu_fState_S1$ENQ), + .DEQ(fpu_fState_S1$DEQ), + .CLR(fpu_fState_S1$CLR), + .D_OUT(fpu_fState_S1$D_OUT), + .FULL_N(fpu_fState_S1$FULL_N), + .EMPTY_N(fpu_fState_S1$EMPTY_N)); + + // submodule fpu_fState_S2 + FIFOL1 #(.width(32'd152)) fpu_fState_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S2$D_IN), + .ENQ(fpu_fState_S2$ENQ), + .DEQ(fpu_fState_S2$DEQ), + .CLR(fpu_fState_S2$CLR), + .D_OUT(fpu_fState_S2$D_OUT), + .FULL_N(fpu_fState_S2$FULL_N), + .EMPTY_N(fpu_fState_S2$EMPTY_N)); + + // submodule fpu_fState_S3 + FIFOL1 #(.width(32'd152)) fpu_fState_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S3$D_IN), + .ENQ(fpu_fState_S3$ENQ), + .DEQ(fpu_fState_S3$DEQ), + .CLR(fpu_fState_S3$CLR), + .D_OUT(fpu_fState_S3$D_OUT), + .FULL_N(fpu_fState_S3$FULL_N), + .EMPTY_N(fpu_fState_S3$EMPTY_N)); + + // submodule fpu_fState_S4 + FIFOL1 #(.width(32'd204)) fpu_fState_S4(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S4$D_IN), + .ENQ(fpu_fState_S4$ENQ), + .DEQ(fpu_fState_S4$DEQ), + .CLR(fpu_fState_S4$CLR), + .D_OUT(fpu_fState_S4$D_OUT), + .FULL_N(fpu_fState_S4$FULL_N), + .EMPTY_N(fpu_fState_S4$EMPTY_N)); + + // submodule fpu_fState_S5 + FIFOL1 #(.width(32'd216)) fpu_fState_S5(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S5$D_IN), + .ENQ(fpu_fState_S5$ENQ), + .DEQ(fpu_fState_S5$DEQ), + .CLR(fpu_fState_S5$CLR), + .D_OUT(fpu_fState_S5$D_OUT), + .FULL_N(fpu_fState_S5$FULL_N), + .EMPTY_N(fpu_fState_S5$EMPTY_N)); + + // submodule fpu_fState_S6 + FIFOL1 #(.width(32'd203)) fpu_fState_S6(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S6$D_IN), + .ENQ(fpu_fState_S6$ENQ), + .DEQ(fpu_fState_S6$DEQ), + .CLR(fpu_fState_S6$CLR), + .D_OUT(fpu_fState_S6$D_OUT), + .FULL_N(fpu_fState_S6$FULL_N), + .EMPTY_N(fpu_fState_S6$EMPTY_N)); + + // submodule fpu_fState_S7 + FIFOL1 #(.width(32'd203)) fpu_fState_S7(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S7$D_IN), + .ENQ(fpu_fState_S7$ENQ), + .DEQ(fpu_fState_S7$DEQ), + .CLR(fpu_fState_S7$CLR), + .D_OUT(fpu_fState_S7$D_OUT), + .FULL_N(fpu_fState_S7$FULL_N), + .EMPTY_N(fpu_fState_S7$EMPTY_N)); + + // submodule fpu_fState_S8 + FIFOL1 #(.width(32'd141)) fpu_fState_S8(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S8$D_IN), + .ENQ(fpu_fState_S8$ENQ), + .DEQ(fpu_fState_S8$DEQ), + .CLR(fpu_fState_S8$CLR), + .D_OUT(fpu_fState_S8$D_OUT), + .FULL_N(fpu_fState_S8$FULL_N), + .EMPTY_N(fpu_fState_S8$EMPTY_N)); + + // rule RL_fpu_s9_stage + assign CAN_FIRE_RL_fpu_s9_stage = + fpu_fState_S8$EMPTY_N && fpu_fResult_S9$FULL_N ; + assign WILL_FIRE_RL_fpu_s9_stage = CAN_FIRE_RL_fpu_s9_stage ; + + // rule RL_fpu_s8_stage + assign CAN_FIRE_RL_fpu_s8_stage = + fpu_fState_S7$EMPTY_N && fpu_fState_S8$FULL_N ; + assign WILL_FIRE_RL_fpu_s8_stage = CAN_FIRE_RL_fpu_s8_stage ; + + // rule RL_fpu_s7_stage + assign CAN_FIRE_RL_fpu_s7_stage = + fpu_fState_S6$EMPTY_N && fpu_fState_S7$FULL_N ; + assign WILL_FIRE_RL_fpu_s7_stage = CAN_FIRE_RL_fpu_s7_stage ; + + // rule RL_fpu_s6_stage + assign CAN_FIRE_RL_fpu_s6_stage = + fpu_fState_S5$EMPTY_N && fpu_fState_S6$FULL_N ; + assign WILL_FIRE_RL_fpu_s6_stage = CAN_FIRE_RL_fpu_s6_stage ; + + // rule RL_fpu_s5_stage + assign CAN_FIRE_RL_fpu_s5_stage = + fpu_fState_S4$EMPTY_N && fpu_fState_S5$FULL_N ; + assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; + + // rule RL_fpu_s4_stage + assign CAN_FIRE_RL_fpu_s4_stage = + fpu_fState_S3$EMPTY_N && fpu_fProd_S3$EMPTY_N && + fpu_fState_S4$FULL_N ; + assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; + + // rule RL_fpu_s3_stage + assign CAN_FIRE_RL_fpu_s3_stage = + fpu_fState_S2$EMPTY_N && fpu_fProd_S2$EMPTY_N && + fpu_fProd_S3$FULL_N && + fpu_fState_S3$FULL_N ; + assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; + + // rule RL_fpu_s2_stage + assign CAN_FIRE_RL_fpu_s2_stage = + fpu_fState_S1$EMPTY_N && fpu_fProd_S2$FULL_N && + fpu_fState_S2$FULL_N ; + assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; + + // rule RL_fpu_s1_stage + assign CAN_FIRE_RL_fpu_s1_stage = + fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; + assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; + + // submodule fpu_fOperand_S0 + assign fpu_fOperand_S0$D_IN = request_put ; + assign fpu_fOperand_S0$ENQ = EN_request_put ; + assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fOperand_S0$CLR = 1'b0 ; + + // submodule fpu_fProd_S2 + assign fpu_fProd_S2$D_IN = + fpu_fState_S1$D_OUT[105:53] * fpu_fState_S1$D_OUT[52:0] ; + assign fpu_fProd_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fProd_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fProd_S2$CLR = 1'b0 ; + + // submodule fpu_fProd_S3 + assign fpu_fProd_S3$D_IN = fpu_fProd_S2$D_OUT ; + assign fpu_fProd_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fProd_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fProd_S3$CLR = 1'b0 ; + + // submodule fpu_fResult_S9 + assign fpu_fResult_S9$D_IN = + fpu_fState_S8$D_OUT[140] ? + fpu_fState_S8$D_OUT[139:71] : + IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 ; + assign fpu_fResult_S9$ENQ = CAN_FIRE_RL_fpu_s9_stage ; + assign fpu_fResult_S9$DEQ = EN_response_get ; + assign fpu_fResult_S9$CLR = 1'b0 ; + + // submodule fpu_fState_S1 + assign fpu_fState_S1$D_IN = + { x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && + !_theResult___fst_sfd__h396[51] || + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperand_S0$D_OUT[118] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54] || + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, + 4'd0, + fpu_fOperand_S0$D_OUT[2:0], + fpu_fOperand_S0$D_OUT[195], + fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 } ; + assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S1$CLR = 1'b0 ; + + // submodule fpu_fState_S2 + assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[257:106] ; + assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S2$CLR = 1'b0 ; + + // submodule fpu_fState_S3 + assign fpu_fState_S3$D_IN = fpu_fState_S2$D_OUT ; + assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S3$CLR = 1'b0 ; + + // submodule fpu_fState_S4 + assign fpu_fState_S4$D_IN = + { fpu_fState_S3$D_OUT[151:87], + IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, + fpu_fState_S3$D_OUT[81:14], + !fpu_fState_S3$D_OUT[151] && fpu_fState_S3$D_OUT[13], + fpu_fState_S3$D_OUT[151] ? + 63'd0 : + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737, + x__h35221 } ; + assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S4$CLR = 1'b0 ; + + // submodule fpu_fState_S5 + assign fpu_fState_S5$D_IN = + { fpu_fState_S4$D_OUT[203:130], + fpu_fState_S4$D_OUT[129] != fpu_fState_S4$D_OUT[65], + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + fpu_fState_S4$D_OUT[65] : + fpu_fState_S4$D_OUT[129], + IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 } ; + assign fpu_fState_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S5$DEQ = CAN_FIRE_RL_fpu_s6_stage ; + assign fpu_fState_S5$CLR = 1'b0 ; + + // submodule fpu_fState_S6 + assign fpu_fState_S6$D_IN = + { fpu_fState_S5$D_OUT[215:127], + fpu_fState_S5$D_OUT[113:57], + x__h36174 } ; + assign fpu_fState_S6$ENQ = CAN_FIRE_RL_fpu_s6_stage ; + assign fpu_fState_S6$DEQ = CAN_FIRE_RL_fpu_s7_stage ; + assign fpu_fState_S6$CLR = 1'b0 ; + + // submodule fpu_fState_S7 + assign fpu_fState_S7$D_IN = + { fpu_fState_S6$D_OUT[202:114], x__h36686, x__h36695 } ; + assign fpu_fState_S7$ENQ = CAN_FIRE_RL_fpu_s7_stage ; + assign fpu_fState_S7$DEQ = CAN_FIRE_RL_fpu_s8_stage ; + assign fpu_fState_S7$CLR = 1'b0 ; + + // submodule fpu_fState_S8 + assign fpu_fState_S8$D_IN = + { fpu_fState_S7$D_OUT[202:138], + fpu_fState_S7$D_OUT[202] ? + fpu_fState_S7$D_OUT[137:133] : + fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, + fpu_fState_S7$D_OUT[132:129], + !fpu_fState_S7$D_OUT[202] && fpu_fState_S7$D_OUT[127], + fpu_fState_S7$D_OUT[202] ? + 63'd0 : + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, + x__h45575, + fpu_fState_S7$D_OUT[128] } ; + assign fpu_fState_S8$ENQ = CAN_FIRE_RL_fpu_s8_stage ; + assign fpu_fState_S8$DEQ = CAN_FIRE_RL_fpu_s9_stage ; + assign fpu_fState_S8$CLR = 1'b0 ; + + // remaining internal signals + assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4 = + _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 ? + _theResult___snd__h34838 : + _theResult___snd__h34833 ; + assign IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9 = + _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 ? + _theResult___snd__h45264 : + _theResult___snd__h45259 ; + assign IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 = + sfd__h45855[53] ? + ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? + 63'h7FF0000000000000 : + { din_inc___2_exp__h46444, sfd__h45855[52:1] }) : + { IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, + sfd__h45855[51:0] } ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 = + (din_exp__h34681 == 11'd0) ? + 12'd3074 : + { din_exp4681_MINUS_1023__q3[10], + din_exp4681_MINUS_1023__q3 } ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 = + (sfdBC__h19477[105] ? + 7'd0 : + (sfdBC__h19477[104] ? + 7'd1 : + (sfdBC__h19477[103] ? + 7'd2 : + (sfdBC__h19477[102] ? + 7'd3 : + (sfdBC__h19477[101] ? + 7'd4 : + (sfdBC__h19477[100] ? + 7'd5 : + (sfdBC__h19477[99] ? + 7'd6 : + (sfdBC__h19477[98] ? + 7'd7 : + (sfdBC__h19477[97] ? + 7'd8 : + (sfdBC__h19477[96] ? + 7'd9 : + (sfdBC__h19477[95] ? + 7'd10 : + (sfdBC__h19477[94] ? + 7'd11 : + (sfdBC__h19477[93] ? + 7'd12 : + (sfdBC__h19477[92] ? + 7'd13 : + (sfdBC__h19477[91] ? + 7'd14 : + (sfdBC__h19477[90] ? + 7'd15 : + (sfdBC__h19477[89] ? + 7'd16 : + (sfdBC__h19477[88] ? + 7'd17 : + (sfdBC__h19477[87] ? + 7'd18 : + (sfdBC__h19477[86] ? + 7'd19 : + (sfdBC__h19477[85] ? + 7'd20 : + (sfdBC__h19477[84] ? + 7'd21 : + (sfdBC__h19477[83] ? + 7'd22 : + (sfdBC__h19477[82] ? + 7'd23 : + (sfdBC__h19477[81] ? + 7'd24 : + (sfdBC__h19477[80] ? + 7'd25 : + (sfdBC__h19477[79] ? + 7'd26 : + (sfdBC__h19477[78] ? + 7'd27 : + (sfdBC__h19477[77] ? + 7'd28 : + (sfdBC__h19477[76] ? + 7'd29 : + (sfdBC__h19477[75] ? + 7'd30 : + (sfdBC__h19477[74] ? + 7'd31 : + (sfdBC__h19477[73] ? + 7'd32 : + (sfdBC__h19477[72] ? + 7'd33 : + (sfdBC__h19477[71] ? + 7'd34 : + (sfdBC__h19477[70] ? + 7'd35 : + (sfdBC__h19477[69] ? + 7'd36 : + (sfdBC__h19477[68] ? + 7'd37 : + (sfdBC__h19477[67] ? + 7'd38 : + (sfdBC__h19477[66] ? + 7'd39 : + (sfdBC__h19477[65] ? + 7'd40 : + (sfdBC__h19477[64] ? + 7'd41 : + (sfdBC__h19477[63] ? + 7'd42 : + (sfdBC__h19477[62] ? + 7'd43 : + (sfdBC__h19477[61] ? + 7'd44 : + (sfdBC__h19477[60] ? + 7'd45 : + (sfdBC__h19477[59] ? + 7'd46 : + (sfdBC__h19477[58] ? + 7'd47 : + (sfdBC__h19477[57] ? + 7'd48 : + (sfdBC__h19477[56] ? + 7'd49 : + (sfdBC__h19477[55] ? + 7'd50 : + (sfdBC__h19477[54] ? + 7'd51 : + (sfdBC__h19477[53] ? + 7'd52 : + (sfdBC__h19477[52] ? + 7'd53 : + (sfdBC__h19477[51] ? + 7'd54 : + (sfdBC__h19477[50] ? + 7'd55 : + (sfdBC__h19477[49] ? + 7'd56 : + (sfdBC__h19477[48] ? + 7'd57 : + (sfdBC__h19477[47] ? + 7'd58 : + (sfdBC__h19477[46] ? + 7'd59 : + (sfdBC__h19477[45] ? + 7'd60 : + (sfdBC__h19477[44] ? + 7'd61 : + (sfdBC__h19477[43] ? + 7'd62 : + (sfdBC__h19477[42] ? + 7'd63 : + (sfdBC__h19477[41] ? + 7'd64 : + (sfdBC__h19477[40] ? + 7'd65 : + (sfdBC__h19477[39] ? + 7'd66 : + (sfdBC__h19477[38] ? + 7'd67 : + (sfdBC__h19477[37] ? + 7'd68 : + (sfdBC__h19477[36] ? + 7'd69 : + (sfdBC__h19477[35] ? + 7'd70 : + (sfdBC__h19477[34] ? + 7'd71 : + (sfdBC__h19477[33] ? + 7'd72 : + (sfdBC__h19477[32] ? + 7'd73 : + (sfdBC__h19477[31] ? + 7'd74 : + (sfdBC__h19477[30] ? + 7'd75 : + (sfdBC__h19477[29] ? + 7'd76 : + (sfdBC__h19477[28] ? + 7'd77 : + (sfdBC__h19477[27] ? + 7'd78 : + (sfdBC__h19477[26] ? + 7'd79 : + (sfdBC__h19477[25] ? + 7'd80 : + (sfdBC__h19477[24] ? + 7'd81 : + (sfdBC__h19477[23] ? + 7'd82 : + (sfdBC__h19477[22] ? + 7'd83 : + (sfdBC__h19477[21] ? + 7'd84 : + (sfdBC__h19477[20] ? + 7'd85 : + (sfdBC__h19477[19] ? + 7'd86 : + (sfdBC__h19477[18] ? + 7'd87 : + (sfdBC__h19477[17] ? + 7'd88 : + (sfdBC__h19477[16] ? + 7'd89 : + (sfdBC__h19477[15] ? + 7'd90 : + (sfdBC__h19477[14] ? + 7'd91 : + (sfdBC__h19477[13] ? + 7'd92 : + (sfdBC__h19477[12] ? + 7'd93 : + (sfdBC__h19477[11] ? + 7'd94 : + (sfdBC__h19477[10] ? + 7'd95 : + (sfdBC__h19477[9] ? + 7'd96 : + (sfdBC__h19477[8] ? + 7'd97 : + (sfdBC__h19477[7] ? + 7'd98 : + (sfdBC__h19477[6] ? + 7'd99 : + (sfdBC__h19477[5] ? + 7'd100 : + (sfdBC__h19477[4] ? + 7'd101 : + (sfdBC__h19477[3] ? + 7'd102 : + (sfdBC__h19477[2] ? + 7'd103 : + (sfdBC__h19477[1] ? + 7'd104 : + (sfdBC__h19477[0] ? + 7'd105 : + 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 7'd1 ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 = + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 - + 12'd3074 ; + assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735 = + (sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h34764, sfdin__h34758[105:54] } ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? + fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194] : + ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 : + fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 : + ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? + 63'h7FF0000000000000 : + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112) ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51]) ? + { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 } : + ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118]) ? + fpu_fOperand_S0$D_OUT[130:67] : + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54]) ? + fpu_fOperand_S0$D_OUT[66:3] : + { NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 })) ; + assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140 = + (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && + !_theResult___fst_sfd__h396[51]) ? + { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], + x__h327, + sfd__h3208 } : + IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 ; + assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 = + (sfd__h36934[56] ? + 6'd0 : + (sfd__h36934[55] ? + 6'd1 : + (sfd__h36934[54] ? + 6'd2 : + (sfd__h36934[53] ? + 6'd3 : + (sfd__h36934[52] ? + 6'd4 : + (sfd__h36934[51] ? + 6'd5 : + (sfd__h36934[50] ? + 6'd6 : + (sfd__h36934[49] ? + 6'd7 : + (sfd__h36934[48] ? + 6'd8 : + (sfd__h36934[47] ? + 6'd9 : + (sfd__h36934[46] ? + 6'd10 : + (sfd__h36934[45] ? + 6'd11 : + (sfd__h36934[44] ? + 6'd12 : + (sfd__h36934[43] ? + 6'd13 : + (sfd__h36934[42] ? + 6'd14 : + (sfd__h36934[41] ? + 6'd15 : + (sfd__h36934[40] ? + 6'd16 : + (sfd__h36934[39] ? + 6'd17 : + (sfd__h36934[38] ? + 6'd18 : + (sfd__h36934[37] ? + 6'd19 : + (sfd__h36934[36] ? + 6'd20 : + (sfd__h36934[35] ? + 6'd21 : + (sfd__h36934[34] ? + 6'd22 : + (sfd__h36934[33] ? + 6'd23 : + (sfd__h36934[32] ? + 6'd24 : + (sfd__h36934[31] ? + 6'd25 : + (sfd__h36934[30] ? + 6'd26 : + (sfd__h36934[29] ? + 6'd27 : + (sfd__h36934[28] ? + 6'd28 : + (sfd__h36934[27] ? + 6'd29 : + (sfd__h36934[26] ? + 6'd30 : + (sfd__h36934[25] ? + 6'd31 : + (sfd__h36934[24] ? + 6'd32 : + (sfd__h36934[23] ? + 6'd33 : + (sfd__h36934[22] ? + 6'd34 : + (sfd__h36934[21] ? + 6'd35 : + (sfd__h36934[20] ? + 6'd36 : + (sfd__h36934[19] ? + 6'd37 : + (sfd__h36934[18] ? + 6'd38 : + (sfd__h36934[17] ? + 6'd39 : + (sfd__h36934[16] ? + 6'd40 : + (sfd__h36934[15] ? + 6'd41 : + (sfd__h36934[14] ? + 6'd42 : + (sfd__h36934[13] ? + 6'd43 : + (sfd__h36934[12] ? + 6'd44 : + (sfd__h36934[11] ? + 6'd45 : + (sfd__h36934[10] ? + 6'd46 : + (sfd__h36934[9] ? + 6'd47 : + (sfd__h36934[8] ? + 6'd48 : + (sfd__h36934[7] ? + 6'd49 : + (sfd__h36934[6] ? + 6'd50 : + (sfd__h36934[5] ? + 6'd51 : + (sfd__h36934[4] ? + 6'd52 : + (sfd__h36934[3] ? + 6'd53 : + (sfd__h36934[2] ? + 6'd54 : + (sfd__h36934[1] ? + 6'd55 : + (sfd__h36934[0] ? + 6'd56 : + 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 6'd1 ; + assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153 = + (sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h45190, sfdin__h45184[56:5] } ; + assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704 = + (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? + fpu_fState_S3$D_OUT[86] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[4] ; + assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707 = + (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? + fpu_fState_S3$D_OUT[85] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[3] ; + assign IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 = + { NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 : + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 - + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 : + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 - + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, + x__h35755, + x__h35759 } ; + assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 = + (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && + !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ? + 63'h7FF8000000000000 : + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 ; + assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 = + (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperand_S0$D_OUT[118]) ? + { fpu_fOperand_S0$D_OUT[130:119], sfd__h3211 } : + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54]) ? + { fpu_fOperand_S0$D_OUT[66:55], sfd__h3214 } : + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137) ; + assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 = + { ((fpu_fOperand_S0$D_OUT[129:119] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15[10]}}, + fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 }) + + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16[10]}}, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 }), + x__h18058, + x__h18070 } ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 = + fpu_fOperand_S0$D_OUT[195] ? + fpu_fOperand_S0$D_OUT[193:131] : + 63'd0 ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 = + x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 && + (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148 = + x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && + !_theResult___fst_sfd__h396[51] || + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && + !fpu_fOperand_S0$D_OUT[118] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54] || + NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 ; + assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62 = + x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51] || + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54] || + x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 || + fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 ; + assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? + (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + 63'd0 : + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735) : + 63'h7FEFFFFFFFFFFFFF ; + assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[83] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[1] ; + assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[82] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[0] ; + assign IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726 = + fpu_fState_S3$D_OUT[151] ? + fpu_fState_S3$D_OUT[86:82] : + { IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, + IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, + NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 } ; + assign IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 = + (fpu_fState_S4$D_OUT[128:118] == 11'd0) ? + 13'd7170 : + { {2{fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7[10]}}, + fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 } ; + assign IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 = + (fpu_fState_S4$D_OUT[64:54] == 11'd0) ? + 13'd7170 : + { {2{fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6[10]}}, + fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 } ; + assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 = + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 - + 12'd3074 ; + assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 = + (value__h45122[10:0] == 11'd0) ? + 12'd3074 : + { value5122_BITS_10_TO_0_MINUS_1023__q8[10], + value5122_BITS_10_TO_0_MINUS_1023__q8 } ; + assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 = + (fpu_fState_S8$D_OUT[65:55] == 11'd0 && + sfd__h45855[53:52] == 2'b01) ? + 11'd1 : + fpu_fState_S8$D_OUT[65:55] ; + assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 = + (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[65:55] : + _theResult___fst_exp__h46437 ; + assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261 = + (fpu_fState_S8$D_OUT[67] && + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == + 11'd0 && + ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[54:3] : + _theResult___fst_sfd__h46438) == + 52'd0 && + !fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244[0] && + fpu_fState_S8$D_OUT[0]) ? + fpu_fState_S8$D_OUT[70:68] == 3'd3 : + ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[66] : + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14) ; + assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 = + { IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, + (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[65:3] : + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19, + fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 } ; + assign IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5 = + sfdin__h34758[53] ? 2'd2 : 2'd0 ; + assign IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10 = + sfdin__h45184[4] ? 2'd2 : 2'd0 ; + assign NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 = + (x__h327 != 11'd2047 || !_theResult___fst_sfd__h396[51]) && + (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || + !fpu_fOperand_S0$D_OUT[118]) && + (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || + !fpu_fOperand_S0$D_OUT[54]) && + (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || + IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && + !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ; + assign NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124 = + (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] != 11'd0 || + fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && + (fpu_fOperand_S0$D_OUT[129:119] != 11'd0 || + fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && + (x__h327 != 11'd2047 || _theResult___fst_sfd__h396 != 52'd0 || + (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || + fpu_fOperand_S0$D_OUT[118:67] != 52'd0) && + (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || + fpu_fOperand_S0$D_OUT[54:3] != 52'd0) || + fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) && + IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 ; + assign NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 = + fpu_fOperand_S0$D_OUT[130] != fpu_fOperand_S0$D_OUT[66] ; + assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711 = + !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + fpu_fState_S3$D_OUT[84] : + fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[2]) ; + assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 = + { NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 : + fpu_fState_S3$D_OUT[83], + !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || + IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 } ; + assign NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 = + !fpu_fState_S4$D_OUT[130] || + (IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 ^ + 13'h1000) > + (IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 ^ + 13'h1000) || + IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 == + IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 && + sfdBC__h35393 > sfdA__h35392 ; + assign _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 = + ({ 5'd0, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ^ + 12'h800) <= + (IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ^ + 12'h800) ; + assign _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 = + ({ 6'd0, + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ^ + 12'h800) <= + (IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ^ + 12'h800) ; + assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 = + 13'd7170 - fpu_fState_S3$D_OUT[12:0] ; + assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 = + (_7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ^ + 13'h1000) <= + 13'd4096 ; + assign _theResult___exp__h46359 = + sfd__h45855[53] ? + ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? + 11'd2047 : + din_inc___2_exp__h46444) : + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 ; + assign _theResult___fst__h20642 = + { fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[105:1], + fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[0] | + sfdlsb__h20640 } ; + assign _theResult___fst_exp__h34764 = + sfdBC__h19477[105] ? + _theResult___fst_exp__h34786 : + _theResult___fst_exp__h34849 ; + assign _theResult___fst_exp__h34767 = + (sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h34764 ; + assign _theResult___fst_exp__h34786 = + (din_exp__h34681 == 11'd0) ? 11'd2 : din_exp__h34681 + 11'd1 ; + assign _theResult___fst_exp__h34801 = + (din_exp__h34681 == 11'd0) ? 11'd1 : din_exp__h34681 ; + assign _theResult___fst_exp__h34840 = + din_exp__h34681 - + { 4'd0, + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ; + assign _theResult___fst_exp__h34846 = + (!sfdBC__h19477[105] && !sfdBC__h19477[104] && + !sfdBC__h19477[103] && + !sfdBC__h19477[102] && + !sfdBC__h19477[101] && + !sfdBC__h19477[100] && + !sfdBC__h19477[99] && + !sfdBC__h19477[98] && + !sfdBC__h19477[97] && + !sfdBC__h19477[96] && + !sfdBC__h19477[95] && + !sfdBC__h19477[94] && + !sfdBC__h19477[93] && + !sfdBC__h19477[92] && + !sfdBC__h19477[91] && + !sfdBC__h19477[90] && + !sfdBC__h19477[89] && + !sfdBC__h19477[88] && + !sfdBC__h19477[87] && + !sfdBC__h19477[86] && + !sfdBC__h19477[85] && + !sfdBC__h19477[84] && + !sfdBC__h19477[83] && + !sfdBC__h19477[82] && + !sfdBC__h19477[81] && + !sfdBC__h19477[80] && + !sfdBC__h19477[79] && + !sfdBC__h19477[78] && + !sfdBC__h19477[77] && + !sfdBC__h19477[76] && + !sfdBC__h19477[75] && + !sfdBC__h19477[74] && + !sfdBC__h19477[73] && + !sfdBC__h19477[72] && + !sfdBC__h19477[71] && + !sfdBC__h19477[70] && + !sfdBC__h19477[69] && + !sfdBC__h19477[68] && + !sfdBC__h19477[67] && + !sfdBC__h19477[66] && + !sfdBC__h19477[65] && + !sfdBC__h19477[64] && + !sfdBC__h19477[63] && + !sfdBC__h19477[62] && + !sfdBC__h19477[61] && + !sfdBC__h19477[60] && + !sfdBC__h19477[59] && + !sfdBC__h19477[58] && + !sfdBC__h19477[57] && + !sfdBC__h19477[56] && + !sfdBC__h19477[55] && + !sfdBC__h19477[54] && + !sfdBC__h19477[53] && + !sfdBC__h19477[52] && + !sfdBC__h19477[51] && + !sfdBC__h19477[50] && + !sfdBC__h19477[49] && + !sfdBC__h19477[48] && + !sfdBC__h19477[47] && + !sfdBC__h19477[46] && + !sfdBC__h19477[45] && + !sfdBC__h19477[44] && + !sfdBC__h19477[43] && + !sfdBC__h19477[42] && + !sfdBC__h19477[41] && + !sfdBC__h19477[40] && + !sfdBC__h19477[39] && + !sfdBC__h19477[38] && + !sfdBC__h19477[37] && + !sfdBC__h19477[36] && + !sfdBC__h19477[35] && + !sfdBC__h19477[34] && + !sfdBC__h19477[33] && + !sfdBC__h19477[32] && + !sfdBC__h19477[31] && + !sfdBC__h19477[30] && + !sfdBC__h19477[29] && + !sfdBC__h19477[28] && + !sfdBC__h19477[27] && + !sfdBC__h19477[26] && + !sfdBC__h19477[25] && + !sfdBC__h19477[24] && + !sfdBC__h19477[23] && + !sfdBC__h19477[22] && + !sfdBC__h19477[21] && + !sfdBC__h19477[20] && + !sfdBC__h19477[19] && + !sfdBC__h19477[18] && + !sfdBC__h19477[17] && + !sfdBC__h19477[16] && + !sfdBC__h19477[15] && + !sfdBC__h19477[14] && + !sfdBC__h19477[13] && + !sfdBC__h19477[12] && + !sfdBC__h19477[11] && + !sfdBC__h19477[10] && + !sfdBC__h19477[9] && + !sfdBC__h19477[8] && + !sfdBC__h19477[7] && + !sfdBC__h19477[6] && + !sfdBC__h19477[5] && + !sfdBC__h19477[4] && + !sfdBC__h19477[3] && + !sfdBC__h19477[2] && + !sfdBC__h19477[1] && + !sfdBC__h19477[0] || + !_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664) ? + 11'd0 : + _theResult___fst_exp__h34840 ; + assign _theResult___fst_exp__h34849 = + (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? + _theResult___fst_exp__h34801 : + _theResult___fst_exp__h34846 ; + assign _theResult___fst_exp__h45190 = + sfd__h36934[56] ? + _theResult___fst_exp__h45212 : + _theResult___fst_exp__h45275 ; + assign _theResult___fst_exp__h45193 = + (sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h45190 ; + assign _theResult___fst_exp__h45212 = + (value__h45122[10:0] == 11'd0) ? + 11'd2 : + value__h45122[10:0] + 11'd1 ; + assign _theResult___fst_exp__h45227 = + (value__h45122[10:0] == 11'd0) ? 11'd1 : value__h45122[10:0] ; + assign _theResult___fst_exp__h45266 = + value__h45122[10:0] - + { 5'd0, + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ; + assign _theResult___fst_exp__h45272 = + (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && + !sfd__h36934[53] && + !sfd__h36934[52] && + !sfd__h36934[51] && + !sfd__h36934[50] && + !sfd__h36934[49] && + !sfd__h36934[48] && + !sfd__h36934[47] && + !sfd__h36934[46] && + !sfd__h36934[45] && + !sfd__h36934[44] && + !sfd__h36934[43] && + !sfd__h36934[42] && + !sfd__h36934[41] && + !sfd__h36934[40] && + !sfd__h36934[39] && + !sfd__h36934[38] && + !sfd__h36934[37] && + !sfd__h36934[36] && + !sfd__h36934[35] && + !sfd__h36934[34] && + !sfd__h36934[33] && + !sfd__h36934[32] && + !sfd__h36934[31] && + !sfd__h36934[30] && + !sfd__h36934[29] && + !sfd__h36934[28] && + !sfd__h36934[27] && + !sfd__h36934[26] && + !sfd__h36934[25] && + !sfd__h36934[24] && + !sfd__h36934[23] && + !sfd__h36934[22] && + !sfd__h36934[21] && + !sfd__h36934[20] && + !sfd__h36934[19] && + !sfd__h36934[18] && + !sfd__h36934[17] && + !sfd__h36934[16] && + !sfd__h36934[15] && + !sfd__h36934[14] && + !sfd__h36934[13] && + !sfd__h36934[12] && + !sfd__h36934[11] && + !sfd__h36934[10] && + !sfd__h36934[9] && + !sfd__h36934[8] && + !sfd__h36934[7] && + !sfd__h36934[6] && + !sfd__h36934[5] && + !sfd__h36934[4] && + !sfd__h36934[3] && + !sfd__h36934[2] && + !sfd__h36934[1] && + !sfd__h36934[0] || + !_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105) ? + 11'd0 : + _theResult___fst_exp__h45266 ; + assign _theResult___fst_exp__h45275 = + (!sfd__h36934[56] && sfd__h36934[55]) ? + _theResult___fst_exp__h45227 : + _theResult___fst_exp__h45272 ; + assign _theResult___fst_sfd__h396 = + fpu_fOperand_S0$D_OUT[195] ? + fpu_fOperand_S0$D_OUT[182:131] : + 52'd0 ; + assign _theResult___sfd__h46360 = + sfd__h45855[53] ? + ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? + 52'd0 : + sfd__h45855[52:1]) : + sfd__h45855[51:0] ; + assign _theResult___snd__h34781 = { sfdBC__h19477[104:0], 1'd0 } ; + assign _theResult___snd__h34795 = + (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? + _theResult___snd__h34797 : + _theResult___snd__h34809 ; + assign _theResult___snd__h34797 = { sfdBC__h19477[103:0], 2'd0 } ; + assign _theResult___snd__h34809 = + (!sfdBC__h19477[105] && !sfdBC__h19477[104] && + !sfdBC__h19477[103] && + !sfdBC__h19477[102] && + !sfdBC__h19477[101] && + !sfdBC__h19477[100] && + !sfdBC__h19477[99] && + !sfdBC__h19477[98] && + !sfdBC__h19477[97] && + !sfdBC__h19477[96] && + !sfdBC__h19477[95] && + !sfdBC__h19477[94] && + !sfdBC__h19477[93] && + !sfdBC__h19477[92] && + !sfdBC__h19477[91] && + !sfdBC__h19477[90] && + !sfdBC__h19477[89] && + !sfdBC__h19477[88] && + !sfdBC__h19477[87] && + !sfdBC__h19477[86] && + !sfdBC__h19477[85] && + !sfdBC__h19477[84] && + !sfdBC__h19477[83] && + !sfdBC__h19477[82] && + !sfdBC__h19477[81] && + !sfdBC__h19477[80] && + !sfdBC__h19477[79] && + !sfdBC__h19477[78] && + !sfdBC__h19477[77] && + !sfdBC__h19477[76] && + !sfdBC__h19477[75] && + !sfdBC__h19477[74] && + !sfdBC__h19477[73] && + !sfdBC__h19477[72] && + !sfdBC__h19477[71] && + !sfdBC__h19477[70] && + !sfdBC__h19477[69] && + !sfdBC__h19477[68] && + !sfdBC__h19477[67] && + !sfdBC__h19477[66] && + !sfdBC__h19477[65] && + !sfdBC__h19477[64] && + !sfdBC__h19477[63] && + !sfdBC__h19477[62] && + !sfdBC__h19477[61] && + !sfdBC__h19477[60] && + !sfdBC__h19477[59] && + !sfdBC__h19477[58] && + !sfdBC__h19477[57] && + !sfdBC__h19477[56] && + !sfdBC__h19477[55] && + !sfdBC__h19477[54] && + !sfdBC__h19477[53] && + !sfdBC__h19477[52] && + !sfdBC__h19477[51] && + !sfdBC__h19477[50] && + !sfdBC__h19477[49] && + !sfdBC__h19477[48] && + !sfdBC__h19477[47] && + !sfdBC__h19477[46] && + !sfdBC__h19477[45] && + !sfdBC__h19477[44] && + !sfdBC__h19477[43] && + !sfdBC__h19477[42] && + !sfdBC__h19477[41] && + !sfdBC__h19477[40] && + !sfdBC__h19477[39] && + !sfdBC__h19477[38] && + !sfdBC__h19477[37] && + !sfdBC__h19477[36] && + !sfdBC__h19477[35] && + !sfdBC__h19477[34] && + !sfdBC__h19477[33] && + !sfdBC__h19477[32] && + !sfdBC__h19477[31] && + !sfdBC__h19477[30] && + !sfdBC__h19477[29] && + !sfdBC__h19477[28] && + !sfdBC__h19477[27] && + !sfdBC__h19477[26] && + !sfdBC__h19477[25] && + !sfdBC__h19477[24] && + !sfdBC__h19477[23] && + !sfdBC__h19477[22] && + !sfdBC__h19477[21] && + !sfdBC__h19477[20] && + !sfdBC__h19477[19] && + !sfdBC__h19477[18] && + !sfdBC__h19477[17] && + !sfdBC__h19477[16] && + !sfdBC__h19477[15] && + !sfdBC__h19477[14] && + !sfdBC__h19477[13] && + !sfdBC__h19477[12] && + !sfdBC__h19477[11] && + !sfdBC__h19477[10] && + !sfdBC__h19477[9] && + !sfdBC__h19477[8] && + !sfdBC__h19477[7] && + !sfdBC__h19477[6] && + !sfdBC__h19477[5] && + !sfdBC__h19477[4] && + !sfdBC__h19477[3] && + !sfdBC__h19477[2] && + !sfdBC__h19477[1] && + !sfdBC__h19477[0]) ? + sfdBC__h19477 : + _theResult___snd__h34815 ; + assign _theResult___snd__h34815 = + { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4[103:0], + 2'd0 } ; + assign _theResult___snd__h34833 = + sfdBC__h19477 << + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ; + assign _theResult___snd__h34838 = + sfdBC__h19477 << + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 ; + assign _theResult___snd__h45207 = { sfd__h36934[55:0], 1'd0 } ; + assign _theResult___snd__h45221 = + (!sfd__h36934[56] && sfd__h36934[55]) ? + _theResult___snd__h45223 : + _theResult___snd__h45235 ; + assign _theResult___snd__h45223 = { sfd__h36934[54:0], 2'd0 } ; + assign _theResult___snd__h45235 = + (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && + !sfd__h36934[53] && + !sfd__h36934[52] && + !sfd__h36934[51] && + !sfd__h36934[50] && + !sfd__h36934[49] && + !sfd__h36934[48] && + !sfd__h36934[47] && + !sfd__h36934[46] && + !sfd__h36934[45] && + !sfd__h36934[44] && + !sfd__h36934[43] && + !sfd__h36934[42] && + !sfd__h36934[41] && + !sfd__h36934[40] && + !sfd__h36934[39] && + !sfd__h36934[38] && + !sfd__h36934[37] && + !sfd__h36934[36] && + !sfd__h36934[35] && + !sfd__h36934[34] && + !sfd__h36934[33] && + !sfd__h36934[32] && + !sfd__h36934[31] && + !sfd__h36934[30] && + !sfd__h36934[29] && + !sfd__h36934[28] && + !sfd__h36934[27] && + !sfd__h36934[26] && + !sfd__h36934[25] && + !sfd__h36934[24] && + !sfd__h36934[23] && + !sfd__h36934[22] && + !sfd__h36934[21] && + !sfd__h36934[20] && + !sfd__h36934[19] && + !sfd__h36934[18] && + !sfd__h36934[17] && + !sfd__h36934[16] && + !sfd__h36934[15] && + !sfd__h36934[14] && + !sfd__h36934[13] && + !sfd__h36934[12] && + !sfd__h36934[11] && + !sfd__h36934[10] && + !sfd__h36934[9] && + !sfd__h36934[8] && + !sfd__h36934[7] && + !sfd__h36934[6] && + !sfd__h36934[5] && + !sfd__h36934[4] && + !sfd__h36934[3] && + !sfd__h36934[2] && + !sfd__h36934[1] && + !sfd__h36934[0]) ? + sfd__h36934 : + _theResult___snd__h45241 ; + assign _theResult___snd__h45241 = + { IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9[54:0], + 2'd0 } ; + assign _theResult___snd__h45259 = + sfd__h36934 << + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ; + assign _theResult___snd__h45264 = + sfd__h36934 << + IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 ; + assign _theResult___snd_fst__h34866 = + { IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5[1], + { sfdin__h34758[52:0], 52'd0 } != 105'd0 } ; + assign _theResult___snd_fst__h45292 = + { IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10[1], + { sfdin__h45184[3:0], 52'd0 } != 56'd0 } ; + assign _theResult___snd_snd__h35186 = + (fpu_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; + assign _theResult___snd_snd_snd__h35184 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? + _theResult___snd_snd__h35186 : + guardBC__h19481 ; + assign din_exp4681_MINUS_1023__q3 = din_exp__h34681 - 11'd1023 ; + assign din_exp__h34681 = + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? + value__h34698[10:0] : + 11'd0 ; + assign din_inc___2_exp__h46444 = fpu_fState_S8$D_OUT[65:55] + 11'd1 ; + assign fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 = + fpu_fOperand_S0$D_OUT[129:119] - 11'd1023 ; + assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 = + fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; + assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 = + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ; + assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 = + fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || + x__h327 == 11'd0 && _theResult___fst_sfd__h396 == 52'd0 && + (fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && + fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0) && + fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 ; + assign fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 = + (fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) == + NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 ; + assign fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213 = + fpu_fProd_S3$D_OUT >> + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; + assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 = + (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; + assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 = + (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; + assign fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702 = + fpu_fState_S3$D_OUT[86:82] | + { 2'd0, + sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023, + _theResult___fst_exp__h34767 == 11'd0 && + guardBC__h19481 != 2'd0, + sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023 } ; + assign fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 = + fpu_fState_S4$D_OUT[128:118] - 11'd1023 ; + assign fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 = + fpu_fState_S4$D_OUT[64:54] - 11'd1023 ; + assign fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816 = + fpu_fState_S5$D_OUT[56:0] >> fpu_fState_S5$D_OUT[126:114] ; + assign fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143 = + fpu_fState_S7$D_OUT[137:133] | + { 2'd0, + sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023, + _theResult___fst_exp__h45193 == 11'd0 && guard__h36938 != 2'd0, + sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023 } ; + assign fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 = + fpu_fState_S8$D_OUT[75:71] | + { 2'd0, + IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == + 11'd2047 && + ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? + fpu_fState_S8$D_OUT[54:3] : + _theResult___fst_sfd__h46438) == + 52'd0, + 1'd0, + fpu_fState_S8$D_OUT[65:55] != 11'd2047 && + fpu_fState_S8$D_OUT[2:1] != 2'b0 } ; + assign guardBC__h19481 = + (sfdBC__h19477[105] && + IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h34866 ; + assign guard__h36182 = fpu_fState_S5$D_OUT[56:0] << x__h36286 ; + assign guard__h36938 = + (sfd__h36934[56] && + IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h45292 ; + assign out_exp__h46362 = + fpu_fState_S8$D_OUT[3] ? + _theResult___exp__h46359 : + fpu_fState_S8$D_OUT[65:55] ; + assign out_sfd__h46363 = + fpu_fState_S8$D_OUT[3] ? + _theResult___sfd__h46360 : + fpu_fState_S8$D_OUT[54:3] ; + assign result__h36187 = + { fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[56:1], + fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[0] | + guard__h36182 != 57'd0 } ; + assign sfdA__h35392 = + { 1'b0, + fpu_fState_S4$D_OUT[128:118] != 11'd0, + fpu_fState_S4$D_OUT[117:66], + 3'b0 } ; + assign sfdBC__h19477 = + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? + fpu_fProd_S3$D_OUT : + _theResult___fst__h20642 ; + assign sfdBC__h35393 = + { 1'b0, + fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:0], + 1'b0 } ; + assign sfd__h3208 = { 1'd1, _theResult___fst_sfd__h396[50:0] } ; + assign sfd__h3211 = { 1'd1, fpu_fOperand_S0$D_OUT[117:67] } ; + assign sfd__h3214 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; + assign sfd__h36934 = + fpu_fState_S7$D_OUT[128] ? + fpu_fState_S7$D_OUT[56:0] : + fpu_fState_S7$D_OUT[113:57] ; + assign sfd__h45855 = + { 1'b0, + fpu_fState_S8$D_OUT[65:55] != 11'd0, + fpu_fState_S8$D_OUT[54:3] } + + 54'd1 ; + assign sfdin__h34758 = + sfdBC__h19477[105] ? + _theResult___snd__h34781 : + _theResult___snd__h34795 ; + assign sfdin__h45184 = + sfd__h36934[56] ? + _theResult___snd__h45207 : + _theResult___snd__h45221 ; + assign sfdlsb__h20640 = x__h20711 != 106'd0 ; + assign value5122_BITS_10_TO_0_MINUS_1023__q8 = + value__h45122[10:0] - 11'd1023 ; + assign value__h34698 = fpu_fState_S3$D_OUT[12:0] + 13'd1023 ; + assign value__h45122 = fpu_fState_S7$D_OUT[126:114] + 13'd1023 ; + assign x__h18058 = + { fpu_fOperand_S0$D_OUT[129:119] != 11'd0, + fpu_fOperand_S0$D_OUT[118:67] } ; + assign x__h18070 = + { fpu_fOperand_S0$D_OUT[65:55] != 11'd0, + fpu_fOperand_S0$D_OUT[54:3] } ; + assign x__h20711 = fpu_fProd_S3$D_OUT << x__h20744 ; + assign x__h20744 = + 13'd106 - + _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; + assign x__h327 = + fpu_fOperand_S0$D_OUT[195] ? + fpu_fOperand_S0$D_OUT[193:183] : + 11'd0 ; + assign x__h35221 = + fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? + _theResult___snd_snd_snd__h35184 : + 2'd3 ; + assign x__h35755 = + { 1'b0, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + { fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:0], + 1'b0 } : + { fpu_fState_S4$D_OUT[128:118] != 11'd0, + fpu_fState_S4$D_OUT[117:66], + 3'b0 } } ; + assign x__h35759 = + { 1'b0, + NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? + { fpu_fState_S4$D_OUT[128:118] != 11'd0, + fpu_fState_S4$D_OUT[117:66], + 3'b0 } : + { fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:0], + 1'b0 } } ; + assign x__h36174 = + fpu_fState_S5$D_OUT[215] ? + fpu_fState_S5$D_OUT[56:0] : + (((fpu_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? + result__h36187 : + ((fpu_fState_S5$D_OUT[56:0] == 57'd0) ? + fpu_fState_S5$D_OUT[56:0] : + 57'd1)) ; + assign x__h36286 = 13'd57 - fpu_fState_S5$D_OUT[126:114] ; + assign x__h36686 = fpu_fState_S6$D_OUT[113:57] + fpu_fState_S6$D_OUT[56:0] ; + assign x__h36695 = fpu_fState_S6$D_OUT[113:57] - fpu_fState_S6$D_OUT[56:0] ; + assign x__h45575 = fpu_fState_S7$D_OUT[202] ? 2'd0 : guard__h36938 ; + always@(fpu_fState_S8$D_OUT or out_sfd__h46363 or _theResult___sfd__h46360) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = + fpu_fState_S8$D_OUT[54:3]; + 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = + out_sfd__h46363; + 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = + _theResult___sfd__h46360; + endcase + end + always@(fpu_fState_S8$D_OUT or _theResult___sfd__h46360) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = + fpu_fState_S8$D_OUT[54:3]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = + _theResult___sfd__h46360; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 or + _theResult___sfd__h46360) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + _theResult___fst_sfd__h46438 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1; + 3'd1: + _theResult___fst_sfd__h46438 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2; + 3'd2: + _theResult___fst_sfd__h46438 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? + fpu_fState_S8$D_OUT[54:3] : + _theResult___sfd__h46360; + 3'd3: + _theResult___fst_sfd__h46438 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[54:3] : + (fpu_fState_S8$D_OUT[66] ? + _theResult___sfd__h46360 : + fpu_fState_S8$D_OUT[54:3]); + 3'd4: _theResult___fst_sfd__h46438 = fpu_fState_S8$D_OUT[54:3]; + default: _theResult___fst_sfd__h46438 = 52'd0; + endcase + end + always@(fpu_fState_S8$D_OUT or out_exp__h46362 or _theResult___exp__h46359) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = + fpu_fState_S8$D_OUT[65:55]; + 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = + out_exp__h46362; + 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = + _theResult___exp__h46359; + endcase + end + always@(fpu_fState_S8$D_OUT or _theResult___exp__h46359) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = + fpu_fState_S8$D_OUT[65:55]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = + _theResult___exp__h46359; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 or + _theResult___exp__h46359) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + _theResult___fst_exp__h46437 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11; + 3'd1: + _theResult___fst_exp__h46437 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12; + 3'd2: + _theResult___fst_exp__h46437 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? + fpu_fState_S8$D_OUT[65:55] : + _theResult___exp__h46359; + 3'd3: + _theResult___fst_exp__h46437 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[65:55] : + (fpu_fState_S8$D_OUT[66] ? + _theResult___exp__h46359 : + fpu_fState_S8$D_OUT[65:55]); + 3'd4: _theResult___fst_exp__h46437 = fpu_fState_S8$D_OUT[65:55]; + default: _theResult___fst_exp__h46437 = 11'd0; + endcase + end + always@(fpu_fState_S8$D_OUT) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01, 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = + fpu_fState_S8$D_OUT[66]; + 2'd3: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = + fpu_fState_S8$D_OUT[2:1] == 2'b11 && fpu_fState_S8$D_OUT[66]; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13; + 3'd1: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[66] : + (fpu_fState_S8$D_OUT[2:1] == 2'b01 || + fpu_fState_S8$D_OUT[2:1] == 2'b10 || + fpu_fState_S8$D_OUT[2:1] == 2'b11) && + fpu_fState_S8$D_OUT[66]; + 3'd2, 3'd3: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + fpu_fState_S8$D_OUT[66]; + default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = + fpu_fState_S8$D_OUT[70:68] == 3'd4 && + fpu_fState_S8$D_OUT[66]; + endcase + end + always@(fpu_fState_S8$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0, 2'b01: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = + fpu_fState_S8$D_OUT[65:3]; + 2'b10: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = + fpu_fState_S8$D_OUT[3] ? + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : + fpu_fState_S8$D_OUT[65:3]; + 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; + endcase + end + always@(fpu_fState_S8$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) + begin + case (fpu_fState_S8$D_OUT[2:1]) + 2'b0: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = + fpu_fState_S8$D_OUT[65:3]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; + endcase + end + always@(fpu_fState_S8$D_OUT or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 or + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 or + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) + begin + case (fpu_fState_S8$D_OUT[70:68]) + 3'd0: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17; + 3'd1: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18; + 3'd2: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? + fpu_fState_S8$D_OUT[65:3] : + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; + 3'd3: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? + fpu_fState_S8$D_OUT[65:3] : + (fpu_fState_S8$D_OUT[66] ? + IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : + fpu_fState_S8$D_OUT[65:3]); + 3'd4: + CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = + fpu_fState_S8$D_OUT[65:3]; + default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = 63'd0; + endcase + end endmodule // mkDoubleFMA diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v index 22b5f44..9ba65dd 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -7,15 +7,16 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 -// RDY_response_get O 1 +// response_get O 69 reg +// RDY_response_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// request_put I 67 +// request_put I 67 reg // EN_request_put I 1 // EN_response_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// EN_response_get -> RDY_request_put // // @@ -59,44 +60,5579 @@ module mkDoubleSqrt(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu - wire [68 : 0] fpu$response_get; - wire [66 : 0] fpu$request_put; - wire fpu$EN_request_put, - fpu$EN_response_get, - fpu$RDY_request_put, - fpu$RDY_response_get; + // ports of submodule fpu_fOperand_S0 + wire [66 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; + wire fpu_fOperand_S0$CLR, + fpu_fOperand_S0$DEQ, + fpu_fOperand_S0$EMPTY_N, + fpu_fOperand_S0$ENQ, + fpu_fOperand_S0$FULL_N; + + // ports of submodule fpu_fResult_S5 + wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; + wire fpu_fResult_S5$CLR, + fpu_fResult_S5$DEQ, + fpu_fResult_S5$EMPTY_N, + fpu_fResult_S5$ENQ, + fpu_fResult_S5$FULL_N; + + // ports of submodule fpu_fState_S1 + wire [194 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; + wire fpu_fState_S1$CLR, + fpu_fState_S1$DEQ, + fpu_fState_S1$EMPTY_N, + fpu_fState_S1$ENQ, + fpu_fState_S1$FULL_N; + + // ports of submodule fpu_fState_S2 + wire [136 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; + wire fpu_fState_S2$CLR, + fpu_fState_S2$DEQ, + fpu_fState_S2$EMPTY_N, + fpu_fState_S2$ENQ, + fpu_fState_S2$FULL_N; + + // ports of submodule fpu_fState_S3 + wire [195 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; + wire fpu_fState_S3$CLR, + fpu_fState_S3$DEQ, + fpu_fState_S3$EMPTY_N, + fpu_fState_S3$ENQ, + fpu_fState_S3$FULL_N; + + // ports of submodule fpu_fState_S4 + wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; + wire fpu_fState_S4$CLR, + fpu_fState_S4$DEQ, + fpu_fState_S4$EMPTY_N, + fpu_fState_S4$ENQ, + fpu_fState_S4$FULL_N; + + // ports of submodule int_sqrt_fFirst + wire [464 : 0] int_sqrt_fFirst$D_IN, int_sqrt_fFirst$D_OUT; + wire int_sqrt_fFirst$CLR, + int_sqrt_fFirst$DEQ, + int_sqrt_fFirst$EMPTY_N, + int_sqrt_fFirst$ENQ, + int_sqrt_fFirst$FULL_N; + + // ports of submodule int_sqrt_fNext_0 + wire [464 : 0] int_sqrt_fNext_0$D_IN, int_sqrt_fNext_0$D_OUT; + wire int_sqrt_fNext_0$CLR, + int_sqrt_fNext_0$DEQ, + int_sqrt_fNext_0$EMPTY_N, + int_sqrt_fNext_0$ENQ, + int_sqrt_fNext_0$FULL_N; + + // ports of submodule int_sqrt_fNext_1 + wire [464 : 0] int_sqrt_fNext_1$D_IN, int_sqrt_fNext_1$D_OUT; + wire int_sqrt_fNext_1$CLR, + int_sqrt_fNext_1$DEQ, + int_sqrt_fNext_1$EMPTY_N, + int_sqrt_fNext_1$ENQ, + int_sqrt_fNext_1$FULL_N; + + // ports of submodule int_sqrt_fNext_10 + wire [464 : 0] int_sqrt_fNext_10$D_IN, int_sqrt_fNext_10$D_OUT; + wire int_sqrt_fNext_10$CLR, + int_sqrt_fNext_10$DEQ, + int_sqrt_fNext_10$EMPTY_N, + int_sqrt_fNext_10$ENQ, + int_sqrt_fNext_10$FULL_N; + + // ports of submodule int_sqrt_fNext_11 + wire [464 : 0] int_sqrt_fNext_11$D_IN, int_sqrt_fNext_11$D_OUT; + wire int_sqrt_fNext_11$CLR, + int_sqrt_fNext_11$DEQ, + int_sqrt_fNext_11$EMPTY_N, + int_sqrt_fNext_11$ENQ, + int_sqrt_fNext_11$FULL_N; + + // ports of submodule int_sqrt_fNext_12 + wire [464 : 0] int_sqrt_fNext_12$D_IN, int_sqrt_fNext_12$D_OUT; + wire int_sqrt_fNext_12$CLR, + int_sqrt_fNext_12$DEQ, + int_sqrt_fNext_12$EMPTY_N, + int_sqrt_fNext_12$ENQ, + int_sqrt_fNext_12$FULL_N; + + // ports of submodule int_sqrt_fNext_13 + wire [464 : 0] int_sqrt_fNext_13$D_IN, int_sqrt_fNext_13$D_OUT; + wire int_sqrt_fNext_13$CLR, + int_sqrt_fNext_13$DEQ, + int_sqrt_fNext_13$EMPTY_N, + int_sqrt_fNext_13$ENQ, + int_sqrt_fNext_13$FULL_N; + + // ports of submodule int_sqrt_fNext_14 + wire [464 : 0] int_sqrt_fNext_14$D_IN, int_sqrt_fNext_14$D_OUT; + wire int_sqrt_fNext_14$CLR, + int_sqrt_fNext_14$DEQ, + int_sqrt_fNext_14$EMPTY_N, + int_sqrt_fNext_14$ENQ, + int_sqrt_fNext_14$FULL_N; + + // ports of submodule int_sqrt_fNext_15 + wire [464 : 0] int_sqrt_fNext_15$D_IN, int_sqrt_fNext_15$D_OUT; + wire int_sqrt_fNext_15$CLR, + int_sqrt_fNext_15$DEQ, + int_sqrt_fNext_15$EMPTY_N, + int_sqrt_fNext_15$ENQ, + int_sqrt_fNext_15$FULL_N; + + // ports of submodule int_sqrt_fNext_16 + wire [464 : 0] int_sqrt_fNext_16$D_IN, int_sqrt_fNext_16$D_OUT; + wire int_sqrt_fNext_16$CLR, + int_sqrt_fNext_16$DEQ, + int_sqrt_fNext_16$EMPTY_N, + int_sqrt_fNext_16$ENQ, + int_sqrt_fNext_16$FULL_N; + + // ports of submodule int_sqrt_fNext_17 + wire [464 : 0] int_sqrt_fNext_17$D_IN, int_sqrt_fNext_17$D_OUT; + wire int_sqrt_fNext_17$CLR, + int_sqrt_fNext_17$DEQ, + int_sqrt_fNext_17$EMPTY_N, + int_sqrt_fNext_17$ENQ, + int_sqrt_fNext_17$FULL_N; + + // ports of submodule int_sqrt_fNext_18 + wire [464 : 0] int_sqrt_fNext_18$D_IN, int_sqrt_fNext_18$D_OUT; + wire int_sqrt_fNext_18$CLR, + int_sqrt_fNext_18$DEQ, + int_sqrt_fNext_18$EMPTY_N, + int_sqrt_fNext_18$ENQ, + int_sqrt_fNext_18$FULL_N; + + // ports of submodule int_sqrt_fNext_19 + wire [464 : 0] int_sqrt_fNext_19$D_IN, int_sqrt_fNext_19$D_OUT; + wire int_sqrt_fNext_19$CLR, + int_sqrt_fNext_19$DEQ, + int_sqrt_fNext_19$EMPTY_N, + int_sqrt_fNext_19$ENQ, + int_sqrt_fNext_19$FULL_N; + + // ports of submodule int_sqrt_fNext_2 + wire [464 : 0] int_sqrt_fNext_2$D_IN, int_sqrt_fNext_2$D_OUT; + wire int_sqrt_fNext_2$CLR, + int_sqrt_fNext_2$DEQ, + int_sqrt_fNext_2$EMPTY_N, + int_sqrt_fNext_2$ENQ, + int_sqrt_fNext_2$FULL_N; + + // ports of submodule int_sqrt_fNext_20 + wire [464 : 0] int_sqrt_fNext_20$D_IN, int_sqrt_fNext_20$D_OUT; + wire int_sqrt_fNext_20$CLR, + int_sqrt_fNext_20$DEQ, + int_sqrt_fNext_20$EMPTY_N, + int_sqrt_fNext_20$ENQ, + int_sqrt_fNext_20$FULL_N; + + // ports of submodule int_sqrt_fNext_21 + wire [464 : 0] int_sqrt_fNext_21$D_IN, int_sqrt_fNext_21$D_OUT; + wire int_sqrt_fNext_21$CLR, + int_sqrt_fNext_21$DEQ, + int_sqrt_fNext_21$EMPTY_N, + int_sqrt_fNext_21$ENQ, + int_sqrt_fNext_21$FULL_N; + + // ports of submodule int_sqrt_fNext_22 + wire [464 : 0] int_sqrt_fNext_22$D_IN, int_sqrt_fNext_22$D_OUT; + wire int_sqrt_fNext_22$CLR, + int_sqrt_fNext_22$DEQ, + int_sqrt_fNext_22$EMPTY_N, + int_sqrt_fNext_22$ENQ, + int_sqrt_fNext_22$FULL_N; + + // ports of submodule int_sqrt_fNext_23 + wire [464 : 0] int_sqrt_fNext_23$D_IN, int_sqrt_fNext_23$D_OUT; + wire int_sqrt_fNext_23$CLR, + int_sqrt_fNext_23$DEQ, + int_sqrt_fNext_23$EMPTY_N, + int_sqrt_fNext_23$ENQ, + int_sqrt_fNext_23$FULL_N; + + // ports of submodule int_sqrt_fNext_24 + wire [464 : 0] int_sqrt_fNext_24$D_IN, int_sqrt_fNext_24$D_OUT; + wire int_sqrt_fNext_24$CLR, + int_sqrt_fNext_24$DEQ, + int_sqrt_fNext_24$EMPTY_N, + int_sqrt_fNext_24$ENQ, + int_sqrt_fNext_24$FULL_N; + + // ports of submodule int_sqrt_fNext_25 + wire [464 : 0] int_sqrt_fNext_25$D_IN, int_sqrt_fNext_25$D_OUT; + wire int_sqrt_fNext_25$CLR, + int_sqrt_fNext_25$DEQ, + int_sqrt_fNext_25$EMPTY_N, + int_sqrt_fNext_25$ENQ, + int_sqrt_fNext_25$FULL_N; + + // ports of submodule int_sqrt_fNext_26 + wire [464 : 0] int_sqrt_fNext_26$D_IN, int_sqrt_fNext_26$D_OUT; + wire int_sqrt_fNext_26$CLR, + int_sqrt_fNext_26$DEQ, + int_sqrt_fNext_26$EMPTY_N, + int_sqrt_fNext_26$ENQ, + int_sqrt_fNext_26$FULL_N; + + // ports of submodule int_sqrt_fNext_27 + wire [464 : 0] int_sqrt_fNext_27$D_IN, int_sqrt_fNext_27$D_OUT; + wire int_sqrt_fNext_27$CLR, + int_sqrt_fNext_27$DEQ, + int_sqrt_fNext_27$EMPTY_N, + int_sqrt_fNext_27$ENQ, + int_sqrt_fNext_27$FULL_N; + + // ports of submodule int_sqrt_fNext_28 + wire [464 : 0] int_sqrt_fNext_28$D_IN, int_sqrt_fNext_28$D_OUT; + wire int_sqrt_fNext_28$CLR, + int_sqrt_fNext_28$DEQ, + int_sqrt_fNext_28$EMPTY_N, + int_sqrt_fNext_28$ENQ, + int_sqrt_fNext_28$FULL_N; + + // ports of submodule int_sqrt_fNext_29 + wire [464 : 0] int_sqrt_fNext_29$D_IN, int_sqrt_fNext_29$D_OUT; + wire int_sqrt_fNext_29$CLR, + int_sqrt_fNext_29$DEQ, + int_sqrt_fNext_29$EMPTY_N, + int_sqrt_fNext_29$ENQ, + int_sqrt_fNext_29$FULL_N; + + // ports of submodule int_sqrt_fNext_3 + wire [464 : 0] int_sqrt_fNext_3$D_IN, int_sqrt_fNext_3$D_OUT; + wire int_sqrt_fNext_3$CLR, + int_sqrt_fNext_3$DEQ, + int_sqrt_fNext_3$EMPTY_N, + int_sqrt_fNext_3$ENQ, + int_sqrt_fNext_3$FULL_N; + + // ports of submodule int_sqrt_fNext_30 + wire [464 : 0] int_sqrt_fNext_30$D_IN, int_sqrt_fNext_30$D_OUT; + wire int_sqrt_fNext_30$CLR, + int_sqrt_fNext_30$DEQ, + int_sqrt_fNext_30$EMPTY_N, + int_sqrt_fNext_30$ENQ, + int_sqrt_fNext_30$FULL_N; + + // ports of submodule int_sqrt_fNext_31 + wire [464 : 0] int_sqrt_fNext_31$D_IN, int_sqrt_fNext_31$D_OUT; + wire int_sqrt_fNext_31$CLR, + int_sqrt_fNext_31$DEQ, + int_sqrt_fNext_31$EMPTY_N, + int_sqrt_fNext_31$ENQ, + int_sqrt_fNext_31$FULL_N; + + // ports of submodule int_sqrt_fNext_32 + wire [464 : 0] int_sqrt_fNext_32$D_IN, int_sqrt_fNext_32$D_OUT; + wire int_sqrt_fNext_32$CLR, + int_sqrt_fNext_32$DEQ, + int_sqrt_fNext_32$EMPTY_N, + int_sqrt_fNext_32$ENQ, + int_sqrt_fNext_32$FULL_N; + + // ports of submodule int_sqrt_fNext_33 + wire [464 : 0] int_sqrt_fNext_33$D_IN, int_sqrt_fNext_33$D_OUT; + wire int_sqrt_fNext_33$CLR, + int_sqrt_fNext_33$DEQ, + int_sqrt_fNext_33$EMPTY_N, + int_sqrt_fNext_33$ENQ, + int_sqrt_fNext_33$FULL_N; + + // ports of submodule int_sqrt_fNext_34 + wire [464 : 0] int_sqrt_fNext_34$D_IN, int_sqrt_fNext_34$D_OUT; + wire int_sqrt_fNext_34$CLR, + int_sqrt_fNext_34$DEQ, + int_sqrt_fNext_34$EMPTY_N, + int_sqrt_fNext_34$ENQ, + int_sqrt_fNext_34$FULL_N; + + // ports of submodule int_sqrt_fNext_35 + wire [464 : 0] int_sqrt_fNext_35$D_IN, int_sqrt_fNext_35$D_OUT; + wire int_sqrt_fNext_35$CLR, + int_sqrt_fNext_35$DEQ, + int_sqrt_fNext_35$EMPTY_N, + int_sqrt_fNext_35$ENQ, + int_sqrt_fNext_35$FULL_N; + + // ports of submodule int_sqrt_fNext_36 + wire [464 : 0] int_sqrt_fNext_36$D_IN, int_sqrt_fNext_36$D_OUT; + wire int_sqrt_fNext_36$CLR, + int_sqrt_fNext_36$DEQ, + int_sqrt_fNext_36$EMPTY_N, + int_sqrt_fNext_36$ENQ, + int_sqrt_fNext_36$FULL_N; + + // ports of submodule int_sqrt_fNext_37 + wire [464 : 0] int_sqrt_fNext_37$D_IN, int_sqrt_fNext_37$D_OUT; + wire int_sqrt_fNext_37$CLR, + int_sqrt_fNext_37$DEQ, + int_sqrt_fNext_37$EMPTY_N, + int_sqrt_fNext_37$ENQ, + int_sqrt_fNext_37$FULL_N; + + // ports of submodule int_sqrt_fNext_38 + wire [464 : 0] int_sqrt_fNext_38$D_IN, int_sqrt_fNext_38$D_OUT; + wire int_sqrt_fNext_38$CLR, + int_sqrt_fNext_38$DEQ, + int_sqrt_fNext_38$EMPTY_N, + int_sqrt_fNext_38$ENQ, + int_sqrt_fNext_38$FULL_N; + + // ports of submodule int_sqrt_fNext_39 + wire [464 : 0] int_sqrt_fNext_39$D_IN, int_sqrt_fNext_39$D_OUT; + wire int_sqrt_fNext_39$CLR, + int_sqrt_fNext_39$DEQ, + int_sqrt_fNext_39$EMPTY_N, + int_sqrt_fNext_39$ENQ, + int_sqrt_fNext_39$FULL_N; + + // ports of submodule int_sqrt_fNext_4 + wire [464 : 0] int_sqrt_fNext_4$D_IN, int_sqrt_fNext_4$D_OUT; + wire int_sqrt_fNext_4$CLR, + int_sqrt_fNext_4$DEQ, + int_sqrt_fNext_4$EMPTY_N, + int_sqrt_fNext_4$ENQ, + int_sqrt_fNext_4$FULL_N; + + // ports of submodule int_sqrt_fNext_40 + wire [464 : 0] int_sqrt_fNext_40$D_IN, int_sqrt_fNext_40$D_OUT; + wire int_sqrt_fNext_40$CLR, + int_sqrt_fNext_40$DEQ, + int_sqrt_fNext_40$EMPTY_N, + int_sqrt_fNext_40$ENQ, + int_sqrt_fNext_40$FULL_N; + + // ports of submodule int_sqrt_fNext_41 + wire [464 : 0] int_sqrt_fNext_41$D_IN, int_sqrt_fNext_41$D_OUT; + wire int_sqrt_fNext_41$CLR, + int_sqrt_fNext_41$DEQ, + int_sqrt_fNext_41$EMPTY_N, + int_sqrt_fNext_41$ENQ, + int_sqrt_fNext_41$FULL_N; + + // ports of submodule int_sqrt_fNext_42 + wire [464 : 0] int_sqrt_fNext_42$D_IN, int_sqrt_fNext_42$D_OUT; + wire int_sqrt_fNext_42$CLR, + int_sqrt_fNext_42$DEQ, + int_sqrt_fNext_42$EMPTY_N, + int_sqrt_fNext_42$ENQ, + int_sqrt_fNext_42$FULL_N; + + // ports of submodule int_sqrt_fNext_43 + wire [464 : 0] int_sqrt_fNext_43$D_IN, int_sqrt_fNext_43$D_OUT; + wire int_sqrt_fNext_43$CLR, + int_sqrt_fNext_43$DEQ, + int_sqrt_fNext_43$EMPTY_N, + int_sqrt_fNext_43$ENQ, + int_sqrt_fNext_43$FULL_N; + + // ports of submodule int_sqrt_fNext_44 + wire [464 : 0] int_sqrt_fNext_44$D_IN, int_sqrt_fNext_44$D_OUT; + wire int_sqrt_fNext_44$CLR, + int_sqrt_fNext_44$DEQ, + int_sqrt_fNext_44$EMPTY_N, + int_sqrt_fNext_44$ENQ, + int_sqrt_fNext_44$FULL_N; + + // ports of submodule int_sqrt_fNext_45 + wire [464 : 0] int_sqrt_fNext_45$D_IN, int_sqrt_fNext_45$D_OUT; + wire int_sqrt_fNext_45$CLR, + int_sqrt_fNext_45$DEQ, + int_sqrt_fNext_45$EMPTY_N, + int_sqrt_fNext_45$ENQ, + int_sqrt_fNext_45$FULL_N; + + // ports of submodule int_sqrt_fNext_46 + wire [464 : 0] int_sqrt_fNext_46$D_IN, int_sqrt_fNext_46$D_OUT; + wire int_sqrt_fNext_46$CLR, + int_sqrt_fNext_46$DEQ, + int_sqrt_fNext_46$EMPTY_N, + int_sqrt_fNext_46$ENQ, + int_sqrt_fNext_46$FULL_N; + + // ports of submodule int_sqrt_fNext_47 + wire [464 : 0] int_sqrt_fNext_47$D_IN, int_sqrt_fNext_47$D_OUT; + wire int_sqrt_fNext_47$CLR, + int_sqrt_fNext_47$DEQ, + int_sqrt_fNext_47$EMPTY_N, + int_sqrt_fNext_47$ENQ, + int_sqrt_fNext_47$FULL_N; + + // ports of submodule int_sqrt_fNext_48 + wire [464 : 0] int_sqrt_fNext_48$D_IN, int_sqrt_fNext_48$D_OUT; + wire int_sqrt_fNext_48$CLR, + int_sqrt_fNext_48$DEQ, + int_sqrt_fNext_48$EMPTY_N, + int_sqrt_fNext_48$ENQ, + int_sqrt_fNext_48$FULL_N; + + // ports of submodule int_sqrt_fNext_49 + wire [464 : 0] int_sqrt_fNext_49$D_IN, int_sqrt_fNext_49$D_OUT; + wire int_sqrt_fNext_49$CLR, + int_sqrt_fNext_49$DEQ, + int_sqrt_fNext_49$EMPTY_N, + int_sqrt_fNext_49$ENQ, + int_sqrt_fNext_49$FULL_N; + + // ports of submodule int_sqrt_fNext_5 + wire [464 : 0] int_sqrt_fNext_5$D_IN, int_sqrt_fNext_5$D_OUT; + wire int_sqrt_fNext_5$CLR, + int_sqrt_fNext_5$DEQ, + int_sqrt_fNext_5$EMPTY_N, + int_sqrt_fNext_5$ENQ, + int_sqrt_fNext_5$FULL_N; + + // ports of submodule int_sqrt_fNext_50 + wire [464 : 0] int_sqrt_fNext_50$D_IN, int_sqrt_fNext_50$D_OUT; + wire int_sqrt_fNext_50$CLR, + int_sqrt_fNext_50$DEQ, + int_sqrt_fNext_50$EMPTY_N, + int_sqrt_fNext_50$ENQ, + int_sqrt_fNext_50$FULL_N; + + // ports of submodule int_sqrt_fNext_51 + wire [464 : 0] int_sqrt_fNext_51$D_IN, int_sqrt_fNext_51$D_OUT; + wire int_sqrt_fNext_51$CLR, + int_sqrt_fNext_51$DEQ, + int_sqrt_fNext_51$EMPTY_N, + int_sqrt_fNext_51$ENQ, + int_sqrt_fNext_51$FULL_N; + + // ports of submodule int_sqrt_fNext_52 + wire [464 : 0] int_sqrt_fNext_52$D_IN, int_sqrt_fNext_52$D_OUT; + wire int_sqrt_fNext_52$CLR, + int_sqrt_fNext_52$DEQ, + int_sqrt_fNext_52$EMPTY_N, + int_sqrt_fNext_52$ENQ, + int_sqrt_fNext_52$FULL_N; + + // ports of submodule int_sqrt_fNext_53 + wire [464 : 0] int_sqrt_fNext_53$D_IN, int_sqrt_fNext_53$D_OUT; + wire int_sqrt_fNext_53$CLR, + int_sqrt_fNext_53$DEQ, + int_sqrt_fNext_53$EMPTY_N, + int_sqrt_fNext_53$ENQ, + int_sqrt_fNext_53$FULL_N; + + // ports of submodule int_sqrt_fNext_54 + wire [464 : 0] int_sqrt_fNext_54$D_IN, int_sqrt_fNext_54$D_OUT; + wire int_sqrt_fNext_54$CLR, + int_sqrt_fNext_54$DEQ, + int_sqrt_fNext_54$EMPTY_N, + int_sqrt_fNext_54$ENQ, + int_sqrt_fNext_54$FULL_N; + + // ports of submodule int_sqrt_fNext_55 + wire [464 : 0] int_sqrt_fNext_55$D_IN, int_sqrt_fNext_55$D_OUT; + wire int_sqrt_fNext_55$CLR, + int_sqrt_fNext_55$DEQ, + int_sqrt_fNext_55$EMPTY_N, + int_sqrt_fNext_55$ENQ, + int_sqrt_fNext_55$FULL_N; + + // ports of submodule int_sqrt_fNext_56 + wire [464 : 0] int_sqrt_fNext_56$D_IN, int_sqrt_fNext_56$D_OUT; + wire int_sqrt_fNext_56$CLR, + int_sqrt_fNext_56$DEQ, + int_sqrt_fNext_56$EMPTY_N, + int_sqrt_fNext_56$ENQ, + int_sqrt_fNext_56$FULL_N; + + // ports of submodule int_sqrt_fNext_57 + wire [464 : 0] int_sqrt_fNext_57$D_IN, int_sqrt_fNext_57$D_OUT; + wire int_sqrt_fNext_57$CLR, + int_sqrt_fNext_57$DEQ, + int_sqrt_fNext_57$EMPTY_N, + int_sqrt_fNext_57$ENQ, + int_sqrt_fNext_57$FULL_N; + + // ports of submodule int_sqrt_fNext_58 + wire [464 : 0] int_sqrt_fNext_58$D_IN, int_sqrt_fNext_58$D_OUT; + wire int_sqrt_fNext_58$CLR, + int_sqrt_fNext_58$DEQ, + int_sqrt_fNext_58$EMPTY_N, + int_sqrt_fNext_58$ENQ, + int_sqrt_fNext_58$FULL_N; + + // ports of submodule int_sqrt_fNext_6 + wire [464 : 0] int_sqrt_fNext_6$D_IN, int_sqrt_fNext_6$D_OUT; + wire int_sqrt_fNext_6$CLR, + int_sqrt_fNext_6$DEQ, + int_sqrt_fNext_6$EMPTY_N, + int_sqrt_fNext_6$ENQ, + int_sqrt_fNext_6$FULL_N; + + // ports of submodule int_sqrt_fNext_7 + wire [464 : 0] int_sqrt_fNext_7$D_IN, int_sqrt_fNext_7$D_OUT; + wire int_sqrt_fNext_7$CLR, + int_sqrt_fNext_7$DEQ, + int_sqrt_fNext_7$EMPTY_N, + int_sqrt_fNext_7$ENQ, + int_sqrt_fNext_7$FULL_N; + + // ports of submodule int_sqrt_fNext_8 + wire [464 : 0] int_sqrt_fNext_8$D_IN, int_sqrt_fNext_8$D_OUT; + wire int_sqrt_fNext_8$CLR, + int_sqrt_fNext_8$DEQ, + int_sqrt_fNext_8$EMPTY_N, + int_sqrt_fNext_8$ENQ, + int_sqrt_fNext_8$FULL_N; + + // ports of submodule int_sqrt_fNext_9 + wire [464 : 0] int_sqrt_fNext_9$D_IN, int_sqrt_fNext_9$D_OUT; + wire int_sqrt_fNext_9$CLR, + int_sqrt_fNext_9$DEQ, + int_sqrt_fNext_9$EMPTY_N, + int_sqrt_fNext_9$ENQ, + int_sqrt_fNext_9$FULL_N; + + // ports of submodule int_sqrt_fRequest + wire [115 : 0] int_sqrt_fRequest$D_IN, int_sqrt_fRequest$D_OUT; + wire int_sqrt_fRequest$CLR, + int_sqrt_fRequest$DEQ, + int_sqrt_fRequest$EMPTY_N, + int_sqrt_fRequest$ENQ, + int_sqrt_fRequest$FULL_N; + + // ports of submodule int_sqrt_fResponse + wire [116 : 0] int_sqrt_fResponse$D_IN, int_sqrt_fResponse$D_OUT; + wire int_sqrt_fResponse$CLR, + int_sqrt_fResponse$DEQ, + int_sqrt_fResponse$EMPTY_N, + int_sqrt_fResponse$ENQ, + int_sqrt_fResponse$FULL_N; // rule scheduling signals - wire CAN_FIRE_request_put, + wire CAN_FIRE_RL_fpu_s1_stage, + CAN_FIRE_RL_fpu_s2_stage, + CAN_FIRE_RL_fpu_s3_stage, + CAN_FIRE_RL_fpu_s4_stage, + CAN_FIRE_RL_fpu_s5_stage, + CAN_FIRE_RL_int_sqrt_finish, + CAN_FIRE_RL_int_sqrt_start, + CAN_FIRE_RL_int_sqrt_work, + CAN_FIRE_RL_int_sqrt_work_1, + CAN_FIRE_RL_int_sqrt_work_10, + CAN_FIRE_RL_int_sqrt_work_11, + CAN_FIRE_RL_int_sqrt_work_12, + CAN_FIRE_RL_int_sqrt_work_13, + CAN_FIRE_RL_int_sqrt_work_14, + CAN_FIRE_RL_int_sqrt_work_15, + CAN_FIRE_RL_int_sqrt_work_16, + CAN_FIRE_RL_int_sqrt_work_17, + CAN_FIRE_RL_int_sqrt_work_18, + CAN_FIRE_RL_int_sqrt_work_19, + CAN_FIRE_RL_int_sqrt_work_2, + CAN_FIRE_RL_int_sqrt_work_20, + CAN_FIRE_RL_int_sqrt_work_21, + CAN_FIRE_RL_int_sqrt_work_22, + CAN_FIRE_RL_int_sqrt_work_23, + CAN_FIRE_RL_int_sqrt_work_24, + CAN_FIRE_RL_int_sqrt_work_25, + CAN_FIRE_RL_int_sqrt_work_26, + CAN_FIRE_RL_int_sqrt_work_27, + CAN_FIRE_RL_int_sqrt_work_28, + CAN_FIRE_RL_int_sqrt_work_29, + CAN_FIRE_RL_int_sqrt_work_3, + CAN_FIRE_RL_int_sqrt_work_30, + CAN_FIRE_RL_int_sqrt_work_31, + CAN_FIRE_RL_int_sqrt_work_32, + CAN_FIRE_RL_int_sqrt_work_33, + CAN_FIRE_RL_int_sqrt_work_34, + CAN_FIRE_RL_int_sqrt_work_35, + CAN_FIRE_RL_int_sqrt_work_36, + CAN_FIRE_RL_int_sqrt_work_37, + CAN_FIRE_RL_int_sqrt_work_38, + CAN_FIRE_RL_int_sqrt_work_39, + CAN_FIRE_RL_int_sqrt_work_4, + CAN_FIRE_RL_int_sqrt_work_40, + CAN_FIRE_RL_int_sqrt_work_41, + CAN_FIRE_RL_int_sqrt_work_42, + CAN_FIRE_RL_int_sqrt_work_43, + CAN_FIRE_RL_int_sqrt_work_44, + CAN_FIRE_RL_int_sqrt_work_45, + CAN_FIRE_RL_int_sqrt_work_46, + CAN_FIRE_RL_int_sqrt_work_47, + CAN_FIRE_RL_int_sqrt_work_48, + CAN_FIRE_RL_int_sqrt_work_49, + CAN_FIRE_RL_int_sqrt_work_5, + CAN_FIRE_RL_int_sqrt_work_50, + CAN_FIRE_RL_int_sqrt_work_51, + CAN_FIRE_RL_int_sqrt_work_52, + CAN_FIRE_RL_int_sqrt_work_53, + CAN_FIRE_RL_int_sqrt_work_54, + CAN_FIRE_RL_int_sqrt_work_55, + CAN_FIRE_RL_int_sqrt_work_56, + CAN_FIRE_RL_int_sqrt_work_57, + CAN_FIRE_RL_int_sqrt_work_58, + CAN_FIRE_RL_int_sqrt_work_6, + CAN_FIRE_RL_int_sqrt_work_7, + CAN_FIRE_RL_int_sqrt_work_8, + CAN_FIRE_RL_int_sqrt_work_9, + CAN_FIRE_request_put, CAN_FIRE_response_get, + WILL_FIRE_RL_fpu_s1_stage, + WILL_FIRE_RL_fpu_s2_stage, + WILL_FIRE_RL_fpu_s3_stage, + WILL_FIRE_RL_fpu_s4_stage, + WILL_FIRE_RL_fpu_s5_stage, + WILL_FIRE_RL_int_sqrt_finish, + WILL_FIRE_RL_int_sqrt_start, + WILL_FIRE_RL_int_sqrt_work, + WILL_FIRE_RL_int_sqrt_work_1, + WILL_FIRE_RL_int_sqrt_work_10, + WILL_FIRE_RL_int_sqrt_work_11, + WILL_FIRE_RL_int_sqrt_work_12, + WILL_FIRE_RL_int_sqrt_work_13, + WILL_FIRE_RL_int_sqrt_work_14, + WILL_FIRE_RL_int_sqrt_work_15, + WILL_FIRE_RL_int_sqrt_work_16, + WILL_FIRE_RL_int_sqrt_work_17, + WILL_FIRE_RL_int_sqrt_work_18, + WILL_FIRE_RL_int_sqrt_work_19, + WILL_FIRE_RL_int_sqrt_work_2, + WILL_FIRE_RL_int_sqrt_work_20, + WILL_FIRE_RL_int_sqrt_work_21, + WILL_FIRE_RL_int_sqrt_work_22, + WILL_FIRE_RL_int_sqrt_work_23, + WILL_FIRE_RL_int_sqrt_work_24, + WILL_FIRE_RL_int_sqrt_work_25, + WILL_FIRE_RL_int_sqrt_work_26, + WILL_FIRE_RL_int_sqrt_work_27, + WILL_FIRE_RL_int_sqrt_work_28, + WILL_FIRE_RL_int_sqrt_work_29, + WILL_FIRE_RL_int_sqrt_work_3, + WILL_FIRE_RL_int_sqrt_work_30, + WILL_FIRE_RL_int_sqrt_work_31, + WILL_FIRE_RL_int_sqrt_work_32, + WILL_FIRE_RL_int_sqrt_work_33, + WILL_FIRE_RL_int_sqrt_work_34, + WILL_FIRE_RL_int_sqrt_work_35, + WILL_FIRE_RL_int_sqrt_work_36, + WILL_FIRE_RL_int_sqrt_work_37, + WILL_FIRE_RL_int_sqrt_work_38, + WILL_FIRE_RL_int_sqrt_work_39, + WILL_FIRE_RL_int_sqrt_work_4, + WILL_FIRE_RL_int_sqrt_work_40, + WILL_FIRE_RL_int_sqrt_work_41, + WILL_FIRE_RL_int_sqrt_work_42, + WILL_FIRE_RL_int_sqrt_work_43, + WILL_FIRE_RL_int_sqrt_work_44, + WILL_FIRE_RL_int_sqrt_work_45, + WILL_FIRE_RL_int_sqrt_work_46, + WILL_FIRE_RL_int_sqrt_work_47, + WILL_FIRE_RL_int_sqrt_work_48, + WILL_FIRE_RL_int_sqrt_work_49, + WILL_FIRE_RL_int_sqrt_work_5, + WILL_FIRE_RL_int_sqrt_work_50, + WILL_FIRE_RL_int_sqrt_work_51, + WILL_FIRE_RL_int_sqrt_work_52, + WILL_FIRE_RL_int_sqrt_work_53, + WILL_FIRE_RL_int_sqrt_work_54, + WILL_FIRE_RL_int_sqrt_work_55, + WILL_FIRE_RL_int_sqrt_work_56, + WILL_FIRE_RL_int_sqrt_work_57, + WILL_FIRE_RL_int_sqrt_work_58, + WILL_FIRE_RL_int_sqrt_work_6, + WILL_FIRE_RL_int_sqrt_work_7, + WILL_FIRE_RL_int_sqrt_work_8, + WILL_FIRE_RL_int_sqrt_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; + // remaining internal signals + reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15; + reg [62 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11; + reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, + _theResult___fst_sfd__h76507; + reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4, + _theResult___fst_exp__h76506; + reg CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10; + wire [194 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477; + wire [115 : 0] _theResult___snd_fst__h25299, + _theResult___snd_fst__h25701, + _theResult___snd_fst__h26101, + _theResult___snd_fst__h26501, + _theResult___snd_fst__h26901, + _theResult___snd_fst__h27301, + _theResult___snd_fst__h27701, + _theResult___snd_fst__h28101, + _theResult___snd_fst__h28501, + _theResult___snd_fst__h28901, + _theResult___snd_fst__h29301, + _theResult___snd_fst__h29701, + _theResult___snd_fst__h30101, + _theResult___snd_fst__h30501, + _theResult___snd_fst__h30901, + _theResult___snd_fst__h31301, + _theResult___snd_fst__h31701, + _theResult___snd_fst__h32101, + _theResult___snd_fst__h32501, + _theResult___snd_fst__h32901, + _theResult___snd_fst__h33301, + _theResult___snd_fst__h33701, + _theResult___snd_fst__h34101, + _theResult___snd_fst__h34501, + _theResult___snd_fst__h34901, + _theResult___snd_fst__h35301, + _theResult___snd_fst__h35701, + _theResult___snd_fst__h36101, + _theResult___snd_fst__h36501, + _theResult___snd_fst__h36901, + _theResult___snd_fst__h37301, + _theResult___snd_fst__h37701, + _theResult___snd_fst__h38101, + _theResult___snd_fst__h38501, + _theResult___snd_fst__h38901, + _theResult___snd_fst__h39301, + _theResult___snd_fst__h39701, + _theResult___snd_fst__h40101, + _theResult___snd_fst__h40501, + _theResult___snd_fst__h40901, + _theResult___snd_fst__h41301, + _theResult___snd_fst__h41701, + _theResult___snd_fst__h42101, + _theResult___snd_fst__h42501, + _theResult___snd_fst__h42901, + _theResult___snd_fst__h43301, + _theResult___snd_fst__h43701, + _theResult___snd_fst__h44101, + _theResult___snd_fst__h44501, + _theResult___snd_fst__h44901, + _theResult___snd_fst__h45301, + _theResult___snd_fst__h45701, + _theResult___snd_fst__h46101, + _theResult___snd_fst__h46501, + _theResult___snd_fst__h46901, + _theResult___snd_fst__h47301, + _theResult___snd_fst__h47701, + _theResult___snd_fst__h48101, + _theResult___snd_fst__h48501, + _theResult___snd_snd__h25377, + _theResult___snd_snd__h25777, + _theResult___snd_snd__h26177, + _theResult___snd_snd__h26577, + _theResult___snd_snd__h26977, + _theResult___snd_snd__h27377, + _theResult___snd_snd__h27777, + _theResult___snd_snd__h28177, + _theResult___snd_snd__h28577, + _theResult___snd_snd__h28977, + _theResult___snd_snd__h29377, + _theResult___snd_snd__h29777, + _theResult___snd_snd__h30177, + _theResult___snd_snd__h30577, + _theResult___snd_snd__h30977, + _theResult___snd_snd__h31377, + _theResult___snd_snd__h31777, + _theResult___snd_snd__h32177, + _theResult___snd_snd__h32577, + _theResult___snd_snd__h32977, + _theResult___snd_snd__h33377, + _theResult___snd_snd__h33777, + _theResult___snd_snd__h34177, + _theResult___snd_snd__h34577, + _theResult___snd_snd__h34977, + _theResult___snd_snd__h35377, + _theResult___snd_snd__h35777, + _theResult___snd_snd__h36177, + _theResult___snd_snd__h36577, + _theResult___snd_snd__h36977, + _theResult___snd_snd__h37377, + _theResult___snd_snd__h37777, + _theResult___snd_snd__h38177, + _theResult___snd_snd__h38577, + _theResult___snd_snd__h38977, + _theResult___snd_snd__h39377, + _theResult___snd_snd__h39777, + _theResult___snd_snd__h40177, + _theResult___snd_snd__h40577, + _theResult___snd_snd__h40977, + _theResult___snd_snd__h41377, + _theResult___snd_snd__h41777, + _theResult___snd_snd__h42177, + _theResult___snd_snd__h42577, + _theResult___snd_snd__h42977, + _theResult___snd_snd__h43377, + _theResult___snd_snd__h43777, + _theResult___snd_snd__h44177, + _theResult___snd_snd__h44577, + _theResult___snd_snd__h44977, + _theResult___snd_snd__h45377, + _theResult___snd_snd__h45777, + _theResult___snd_snd__h46177, + _theResult___snd_snd__h46577, + _theResult___snd_snd__h46977, + _theResult___snd_snd__h47377, + _theResult___snd_snd__h47777, + _theResult___snd_snd__h48177, + _theResult___snd_snd__h48577, + b___1__h16687, + b__h25374, + b__h25774, + b__h26174, + b__h26574, + b__h26974, + b__h27374, + b__h27774, + b__h28174, + b__h28574, + b__h28974, + b__h29374, + b__h29774, + b__h30174, + b__h30574, + b__h30974, + b__h31374, + b__h31774, + b__h32174, + b__h32574, + b__h32974, + b__h33374, + b__h33774, + b__h34174, + b__h34574, + b__h34974, + b__h35374, + b__h35774, + b__h36174, + b__h36574, + b__h36974, + b__h37374, + b__h37774, + b__h38174, + b__h38574, + b__h38974, + b__h39374, + b__h39774, + b__h40174, + b__h40574, + b__h40974, + b__h41374, + b__h41774, + b__h42174, + b__h42574, + b__h42974, + b__h43374, + b__h43774, + b__h44174, + b__h44574, + b__h44974, + b__h45374, + b__h45774, + b__h46174, + b__h46574, + b__h46974, + b__h47374, + b__h47774, + b__h48174, + b__h48574, + b__h48712, + r__h25386, + r__h25394, + r__h25786, + r__h25794, + r__h26186, + r__h26194, + r__h26586, + r__h26594, + r__h26986, + r__h26994, + r__h27386, + r__h27394, + r__h27786, + r__h27794, + r__h28186, + r__h28194, + r__h28586, + r__h28594, + r__h28986, + r__h28994, + r__h29386, + r__h29394, + r__h29786, + r__h29794, + r__h30186, + r__h30194, + r__h30586, + r__h30594, + r__h30986, + r__h30994, + r__h31386, + r__h31394, + r__h31786, + r__h31794, + r__h32186, + r__h32194, + r__h32586, + r__h32594, + r__h32986, + r__h32994, + r__h33386, + r__h33394, + r__h33786, + r__h33794, + r__h34186, + r__h34194, + r__h34586, + r__h34594, + r__h34986, + r__h34994, + r__h35386, + r__h35394, + r__h35786, + r__h35794, + r__h36186, + r__h36194, + r__h36586, + r__h36594, + r__h36986, + r__h36994, + r__h37386, + r__h37394, + r__h37786, + r__h37794, + r__h38186, + r__h38194, + r__h38586, + r__h38594, + r__h38986, + r__h38994, + r__h39386, + r__h39394, + r__h39786, + r__h39794, + r__h40186, + r__h40194, + r__h40586, + r__h40594, + r__h40986, + r__h40994, + r__h41386, + r__h41394, + r__h41786, + r__h41794, + r__h42186, + r__h42194, + r__h42586, + r__h42594, + r__h42986, + r__h42994, + r__h43386, + r__h43394, + r__h43786, + r__h43794, + r__h44186, + r__h44194, + r__h44586, + r__h44594, + r__h44986, + r__h44994, + r__h45386, + r__h45394, + r__h45786, + r__h45794, + r__h46186, + r__h46194, + r__h46586, + r__h46594, + r__h46986, + r__h46994, + r__h47386, + r__h47394, + r__h47786, + r__h47794, + r__h48186, + r__h48194, + r__h48586, + r__h48594, + s__h25385, + s__h25785, + s__h26185, + s__h26585, + s__h26985, + s__h27385, + s__h27785, + s__h28185, + s__h28585, + s__h28985, + s__h29385, + s__h29785, + s__h30185, + s__h30585, + s__h30985, + s__h31385, + s__h31785, + s__h32185, + s__h32585, + s__h32985, + s__h33385, + s__h33785, + s__h34185, + s__h34585, + s__h34985, + s__h35385, + s__h35785, + s__h36185, + s__h36585, + s__h36985, + s__h37385, + s__h37785, + s__h38185, + s__h38585, + s__h38985, + s__h39385, + s__h39785, + s__h40185, + s__h40585, + s__h40985, + s__h41385, + s__h41785, + s__h42185, + s__h42585, + s__h42985, + s__h43385, + s__h43785, + s__h44185, + s__h44585, + s__h44985, + s__h45385, + s__h45785, + s__h46185, + s__h46585, + s__h46985, + s__h47385, + s__h47785, + s__h48185, + s__h48585, + sum__h25372, + sum__h25772, + sum__h26172, + sum__h26572, + sum__h26972, + sum__h27372, + sum__h27772, + sum__h28172, + sum__h28572, + sum__h28972, + sum__h29372, + sum__h29772, + sum__h30172, + sum__h30572, + sum__h30972, + sum__h31372, + sum__h31772, + sum__h32172, + sum__h32572, + sum__h32972, + sum__h33372, + sum__h33772, + sum__h34172, + sum__h34572, + sum__h34972, + sum__h35372, + sum__h35772, + sum__h36172, + sum__h36572, + sum__h36972, + sum__h37372, + sum__h37772, + sum__h38172, + sum__h38572, + sum__h38972, + sum__h39372, + sum__h39772, + sum__h40172, + sum__h40572, + sum__h40972, + sum__h41372, + sum__h41772, + sum__h42172, + sum__h42572, + sum__h42972, + sum__h43372, + sum__h43772, + sum__h44172, + sum__h44572, + sum__h44972, + sum__h45372, + sum__h45772, + sum__h46172, + sum__h46572, + sum__h46972, + sum__h47372, + sum__h47772, + sum__h48172, + sum__h48572, + x__h402; + wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866, + IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820; + wire [58 : 0] IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6, + _theResult___snd__h75283, + _theResult___snd__h75298, + _theResult___snd__h75300, + _theResult___snd__h75313, + _theResult___snd__h75319, + _theResult___snd__h75337, + _theResult___snd__h75342, + result__h66451, + sfdin__h75260, + x__h66665; + wire [57 : 0] sfd___1__h65692, sfd__h49936, sfd__h49938, x__h65683; + wire [53 : 0] sfd__h75932, value__h58164; + wire [51 : 0] _theResult___fst_sfd__h76510, + _theResult___sfd__h76429, + out_sfd__h76432, + sfd__h49989; + wire [12 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460, + x__h57541, + x__h57559; + wire [11 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9, + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531, + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774; + wire [10 : 0] IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, + _theResult___exp__h76428, + _theResult___fst_exp__h75266, + _theResult___fst_exp__h75269, + _theResult___fst_exp__h75289, + _theResult___fst_exp__h75305, + _theResult___fst_exp__h75344, + _theResult___fst_exp__h75350, + _theResult___fst_exp__h75353, + _theResult___fst_exp__h76509, + din_inc___2_exp__h76519, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8, + fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5, + out_exp__h76431; + wire [6 : 0] IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237, + x__h24992; + wire [5 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458, + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772, + x__h65722; + wire [2 : 0] IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813; + wire [1 : 0] IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7, + _theResult___snd_fst__h75372, + guard__h66951, + x__h75654; + wire _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775, + int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264, + int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299, + int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649, + int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684, + int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719, + int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754, + int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789, + int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824, + int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859, + int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894, + int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929, + int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964, + int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334, + int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999, + int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034, + int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069, + int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104, + int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139, + int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174, + int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209, + int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244, + int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279, + int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314, + int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369, + int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349, + int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384, + int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419, + int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454, + int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489, + int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524, + int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559, + int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594, + int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629, + int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664, + int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404, + int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699, + int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734, + int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769, + int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804, + int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839, + int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874, + int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909, + int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944, + int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979, + int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014, + int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439, + int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049, + int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084, + int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119, + int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154, + int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189, + int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224, + int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259, + int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294, + int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474, + int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509, + int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544, + int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579, + int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614, + value_BIT_52___h58260; + // action method request_put - assign RDY_request_put = fpu$RDY_request_put ; - assign CAN_FIRE_request_put = fpu$RDY_request_put ; + assign RDY_request_put = fpu_fOperand_S0$FULL_N ; + assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu$response_get ; - assign RDY_response_get = fpu$RDY_response_get ; - assign CAN_FIRE_response_get = fpu$RDY_response_get ; + assign response_get = fpu_fResult_S5$D_OUT ; + assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; + assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu - mkXilinxFpSqrt fpu(.CLK(CLK), - .RST_N(RST_N), - .request_put(fpu$request_put), - .EN_request_put(fpu$EN_request_put), - .EN_response_get(fpu$EN_response_get), - .RDY_request_put(fpu$RDY_request_put), - .response_get(fpu$response_get), - .RDY_response_get(fpu$RDY_response_get)); + // submodule fpu_fOperand_S0 + FIFOL1 #(.width(32'd67)) fpu_fOperand_S0(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fOperand_S0$D_IN), + .ENQ(fpu_fOperand_S0$ENQ), + .DEQ(fpu_fOperand_S0$DEQ), + .CLR(fpu_fOperand_S0$CLR), + .D_OUT(fpu_fOperand_S0$D_OUT), + .FULL_N(fpu_fOperand_S0$FULL_N), + .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); - // submodule fpu - assign fpu$request_put = request_put ; - assign fpu$EN_request_put = EN_request_put ; - assign fpu$EN_response_get = EN_response_get ; + // submodule fpu_fResult_S5 + FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fResult_S5$D_IN), + .ENQ(fpu_fResult_S5$ENQ), + .DEQ(fpu_fResult_S5$DEQ), + .CLR(fpu_fResult_S5$CLR), + .D_OUT(fpu_fResult_S5$D_OUT), + .FULL_N(fpu_fResult_S5$FULL_N), + .EMPTY_N(fpu_fResult_S5$EMPTY_N)); + + // submodule fpu_fState_S1 + FIFOL1 #(.width(32'd195)) fpu_fState_S1(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S1$D_IN), + .ENQ(fpu_fState_S1$ENQ), + .DEQ(fpu_fState_S1$DEQ), + .CLR(fpu_fState_S1$CLR), + .D_OUT(fpu_fState_S1$D_OUT), + .FULL_N(fpu_fState_S1$FULL_N), + .EMPTY_N(fpu_fState_S1$EMPTY_N)); + + // submodule fpu_fState_S2 + FIFOL1 #(.width(32'd137)) fpu_fState_S2(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S2$D_IN), + .ENQ(fpu_fState_S2$ENQ), + .DEQ(fpu_fState_S2$DEQ), + .CLR(fpu_fState_S2$CLR), + .D_OUT(fpu_fState_S2$D_OUT), + .FULL_N(fpu_fState_S2$FULL_N), + .EMPTY_N(fpu_fState_S2$EMPTY_N)); + + // submodule fpu_fState_S3 + FIFOL1 #(.width(32'd196)) fpu_fState_S3(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S3$D_IN), + .ENQ(fpu_fState_S3$ENQ), + .DEQ(fpu_fState_S3$DEQ), + .CLR(fpu_fState_S3$CLR), + .D_OUT(fpu_fState_S3$D_OUT), + .FULL_N(fpu_fState_S3$FULL_N), + .EMPTY_N(fpu_fState_S3$EMPTY_N)); + + // submodule fpu_fState_S4 + FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), + .CLK(CLK), + .D_IN(fpu_fState_S4$D_IN), + .ENQ(fpu_fState_S4$ENQ), + .DEQ(fpu_fState_S4$DEQ), + .CLR(fpu_fState_S4$CLR), + .D_OUT(fpu_fState_S4$D_OUT), + .FULL_N(fpu_fState_S4$FULL_N), + .EMPTY_N(fpu_fState_S4$EMPTY_N)); + + // submodule int_sqrt_fFirst + FIFOL1 #(.width(32'd465)) int_sqrt_fFirst(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fFirst$D_IN), + .ENQ(int_sqrt_fFirst$ENQ), + .DEQ(int_sqrt_fFirst$DEQ), + .CLR(int_sqrt_fFirst$CLR), + .D_OUT(int_sqrt_fFirst$D_OUT), + .FULL_N(int_sqrt_fFirst$FULL_N), + .EMPTY_N(int_sqrt_fFirst$EMPTY_N)); + + // submodule int_sqrt_fNext_0 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_0(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_0$D_IN), + .ENQ(int_sqrt_fNext_0$ENQ), + .DEQ(int_sqrt_fNext_0$DEQ), + .CLR(int_sqrt_fNext_0$CLR), + .D_OUT(int_sqrt_fNext_0$D_OUT), + .FULL_N(int_sqrt_fNext_0$FULL_N), + .EMPTY_N(int_sqrt_fNext_0$EMPTY_N)); + + // submodule int_sqrt_fNext_1 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_1(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_1$D_IN), + .ENQ(int_sqrt_fNext_1$ENQ), + .DEQ(int_sqrt_fNext_1$DEQ), + .CLR(int_sqrt_fNext_1$CLR), + .D_OUT(int_sqrt_fNext_1$D_OUT), + .FULL_N(int_sqrt_fNext_1$FULL_N), + .EMPTY_N(int_sqrt_fNext_1$EMPTY_N)); + + // submodule int_sqrt_fNext_10 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_10(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_10$D_IN), + .ENQ(int_sqrt_fNext_10$ENQ), + .DEQ(int_sqrt_fNext_10$DEQ), + .CLR(int_sqrt_fNext_10$CLR), + .D_OUT(int_sqrt_fNext_10$D_OUT), + .FULL_N(int_sqrt_fNext_10$FULL_N), + .EMPTY_N(int_sqrt_fNext_10$EMPTY_N)); + + // submodule int_sqrt_fNext_11 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_11(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_11$D_IN), + .ENQ(int_sqrt_fNext_11$ENQ), + .DEQ(int_sqrt_fNext_11$DEQ), + .CLR(int_sqrt_fNext_11$CLR), + .D_OUT(int_sqrt_fNext_11$D_OUT), + .FULL_N(int_sqrt_fNext_11$FULL_N), + .EMPTY_N(int_sqrt_fNext_11$EMPTY_N)); + + // submodule int_sqrt_fNext_12 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_12(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_12$D_IN), + .ENQ(int_sqrt_fNext_12$ENQ), + .DEQ(int_sqrt_fNext_12$DEQ), + .CLR(int_sqrt_fNext_12$CLR), + .D_OUT(int_sqrt_fNext_12$D_OUT), + .FULL_N(int_sqrt_fNext_12$FULL_N), + .EMPTY_N(int_sqrt_fNext_12$EMPTY_N)); + + // submodule int_sqrt_fNext_13 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_13(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_13$D_IN), + .ENQ(int_sqrt_fNext_13$ENQ), + .DEQ(int_sqrt_fNext_13$DEQ), + .CLR(int_sqrt_fNext_13$CLR), + .D_OUT(int_sqrt_fNext_13$D_OUT), + .FULL_N(int_sqrt_fNext_13$FULL_N), + .EMPTY_N(int_sqrt_fNext_13$EMPTY_N)); + + // submodule int_sqrt_fNext_14 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_14(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_14$D_IN), + .ENQ(int_sqrt_fNext_14$ENQ), + .DEQ(int_sqrt_fNext_14$DEQ), + .CLR(int_sqrt_fNext_14$CLR), + .D_OUT(int_sqrt_fNext_14$D_OUT), + .FULL_N(int_sqrt_fNext_14$FULL_N), + .EMPTY_N(int_sqrt_fNext_14$EMPTY_N)); + + // submodule int_sqrt_fNext_15 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_15(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_15$D_IN), + .ENQ(int_sqrt_fNext_15$ENQ), + .DEQ(int_sqrt_fNext_15$DEQ), + .CLR(int_sqrt_fNext_15$CLR), + .D_OUT(int_sqrt_fNext_15$D_OUT), + .FULL_N(int_sqrt_fNext_15$FULL_N), + .EMPTY_N(int_sqrt_fNext_15$EMPTY_N)); + + // submodule int_sqrt_fNext_16 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_16(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_16$D_IN), + .ENQ(int_sqrt_fNext_16$ENQ), + .DEQ(int_sqrt_fNext_16$DEQ), + .CLR(int_sqrt_fNext_16$CLR), + .D_OUT(int_sqrt_fNext_16$D_OUT), + .FULL_N(int_sqrt_fNext_16$FULL_N), + .EMPTY_N(int_sqrt_fNext_16$EMPTY_N)); + + // submodule int_sqrt_fNext_17 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_17(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_17$D_IN), + .ENQ(int_sqrt_fNext_17$ENQ), + .DEQ(int_sqrt_fNext_17$DEQ), + .CLR(int_sqrt_fNext_17$CLR), + .D_OUT(int_sqrt_fNext_17$D_OUT), + .FULL_N(int_sqrt_fNext_17$FULL_N), + .EMPTY_N(int_sqrt_fNext_17$EMPTY_N)); + + // submodule int_sqrt_fNext_18 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_18(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_18$D_IN), + .ENQ(int_sqrt_fNext_18$ENQ), + .DEQ(int_sqrt_fNext_18$DEQ), + .CLR(int_sqrt_fNext_18$CLR), + .D_OUT(int_sqrt_fNext_18$D_OUT), + .FULL_N(int_sqrt_fNext_18$FULL_N), + .EMPTY_N(int_sqrt_fNext_18$EMPTY_N)); + + // submodule int_sqrt_fNext_19 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_19(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_19$D_IN), + .ENQ(int_sqrt_fNext_19$ENQ), + .DEQ(int_sqrt_fNext_19$DEQ), + .CLR(int_sqrt_fNext_19$CLR), + .D_OUT(int_sqrt_fNext_19$D_OUT), + .FULL_N(int_sqrt_fNext_19$FULL_N), + .EMPTY_N(int_sqrt_fNext_19$EMPTY_N)); + + // submodule int_sqrt_fNext_2 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_2(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_2$D_IN), + .ENQ(int_sqrt_fNext_2$ENQ), + .DEQ(int_sqrt_fNext_2$DEQ), + .CLR(int_sqrt_fNext_2$CLR), + .D_OUT(int_sqrt_fNext_2$D_OUT), + .FULL_N(int_sqrt_fNext_2$FULL_N), + .EMPTY_N(int_sqrt_fNext_2$EMPTY_N)); + + // submodule int_sqrt_fNext_20 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_20(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_20$D_IN), + .ENQ(int_sqrt_fNext_20$ENQ), + .DEQ(int_sqrt_fNext_20$DEQ), + .CLR(int_sqrt_fNext_20$CLR), + .D_OUT(int_sqrt_fNext_20$D_OUT), + .FULL_N(int_sqrt_fNext_20$FULL_N), + .EMPTY_N(int_sqrt_fNext_20$EMPTY_N)); + + // submodule int_sqrt_fNext_21 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_21(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_21$D_IN), + .ENQ(int_sqrt_fNext_21$ENQ), + .DEQ(int_sqrt_fNext_21$DEQ), + .CLR(int_sqrt_fNext_21$CLR), + .D_OUT(int_sqrt_fNext_21$D_OUT), + .FULL_N(int_sqrt_fNext_21$FULL_N), + .EMPTY_N(int_sqrt_fNext_21$EMPTY_N)); + + // submodule int_sqrt_fNext_22 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_22(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_22$D_IN), + .ENQ(int_sqrt_fNext_22$ENQ), + .DEQ(int_sqrt_fNext_22$DEQ), + .CLR(int_sqrt_fNext_22$CLR), + .D_OUT(int_sqrt_fNext_22$D_OUT), + .FULL_N(int_sqrt_fNext_22$FULL_N), + .EMPTY_N(int_sqrt_fNext_22$EMPTY_N)); + + // submodule int_sqrt_fNext_23 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_23(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_23$D_IN), + .ENQ(int_sqrt_fNext_23$ENQ), + .DEQ(int_sqrt_fNext_23$DEQ), + .CLR(int_sqrt_fNext_23$CLR), + .D_OUT(int_sqrt_fNext_23$D_OUT), + .FULL_N(int_sqrt_fNext_23$FULL_N), + .EMPTY_N(int_sqrt_fNext_23$EMPTY_N)); + + // submodule int_sqrt_fNext_24 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_24(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_24$D_IN), + .ENQ(int_sqrt_fNext_24$ENQ), + .DEQ(int_sqrt_fNext_24$DEQ), + .CLR(int_sqrt_fNext_24$CLR), + .D_OUT(int_sqrt_fNext_24$D_OUT), + .FULL_N(int_sqrt_fNext_24$FULL_N), + .EMPTY_N(int_sqrt_fNext_24$EMPTY_N)); + + // submodule int_sqrt_fNext_25 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_25(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_25$D_IN), + .ENQ(int_sqrt_fNext_25$ENQ), + .DEQ(int_sqrt_fNext_25$DEQ), + .CLR(int_sqrt_fNext_25$CLR), + .D_OUT(int_sqrt_fNext_25$D_OUT), + .FULL_N(int_sqrt_fNext_25$FULL_N), + .EMPTY_N(int_sqrt_fNext_25$EMPTY_N)); + + // submodule int_sqrt_fNext_26 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_26(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_26$D_IN), + .ENQ(int_sqrt_fNext_26$ENQ), + .DEQ(int_sqrt_fNext_26$DEQ), + .CLR(int_sqrt_fNext_26$CLR), + .D_OUT(int_sqrt_fNext_26$D_OUT), + .FULL_N(int_sqrt_fNext_26$FULL_N), + .EMPTY_N(int_sqrt_fNext_26$EMPTY_N)); + + // submodule int_sqrt_fNext_27 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_27(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_27$D_IN), + .ENQ(int_sqrt_fNext_27$ENQ), + .DEQ(int_sqrt_fNext_27$DEQ), + .CLR(int_sqrt_fNext_27$CLR), + .D_OUT(int_sqrt_fNext_27$D_OUT), + .FULL_N(int_sqrt_fNext_27$FULL_N), + .EMPTY_N(int_sqrt_fNext_27$EMPTY_N)); + + // submodule int_sqrt_fNext_28 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_28(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_28$D_IN), + .ENQ(int_sqrt_fNext_28$ENQ), + .DEQ(int_sqrt_fNext_28$DEQ), + .CLR(int_sqrt_fNext_28$CLR), + .D_OUT(int_sqrt_fNext_28$D_OUT), + .FULL_N(int_sqrt_fNext_28$FULL_N), + .EMPTY_N(int_sqrt_fNext_28$EMPTY_N)); + + // submodule int_sqrt_fNext_29 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_29(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_29$D_IN), + .ENQ(int_sqrt_fNext_29$ENQ), + .DEQ(int_sqrt_fNext_29$DEQ), + .CLR(int_sqrt_fNext_29$CLR), + .D_OUT(int_sqrt_fNext_29$D_OUT), + .FULL_N(int_sqrt_fNext_29$FULL_N), + .EMPTY_N(int_sqrt_fNext_29$EMPTY_N)); + + // submodule int_sqrt_fNext_3 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_3(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_3$D_IN), + .ENQ(int_sqrt_fNext_3$ENQ), + .DEQ(int_sqrt_fNext_3$DEQ), + .CLR(int_sqrt_fNext_3$CLR), + .D_OUT(int_sqrt_fNext_3$D_OUT), + .FULL_N(int_sqrt_fNext_3$FULL_N), + .EMPTY_N(int_sqrt_fNext_3$EMPTY_N)); + + // submodule int_sqrt_fNext_30 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_30(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_30$D_IN), + .ENQ(int_sqrt_fNext_30$ENQ), + .DEQ(int_sqrt_fNext_30$DEQ), + .CLR(int_sqrt_fNext_30$CLR), + .D_OUT(int_sqrt_fNext_30$D_OUT), + .FULL_N(int_sqrt_fNext_30$FULL_N), + .EMPTY_N(int_sqrt_fNext_30$EMPTY_N)); + + // submodule int_sqrt_fNext_31 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_31(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_31$D_IN), + .ENQ(int_sqrt_fNext_31$ENQ), + .DEQ(int_sqrt_fNext_31$DEQ), + .CLR(int_sqrt_fNext_31$CLR), + .D_OUT(int_sqrt_fNext_31$D_OUT), + .FULL_N(int_sqrt_fNext_31$FULL_N), + .EMPTY_N(int_sqrt_fNext_31$EMPTY_N)); + + // submodule int_sqrt_fNext_32 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_32(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_32$D_IN), + .ENQ(int_sqrt_fNext_32$ENQ), + .DEQ(int_sqrt_fNext_32$DEQ), + .CLR(int_sqrt_fNext_32$CLR), + .D_OUT(int_sqrt_fNext_32$D_OUT), + .FULL_N(int_sqrt_fNext_32$FULL_N), + .EMPTY_N(int_sqrt_fNext_32$EMPTY_N)); + + // submodule int_sqrt_fNext_33 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_33(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_33$D_IN), + .ENQ(int_sqrt_fNext_33$ENQ), + .DEQ(int_sqrt_fNext_33$DEQ), + .CLR(int_sqrt_fNext_33$CLR), + .D_OUT(int_sqrt_fNext_33$D_OUT), + .FULL_N(int_sqrt_fNext_33$FULL_N), + .EMPTY_N(int_sqrt_fNext_33$EMPTY_N)); + + // submodule int_sqrt_fNext_34 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_34(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_34$D_IN), + .ENQ(int_sqrt_fNext_34$ENQ), + .DEQ(int_sqrt_fNext_34$DEQ), + .CLR(int_sqrt_fNext_34$CLR), + .D_OUT(int_sqrt_fNext_34$D_OUT), + .FULL_N(int_sqrt_fNext_34$FULL_N), + .EMPTY_N(int_sqrt_fNext_34$EMPTY_N)); + + // submodule int_sqrt_fNext_35 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_35(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_35$D_IN), + .ENQ(int_sqrt_fNext_35$ENQ), + .DEQ(int_sqrt_fNext_35$DEQ), + .CLR(int_sqrt_fNext_35$CLR), + .D_OUT(int_sqrt_fNext_35$D_OUT), + .FULL_N(int_sqrt_fNext_35$FULL_N), + .EMPTY_N(int_sqrt_fNext_35$EMPTY_N)); + + // submodule int_sqrt_fNext_36 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_36(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_36$D_IN), + .ENQ(int_sqrt_fNext_36$ENQ), + .DEQ(int_sqrt_fNext_36$DEQ), + .CLR(int_sqrt_fNext_36$CLR), + .D_OUT(int_sqrt_fNext_36$D_OUT), + .FULL_N(int_sqrt_fNext_36$FULL_N), + .EMPTY_N(int_sqrt_fNext_36$EMPTY_N)); + + // submodule int_sqrt_fNext_37 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_37(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_37$D_IN), + .ENQ(int_sqrt_fNext_37$ENQ), + .DEQ(int_sqrt_fNext_37$DEQ), + .CLR(int_sqrt_fNext_37$CLR), + .D_OUT(int_sqrt_fNext_37$D_OUT), + .FULL_N(int_sqrt_fNext_37$FULL_N), + .EMPTY_N(int_sqrt_fNext_37$EMPTY_N)); + + // submodule int_sqrt_fNext_38 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_38(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_38$D_IN), + .ENQ(int_sqrt_fNext_38$ENQ), + .DEQ(int_sqrt_fNext_38$DEQ), + .CLR(int_sqrt_fNext_38$CLR), + .D_OUT(int_sqrt_fNext_38$D_OUT), + .FULL_N(int_sqrt_fNext_38$FULL_N), + .EMPTY_N(int_sqrt_fNext_38$EMPTY_N)); + + // submodule int_sqrt_fNext_39 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_39(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_39$D_IN), + .ENQ(int_sqrt_fNext_39$ENQ), + .DEQ(int_sqrt_fNext_39$DEQ), + .CLR(int_sqrt_fNext_39$CLR), + .D_OUT(int_sqrt_fNext_39$D_OUT), + .FULL_N(int_sqrt_fNext_39$FULL_N), + .EMPTY_N(int_sqrt_fNext_39$EMPTY_N)); + + // submodule int_sqrt_fNext_4 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_4(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_4$D_IN), + .ENQ(int_sqrt_fNext_4$ENQ), + .DEQ(int_sqrt_fNext_4$DEQ), + .CLR(int_sqrt_fNext_4$CLR), + .D_OUT(int_sqrt_fNext_4$D_OUT), + .FULL_N(int_sqrt_fNext_4$FULL_N), + .EMPTY_N(int_sqrt_fNext_4$EMPTY_N)); + + // submodule int_sqrt_fNext_40 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_40(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_40$D_IN), + .ENQ(int_sqrt_fNext_40$ENQ), + .DEQ(int_sqrt_fNext_40$DEQ), + .CLR(int_sqrt_fNext_40$CLR), + .D_OUT(int_sqrt_fNext_40$D_OUT), + .FULL_N(int_sqrt_fNext_40$FULL_N), + .EMPTY_N(int_sqrt_fNext_40$EMPTY_N)); + + // submodule int_sqrt_fNext_41 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_41(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_41$D_IN), + .ENQ(int_sqrt_fNext_41$ENQ), + .DEQ(int_sqrt_fNext_41$DEQ), + .CLR(int_sqrt_fNext_41$CLR), + .D_OUT(int_sqrt_fNext_41$D_OUT), + .FULL_N(int_sqrt_fNext_41$FULL_N), + .EMPTY_N(int_sqrt_fNext_41$EMPTY_N)); + + // submodule int_sqrt_fNext_42 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_42(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_42$D_IN), + .ENQ(int_sqrt_fNext_42$ENQ), + .DEQ(int_sqrt_fNext_42$DEQ), + .CLR(int_sqrt_fNext_42$CLR), + .D_OUT(int_sqrt_fNext_42$D_OUT), + .FULL_N(int_sqrt_fNext_42$FULL_N), + .EMPTY_N(int_sqrt_fNext_42$EMPTY_N)); + + // submodule int_sqrt_fNext_43 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_43(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_43$D_IN), + .ENQ(int_sqrt_fNext_43$ENQ), + .DEQ(int_sqrt_fNext_43$DEQ), + .CLR(int_sqrt_fNext_43$CLR), + .D_OUT(int_sqrt_fNext_43$D_OUT), + .FULL_N(int_sqrt_fNext_43$FULL_N), + .EMPTY_N(int_sqrt_fNext_43$EMPTY_N)); + + // submodule int_sqrt_fNext_44 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_44(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_44$D_IN), + .ENQ(int_sqrt_fNext_44$ENQ), + .DEQ(int_sqrt_fNext_44$DEQ), + .CLR(int_sqrt_fNext_44$CLR), + .D_OUT(int_sqrt_fNext_44$D_OUT), + .FULL_N(int_sqrt_fNext_44$FULL_N), + .EMPTY_N(int_sqrt_fNext_44$EMPTY_N)); + + // submodule int_sqrt_fNext_45 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_45(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_45$D_IN), + .ENQ(int_sqrt_fNext_45$ENQ), + .DEQ(int_sqrt_fNext_45$DEQ), + .CLR(int_sqrt_fNext_45$CLR), + .D_OUT(int_sqrt_fNext_45$D_OUT), + .FULL_N(int_sqrt_fNext_45$FULL_N), + .EMPTY_N(int_sqrt_fNext_45$EMPTY_N)); + + // submodule int_sqrt_fNext_46 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_46(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_46$D_IN), + .ENQ(int_sqrt_fNext_46$ENQ), + .DEQ(int_sqrt_fNext_46$DEQ), + .CLR(int_sqrt_fNext_46$CLR), + .D_OUT(int_sqrt_fNext_46$D_OUT), + .FULL_N(int_sqrt_fNext_46$FULL_N), + .EMPTY_N(int_sqrt_fNext_46$EMPTY_N)); + + // submodule int_sqrt_fNext_47 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_47(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_47$D_IN), + .ENQ(int_sqrt_fNext_47$ENQ), + .DEQ(int_sqrt_fNext_47$DEQ), + .CLR(int_sqrt_fNext_47$CLR), + .D_OUT(int_sqrt_fNext_47$D_OUT), + .FULL_N(int_sqrt_fNext_47$FULL_N), + .EMPTY_N(int_sqrt_fNext_47$EMPTY_N)); + + // submodule int_sqrt_fNext_48 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_48(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_48$D_IN), + .ENQ(int_sqrt_fNext_48$ENQ), + .DEQ(int_sqrt_fNext_48$DEQ), + .CLR(int_sqrt_fNext_48$CLR), + .D_OUT(int_sqrt_fNext_48$D_OUT), + .FULL_N(int_sqrt_fNext_48$FULL_N), + .EMPTY_N(int_sqrt_fNext_48$EMPTY_N)); + + // submodule int_sqrt_fNext_49 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_49(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_49$D_IN), + .ENQ(int_sqrt_fNext_49$ENQ), + .DEQ(int_sqrt_fNext_49$DEQ), + .CLR(int_sqrt_fNext_49$CLR), + .D_OUT(int_sqrt_fNext_49$D_OUT), + .FULL_N(int_sqrt_fNext_49$FULL_N), + .EMPTY_N(int_sqrt_fNext_49$EMPTY_N)); + + // submodule int_sqrt_fNext_5 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_5(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_5$D_IN), + .ENQ(int_sqrt_fNext_5$ENQ), + .DEQ(int_sqrt_fNext_5$DEQ), + .CLR(int_sqrt_fNext_5$CLR), + .D_OUT(int_sqrt_fNext_5$D_OUT), + .FULL_N(int_sqrt_fNext_5$FULL_N), + .EMPTY_N(int_sqrt_fNext_5$EMPTY_N)); + + // submodule int_sqrt_fNext_50 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_50(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_50$D_IN), + .ENQ(int_sqrt_fNext_50$ENQ), + .DEQ(int_sqrt_fNext_50$DEQ), + .CLR(int_sqrt_fNext_50$CLR), + .D_OUT(int_sqrt_fNext_50$D_OUT), + .FULL_N(int_sqrt_fNext_50$FULL_N), + .EMPTY_N(int_sqrt_fNext_50$EMPTY_N)); + + // submodule int_sqrt_fNext_51 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_51(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_51$D_IN), + .ENQ(int_sqrt_fNext_51$ENQ), + .DEQ(int_sqrt_fNext_51$DEQ), + .CLR(int_sqrt_fNext_51$CLR), + .D_OUT(int_sqrt_fNext_51$D_OUT), + .FULL_N(int_sqrt_fNext_51$FULL_N), + .EMPTY_N(int_sqrt_fNext_51$EMPTY_N)); + + // submodule int_sqrt_fNext_52 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_52(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_52$D_IN), + .ENQ(int_sqrt_fNext_52$ENQ), + .DEQ(int_sqrt_fNext_52$DEQ), + .CLR(int_sqrt_fNext_52$CLR), + .D_OUT(int_sqrt_fNext_52$D_OUT), + .FULL_N(int_sqrt_fNext_52$FULL_N), + .EMPTY_N(int_sqrt_fNext_52$EMPTY_N)); + + // submodule int_sqrt_fNext_53 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_53(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_53$D_IN), + .ENQ(int_sqrt_fNext_53$ENQ), + .DEQ(int_sqrt_fNext_53$DEQ), + .CLR(int_sqrt_fNext_53$CLR), + .D_OUT(int_sqrt_fNext_53$D_OUT), + .FULL_N(int_sqrt_fNext_53$FULL_N), + .EMPTY_N(int_sqrt_fNext_53$EMPTY_N)); + + // submodule int_sqrt_fNext_54 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_54(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_54$D_IN), + .ENQ(int_sqrt_fNext_54$ENQ), + .DEQ(int_sqrt_fNext_54$DEQ), + .CLR(int_sqrt_fNext_54$CLR), + .D_OUT(int_sqrt_fNext_54$D_OUT), + .FULL_N(int_sqrt_fNext_54$FULL_N), + .EMPTY_N(int_sqrt_fNext_54$EMPTY_N)); + + // submodule int_sqrt_fNext_55 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_55(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_55$D_IN), + .ENQ(int_sqrt_fNext_55$ENQ), + .DEQ(int_sqrt_fNext_55$DEQ), + .CLR(int_sqrt_fNext_55$CLR), + .D_OUT(int_sqrt_fNext_55$D_OUT), + .FULL_N(int_sqrt_fNext_55$FULL_N), + .EMPTY_N(int_sqrt_fNext_55$EMPTY_N)); + + // submodule int_sqrt_fNext_56 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_56(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_56$D_IN), + .ENQ(int_sqrt_fNext_56$ENQ), + .DEQ(int_sqrt_fNext_56$DEQ), + .CLR(int_sqrt_fNext_56$CLR), + .D_OUT(int_sqrt_fNext_56$D_OUT), + .FULL_N(int_sqrt_fNext_56$FULL_N), + .EMPTY_N(int_sqrt_fNext_56$EMPTY_N)); + + // submodule int_sqrt_fNext_57 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_57(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_57$D_IN), + .ENQ(int_sqrt_fNext_57$ENQ), + .DEQ(int_sqrt_fNext_57$DEQ), + .CLR(int_sqrt_fNext_57$CLR), + .D_OUT(int_sqrt_fNext_57$D_OUT), + .FULL_N(int_sqrt_fNext_57$FULL_N), + .EMPTY_N(int_sqrt_fNext_57$EMPTY_N)); + + // submodule int_sqrt_fNext_58 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_58(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_58$D_IN), + .ENQ(int_sqrt_fNext_58$ENQ), + .DEQ(int_sqrt_fNext_58$DEQ), + .CLR(int_sqrt_fNext_58$CLR), + .D_OUT(int_sqrt_fNext_58$D_OUT), + .FULL_N(int_sqrt_fNext_58$FULL_N), + .EMPTY_N(int_sqrt_fNext_58$EMPTY_N)); + + // submodule int_sqrt_fNext_6 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_6(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_6$D_IN), + .ENQ(int_sqrt_fNext_6$ENQ), + .DEQ(int_sqrt_fNext_6$DEQ), + .CLR(int_sqrt_fNext_6$CLR), + .D_OUT(int_sqrt_fNext_6$D_OUT), + .FULL_N(int_sqrt_fNext_6$FULL_N), + .EMPTY_N(int_sqrt_fNext_6$EMPTY_N)); + + // submodule int_sqrt_fNext_7 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_7(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_7$D_IN), + .ENQ(int_sqrt_fNext_7$ENQ), + .DEQ(int_sqrt_fNext_7$DEQ), + .CLR(int_sqrt_fNext_7$CLR), + .D_OUT(int_sqrt_fNext_7$D_OUT), + .FULL_N(int_sqrt_fNext_7$FULL_N), + .EMPTY_N(int_sqrt_fNext_7$EMPTY_N)); + + // submodule int_sqrt_fNext_8 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_8(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_8$D_IN), + .ENQ(int_sqrt_fNext_8$ENQ), + .DEQ(int_sqrt_fNext_8$DEQ), + .CLR(int_sqrt_fNext_8$CLR), + .D_OUT(int_sqrt_fNext_8$D_OUT), + .FULL_N(int_sqrt_fNext_8$FULL_N), + .EMPTY_N(int_sqrt_fNext_8$EMPTY_N)); + + // submodule int_sqrt_fNext_9 + FIFOL1 #(.width(32'd465)) int_sqrt_fNext_9(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fNext_9$D_IN), + .ENQ(int_sqrt_fNext_9$ENQ), + .DEQ(int_sqrt_fNext_9$DEQ), + .CLR(int_sqrt_fNext_9$CLR), + .D_OUT(int_sqrt_fNext_9$D_OUT), + .FULL_N(int_sqrt_fNext_9$FULL_N), + .EMPTY_N(int_sqrt_fNext_9$EMPTY_N)); + + // submodule int_sqrt_fRequest + FIFOL1 #(.width(32'd116)) int_sqrt_fRequest(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fRequest$D_IN), + .ENQ(int_sqrt_fRequest$ENQ), + .DEQ(int_sqrt_fRequest$DEQ), + .CLR(int_sqrt_fRequest$CLR), + .D_OUT(int_sqrt_fRequest$D_OUT), + .FULL_N(int_sqrt_fRequest$FULL_N), + .EMPTY_N(int_sqrt_fRequest$EMPTY_N)); + + // submodule int_sqrt_fResponse + FIFOL1 #(.width(32'd117)) int_sqrt_fResponse(.RST(RST_N), + .CLK(CLK), + .D_IN(int_sqrt_fResponse$D_IN), + .ENQ(int_sqrt_fResponse$ENQ), + .DEQ(int_sqrt_fResponse$DEQ), + .CLR(int_sqrt_fResponse$CLR), + .D_OUT(int_sqrt_fResponse$D_OUT), + .FULL_N(int_sqrt_fResponse$FULL_N), + .EMPTY_N(int_sqrt_fResponse$EMPTY_N)); + + // rule RL_fpu_s5_stage + assign CAN_FIRE_RL_fpu_s5_stage = + fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; + assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; + + // rule RL_fpu_s4_stage + assign CAN_FIRE_RL_fpu_s4_stage = + fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; + assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; + + // rule RL_fpu_s3_stage + assign CAN_FIRE_RL_fpu_s3_stage = + fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && + (fpu_fState_S2$D_OUT[136] || int_sqrt_fResponse$EMPTY_N) ; + assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; + + // rule RL_int_sqrt_finish + assign CAN_FIRE_RL_int_sqrt_finish = + int_sqrt_fNext_58$EMPTY_N && int_sqrt_fResponse$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_finish = CAN_FIRE_RL_int_sqrt_finish ; + + // rule RL_int_sqrt_work_58 + assign CAN_FIRE_RL_int_sqrt_work_58 = + int_sqrt_fNext_57$EMPTY_N && int_sqrt_fNext_58$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_58 = CAN_FIRE_RL_int_sqrt_work_58 ; + + // rule RL_int_sqrt_work_57 + assign CAN_FIRE_RL_int_sqrt_work_57 = + int_sqrt_fNext_56$EMPTY_N && int_sqrt_fNext_57$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_57 = CAN_FIRE_RL_int_sqrt_work_57 ; + + // rule RL_int_sqrt_work_56 + assign CAN_FIRE_RL_int_sqrt_work_56 = + int_sqrt_fNext_55$EMPTY_N && int_sqrt_fNext_56$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_56 = CAN_FIRE_RL_int_sqrt_work_56 ; + + // rule RL_int_sqrt_work_55 + assign CAN_FIRE_RL_int_sqrt_work_55 = + int_sqrt_fNext_54$EMPTY_N && int_sqrt_fNext_55$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_55 = CAN_FIRE_RL_int_sqrt_work_55 ; + + // rule RL_int_sqrt_work_54 + assign CAN_FIRE_RL_int_sqrt_work_54 = + int_sqrt_fNext_53$EMPTY_N && int_sqrt_fNext_54$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_54 = CAN_FIRE_RL_int_sqrt_work_54 ; + + // rule RL_int_sqrt_work_53 + assign CAN_FIRE_RL_int_sqrt_work_53 = + int_sqrt_fNext_52$EMPTY_N && int_sqrt_fNext_53$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_53 = CAN_FIRE_RL_int_sqrt_work_53 ; + + // rule RL_int_sqrt_work_52 + assign CAN_FIRE_RL_int_sqrt_work_52 = + int_sqrt_fNext_51$EMPTY_N && int_sqrt_fNext_52$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_52 = CAN_FIRE_RL_int_sqrt_work_52 ; + + // rule RL_int_sqrt_work_51 + assign CAN_FIRE_RL_int_sqrt_work_51 = + int_sqrt_fNext_50$EMPTY_N && int_sqrt_fNext_51$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_51 = CAN_FIRE_RL_int_sqrt_work_51 ; + + // rule RL_int_sqrt_work_50 + assign CAN_FIRE_RL_int_sqrt_work_50 = + int_sqrt_fNext_49$EMPTY_N && int_sqrt_fNext_50$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_50 = CAN_FIRE_RL_int_sqrt_work_50 ; + + // rule RL_int_sqrt_work_49 + assign CAN_FIRE_RL_int_sqrt_work_49 = + int_sqrt_fNext_48$EMPTY_N && int_sqrt_fNext_49$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_49 = CAN_FIRE_RL_int_sqrt_work_49 ; + + // rule RL_int_sqrt_work_48 + assign CAN_FIRE_RL_int_sqrt_work_48 = + int_sqrt_fNext_47$EMPTY_N && int_sqrt_fNext_48$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_48 = CAN_FIRE_RL_int_sqrt_work_48 ; + + // rule RL_int_sqrt_work_47 + assign CAN_FIRE_RL_int_sqrt_work_47 = + int_sqrt_fNext_46$EMPTY_N && int_sqrt_fNext_47$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_47 = CAN_FIRE_RL_int_sqrt_work_47 ; + + // rule RL_int_sqrt_work_46 + assign CAN_FIRE_RL_int_sqrt_work_46 = + int_sqrt_fNext_45$EMPTY_N && int_sqrt_fNext_46$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_46 = CAN_FIRE_RL_int_sqrt_work_46 ; + + // rule RL_int_sqrt_work_45 + assign CAN_FIRE_RL_int_sqrt_work_45 = + int_sqrt_fNext_44$EMPTY_N && int_sqrt_fNext_45$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_45 = CAN_FIRE_RL_int_sqrt_work_45 ; + + // rule RL_int_sqrt_work_44 + assign CAN_FIRE_RL_int_sqrt_work_44 = + int_sqrt_fNext_43$EMPTY_N && int_sqrt_fNext_44$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_44 = CAN_FIRE_RL_int_sqrt_work_44 ; + + // rule RL_int_sqrt_work_43 + assign CAN_FIRE_RL_int_sqrt_work_43 = + int_sqrt_fNext_42$EMPTY_N && int_sqrt_fNext_43$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_43 = CAN_FIRE_RL_int_sqrt_work_43 ; + + // rule RL_int_sqrt_work_42 + assign CAN_FIRE_RL_int_sqrt_work_42 = + int_sqrt_fNext_41$EMPTY_N && int_sqrt_fNext_42$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_42 = CAN_FIRE_RL_int_sqrt_work_42 ; + + // rule RL_int_sqrt_work_41 + assign CAN_FIRE_RL_int_sqrt_work_41 = + int_sqrt_fNext_40$EMPTY_N && int_sqrt_fNext_41$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_41 = CAN_FIRE_RL_int_sqrt_work_41 ; + + // rule RL_int_sqrt_work_40 + assign CAN_FIRE_RL_int_sqrt_work_40 = + int_sqrt_fNext_39$EMPTY_N && int_sqrt_fNext_40$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_40 = CAN_FIRE_RL_int_sqrt_work_40 ; + + // rule RL_int_sqrt_work_39 + assign CAN_FIRE_RL_int_sqrt_work_39 = + int_sqrt_fNext_38$EMPTY_N && int_sqrt_fNext_39$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_39 = CAN_FIRE_RL_int_sqrt_work_39 ; + + // rule RL_int_sqrt_work_38 + assign CAN_FIRE_RL_int_sqrt_work_38 = + int_sqrt_fNext_37$EMPTY_N && int_sqrt_fNext_38$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_38 = CAN_FIRE_RL_int_sqrt_work_38 ; + + // rule RL_int_sqrt_work_37 + assign CAN_FIRE_RL_int_sqrt_work_37 = + int_sqrt_fNext_36$EMPTY_N && int_sqrt_fNext_37$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_37 = CAN_FIRE_RL_int_sqrt_work_37 ; + + // rule RL_int_sqrt_work_36 + assign CAN_FIRE_RL_int_sqrt_work_36 = + int_sqrt_fNext_35$EMPTY_N && int_sqrt_fNext_36$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_36 = CAN_FIRE_RL_int_sqrt_work_36 ; + + // rule RL_int_sqrt_work_35 + assign CAN_FIRE_RL_int_sqrt_work_35 = + int_sqrt_fNext_34$EMPTY_N && int_sqrt_fNext_35$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_35 = CAN_FIRE_RL_int_sqrt_work_35 ; + + // rule RL_int_sqrt_work_34 + assign CAN_FIRE_RL_int_sqrt_work_34 = + int_sqrt_fNext_33$EMPTY_N && int_sqrt_fNext_34$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_34 = CAN_FIRE_RL_int_sqrt_work_34 ; + + // rule RL_int_sqrt_work_33 + assign CAN_FIRE_RL_int_sqrt_work_33 = + int_sqrt_fNext_32$EMPTY_N && int_sqrt_fNext_33$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_33 = CAN_FIRE_RL_int_sqrt_work_33 ; + + // rule RL_int_sqrt_work_32 + assign CAN_FIRE_RL_int_sqrt_work_32 = + int_sqrt_fNext_31$EMPTY_N && int_sqrt_fNext_32$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_32 = CAN_FIRE_RL_int_sqrt_work_32 ; + + // rule RL_int_sqrt_work_31 + assign CAN_FIRE_RL_int_sqrt_work_31 = + int_sqrt_fNext_30$EMPTY_N && int_sqrt_fNext_31$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_31 = CAN_FIRE_RL_int_sqrt_work_31 ; + + // rule RL_int_sqrt_work_30 + assign CAN_FIRE_RL_int_sqrt_work_30 = + int_sqrt_fNext_29$EMPTY_N && int_sqrt_fNext_30$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_30 = CAN_FIRE_RL_int_sqrt_work_30 ; + + // rule RL_int_sqrt_work_29 + assign CAN_FIRE_RL_int_sqrt_work_29 = + int_sqrt_fNext_28$EMPTY_N && int_sqrt_fNext_29$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_29 = CAN_FIRE_RL_int_sqrt_work_29 ; + + // rule RL_int_sqrt_work_28 + assign CAN_FIRE_RL_int_sqrt_work_28 = + int_sqrt_fNext_27$EMPTY_N && int_sqrt_fNext_28$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_28 = CAN_FIRE_RL_int_sqrt_work_28 ; + + // rule RL_int_sqrt_work_27 + assign CAN_FIRE_RL_int_sqrt_work_27 = + int_sqrt_fNext_26$EMPTY_N && int_sqrt_fNext_27$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_27 = CAN_FIRE_RL_int_sqrt_work_27 ; + + // rule RL_int_sqrt_work_26 + assign CAN_FIRE_RL_int_sqrt_work_26 = + int_sqrt_fNext_25$EMPTY_N && int_sqrt_fNext_26$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_26 = CAN_FIRE_RL_int_sqrt_work_26 ; + + // rule RL_int_sqrt_work_25 + assign CAN_FIRE_RL_int_sqrt_work_25 = + int_sqrt_fNext_24$EMPTY_N && int_sqrt_fNext_25$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_25 = CAN_FIRE_RL_int_sqrt_work_25 ; + + // rule RL_int_sqrt_work_24 + assign CAN_FIRE_RL_int_sqrt_work_24 = + int_sqrt_fNext_23$EMPTY_N && int_sqrt_fNext_24$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_24 = CAN_FIRE_RL_int_sqrt_work_24 ; + + // rule RL_int_sqrt_work_23 + assign CAN_FIRE_RL_int_sqrt_work_23 = + int_sqrt_fNext_22$EMPTY_N && int_sqrt_fNext_23$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_23 = CAN_FIRE_RL_int_sqrt_work_23 ; + + // rule RL_int_sqrt_work_22 + assign CAN_FIRE_RL_int_sqrt_work_22 = + int_sqrt_fNext_21$EMPTY_N && int_sqrt_fNext_22$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_22 = CAN_FIRE_RL_int_sqrt_work_22 ; + + // rule RL_int_sqrt_work_21 + assign CAN_FIRE_RL_int_sqrt_work_21 = + int_sqrt_fNext_20$EMPTY_N && int_sqrt_fNext_21$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_21 = CAN_FIRE_RL_int_sqrt_work_21 ; + + // rule RL_int_sqrt_work_20 + assign CAN_FIRE_RL_int_sqrt_work_20 = + int_sqrt_fNext_19$EMPTY_N && int_sqrt_fNext_20$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_20 = CAN_FIRE_RL_int_sqrt_work_20 ; + + // rule RL_int_sqrt_work_19 + assign CAN_FIRE_RL_int_sqrt_work_19 = + int_sqrt_fNext_18$EMPTY_N && int_sqrt_fNext_19$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_19 = CAN_FIRE_RL_int_sqrt_work_19 ; + + // rule RL_int_sqrt_work_18 + assign CAN_FIRE_RL_int_sqrt_work_18 = + int_sqrt_fNext_17$EMPTY_N && int_sqrt_fNext_18$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_18 = CAN_FIRE_RL_int_sqrt_work_18 ; + + // rule RL_int_sqrt_work_17 + assign CAN_FIRE_RL_int_sqrt_work_17 = + int_sqrt_fNext_16$EMPTY_N && int_sqrt_fNext_17$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_17 = CAN_FIRE_RL_int_sqrt_work_17 ; + + // rule RL_int_sqrt_work_16 + assign CAN_FIRE_RL_int_sqrt_work_16 = + int_sqrt_fNext_15$EMPTY_N && int_sqrt_fNext_16$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_16 = CAN_FIRE_RL_int_sqrt_work_16 ; + + // rule RL_int_sqrt_work_15 + assign CAN_FIRE_RL_int_sqrt_work_15 = + int_sqrt_fNext_14$EMPTY_N && int_sqrt_fNext_15$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_15 = CAN_FIRE_RL_int_sqrt_work_15 ; + + // rule RL_int_sqrt_work_14 + assign CAN_FIRE_RL_int_sqrt_work_14 = + int_sqrt_fNext_13$EMPTY_N && int_sqrt_fNext_14$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_14 = CAN_FIRE_RL_int_sqrt_work_14 ; + + // rule RL_int_sqrt_work_13 + assign CAN_FIRE_RL_int_sqrt_work_13 = + int_sqrt_fNext_12$EMPTY_N && int_sqrt_fNext_13$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_13 = CAN_FIRE_RL_int_sqrt_work_13 ; + + // rule RL_int_sqrt_work_12 + assign CAN_FIRE_RL_int_sqrt_work_12 = + int_sqrt_fNext_11$EMPTY_N && int_sqrt_fNext_12$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_12 = CAN_FIRE_RL_int_sqrt_work_12 ; + + // rule RL_int_sqrt_work_11 + assign CAN_FIRE_RL_int_sqrt_work_11 = + int_sqrt_fNext_10$EMPTY_N && int_sqrt_fNext_11$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_11 = CAN_FIRE_RL_int_sqrt_work_11 ; + + // rule RL_int_sqrt_work_10 + assign CAN_FIRE_RL_int_sqrt_work_10 = + int_sqrt_fNext_9$EMPTY_N && int_sqrt_fNext_10$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_10 = CAN_FIRE_RL_int_sqrt_work_10 ; + + // rule RL_int_sqrt_work_9 + assign CAN_FIRE_RL_int_sqrt_work_9 = + int_sqrt_fNext_8$EMPTY_N && int_sqrt_fNext_9$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_9 = CAN_FIRE_RL_int_sqrt_work_9 ; + + // rule RL_int_sqrt_work_8 + assign CAN_FIRE_RL_int_sqrt_work_8 = + int_sqrt_fNext_7$EMPTY_N && int_sqrt_fNext_8$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_8 = CAN_FIRE_RL_int_sqrt_work_8 ; + + // rule RL_int_sqrt_work_7 + assign CAN_FIRE_RL_int_sqrt_work_7 = + int_sqrt_fNext_6$EMPTY_N && int_sqrt_fNext_7$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_7 = CAN_FIRE_RL_int_sqrt_work_7 ; + + // rule RL_int_sqrt_work_6 + assign CAN_FIRE_RL_int_sqrt_work_6 = + int_sqrt_fNext_5$EMPTY_N && int_sqrt_fNext_6$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_6 = CAN_FIRE_RL_int_sqrt_work_6 ; + + // rule RL_int_sqrt_work_5 + assign CAN_FIRE_RL_int_sqrt_work_5 = + int_sqrt_fNext_4$EMPTY_N && int_sqrt_fNext_5$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_5 = CAN_FIRE_RL_int_sqrt_work_5 ; + + // rule RL_int_sqrt_work_4 + assign CAN_FIRE_RL_int_sqrt_work_4 = + int_sqrt_fNext_3$EMPTY_N && int_sqrt_fNext_4$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_4 = CAN_FIRE_RL_int_sqrt_work_4 ; + + // rule RL_int_sqrt_work_3 + assign CAN_FIRE_RL_int_sqrt_work_3 = + int_sqrt_fNext_2$EMPTY_N && int_sqrt_fNext_3$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_3 = CAN_FIRE_RL_int_sqrt_work_3 ; + + // rule RL_int_sqrt_work_2 + assign CAN_FIRE_RL_int_sqrt_work_2 = + int_sqrt_fNext_1$EMPTY_N && int_sqrt_fNext_2$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_2 = CAN_FIRE_RL_int_sqrt_work_2 ; + + // rule RL_int_sqrt_work_1 + assign CAN_FIRE_RL_int_sqrt_work_1 = + int_sqrt_fNext_0$EMPTY_N && int_sqrt_fNext_1$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work_1 = CAN_FIRE_RL_int_sqrt_work_1 ; + + // rule RL_int_sqrt_work + assign CAN_FIRE_RL_int_sqrt_work = + int_sqrt_fFirst$EMPTY_N && int_sqrt_fNext_0$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_work = CAN_FIRE_RL_int_sqrt_work ; + + // rule RL_int_sqrt_start + assign CAN_FIRE_RL_int_sqrt_start = + int_sqrt_fRequest$EMPTY_N && int_sqrt_fFirst$FULL_N ; + assign WILL_FIRE_RL_int_sqrt_start = CAN_FIRE_RL_int_sqrt_start ; + + // rule RL_fpu_s2_stage + assign CAN_FIRE_RL_fpu_s2_stage = + fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && + (fpu_fState_S1$D_OUT[194] || int_sqrt_fRequest$FULL_N) ; + assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; + + // rule RL_fpu_s1_stage + assign CAN_FIRE_RL_fpu_s1_stage = + fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; + assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; + + // submodule fpu_fOperand_S0 + assign fpu_fOperand_S0$D_IN = request_put ; + assign fpu_fOperand_S0$ENQ = EN_request_put ; + assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fOperand_S0$CLR = 1'b0 ; + + // submodule fpu_fResult_S5 + assign fpu_fResult_S5$D_IN = + fpu_fState_S4$D_OUT[138] ? + fpu_fState_S4$D_OUT[137:69] : + { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[65:2] : + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15, + fpu_fState_S4$D_OUT[73:69] | + { 2'd0, + _theResult___fst_exp__h76509 == 11'd2047 && + _theResult___fst_sfd__h76510 == 52'd0, + 1'd0, + fpu_fState_S4$D_OUT[64:54] != 11'd2047 && + fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; + assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fResult_S5$DEQ = EN_response_get ; + assign fpu_fResult_S5$CLR = 1'b0 ; + + // submodule fpu_fState_S1 + assign fpu_fState_S1$D_IN = + (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && + !fpu_fOperand_S0$D_OUT[54]) ? + { 1'd1, + fpu_fOperand_S0$D_OUT[66:55], + sfd__h49989, + 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 ; + assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; + assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S1$CLR = 1'b0 ; + + // submodule fpu_fState_S2 + assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[194:58] ; + assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; + assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S2$CLR = 1'b0 ; + + // submodule fpu_fState_S3 + assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT, x__h66665 } ; + assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; + assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S3$CLR = 1'b0 ; + + // submodule fpu_fState_S4 + assign fpu_fState_S4$D_IN = + { fpu_fState_S3$D_OUT[195:131], + fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[130], + fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[129], + IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813, + fpu_fState_S3$D_OUT[125:122], + fpu_fState_S3$D_OUT[195] ? + fpu_fState_S3$D_OUT[121:59] : + IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820, + x__h75654 } ; + assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; + assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; + assign fpu_fState_S4$CLR = 1'b0 ; + + // submodule int_sqrt_fFirst + assign int_sqrt_fFirst$D_IN = + { 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA, + int_sqrt_fRequest$D_OUT, + 116'd0, + x__h402 } ; + assign int_sqrt_fFirst$ENQ = CAN_FIRE_RL_int_sqrt_start ; + assign int_sqrt_fFirst$DEQ = CAN_FIRE_RL_int_sqrt_work ; + assign int_sqrt_fFirst$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_0 + assign int_sqrt_fNext_0$D_IN = + { int_sqrt_fFirst$D_OUT[464] || + int_sqrt_fFirst$D_OUT[115:0] == 116'd0, + int_sqrt_fFirst$D_OUT[464] ? + int_sqrt_fFirst$D_OUT[463:348] : + ((int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? + int_sqrt_fFirst$D_OUT[231:116] : + int_sqrt_fFirst$D_OUT[463:348]), + int_sqrt_fFirst$D_OUT[464] ? + int_sqrt_fFirst$D_OUT[347:0] : + { _theResult___snd_fst__h25299, + (int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? + int_sqrt_fFirst$D_OUT[231:0] : + { _theResult___snd_snd__h25377, b__h25374 } } } ; + assign int_sqrt_fNext_0$ENQ = CAN_FIRE_RL_int_sqrt_work ; + assign int_sqrt_fNext_0$DEQ = CAN_FIRE_RL_int_sqrt_work_1 ; + assign int_sqrt_fNext_0$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_1 + assign int_sqrt_fNext_1$D_IN = + { int_sqrt_fNext_0$D_OUT[464] || + int_sqrt_fNext_0$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_0$D_OUT[464] ? + int_sqrt_fNext_0$D_OUT[463:348] : + ((int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_0$D_OUT[231:116] : + int_sqrt_fNext_0$D_OUT[463:348]), + int_sqrt_fNext_0$D_OUT[464] ? + int_sqrt_fNext_0$D_OUT[347:0] : + { _theResult___snd_fst__h25701, + (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_0$D_OUT[231:0] : + { _theResult___snd_snd__h25777, b__h25774 } } } ; + assign int_sqrt_fNext_1$ENQ = CAN_FIRE_RL_int_sqrt_work_1 ; + assign int_sqrt_fNext_1$DEQ = CAN_FIRE_RL_int_sqrt_work_2 ; + assign int_sqrt_fNext_1$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_10 + assign int_sqrt_fNext_10$D_IN = + { int_sqrt_fNext_9$D_OUT[464] || + int_sqrt_fNext_9$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_9$D_OUT[464] ? + int_sqrt_fNext_9$D_OUT[463:348] : + ((int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_9$D_OUT[231:116] : + int_sqrt_fNext_9$D_OUT[463:348]), + int_sqrt_fNext_9$D_OUT[464] ? + int_sqrt_fNext_9$D_OUT[347:0] : + { _theResult___snd_fst__h29301, + (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_9$D_OUT[231:0] : + { _theResult___snd_snd__h29377, b__h29374 } } } ; + assign int_sqrt_fNext_10$ENQ = CAN_FIRE_RL_int_sqrt_work_10 ; + assign int_sqrt_fNext_10$DEQ = CAN_FIRE_RL_int_sqrt_work_11 ; + assign int_sqrt_fNext_10$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_11 + assign int_sqrt_fNext_11$D_IN = + { int_sqrt_fNext_10$D_OUT[464] || + int_sqrt_fNext_10$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_10$D_OUT[464] ? + int_sqrt_fNext_10$D_OUT[463:348] : + ((int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_10$D_OUT[231:116] : + int_sqrt_fNext_10$D_OUT[463:348]), + int_sqrt_fNext_10$D_OUT[464] ? + int_sqrt_fNext_10$D_OUT[347:0] : + { _theResult___snd_fst__h29701, + (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_10$D_OUT[231:0] : + { _theResult___snd_snd__h29777, b__h29774 } } } ; + assign int_sqrt_fNext_11$ENQ = CAN_FIRE_RL_int_sqrt_work_11 ; + assign int_sqrt_fNext_11$DEQ = CAN_FIRE_RL_int_sqrt_work_12 ; + assign int_sqrt_fNext_11$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_12 + assign int_sqrt_fNext_12$D_IN = + { int_sqrt_fNext_11$D_OUT[464] || + int_sqrt_fNext_11$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_11$D_OUT[464] ? + int_sqrt_fNext_11$D_OUT[463:348] : + ((int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_11$D_OUT[231:116] : + int_sqrt_fNext_11$D_OUT[463:348]), + int_sqrt_fNext_11$D_OUT[464] ? + int_sqrt_fNext_11$D_OUT[347:0] : + { _theResult___snd_fst__h30101, + (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_11$D_OUT[231:0] : + { _theResult___snd_snd__h30177, b__h30174 } } } ; + assign int_sqrt_fNext_12$ENQ = CAN_FIRE_RL_int_sqrt_work_12 ; + assign int_sqrt_fNext_12$DEQ = CAN_FIRE_RL_int_sqrt_work_13 ; + assign int_sqrt_fNext_12$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_13 + assign int_sqrt_fNext_13$D_IN = + { int_sqrt_fNext_12$D_OUT[464] || + int_sqrt_fNext_12$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_12$D_OUT[464] ? + int_sqrt_fNext_12$D_OUT[463:348] : + ((int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_12$D_OUT[231:116] : + int_sqrt_fNext_12$D_OUT[463:348]), + int_sqrt_fNext_12$D_OUT[464] ? + int_sqrt_fNext_12$D_OUT[347:0] : + { _theResult___snd_fst__h30501, + (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_12$D_OUT[231:0] : + { _theResult___snd_snd__h30577, b__h30574 } } } ; + assign int_sqrt_fNext_13$ENQ = CAN_FIRE_RL_int_sqrt_work_13 ; + assign int_sqrt_fNext_13$DEQ = CAN_FIRE_RL_int_sqrt_work_14 ; + assign int_sqrt_fNext_13$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_14 + assign int_sqrt_fNext_14$D_IN = + { int_sqrt_fNext_13$D_OUT[464] || + int_sqrt_fNext_13$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_13$D_OUT[464] ? + int_sqrt_fNext_13$D_OUT[463:348] : + ((int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_13$D_OUT[231:116] : + int_sqrt_fNext_13$D_OUT[463:348]), + int_sqrt_fNext_13$D_OUT[464] ? + int_sqrt_fNext_13$D_OUT[347:0] : + { _theResult___snd_fst__h30901, + (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_13$D_OUT[231:0] : + { _theResult___snd_snd__h30977, b__h30974 } } } ; + assign int_sqrt_fNext_14$ENQ = CAN_FIRE_RL_int_sqrt_work_14 ; + assign int_sqrt_fNext_14$DEQ = CAN_FIRE_RL_int_sqrt_work_15 ; + assign int_sqrt_fNext_14$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_15 + assign int_sqrt_fNext_15$D_IN = + { int_sqrt_fNext_14$D_OUT[464] || + int_sqrt_fNext_14$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_14$D_OUT[464] ? + int_sqrt_fNext_14$D_OUT[463:348] : + ((int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_14$D_OUT[231:116] : + int_sqrt_fNext_14$D_OUT[463:348]), + int_sqrt_fNext_14$D_OUT[464] ? + int_sqrt_fNext_14$D_OUT[347:0] : + { _theResult___snd_fst__h31301, + (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_14$D_OUT[231:0] : + { _theResult___snd_snd__h31377, b__h31374 } } } ; + assign int_sqrt_fNext_15$ENQ = CAN_FIRE_RL_int_sqrt_work_15 ; + assign int_sqrt_fNext_15$DEQ = CAN_FIRE_RL_int_sqrt_work_16 ; + assign int_sqrt_fNext_15$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_16 + assign int_sqrt_fNext_16$D_IN = + { int_sqrt_fNext_15$D_OUT[464] || + int_sqrt_fNext_15$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_15$D_OUT[464] ? + int_sqrt_fNext_15$D_OUT[463:348] : + ((int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_15$D_OUT[231:116] : + int_sqrt_fNext_15$D_OUT[463:348]), + int_sqrt_fNext_15$D_OUT[464] ? + int_sqrt_fNext_15$D_OUT[347:0] : + { _theResult___snd_fst__h31701, + (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_15$D_OUT[231:0] : + { _theResult___snd_snd__h31777, b__h31774 } } } ; + assign int_sqrt_fNext_16$ENQ = CAN_FIRE_RL_int_sqrt_work_16 ; + assign int_sqrt_fNext_16$DEQ = CAN_FIRE_RL_int_sqrt_work_17 ; + assign int_sqrt_fNext_16$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_17 + assign int_sqrt_fNext_17$D_IN = + { int_sqrt_fNext_16$D_OUT[464] || + int_sqrt_fNext_16$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_16$D_OUT[464] ? + int_sqrt_fNext_16$D_OUT[463:348] : + ((int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_16$D_OUT[231:116] : + int_sqrt_fNext_16$D_OUT[463:348]), + int_sqrt_fNext_16$D_OUT[464] ? + int_sqrt_fNext_16$D_OUT[347:0] : + { _theResult___snd_fst__h32101, + (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_16$D_OUT[231:0] : + { _theResult___snd_snd__h32177, b__h32174 } } } ; + assign int_sqrt_fNext_17$ENQ = CAN_FIRE_RL_int_sqrt_work_17 ; + assign int_sqrt_fNext_17$DEQ = CAN_FIRE_RL_int_sqrt_work_18 ; + assign int_sqrt_fNext_17$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_18 + assign int_sqrt_fNext_18$D_IN = + { int_sqrt_fNext_17$D_OUT[464] || + int_sqrt_fNext_17$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_17$D_OUT[464] ? + int_sqrt_fNext_17$D_OUT[463:348] : + ((int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_17$D_OUT[231:116] : + int_sqrt_fNext_17$D_OUT[463:348]), + int_sqrt_fNext_17$D_OUT[464] ? + int_sqrt_fNext_17$D_OUT[347:0] : + { _theResult___snd_fst__h32501, + (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_17$D_OUT[231:0] : + { _theResult___snd_snd__h32577, b__h32574 } } } ; + assign int_sqrt_fNext_18$ENQ = CAN_FIRE_RL_int_sqrt_work_18 ; + assign int_sqrt_fNext_18$DEQ = CAN_FIRE_RL_int_sqrt_work_19 ; + assign int_sqrt_fNext_18$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_19 + assign int_sqrt_fNext_19$D_IN = + { int_sqrt_fNext_18$D_OUT[464] || + int_sqrt_fNext_18$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_18$D_OUT[464] ? + int_sqrt_fNext_18$D_OUT[463:348] : + ((int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_18$D_OUT[231:116] : + int_sqrt_fNext_18$D_OUT[463:348]), + int_sqrt_fNext_18$D_OUT[464] ? + int_sqrt_fNext_18$D_OUT[347:0] : + { _theResult___snd_fst__h32901, + (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_18$D_OUT[231:0] : + { _theResult___snd_snd__h32977, b__h32974 } } } ; + assign int_sqrt_fNext_19$ENQ = CAN_FIRE_RL_int_sqrt_work_19 ; + assign int_sqrt_fNext_19$DEQ = CAN_FIRE_RL_int_sqrt_work_20 ; + assign int_sqrt_fNext_19$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_2 + assign int_sqrt_fNext_2$D_IN = + { int_sqrt_fNext_1$D_OUT[464] || + int_sqrt_fNext_1$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_1$D_OUT[464] ? + int_sqrt_fNext_1$D_OUT[463:348] : + ((int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_1$D_OUT[231:116] : + int_sqrt_fNext_1$D_OUT[463:348]), + int_sqrt_fNext_1$D_OUT[464] ? + int_sqrt_fNext_1$D_OUT[347:0] : + { _theResult___snd_fst__h26101, + (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_1$D_OUT[231:0] : + { _theResult___snd_snd__h26177, b__h26174 } } } ; + assign int_sqrt_fNext_2$ENQ = CAN_FIRE_RL_int_sqrt_work_2 ; + assign int_sqrt_fNext_2$DEQ = CAN_FIRE_RL_int_sqrt_work_3 ; + assign int_sqrt_fNext_2$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_20 + assign int_sqrt_fNext_20$D_IN = + { int_sqrt_fNext_19$D_OUT[464] || + int_sqrt_fNext_19$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_19$D_OUT[464] ? + int_sqrt_fNext_19$D_OUT[463:348] : + ((int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_19$D_OUT[231:116] : + int_sqrt_fNext_19$D_OUT[463:348]), + int_sqrt_fNext_19$D_OUT[464] ? + int_sqrt_fNext_19$D_OUT[347:0] : + { _theResult___snd_fst__h33301, + (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_19$D_OUT[231:0] : + { _theResult___snd_snd__h33377, b__h33374 } } } ; + assign int_sqrt_fNext_20$ENQ = CAN_FIRE_RL_int_sqrt_work_20 ; + assign int_sqrt_fNext_20$DEQ = CAN_FIRE_RL_int_sqrt_work_21 ; + assign int_sqrt_fNext_20$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_21 + assign int_sqrt_fNext_21$D_IN = + { int_sqrt_fNext_20$D_OUT[464] || + int_sqrt_fNext_20$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_20$D_OUT[464] ? + int_sqrt_fNext_20$D_OUT[463:348] : + ((int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_20$D_OUT[231:116] : + int_sqrt_fNext_20$D_OUT[463:348]), + int_sqrt_fNext_20$D_OUT[464] ? + int_sqrt_fNext_20$D_OUT[347:0] : + { _theResult___snd_fst__h33701, + (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_20$D_OUT[231:0] : + { _theResult___snd_snd__h33777, b__h33774 } } } ; + assign int_sqrt_fNext_21$ENQ = CAN_FIRE_RL_int_sqrt_work_21 ; + assign int_sqrt_fNext_21$DEQ = CAN_FIRE_RL_int_sqrt_work_22 ; + assign int_sqrt_fNext_21$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_22 + assign int_sqrt_fNext_22$D_IN = + { int_sqrt_fNext_21$D_OUT[464] || + int_sqrt_fNext_21$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_21$D_OUT[464] ? + int_sqrt_fNext_21$D_OUT[463:348] : + ((int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_21$D_OUT[231:116] : + int_sqrt_fNext_21$D_OUT[463:348]), + int_sqrt_fNext_21$D_OUT[464] ? + int_sqrt_fNext_21$D_OUT[347:0] : + { _theResult___snd_fst__h34101, + (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_21$D_OUT[231:0] : + { _theResult___snd_snd__h34177, b__h34174 } } } ; + assign int_sqrt_fNext_22$ENQ = CAN_FIRE_RL_int_sqrt_work_22 ; + assign int_sqrt_fNext_22$DEQ = CAN_FIRE_RL_int_sqrt_work_23 ; + assign int_sqrt_fNext_22$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_23 + assign int_sqrt_fNext_23$D_IN = + { int_sqrt_fNext_22$D_OUT[464] || + int_sqrt_fNext_22$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_22$D_OUT[464] ? + int_sqrt_fNext_22$D_OUT[463:348] : + ((int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_22$D_OUT[231:116] : + int_sqrt_fNext_22$D_OUT[463:348]), + int_sqrt_fNext_22$D_OUT[464] ? + int_sqrt_fNext_22$D_OUT[347:0] : + { _theResult___snd_fst__h34501, + (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_22$D_OUT[231:0] : + { _theResult___snd_snd__h34577, b__h34574 } } } ; + assign int_sqrt_fNext_23$ENQ = CAN_FIRE_RL_int_sqrt_work_23 ; + assign int_sqrt_fNext_23$DEQ = CAN_FIRE_RL_int_sqrt_work_24 ; + assign int_sqrt_fNext_23$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_24 + assign int_sqrt_fNext_24$D_IN = + { int_sqrt_fNext_23$D_OUT[464] || + int_sqrt_fNext_23$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_23$D_OUT[464] ? + int_sqrt_fNext_23$D_OUT[463:348] : + ((int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_23$D_OUT[231:116] : + int_sqrt_fNext_23$D_OUT[463:348]), + int_sqrt_fNext_23$D_OUT[464] ? + int_sqrt_fNext_23$D_OUT[347:0] : + { _theResult___snd_fst__h34901, + (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_23$D_OUT[231:0] : + { _theResult___snd_snd__h34977, b__h34974 } } } ; + assign int_sqrt_fNext_24$ENQ = CAN_FIRE_RL_int_sqrt_work_24 ; + assign int_sqrt_fNext_24$DEQ = CAN_FIRE_RL_int_sqrt_work_25 ; + assign int_sqrt_fNext_24$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_25 + assign int_sqrt_fNext_25$D_IN = + { int_sqrt_fNext_24$D_OUT[464] || + int_sqrt_fNext_24$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_24$D_OUT[464] ? + int_sqrt_fNext_24$D_OUT[463:348] : + ((int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_24$D_OUT[231:116] : + int_sqrt_fNext_24$D_OUT[463:348]), + int_sqrt_fNext_24$D_OUT[464] ? + int_sqrt_fNext_24$D_OUT[347:0] : + { _theResult___snd_fst__h35301, + (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_24$D_OUT[231:0] : + { _theResult___snd_snd__h35377, b__h35374 } } } ; + assign int_sqrt_fNext_25$ENQ = CAN_FIRE_RL_int_sqrt_work_25 ; + assign int_sqrt_fNext_25$DEQ = CAN_FIRE_RL_int_sqrt_work_26 ; + assign int_sqrt_fNext_25$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_26 + assign int_sqrt_fNext_26$D_IN = + { int_sqrt_fNext_25$D_OUT[464] || + int_sqrt_fNext_25$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_25$D_OUT[464] ? + int_sqrt_fNext_25$D_OUT[463:348] : + ((int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_25$D_OUT[231:116] : + int_sqrt_fNext_25$D_OUT[463:348]), + int_sqrt_fNext_25$D_OUT[464] ? + int_sqrt_fNext_25$D_OUT[347:0] : + { _theResult___snd_fst__h35701, + (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_25$D_OUT[231:0] : + { _theResult___snd_snd__h35777, b__h35774 } } } ; + assign int_sqrt_fNext_26$ENQ = CAN_FIRE_RL_int_sqrt_work_26 ; + assign int_sqrt_fNext_26$DEQ = CAN_FIRE_RL_int_sqrt_work_27 ; + assign int_sqrt_fNext_26$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_27 + assign int_sqrt_fNext_27$D_IN = + { int_sqrt_fNext_26$D_OUT[464] || + int_sqrt_fNext_26$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_26$D_OUT[464] ? + int_sqrt_fNext_26$D_OUT[463:348] : + ((int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_26$D_OUT[231:116] : + int_sqrt_fNext_26$D_OUT[463:348]), + int_sqrt_fNext_26$D_OUT[464] ? + int_sqrt_fNext_26$D_OUT[347:0] : + { _theResult___snd_fst__h36101, + (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_26$D_OUT[231:0] : + { _theResult___snd_snd__h36177, b__h36174 } } } ; + assign int_sqrt_fNext_27$ENQ = CAN_FIRE_RL_int_sqrt_work_27 ; + assign int_sqrt_fNext_27$DEQ = CAN_FIRE_RL_int_sqrt_work_28 ; + assign int_sqrt_fNext_27$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_28 + assign int_sqrt_fNext_28$D_IN = + { int_sqrt_fNext_27$D_OUT[464] || + int_sqrt_fNext_27$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_27$D_OUT[464] ? + int_sqrt_fNext_27$D_OUT[463:348] : + ((int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_27$D_OUT[231:116] : + int_sqrt_fNext_27$D_OUT[463:348]), + int_sqrt_fNext_27$D_OUT[464] ? + int_sqrt_fNext_27$D_OUT[347:0] : + { _theResult___snd_fst__h36501, + (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_27$D_OUT[231:0] : + { _theResult___snd_snd__h36577, b__h36574 } } } ; + assign int_sqrt_fNext_28$ENQ = CAN_FIRE_RL_int_sqrt_work_28 ; + assign int_sqrt_fNext_28$DEQ = CAN_FIRE_RL_int_sqrt_work_29 ; + assign int_sqrt_fNext_28$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_29 + assign int_sqrt_fNext_29$D_IN = + { int_sqrt_fNext_28$D_OUT[464] || + int_sqrt_fNext_28$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_28$D_OUT[464] ? + int_sqrt_fNext_28$D_OUT[463:348] : + ((int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_28$D_OUT[231:116] : + int_sqrt_fNext_28$D_OUT[463:348]), + int_sqrt_fNext_28$D_OUT[464] ? + int_sqrt_fNext_28$D_OUT[347:0] : + { _theResult___snd_fst__h36901, + (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_28$D_OUT[231:0] : + { _theResult___snd_snd__h36977, b__h36974 } } } ; + assign int_sqrt_fNext_29$ENQ = CAN_FIRE_RL_int_sqrt_work_29 ; + assign int_sqrt_fNext_29$DEQ = CAN_FIRE_RL_int_sqrt_work_30 ; + assign int_sqrt_fNext_29$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_3 + assign int_sqrt_fNext_3$D_IN = + { int_sqrt_fNext_2$D_OUT[464] || + int_sqrt_fNext_2$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_2$D_OUT[464] ? + int_sqrt_fNext_2$D_OUT[463:348] : + ((int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_2$D_OUT[231:116] : + int_sqrt_fNext_2$D_OUT[463:348]), + int_sqrt_fNext_2$D_OUT[464] ? + int_sqrt_fNext_2$D_OUT[347:0] : + { _theResult___snd_fst__h26501, + (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_2$D_OUT[231:0] : + { _theResult___snd_snd__h26577, b__h26574 } } } ; + assign int_sqrt_fNext_3$ENQ = CAN_FIRE_RL_int_sqrt_work_3 ; + assign int_sqrt_fNext_3$DEQ = CAN_FIRE_RL_int_sqrt_work_4 ; + assign int_sqrt_fNext_3$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_30 + assign int_sqrt_fNext_30$D_IN = + { int_sqrt_fNext_29$D_OUT[464] || + int_sqrt_fNext_29$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_29$D_OUT[464] ? + int_sqrt_fNext_29$D_OUT[463:348] : + ((int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_29$D_OUT[231:116] : + int_sqrt_fNext_29$D_OUT[463:348]), + int_sqrt_fNext_29$D_OUT[464] ? + int_sqrt_fNext_29$D_OUT[347:0] : + { _theResult___snd_fst__h37301, + (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_29$D_OUT[231:0] : + { _theResult___snd_snd__h37377, b__h37374 } } } ; + assign int_sqrt_fNext_30$ENQ = CAN_FIRE_RL_int_sqrt_work_30 ; + assign int_sqrt_fNext_30$DEQ = CAN_FIRE_RL_int_sqrt_work_31 ; + assign int_sqrt_fNext_30$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_31 + assign int_sqrt_fNext_31$D_IN = + { int_sqrt_fNext_30$D_OUT[464] || + int_sqrt_fNext_30$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_30$D_OUT[464] ? + int_sqrt_fNext_30$D_OUT[463:348] : + ((int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_30$D_OUT[231:116] : + int_sqrt_fNext_30$D_OUT[463:348]), + int_sqrt_fNext_30$D_OUT[464] ? + int_sqrt_fNext_30$D_OUT[347:0] : + { _theResult___snd_fst__h37701, + (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_30$D_OUT[231:0] : + { _theResult___snd_snd__h37777, b__h37774 } } } ; + assign int_sqrt_fNext_31$ENQ = CAN_FIRE_RL_int_sqrt_work_31 ; + assign int_sqrt_fNext_31$DEQ = CAN_FIRE_RL_int_sqrt_work_32 ; + assign int_sqrt_fNext_31$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_32 + assign int_sqrt_fNext_32$D_IN = + { int_sqrt_fNext_31$D_OUT[464] || + int_sqrt_fNext_31$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_31$D_OUT[464] ? + int_sqrt_fNext_31$D_OUT[463:348] : + ((int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_31$D_OUT[231:116] : + int_sqrt_fNext_31$D_OUT[463:348]), + int_sqrt_fNext_31$D_OUT[464] ? + int_sqrt_fNext_31$D_OUT[347:0] : + { _theResult___snd_fst__h38101, + (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_31$D_OUT[231:0] : + { _theResult___snd_snd__h38177, b__h38174 } } } ; + assign int_sqrt_fNext_32$ENQ = CAN_FIRE_RL_int_sqrt_work_32 ; + assign int_sqrt_fNext_32$DEQ = CAN_FIRE_RL_int_sqrt_work_33 ; + assign int_sqrt_fNext_32$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_33 + assign int_sqrt_fNext_33$D_IN = + { int_sqrt_fNext_32$D_OUT[464] || + int_sqrt_fNext_32$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_32$D_OUT[464] ? + int_sqrt_fNext_32$D_OUT[463:348] : + ((int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_32$D_OUT[231:116] : + int_sqrt_fNext_32$D_OUT[463:348]), + int_sqrt_fNext_32$D_OUT[464] ? + int_sqrt_fNext_32$D_OUT[347:0] : + { _theResult___snd_fst__h38501, + (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_32$D_OUT[231:0] : + { _theResult___snd_snd__h38577, b__h38574 } } } ; + assign int_sqrt_fNext_33$ENQ = CAN_FIRE_RL_int_sqrt_work_33 ; + assign int_sqrt_fNext_33$DEQ = CAN_FIRE_RL_int_sqrt_work_34 ; + assign int_sqrt_fNext_33$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_34 + assign int_sqrt_fNext_34$D_IN = + { int_sqrt_fNext_33$D_OUT[464] || + int_sqrt_fNext_33$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_33$D_OUT[464] ? + int_sqrt_fNext_33$D_OUT[463:348] : + ((int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_33$D_OUT[231:116] : + int_sqrt_fNext_33$D_OUT[463:348]), + int_sqrt_fNext_33$D_OUT[464] ? + int_sqrt_fNext_33$D_OUT[347:0] : + { _theResult___snd_fst__h38901, + (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_33$D_OUT[231:0] : + { _theResult___snd_snd__h38977, b__h38974 } } } ; + assign int_sqrt_fNext_34$ENQ = CAN_FIRE_RL_int_sqrt_work_34 ; + assign int_sqrt_fNext_34$DEQ = CAN_FIRE_RL_int_sqrt_work_35 ; + assign int_sqrt_fNext_34$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_35 + assign int_sqrt_fNext_35$D_IN = + { int_sqrt_fNext_34$D_OUT[464] || + int_sqrt_fNext_34$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_34$D_OUT[464] ? + int_sqrt_fNext_34$D_OUT[463:348] : + ((int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_34$D_OUT[231:116] : + int_sqrt_fNext_34$D_OUT[463:348]), + int_sqrt_fNext_34$D_OUT[464] ? + int_sqrt_fNext_34$D_OUT[347:0] : + { _theResult___snd_fst__h39301, + (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_34$D_OUT[231:0] : + { _theResult___snd_snd__h39377, b__h39374 } } } ; + assign int_sqrt_fNext_35$ENQ = CAN_FIRE_RL_int_sqrt_work_35 ; + assign int_sqrt_fNext_35$DEQ = CAN_FIRE_RL_int_sqrt_work_36 ; + assign int_sqrt_fNext_35$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_36 + assign int_sqrt_fNext_36$D_IN = + { int_sqrt_fNext_35$D_OUT[464] || + int_sqrt_fNext_35$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_35$D_OUT[464] ? + int_sqrt_fNext_35$D_OUT[463:348] : + ((int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_35$D_OUT[231:116] : + int_sqrt_fNext_35$D_OUT[463:348]), + int_sqrt_fNext_35$D_OUT[464] ? + int_sqrt_fNext_35$D_OUT[347:0] : + { _theResult___snd_fst__h39701, + (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_35$D_OUT[231:0] : + { _theResult___snd_snd__h39777, b__h39774 } } } ; + assign int_sqrt_fNext_36$ENQ = CAN_FIRE_RL_int_sqrt_work_36 ; + assign int_sqrt_fNext_36$DEQ = CAN_FIRE_RL_int_sqrt_work_37 ; + assign int_sqrt_fNext_36$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_37 + assign int_sqrt_fNext_37$D_IN = + { int_sqrt_fNext_36$D_OUT[464] || + int_sqrt_fNext_36$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_36$D_OUT[464] ? + int_sqrt_fNext_36$D_OUT[463:348] : + ((int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_36$D_OUT[231:116] : + int_sqrt_fNext_36$D_OUT[463:348]), + int_sqrt_fNext_36$D_OUT[464] ? + int_sqrt_fNext_36$D_OUT[347:0] : + { _theResult___snd_fst__h40101, + (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_36$D_OUT[231:0] : + { _theResult___snd_snd__h40177, b__h40174 } } } ; + assign int_sqrt_fNext_37$ENQ = CAN_FIRE_RL_int_sqrt_work_37 ; + assign int_sqrt_fNext_37$DEQ = CAN_FIRE_RL_int_sqrt_work_38 ; + assign int_sqrt_fNext_37$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_38 + assign int_sqrt_fNext_38$D_IN = + { int_sqrt_fNext_37$D_OUT[464] || + int_sqrt_fNext_37$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_37$D_OUT[464] ? + int_sqrt_fNext_37$D_OUT[463:348] : + ((int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_37$D_OUT[231:116] : + int_sqrt_fNext_37$D_OUT[463:348]), + int_sqrt_fNext_37$D_OUT[464] ? + int_sqrt_fNext_37$D_OUT[347:0] : + { _theResult___snd_fst__h40501, + (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_37$D_OUT[231:0] : + { _theResult___snd_snd__h40577, b__h40574 } } } ; + assign int_sqrt_fNext_38$ENQ = CAN_FIRE_RL_int_sqrt_work_38 ; + assign int_sqrt_fNext_38$DEQ = CAN_FIRE_RL_int_sqrt_work_39 ; + assign int_sqrt_fNext_38$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_39 + assign int_sqrt_fNext_39$D_IN = + { int_sqrt_fNext_38$D_OUT[464] || + int_sqrt_fNext_38$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_38$D_OUT[464] ? + int_sqrt_fNext_38$D_OUT[463:348] : + ((int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_38$D_OUT[231:116] : + int_sqrt_fNext_38$D_OUT[463:348]), + int_sqrt_fNext_38$D_OUT[464] ? + int_sqrt_fNext_38$D_OUT[347:0] : + { _theResult___snd_fst__h40901, + (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_38$D_OUT[231:0] : + { _theResult___snd_snd__h40977, b__h40974 } } } ; + assign int_sqrt_fNext_39$ENQ = CAN_FIRE_RL_int_sqrt_work_39 ; + assign int_sqrt_fNext_39$DEQ = CAN_FIRE_RL_int_sqrt_work_40 ; + assign int_sqrt_fNext_39$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_4 + assign int_sqrt_fNext_4$D_IN = + { int_sqrt_fNext_3$D_OUT[464] || + int_sqrt_fNext_3$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_3$D_OUT[464] ? + int_sqrt_fNext_3$D_OUT[463:348] : + ((int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_3$D_OUT[231:116] : + int_sqrt_fNext_3$D_OUT[463:348]), + int_sqrt_fNext_3$D_OUT[464] ? + int_sqrt_fNext_3$D_OUT[347:0] : + { _theResult___snd_fst__h26901, + (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_3$D_OUT[231:0] : + { _theResult___snd_snd__h26977, b__h26974 } } } ; + assign int_sqrt_fNext_4$ENQ = CAN_FIRE_RL_int_sqrt_work_4 ; + assign int_sqrt_fNext_4$DEQ = CAN_FIRE_RL_int_sqrt_work_5 ; + assign int_sqrt_fNext_4$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_40 + assign int_sqrt_fNext_40$D_IN = + { int_sqrt_fNext_39$D_OUT[464] || + int_sqrt_fNext_39$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_39$D_OUT[464] ? + int_sqrt_fNext_39$D_OUT[463:348] : + ((int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_39$D_OUT[231:116] : + int_sqrt_fNext_39$D_OUT[463:348]), + int_sqrt_fNext_39$D_OUT[464] ? + int_sqrt_fNext_39$D_OUT[347:0] : + { _theResult___snd_fst__h41301, + (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_39$D_OUT[231:0] : + { _theResult___snd_snd__h41377, b__h41374 } } } ; + assign int_sqrt_fNext_40$ENQ = CAN_FIRE_RL_int_sqrt_work_40 ; + assign int_sqrt_fNext_40$DEQ = CAN_FIRE_RL_int_sqrt_work_41 ; + assign int_sqrt_fNext_40$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_41 + assign int_sqrt_fNext_41$D_IN = + { int_sqrt_fNext_40$D_OUT[464] || + int_sqrt_fNext_40$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_40$D_OUT[464] ? + int_sqrt_fNext_40$D_OUT[463:348] : + ((int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_40$D_OUT[231:116] : + int_sqrt_fNext_40$D_OUT[463:348]), + int_sqrt_fNext_40$D_OUT[464] ? + int_sqrt_fNext_40$D_OUT[347:0] : + { _theResult___snd_fst__h41701, + (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_40$D_OUT[231:0] : + { _theResult___snd_snd__h41777, b__h41774 } } } ; + assign int_sqrt_fNext_41$ENQ = CAN_FIRE_RL_int_sqrt_work_41 ; + assign int_sqrt_fNext_41$DEQ = CAN_FIRE_RL_int_sqrt_work_42 ; + assign int_sqrt_fNext_41$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_42 + assign int_sqrt_fNext_42$D_IN = + { int_sqrt_fNext_41$D_OUT[464] || + int_sqrt_fNext_41$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_41$D_OUT[464] ? + int_sqrt_fNext_41$D_OUT[463:348] : + ((int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_41$D_OUT[231:116] : + int_sqrt_fNext_41$D_OUT[463:348]), + int_sqrt_fNext_41$D_OUT[464] ? + int_sqrt_fNext_41$D_OUT[347:0] : + { _theResult___snd_fst__h42101, + (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_41$D_OUT[231:0] : + { _theResult___snd_snd__h42177, b__h42174 } } } ; + assign int_sqrt_fNext_42$ENQ = CAN_FIRE_RL_int_sqrt_work_42 ; + assign int_sqrt_fNext_42$DEQ = CAN_FIRE_RL_int_sqrt_work_43 ; + assign int_sqrt_fNext_42$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_43 + assign int_sqrt_fNext_43$D_IN = + { int_sqrt_fNext_42$D_OUT[464] || + int_sqrt_fNext_42$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_42$D_OUT[464] ? + int_sqrt_fNext_42$D_OUT[463:348] : + ((int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_42$D_OUT[231:116] : + int_sqrt_fNext_42$D_OUT[463:348]), + int_sqrt_fNext_42$D_OUT[464] ? + int_sqrt_fNext_42$D_OUT[347:0] : + { _theResult___snd_fst__h42501, + (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_42$D_OUT[231:0] : + { _theResult___snd_snd__h42577, b__h42574 } } } ; + assign int_sqrt_fNext_43$ENQ = CAN_FIRE_RL_int_sqrt_work_43 ; + assign int_sqrt_fNext_43$DEQ = CAN_FIRE_RL_int_sqrt_work_44 ; + assign int_sqrt_fNext_43$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_44 + assign int_sqrt_fNext_44$D_IN = + { int_sqrt_fNext_43$D_OUT[464] || + int_sqrt_fNext_43$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_43$D_OUT[464] ? + int_sqrt_fNext_43$D_OUT[463:348] : + ((int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_43$D_OUT[231:116] : + int_sqrt_fNext_43$D_OUT[463:348]), + int_sqrt_fNext_43$D_OUT[464] ? + int_sqrt_fNext_43$D_OUT[347:0] : + { _theResult___snd_fst__h42901, + (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_43$D_OUT[231:0] : + { _theResult___snd_snd__h42977, b__h42974 } } } ; + assign int_sqrt_fNext_44$ENQ = CAN_FIRE_RL_int_sqrt_work_44 ; + assign int_sqrt_fNext_44$DEQ = CAN_FIRE_RL_int_sqrt_work_45 ; + assign int_sqrt_fNext_44$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_45 + assign int_sqrt_fNext_45$D_IN = + { int_sqrt_fNext_44$D_OUT[464] || + int_sqrt_fNext_44$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_44$D_OUT[464] ? + int_sqrt_fNext_44$D_OUT[463:348] : + ((int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_44$D_OUT[231:116] : + int_sqrt_fNext_44$D_OUT[463:348]), + int_sqrt_fNext_44$D_OUT[464] ? + int_sqrt_fNext_44$D_OUT[347:0] : + { _theResult___snd_fst__h43301, + (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_44$D_OUT[231:0] : + { _theResult___snd_snd__h43377, b__h43374 } } } ; + assign int_sqrt_fNext_45$ENQ = CAN_FIRE_RL_int_sqrt_work_45 ; + assign int_sqrt_fNext_45$DEQ = CAN_FIRE_RL_int_sqrt_work_46 ; + assign int_sqrt_fNext_45$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_46 + assign int_sqrt_fNext_46$D_IN = + { int_sqrt_fNext_45$D_OUT[464] || + int_sqrt_fNext_45$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_45$D_OUT[464] ? + int_sqrt_fNext_45$D_OUT[463:348] : + ((int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_45$D_OUT[231:116] : + int_sqrt_fNext_45$D_OUT[463:348]), + int_sqrt_fNext_45$D_OUT[464] ? + int_sqrt_fNext_45$D_OUT[347:0] : + { _theResult___snd_fst__h43701, + (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_45$D_OUT[231:0] : + { _theResult___snd_snd__h43777, b__h43774 } } } ; + assign int_sqrt_fNext_46$ENQ = CAN_FIRE_RL_int_sqrt_work_46 ; + assign int_sqrt_fNext_46$DEQ = CAN_FIRE_RL_int_sqrt_work_47 ; + assign int_sqrt_fNext_46$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_47 + assign int_sqrt_fNext_47$D_IN = + { int_sqrt_fNext_46$D_OUT[464] || + int_sqrt_fNext_46$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_46$D_OUT[464] ? + int_sqrt_fNext_46$D_OUT[463:348] : + ((int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_46$D_OUT[231:116] : + int_sqrt_fNext_46$D_OUT[463:348]), + int_sqrt_fNext_46$D_OUT[464] ? + int_sqrt_fNext_46$D_OUT[347:0] : + { _theResult___snd_fst__h44101, + (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_46$D_OUT[231:0] : + { _theResult___snd_snd__h44177, b__h44174 } } } ; + assign int_sqrt_fNext_47$ENQ = CAN_FIRE_RL_int_sqrt_work_47 ; + assign int_sqrt_fNext_47$DEQ = CAN_FIRE_RL_int_sqrt_work_48 ; + assign int_sqrt_fNext_47$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_48 + assign int_sqrt_fNext_48$D_IN = + { int_sqrt_fNext_47$D_OUT[464] || + int_sqrt_fNext_47$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_47$D_OUT[464] ? + int_sqrt_fNext_47$D_OUT[463:348] : + ((int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_47$D_OUT[231:116] : + int_sqrt_fNext_47$D_OUT[463:348]), + int_sqrt_fNext_47$D_OUT[464] ? + int_sqrt_fNext_47$D_OUT[347:0] : + { _theResult___snd_fst__h44501, + (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_47$D_OUT[231:0] : + { _theResult___snd_snd__h44577, b__h44574 } } } ; + assign int_sqrt_fNext_48$ENQ = CAN_FIRE_RL_int_sqrt_work_48 ; + assign int_sqrt_fNext_48$DEQ = CAN_FIRE_RL_int_sqrt_work_49 ; + assign int_sqrt_fNext_48$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_49 + assign int_sqrt_fNext_49$D_IN = + { int_sqrt_fNext_48$D_OUT[464] || + int_sqrt_fNext_48$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_48$D_OUT[464] ? + int_sqrt_fNext_48$D_OUT[463:348] : + ((int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_48$D_OUT[231:116] : + int_sqrt_fNext_48$D_OUT[463:348]), + int_sqrt_fNext_48$D_OUT[464] ? + int_sqrt_fNext_48$D_OUT[347:0] : + { _theResult___snd_fst__h44901, + (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_48$D_OUT[231:0] : + { _theResult___snd_snd__h44977, b__h44974 } } } ; + assign int_sqrt_fNext_49$ENQ = CAN_FIRE_RL_int_sqrt_work_49 ; + assign int_sqrt_fNext_49$DEQ = CAN_FIRE_RL_int_sqrt_work_50 ; + assign int_sqrt_fNext_49$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_5 + assign int_sqrt_fNext_5$D_IN = + { int_sqrt_fNext_4$D_OUT[464] || + int_sqrt_fNext_4$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_4$D_OUT[464] ? + int_sqrt_fNext_4$D_OUT[463:348] : + ((int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_4$D_OUT[231:116] : + int_sqrt_fNext_4$D_OUT[463:348]), + int_sqrt_fNext_4$D_OUT[464] ? + int_sqrt_fNext_4$D_OUT[347:0] : + { _theResult___snd_fst__h27301, + (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_4$D_OUT[231:0] : + { _theResult___snd_snd__h27377, b__h27374 } } } ; + assign int_sqrt_fNext_5$ENQ = CAN_FIRE_RL_int_sqrt_work_5 ; + assign int_sqrt_fNext_5$DEQ = CAN_FIRE_RL_int_sqrt_work_6 ; + assign int_sqrt_fNext_5$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_50 + assign int_sqrt_fNext_50$D_IN = + { int_sqrt_fNext_49$D_OUT[464] || + int_sqrt_fNext_49$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_49$D_OUT[464] ? + int_sqrt_fNext_49$D_OUT[463:348] : + ((int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_49$D_OUT[231:116] : + int_sqrt_fNext_49$D_OUT[463:348]), + int_sqrt_fNext_49$D_OUT[464] ? + int_sqrt_fNext_49$D_OUT[347:0] : + { _theResult___snd_fst__h45301, + (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_49$D_OUT[231:0] : + { _theResult___snd_snd__h45377, b__h45374 } } } ; + assign int_sqrt_fNext_50$ENQ = CAN_FIRE_RL_int_sqrt_work_50 ; + assign int_sqrt_fNext_50$DEQ = CAN_FIRE_RL_int_sqrt_work_51 ; + assign int_sqrt_fNext_50$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_51 + assign int_sqrt_fNext_51$D_IN = + { int_sqrt_fNext_50$D_OUT[464] || + int_sqrt_fNext_50$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_50$D_OUT[464] ? + int_sqrt_fNext_50$D_OUT[463:348] : + ((int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_50$D_OUT[231:116] : + int_sqrt_fNext_50$D_OUT[463:348]), + int_sqrt_fNext_50$D_OUT[464] ? + int_sqrt_fNext_50$D_OUT[347:0] : + { _theResult___snd_fst__h45701, + (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_50$D_OUT[231:0] : + { _theResult___snd_snd__h45777, b__h45774 } } } ; + assign int_sqrt_fNext_51$ENQ = CAN_FIRE_RL_int_sqrt_work_51 ; + assign int_sqrt_fNext_51$DEQ = CAN_FIRE_RL_int_sqrt_work_52 ; + assign int_sqrt_fNext_51$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_52 + assign int_sqrt_fNext_52$D_IN = + { int_sqrt_fNext_51$D_OUT[464] || + int_sqrt_fNext_51$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_51$D_OUT[464] ? + int_sqrt_fNext_51$D_OUT[463:348] : + ((int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_51$D_OUT[231:116] : + int_sqrt_fNext_51$D_OUT[463:348]), + int_sqrt_fNext_51$D_OUT[464] ? + int_sqrt_fNext_51$D_OUT[347:0] : + { _theResult___snd_fst__h46101, + (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_51$D_OUT[231:0] : + { _theResult___snd_snd__h46177, b__h46174 } } } ; + assign int_sqrt_fNext_52$ENQ = CAN_FIRE_RL_int_sqrt_work_52 ; + assign int_sqrt_fNext_52$DEQ = CAN_FIRE_RL_int_sqrt_work_53 ; + assign int_sqrt_fNext_52$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_53 + assign int_sqrt_fNext_53$D_IN = + { int_sqrt_fNext_52$D_OUT[464] || + int_sqrt_fNext_52$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_52$D_OUT[464] ? + int_sqrt_fNext_52$D_OUT[463:348] : + ((int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_52$D_OUT[231:116] : + int_sqrt_fNext_52$D_OUT[463:348]), + int_sqrt_fNext_52$D_OUT[464] ? + int_sqrt_fNext_52$D_OUT[347:0] : + { _theResult___snd_fst__h46501, + (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_52$D_OUT[231:0] : + { _theResult___snd_snd__h46577, b__h46574 } } } ; + assign int_sqrt_fNext_53$ENQ = CAN_FIRE_RL_int_sqrt_work_53 ; + assign int_sqrt_fNext_53$DEQ = CAN_FIRE_RL_int_sqrt_work_54 ; + assign int_sqrt_fNext_53$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_54 + assign int_sqrt_fNext_54$D_IN = + { int_sqrt_fNext_53$D_OUT[464] || + int_sqrt_fNext_53$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_53$D_OUT[464] ? + int_sqrt_fNext_53$D_OUT[463:348] : + ((int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_53$D_OUT[231:116] : + int_sqrt_fNext_53$D_OUT[463:348]), + int_sqrt_fNext_53$D_OUT[464] ? + int_sqrt_fNext_53$D_OUT[347:0] : + { _theResult___snd_fst__h46901, + (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_53$D_OUT[231:0] : + { _theResult___snd_snd__h46977, b__h46974 } } } ; + assign int_sqrt_fNext_54$ENQ = CAN_FIRE_RL_int_sqrt_work_54 ; + assign int_sqrt_fNext_54$DEQ = CAN_FIRE_RL_int_sqrt_work_55 ; + assign int_sqrt_fNext_54$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_55 + assign int_sqrt_fNext_55$D_IN = + { int_sqrt_fNext_54$D_OUT[464] || + int_sqrt_fNext_54$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_54$D_OUT[464] ? + int_sqrt_fNext_54$D_OUT[463:348] : + ((int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_54$D_OUT[231:116] : + int_sqrt_fNext_54$D_OUT[463:348]), + int_sqrt_fNext_54$D_OUT[464] ? + int_sqrt_fNext_54$D_OUT[347:0] : + { _theResult___snd_fst__h47301, + (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_54$D_OUT[231:0] : + { _theResult___snd_snd__h47377, b__h47374 } } } ; + assign int_sqrt_fNext_55$ENQ = CAN_FIRE_RL_int_sqrt_work_55 ; + assign int_sqrt_fNext_55$DEQ = CAN_FIRE_RL_int_sqrt_work_56 ; + assign int_sqrt_fNext_55$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_56 + assign int_sqrt_fNext_56$D_IN = + { int_sqrt_fNext_55$D_OUT[464] || + int_sqrt_fNext_55$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_55$D_OUT[464] ? + int_sqrt_fNext_55$D_OUT[463:348] : + ((int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_55$D_OUT[231:116] : + int_sqrt_fNext_55$D_OUT[463:348]), + int_sqrt_fNext_55$D_OUT[464] ? + int_sqrt_fNext_55$D_OUT[347:0] : + { _theResult___snd_fst__h47701, + (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_55$D_OUT[231:0] : + { _theResult___snd_snd__h47777, b__h47774 } } } ; + assign int_sqrt_fNext_56$ENQ = CAN_FIRE_RL_int_sqrt_work_56 ; + assign int_sqrt_fNext_56$DEQ = CAN_FIRE_RL_int_sqrt_work_57 ; + assign int_sqrt_fNext_56$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_57 + assign int_sqrt_fNext_57$D_IN = + { int_sqrt_fNext_56$D_OUT[464] || + int_sqrt_fNext_56$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_56$D_OUT[464] ? + int_sqrt_fNext_56$D_OUT[463:348] : + ((int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_56$D_OUT[231:116] : + int_sqrt_fNext_56$D_OUT[463:348]), + int_sqrt_fNext_56$D_OUT[464] ? + int_sqrt_fNext_56$D_OUT[347:0] : + { _theResult___snd_fst__h48101, + (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_56$D_OUT[231:0] : + { _theResult___snd_snd__h48177, b__h48174 } } } ; + assign int_sqrt_fNext_57$ENQ = CAN_FIRE_RL_int_sqrt_work_57 ; + assign int_sqrt_fNext_57$DEQ = CAN_FIRE_RL_int_sqrt_work_58 ; + assign int_sqrt_fNext_57$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_58 + assign int_sqrt_fNext_58$D_IN = + { int_sqrt_fNext_57$D_OUT[464] || + int_sqrt_fNext_57$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_57$D_OUT[464] ? + int_sqrt_fNext_57$D_OUT[463:348] : + ((int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_57$D_OUT[231:116] : + int_sqrt_fNext_57$D_OUT[463:348]), + int_sqrt_fNext_57$D_OUT[464] ? + int_sqrt_fNext_57$D_OUT[347:0] : + { _theResult___snd_fst__h48501, + (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_57$D_OUT[231:0] : + { _theResult___snd_snd__h48577, b__h48574 } } } ; + assign int_sqrt_fNext_58$ENQ = CAN_FIRE_RL_int_sqrt_work_58 ; + assign int_sqrt_fNext_58$DEQ = CAN_FIRE_RL_int_sqrt_finish ; + assign int_sqrt_fNext_58$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_6 + assign int_sqrt_fNext_6$D_IN = + { int_sqrt_fNext_5$D_OUT[464] || + int_sqrt_fNext_5$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_5$D_OUT[464] ? + int_sqrt_fNext_5$D_OUT[463:348] : + ((int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_5$D_OUT[231:116] : + int_sqrt_fNext_5$D_OUT[463:348]), + int_sqrt_fNext_5$D_OUT[464] ? + int_sqrt_fNext_5$D_OUT[347:0] : + { _theResult___snd_fst__h27701, + (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_5$D_OUT[231:0] : + { _theResult___snd_snd__h27777, b__h27774 } } } ; + assign int_sqrt_fNext_6$ENQ = CAN_FIRE_RL_int_sqrt_work_6 ; + assign int_sqrt_fNext_6$DEQ = CAN_FIRE_RL_int_sqrt_work_7 ; + assign int_sqrt_fNext_6$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_7 + assign int_sqrt_fNext_7$D_IN = + { int_sqrt_fNext_6$D_OUT[464] || + int_sqrt_fNext_6$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_6$D_OUT[464] ? + int_sqrt_fNext_6$D_OUT[463:348] : + ((int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_6$D_OUT[231:116] : + int_sqrt_fNext_6$D_OUT[463:348]), + int_sqrt_fNext_6$D_OUT[464] ? + int_sqrt_fNext_6$D_OUT[347:0] : + { _theResult___snd_fst__h28101, + (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_6$D_OUT[231:0] : + { _theResult___snd_snd__h28177, b__h28174 } } } ; + assign int_sqrt_fNext_7$ENQ = CAN_FIRE_RL_int_sqrt_work_7 ; + assign int_sqrt_fNext_7$DEQ = CAN_FIRE_RL_int_sqrt_work_8 ; + assign int_sqrt_fNext_7$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_8 + assign int_sqrt_fNext_8$D_IN = + { int_sqrt_fNext_7$D_OUT[464] || + int_sqrt_fNext_7$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_7$D_OUT[464] ? + int_sqrt_fNext_7$D_OUT[463:348] : + ((int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_7$D_OUT[231:116] : + int_sqrt_fNext_7$D_OUT[463:348]), + int_sqrt_fNext_7$D_OUT[464] ? + int_sqrt_fNext_7$D_OUT[347:0] : + { _theResult___snd_fst__h28501, + (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_7$D_OUT[231:0] : + { _theResult___snd_snd__h28577, b__h28574 } } } ; + assign int_sqrt_fNext_8$ENQ = CAN_FIRE_RL_int_sqrt_work_8 ; + assign int_sqrt_fNext_8$DEQ = CAN_FIRE_RL_int_sqrt_work_9 ; + assign int_sqrt_fNext_8$CLR = 1'b0 ; + + // submodule int_sqrt_fNext_9 + assign int_sqrt_fNext_9$D_IN = + { int_sqrt_fNext_8$D_OUT[464] || + int_sqrt_fNext_8$D_OUT[115:0] == 116'd0, + int_sqrt_fNext_8$D_OUT[464] ? + int_sqrt_fNext_8$D_OUT[463:348] : + ((int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_8$D_OUT[231:116] : + int_sqrt_fNext_8$D_OUT[463:348]), + int_sqrt_fNext_8$D_OUT[464] ? + int_sqrt_fNext_8$D_OUT[347:0] : + { _theResult___snd_fst__h28901, + (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? + int_sqrt_fNext_8$D_OUT[231:0] : + { _theResult___snd_snd__h28977, b__h28974 } } } ; + assign int_sqrt_fNext_9$ENQ = CAN_FIRE_RL_int_sqrt_work_9 ; + assign int_sqrt_fNext_9$DEQ = CAN_FIRE_RL_int_sqrt_work_10 ; + assign int_sqrt_fNext_9$CLR = 1'b0 ; + + // submodule int_sqrt_fRequest + assign int_sqrt_fRequest$D_IN = { fpu_fState_S1$D_OUT[57:0], 58'd0 } ; + assign int_sqrt_fRequest$ENQ = + WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[194] ; + assign int_sqrt_fRequest$DEQ = CAN_FIRE_RL_int_sqrt_start ; + assign int_sqrt_fRequest$CLR = 1'b0 ; + + // submodule int_sqrt_fResponse + assign int_sqrt_fResponse$D_IN = + { b__h48712, int_sqrt_fNext_58$D_OUT[347:232] != 116'd0 } ; + assign int_sqrt_fResponse$ENQ = CAN_FIRE_RL_int_sqrt_finish ; + assign int_sqrt_fResponse$DEQ = + WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[136] ; + assign int_sqrt_fResponse$CLR = 1'b0 ; + + // remaining internal signals + assign IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6 = + _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 ? + _theResult___snd__h75342 : + _theResult___snd__h75337 ; + assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 = + sfd__h75932[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 63'h7FF0000000000000 : + { din_inc___2_exp__h76519, sfd__h75932[52:1] }) : + { IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, + sfd__h75932[51:0] } ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 = + (fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? + (fpu_fOperand_S0$D_OUT[54] ? + 6'd2 : + (fpu_fOperand_S0$D_OUT[53] ? + 6'd3 : + (fpu_fOperand_S0$D_OUT[52] ? + 6'd4 : + (fpu_fOperand_S0$D_OUT[51] ? + 6'd5 : + (fpu_fOperand_S0$D_OUT[50] ? + 6'd6 : + (fpu_fOperand_S0$D_OUT[49] ? + 6'd7 : + (fpu_fOperand_S0$D_OUT[48] ? + 6'd8 : + (fpu_fOperand_S0$D_OUT[47] ? + 6'd9 : + (fpu_fOperand_S0$D_OUT[46] ? + 6'd10 : + (fpu_fOperand_S0$D_OUT[45] ? + 6'd11 : + (fpu_fOperand_S0$D_OUT[44] ? + 6'd12 : + (fpu_fOperand_S0$D_OUT[43] ? + 6'd13 : + (fpu_fOperand_S0$D_OUT[42] ? + 6'd14 : + (fpu_fOperand_S0$D_OUT[41] ? + 6'd15 : + (fpu_fOperand_S0$D_OUT[40] ? + 6'd16 : + (fpu_fOperand_S0$D_OUT[39] ? + 6'd17 : + (fpu_fOperand_S0$D_OUT[38] ? + 6'd18 : + (fpu_fOperand_S0$D_OUT[37] ? + 6'd19 : + (fpu_fOperand_S0$D_OUT[36] ? + 6'd20 : + (fpu_fOperand_S0$D_OUT[35] ? + 6'd21 : + (fpu_fOperand_S0$D_OUT[34] ? + 6'd22 : + (fpu_fOperand_S0$D_OUT[33] ? + 6'd23 : + (fpu_fOperand_S0$D_OUT[32] ? + 6'd24 : + (fpu_fOperand_S0$D_OUT[31] ? + 6'd25 : + (fpu_fOperand_S0$D_OUT[30] ? + 6'd26 : + (fpu_fOperand_S0$D_OUT[29] ? + 6'd27 : + (fpu_fOperand_S0$D_OUT[28] ? + 6'd28 : + (fpu_fOperand_S0$D_OUT[27] ? + 6'd29 : + (fpu_fOperand_S0$D_OUT[26] ? + 6'd30 : + (fpu_fOperand_S0$D_OUT[25] ? + 6'd31 : + (fpu_fOperand_S0$D_OUT[24] ? + 6'd32 : + (fpu_fOperand_S0$D_OUT[23] ? + 6'd33 : + (fpu_fOperand_S0$D_OUT[22] ? + 6'd34 : + (fpu_fOperand_S0$D_OUT[21] ? + 6'd35 : + (fpu_fOperand_S0$D_OUT[20] ? + 6'd36 : + (fpu_fOperand_S0$D_OUT[19] ? + 6'd37 : + (fpu_fOperand_S0$D_OUT[18] ? + 6'd38 : + (fpu_fOperand_S0$D_OUT[17] ? + 6'd39 : + (fpu_fOperand_S0$D_OUT[16] ? + 6'd40 : + (fpu_fOperand_S0$D_OUT[15] ? + 6'd41 : + (fpu_fOperand_S0$D_OUT[14] ? + 6'd42 : + (fpu_fOperand_S0$D_OUT[13] ? + 6'd43 : + (fpu_fOperand_S0$D_OUT[12] ? + 6'd44 : + (fpu_fOperand_S0$D_OUT[11] ? + 6'd45 : + (fpu_fOperand_S0$D_OUT[10] ? + 6'd46 : + (fpu_fOperand_S0$D_OUT[9] ? + 6'd47 : + (fpu_fOperand_S0$D_OUT[8] ? + 6'd48 : + (fpu_fOperand_S0$D_OUT[7] ? + 6'd49 : + (fpu_fOperand_S0$D_OUT[6] ? + 6'd50 : + (fpu_fOperand_S0$D_OUT[5] ? + 6'd51 : + (fpu_fOperand_S0$D_OUT[4] ? + 6'd52 : + (fpu_fOperand_S0$D_OUT[3] ? + 6'd53 : + 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : + 6'd1 ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460 = + ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? + 13'd7170 : + { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8[10]}}, + fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 }) - + { 7'd0, + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 } ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 = + (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54] || + fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || + fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && + fpu_fOperand_S0$D_OUT[54:3] == 52'd0 && + !fpu_fOperand_S0$D_OUT[66]) ? + { 1'd1, + fpu_fOperand_S0$D_OUT[66:3], + 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : + (fpu_fOperand_S0$D_OUT[66] ? + 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : + { 70'h155555555555555540, + fpu_fOperand_S0$D_OUT[2:0], + fpu_fOperand_S0$D_OUT[66], + x__h57541[10:0], + fpu_fOperand_S0$D_OUT[54:3], + x__h65683 }) ; + assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 = + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[12:1] ; + assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 = + (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? + 12'd3074 : + { fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5[10], + fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 } ; + assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 = + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 - + 12'd3074 ; + assign IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813 = + fpu_fState_S3$D_OUT[195] ? + fpu_fState_S3$D_OUT[128:126] : + { fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023, + _theResult___fst_exp__h75269 == 11'd0 && + guard__h66951 != 2'd0, + fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023 } ; + assign IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820 = + (fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023) ? + 63'h7FEFFFFFFFFFFFFF : + { _theResult___fst_exp__h75266, sfdin__h75260[58:7] } ; + assign IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 = + (fpu_fState_S3$D_OUT[58] ? + 6'd0 : + (fpu_fState_S3$D_OUT[57] ? + 6'd1 : + (fpu_fState_S3$D_OUT[56] ? + 6'd2 : + (fpu_fState_S3$D_OUT[55] ? + 6'd3 : + (fpu_fState_S3$D_OUT[54] ? + 6'd4 : + (fpu_fState_S3$D_OUT[53] ? + 6'd5 : + (fpu_fState_S3$D_OUT[52] ? + 6'd6 : + (fpu_fState_S3$D_OUT[51] ? + 6'd7 : + (fpu_fState_S3$D_OUT[50] ? + 6'd8 : + (fpu_fState_S3$D_OUT[49] ? + 6'd9 : + (fpu_fState_S3$D_OUT[48] ? + 6'd10 : + (fpu_fState_S3$D_OUT[47] ? + 6'd11 : + (fpu_fState_S3$D_OUT[46] ? + 6'd12 : + (fpu_fState_S3$D_OUT[45] ? + 6'd13 : + (fpu_fState_S3$D_OUT[44] ? + 6'd14 : + (fpu_fState_S3$D_OUT[43] ? + 6'd15 : + (fpu_fState_S3$D_OUT[42] ? + 6'd16 : + (fpu_fState_S3$D_OUT[41] ? + 6'd17 : + (fpu_fState_S3$D_OUT[40] ? + 6'd18 : + (fpu_fState_S3$D_OUT[39] ? + 6'd19 : + (fpu_fState_S3$D_OUT[38] ? + 6'd20 : + (fpu_fState_S3$D_OUT[37] ? + 6'd21 : + (fpu_fState_S3$D_OUT[36] ? + 6'd22 : + (fpu_fState_S3$D_OUT[35] ? + 6'd23 : + (fpu_fState_S3$D_OUT[34] ? + 6'd24 : + (fpu_fState_S3$D_OUT[33] ? + 6'd25 : + (fpu_fState_S3$D_OUT[32] ? + 6'd26 : + (fpu_fState_S3$D_OUT[31] ? + 6'd27 : + (fpu_fState_S3$D_OUT[30] ? + 6'd28 : + (fpu_fState_S3$D_OUT[29] ? + 6'd29 : + (fpu_fState_S3$D_OUT[28] ? + 6'd30 : + (fpu_fState_S3$D_OUT[27] ? + 6'd31 : + (fpu_fState_S3$D_OUT[26] ? + 6'd32 : + (fpu_fState_S3$D_OUT[25] ? + 6'd33 : + (fpu_fState_S3$D_OUT[24] ? + 6'd34 : + (fpu_fState_S3$D_OUT[23] ? + 6'd35 : + (fpu_fState_S3$D_OUT[22] ? + 6'd36 : + (fpu_fState_S3$D_OUT[21] ? + 6'd37 : + (fpu_fState_S3$D_OUT[20] ? + 6'd38 : + (fpu_fState_S3$D_OUT[19] ? + 6'd39 : + (fpu_fState_S3$D_OUT[18] ? + 6'd40 : + (fpu_fState_S3$D_OUT[17] ? + 6'd41 : + (fpu_fState_S3$D_OUT[16] ? + 6'd42 : + (fpu_fState_S3$D_OUT[15] ? + 6'd43 : + (fpu_fState_S3$D_OUT[14] ? + 6'd44 : + (fpu_fState_S3$D_OUT[13] ? + 6'd45 : + (fpu_fState_S3$D_OUT[12] ? + 6'd46 : + (fpu_fState_S3$D_OUT[11] ? + 6'd47 : + (fpu_fState_S3$D_OUT[10] ? + 6'd48 : + (fpu_fState_S3$D_OUT[9] ? + 6'd49 : + (fpu_fState_S3$D_OUT[8] ? + 6'd50 : + (fpu_fState_S3$D_OUT[7] ? + 6'd51 : + (fpu_fState_S3$D_OUT[6] ? + 6'd52 : + (fpu_fState_S3$D_OUT[5] ? + 6'd53 : + (fpu_fState_S3$D_OUT[4] ? + 6'd54 : + (fpu_fState_S3$D_OUT[3] ? + 6'd55 : + (fpu_fState_S3$D_OUT[2] ? + 6'd56 : + (fpu_fState_S3$D_OUT[1] ? + 6'd57 : + (fpu_fState_S3$D_OUT[0] ? + 6'd58 : + 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 6'd1 ; + assign IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 = + (fpu_fState_S4$D_OUT[64:54] == 11'd0 && + sfd__h75932[53:52] == 2'b01) ? + 11'd1 : + fpu_fState_S4$D_OUT[64:54] ; + assign IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 = + (int_sqrt_fRequest$D_OUT[115] ? + 7'd0 : + (int_sqrt_fRequest$D_OUT[114] ? + 7'd1 : + (int_sqrt_fRequest$D_OUT[113] ? + 7'd2 : + (int_sqrt_fRequest$D_OUT[112] ? + 7'd3 : + (int_sqrt_fRequest$D_OUT[111] ? + 7'd4 : + (int_sqrt_fRequest$D_OUT[110] ? + 7'd5 : + (int_sqrt_fRequest$D_OUT[109] ? + 7'd6 : + (int_sqrt_fRequest$D_OUT[108] ? + 7'd7 : + (int_sqrt_fRequest$D_OUT[107] ? + 7'd8 : + (int_sqrt_fRequest$D_OUT[106] ? + 7'd9 : + (int_sqrt_fRequest$D_OUT[105] ? + 7'd10 : + (int_sqrt_fRequest$D_OUT[104] ? + 7'd11 : + (int_sqrt_fRequest$D_OUT[103] ? + 7'd12 : + (int_sqrt_fRequest$D_OUT[102] ? + 7'd13 : + (int_sqrt_fRequest$D_OUT[101] ? + 7'd14 : + (int_sqrt_fRequest$D_OUT[100] ? + 7'd15 : + (int_sqrt_fRequest$D_OUT[99] ? + 7'd16 : + (int_sqrt_fRequest$D_OUT[98] ? + 7'd17 : + (int_sqrt_fRequest$D_OUT[97] ? + 7'd18 : + (int_sqrt_fRequest$D_OUT[96] ? + 7'd19 : + (int_sqrt_fRequest$D_OUT[95] ? + 7'd20 : + (int_sqrt_fRequest$D_OUT[94] ? + 7'd21 : + (int_sqrt_fRequest$D_OUT[93] ? + 7'd22 : + (int_sqrt_fRequest$D_OUT[92] ? + 7'd23 : + (int_sqrt_fRequest$D_OUT[91] ? + 7'd24 : + (int_sqrt_fRequest$D_OUT[90] ? + 7'd25 : + (int_sqrt_fRequest$D_OUT[89] ? + 7'd26 : + (int_sqrt_fRequest$D_OUT[88] ? + 7'd27 : + (int_sqrt_fRequest$D_OUT[87] ? + 7'd28 : + (int_sqrt_fRequest$D_OUT[86] ? + 7'd29 : + (int_sqrt_fRequest$D_OUT[85] ? + 7'd30 : + (int_sqrt_fRequest$D_OUT[84] ? + 7'd31 : + (int_sqrt_fRequest$D_OUT[83] ? + 7'd32 : + (int_sqrt_fRequest$D_OUT[82] ? + 7'd33 : + (int_sqrt_fRequest$D_OUT[81] ? + 7'd34 : + (int_sqrt_fRequest$D_OUT[80] ? + 7'd35 : + (int_sqrt_fRequest$D_OUT[79] ? + 7'd36 : + (int_sqrt_fRequest$D_OUT[78] ? + 7'd37 : + (int_sqrt_fRequest$D_OUT[77] ? + 7'd38 : + (int_sqrt_fRequest$D_OUT[76] ? + 7'd39 : + (int_sqrt_fRequest$D_OUT[75] ? + 7'd40 : + (int_sqrt_fRequest$D_OUT[74] ? + 7'd41 : + (int_sqrt_fRequest$D_OUT[73] ? + 7'd42 : + (int_sqrt_fRequest$D_OUT[72] ? + 7'd43 : + (int_sqrt_fRequest$D_OUT[71] ? + 7'd44 : + (int_sqrt_fRequest$D_OUT[70] ? + 7'd45 : + (int_sqrt_fRequest$D_OUT[69] ? + 7'd46 : + (int_sqrt_fRequest$D_OUT[68] ? + 7'd47 : + (int_sqrt_fRequest$D_OUT[67] ? + 7'd48 : + (int_sqrt_fRequest$D_OUT[66] ? + 7'd49 : + (int_sqrt_fRequest$D_OUT[65] ? + 7'd50 : + (int_sqrt_fRequest$D_OUT[64] ? + 7'd51 : + (int_sqrt_fRequest$D_OUT[63] ? + 7'd52 : + (int_sqrt_fRequest$D_OUT[62] ? + 7'd53 : + (int_sqrt_fRequest$D_OUT[61] ? + 7'd54 : + (int_sqrt_fRequest$D_OUT[60] ? + 7'd55 : + (int_sqrt_fRequest$D_OUT[59] ? + 7'd56 : + (int_sqrt_fRequest$D_OUT[58] ? + 7'd57 : + (int_sqrt_fRequest$D_OUT[57] ? + 7'd58 : + (int_sqrt_fRequest$D_OUT[56] ? + 7'd59 : + (int_sqrt_fRequest$D_OUT[55] ? + 7'd60 : + (int_sqrt_fRequest$D_OUT[54] ? + 7'd61 : + (int_sqrt_fRequest$D_OUT[53] ? + 7'd62 : + (int_sqrt_fRequest$D_OUT[52] ? + 7'd63 : + (int_sqrt_fRequest$D_OUT[51] ? + 7'd64 : + (int_sqrt_fRequest$D_OUT[50] ? + 7'd65 : + (int_sqrt_fRequest$D_OUT[49] ? + 7'd66 : + (int_sqrt_fRequest$D_OUT[48] ? + 7'd67 : + (int_sqrt_fRequest$D_OUT[47] ? + 7'd68 : + (int_sqrt_fRequest$D_OUT[46] ? + 7'd69 : + (int_sqrt_fRequest$D_OUT[45] ? + 7'd70 : + (int_sqrt_fRequest$D_OUT[44] ? + 7'd71 : + (int_sqrt_fRequest$D_OUT[43] ? + 7'd72 : + (int_sqrt_fRequest$D_OUT[42] ? + 7'd73 : + (int_sqrt_fRequest$D_OUT[41] ? + 7'd74 : + (int_sqrt_fRequest$D_OUT[40] ? + 7'd75 : + (int_sqrt_fRequest$D_OUT[39] ? + 7'd76 : + (int_sqrt_fRequest$D_OUT[38] ? + 7'd77 : + (int_sqrt_fRequest$D_OUT[37] ? + 7'd78 : + (int_sqrt_fRequest$D_OUT[36] ? + 7'd79 : + (int_sqrt_fRequest$D_OUT[35] ? + 7'd80 : + (int_sqrt_fRequest$D_OUT[34] ? + 7'd81 : + (int_sqrt_fRequest$D_OUT[33] ? + 7'd82 : + (int_sqrt_fRequest$D_OUT[32] ? + 7'd83 : + (int_sqrt_fRequest$D_OUT[31] ? + 7'd84 : + (int_sqrt_fRequest$D_OUT[30] ? + 7'd85 : + (int_sqrt_fRequest$D_OUT[29] ? + 7'd86 : + (int_sqrt_fRequest$D_OUT[28] ? + 7'd87 : + (int_sqrt_fRequest$D_OUT[27] ? + 7'd88 : + (int_sqrt_fRequest$D_OUT[26] ? + 7'd89 : + (int_sqrt_fRequest$D_OUT[25] ? + 7'd90 : + (int_sqrt_fRequest$D_OUT[24] ? + 7'd91 : + (int_sqrt_fRequest$D_OUT[23] ? + 7'd92 : + (int_sqrt_fRequest$D_OUT[22] ? + 7'd93 : + (int_sqrt_fRequest$D_OUT[21] ? + 7'd94 : + (int_sqrt_fRequest$D_OUT[20] ? + 7'd95 : + (int_sqrt_fRequest$D_OUT[19] ? + 7'd96 : + (int_sqrt_fRequest$D_OUT[18] ? + 7'd97 : + (int_sqrt_fRequest$D_OUT[17] ? + 7'd98 : + (int_sqrt_fRequest$D_OUT[16] ? + 7'd99 : + (int_sqrt_fRequest$D_OUT[15] ? + 7'd100 : + (int_sqrt_fRequest$D_OUT[14] ? + 7'd101 : + (int_sqrt_fRequest$D_OUT[13] ? + 7'd102 : + (int_sqrt_fRequest$D_OUT[12] ? + 7'd103 : + (int_sqrt_fRequest$D_OUT[11] ? + 7'd104 : + (int_sqrt_fRequest$D_OUT[10] ? + 7'd105 : + (int_sqrt_fRequest$D_OUT[9] ? + 7'd106 : + (int_sqrt_fRequest$D_OUT[8] ? + 7'd107 : + (int_sqrt_fRequest$D_OUT[7] ? + 7'd108 : + (int_sqrt_fRequest$D_OUT[6] ? + 7'd109 : + (int_sqrt_fRequest$D_OUT[5] ? + 7'd110 : + (int_sqrt_fRequest$D_OUT[4] ? + 7'd111 : + (int_sqrt_fRequest$D_OUT[3] ? + 7'd112 : + (int_sqrt_fRequest$D_OUT[2] ? + 7'd113 : + (int_sqrt_fRequest$D_OUT[1] ? + 7'd114 : + (int_sqrt_fRequest$D_OUT[0] ? + 7'd115 : + 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - + 7'd1 ; + assign IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7 = + sfdin__h75260[6] ? 2'd2 : 2'd0 ; + assign _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 = + ({ 6'd0, + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ^ + 12'h800) <= + (IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ^ + 12'h800) ; + assign _theResult___exp__h76428 = + sfd__h75932[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 11'd2047 : + din_inc___2_exp__h76519) : + IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 ; + assign _theResult___fst_exp__h75266 = + fpu_fState_S3$D_OUT[58] ? + _theResult___fst_exp__h75289 : + _theResult___fst_exp__h75353 ; + assign _theResult___fst_exp__h75269 = + (fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023) ? + 11'd2046 : + _theResult___fst_exp__h75266 ; + assign _theResult___fst_exp__h75289 = + (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? + 11'd2 : + fpu_fState_S3$D_OUT[121:111] + 11'd1 ; + assign _theResult___fst_exp__h75305 = + (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? + 11'd1 : + fpu_fState_S3$D_OUT[121:111] ; + assign _theResult___fst_exp__h75344 = + fpu_fState_S3$D_OUT[121:111] - + { 5'd0, + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ; + assign _theResult___fst_exp__h75350 = + (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && + !fpu_fState_S3$D_OUT[56] && + !fpu_fState_S3$D_OUT[55] && + !fpu_fState_S3$D_OUT[54] && + !fpu_fState_S3$D_OUT[53] && + !fpu_fState_S3$D_OUT[52] && + !fpu_fState_S3$D_OUT[51] && + !fpu_fState_S3$D_OUT[50] && + !fpu_fState_S3$D_OUT[49] && + !fpu_fState_S3$D_OUT[48] && + !fpu_fState_S3$D_OUT[47] && + !fpu_fState_S3$D_OUT[46] && + !fpu_fState_S3$D_OUT[45] && + !fpu_fState_S3$D_OUT[44] && + !fpu_fState_S3$D_OUT[43] && + !fpu_fState_S3$D_OUT[42] && + !fpu_fState_S3$D_OUT[41] && + !fpu_fState_S3$D_OUT[40] && + !fpu_fState_S3$D_OUT[39] && + !fpu_fState_S3$D_OUT[38] && + !fpu_fState_S3$D_OUT[37] && + !fpu_fState_S3$D_OUT[36] && + !fpu_fState_S3$D_OUT[35] && + !fpu_fState_S3$D_OUT[34] && + !fpu_fState_S3$D_OUT[33] && + !fpu_fState_S3$D_OUT[32] && + !fpu_fState_S3$D_OUT[31] && + !fpu_fState_S3$D_OUT[30] && + !fpu_fState_S3$D_OUT[29] && + !fpu_fState_S3$D_OUT[28] && + !fpu_fState_S3$D_OUT[27] && + !fpu_fState_S3$D_OUT[26] && + !fpu_fState_S3$D_OUT[25] && + !fpu_fState_S3$D_OUT[24] && + !fpu_fState_S3$D_OUT[23] && + !fpu_fState_S3$D_OUT[22] && + !fpu_fState_S3$D_OUT[21] && + !fpu_fState_S3$D_OUT[20] && + !fpu_fState_S3$D_OUT[19] && + !fpu_fState_S3$D_OUT[18] && + !fpu_fState_S3$D_OUT[17] && + !fpu_fState_S3$D_OUT[16] && + !fpu_fState_S3$D_OUT[15] && + !fpu_fState_S3$D_OUT[14] && + !fpu_fState_S3$D_OUT[13] && + !fpu_fState_S3$D_OUT[12] && + !fpu_fState_S3$D_OUT[11] && + !fpu_fState_S3$D_OUT[10] && + !fpu_fState_S3$D_OUT[9] && + !fpu_fState_S3$D_OUT[8] && + !fpu_fState_S3$D_OUT[7] && + !fpu_fState_S3$D_OUT[6] && + !fpu_fState_S3$D_OUT[5] && + !fpu_fState_S3$D_OUT[4] && + !fpu_fState_S3$D_OUT[3] && + !fpu_fState_S3$D_OUT[2] && + !fpu_fState_S3$D_OUT[1] && + !fpu_fState_S3$D_OUT[0] || + !_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775) ? + 11'd0 : + _theResult___fst_exp__h75344 ; + assign _theResult___fst_exp__h75353 = + (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? + _theResult___fst_exp__h75305 : + _theResult___fst_exp__h75350 ; + assign _theResult___fst_exp__h76509 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___fst_exp__h76506 ; + assign _theResult___fst_sfd__h76510 = + (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___fst_sfd__h76507 ; + assign _theResult___sfd__h76429 = + sfd__h75932[53] ? + ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? + 52'd0 : + sfd__h75932[52:1]) : + sfd__h75932[51:0] ; + assign _theResult___snd__h75283 = { fpu_fState_S3$D_OUT[57:0], 1'd0 } ; + assign _theResult___snd__h75298 = + (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? + _theResult___snd__h75300 : + _theResult___snd__h75313 ; + assign _theResult___snd__h75300 = { fpu_fState_S3$D_OUT[56:0], 2'd0 } ; + assign _theResult___snd__h75313 = + (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && + !fpu_fState_S3$D_OUT[56] && + !fpu_fState_S3$D_OUT[55] && + !fpu_fState_S3$D_OUT[54] && + !fpu_fState_S3$D_OUT[53] && + !fpu_fState_S3$D_OUT[52] && + !fpu_fState_S3$D_OUT[51] && + !fpu_fState_S3$D_OUT[50] && + !fpu_fState_S3$D_OUT[49] && + !fpu_fState_S3$D_OUT[48] && + !fpu_fState_S3$D_OUT[47] && + !fpu_fState_S3$D_OUT[46] && + !fpu_fState_S3$D_OUT[45] && + !fpu_fState_S3$D_OUT[44] && + !fpu_fState_S3$D_OUT[43] && + !fpu_fState_S3$D_OUT[42] && + !fpu_fState_S3$D_OUT[41] && + !fpu_fState_S3$D_OUT[40] && + !fpu_fState_S3$D_OUT[39] && + !fpu_fState_S3$D_OUT[38] && + !fpu_fState_S3$D_OUT[37] && + !fpu_fState_S3$D_OUT[36] && + !fpu_fState_S3$D_OUT[35] && + !fpu_fState_S3$D_OUT[34] && + !fpu_fState_S3$D_OUT[33] && + !fpu_fState_S3$D_OUT[32] && + !fpu_fState_S3$D_OUT[31] && + !fpu_fState_S3$D_OUT[30] && + !fpu_fState_S3$D_OUT[29] && + !fpu_fState_S3$D_OUT[28] && + !fpu_fState_S3$D_OUT[27] && + !fpu_fState_S3$D_OUT[26] && + !fpu_fState_S3$D_OUT[25] && + !fpu_fState_S3$D_OUT[24] && + !fpu_fState_S3$D_OUT[23] && + !fpu_fState_S3$D_OUT[22] && + !fpu_fState_S3$D_OUT[21] && + !fpu_fState_S3$D_OUT[20] && + !fpu_fState_S3$D_OUT[19] && + !fpu_fState_S3$D_OUT[18] && + !fpu_fState_S3$D_OUT[17] && + !fpu_fState_S3$D_OUT[16] && + !fpu_fState_S3$D_OUT[15] && + !fpu_fState_S3$D_OUT[14] && + !fpu_fState_S3$D_OUT[13] && + !fpu_fState_S3$D_OUT[12] && + !fpu_fState_S3$D_OUT[11] && + !fpu_fState_S3$D_OUT[10] && + !fpu_fState_S3$D_OUT[9] && + !fpu_fState_S3$D_OUT[8] && + !fpu_fState_S3$D_OUT[7] && + !fpu_fState_S3$D_OUT[6] && + !fpu_fState_S3$D_OUT[5] && + !fpu_fState_S3$D_OUT[4] && + !fpu_fState_S3$D_OUT[3] && + !fpu_fState_S3$D_OUT[2] && + !fpu_fState_S3$D_OUT[1] && + !fpu_fState_S3$D_OUT[0]) ? + fpu_fState_S3$D_OUT[58:0] : + _theResult___snd__h75319 ; + assign _theResult___snd__h75319 = + { IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6[56:0], + 2'd0 } ; + assign _theResult___snd__h75337 = + fpu_fState_S3$D_OUT[58:0] << + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ; + assign _theResult___snd__h75342 = + fpu_fState_S3$D_OUT[58:0] << + IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 ; + assign _theResult___snd_fst__h25299 = + (int_sqrt_fFirst$D_OUT[115:0] == 116'd0 || + int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264) ? + int_sqrt_fFirst$D_OUT[347:232] : + s__h25385 ; + assign _theResult___snd_fst__h25701 = + (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299) ? + int_sqrt_fNext_0$D_OUT[347:232] : + s__h25785 ; + assign _theResult___snd_fst__h26101 = + (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334) ? + int_sqrt_fNext_1$D_OUT[347:232] : + s__h26185 ; + assign _theResult___snd_fst__h26501 = + (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369) ? + int_sqrt_fNext_2$D_OUT[347:232] : + s__h26585 ; + assign _theResult___snd_fst__h26901 = + (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404) ? + int_sqrt_fNext_3$D_OUT[347:232] : + s__h26985 ; + assign _theResult___snd_fst__h27301 = + (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439) ? + int_sqrt_fNext_4$D_OUT[347:232] : + s__h27385 ; + assign _theResult___snd_fst__h27701 = + (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474) ? + int_sqrt_fNext_5$D_OUT[347:232] : + s__h27785 ; + assign _theResult___snd_fst__h28101 = + (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509) ? + int_sqrt_fNext_6$D_OUT[347:232] : + s__h28185 ; + assign _theResult___snd_fst__h28501 = + (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544) ? + int_sqrt_fNext_7$D_OUT[347:232] : + s__h28585 ; + assign _theResult___snd_fst__h28901 = + (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579) ? + int_sqrt_fNext_8$D_OUT[347:232] : + s__h28985 ; + assign _theResult___snd_fst__h29301 = + (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614) ? + int_sqrt_fNext_9$D_OUT[347:232] : + s__h29385 ; + assign _theResult___snd_fst__h29701 = + (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649) ? + int_sqrt_fNext_10$D_OUT[347:232] : + s__h29785 ; + assign _theResult___snd_fst__h30101 = + (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684) ? + int_sqrt_fNext_11$D_OUT[347:232] : + s__h30185 ; + assign _theResult___snd_fst__h30501 = + (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719) ? + int_sqrt_fNext_12$D_OUT[347:232] : + s__h30585 ; + assign _theResult___snd_fst__h30901 = + (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754) ? + int_sqrt_fNext_13$D_OUT[347:232] : + s__h30985 ; + assign _theResult___snd_fst__h31301 = + (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789) ? + int_sqrt_fNext_14$D_OUT[347:232] : + s__h31385 ; + assign _theResult___snd_fst__h31701 = + (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824) ? + int_sqrt_fNext_15$D_OUT[347:232] : + s__h31785 ; + assign _theResult___snd_fst__h32101 = + (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859) ? + int_sqrt_fNext_16$D_OUT[347:232] : + s__h32185 ; + assign _theResult___snd_fst__h32501 = + (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894) ? + int_sqrt_fNext_17$D_OUT[347:232] : + s__h32585 ; + assign _theResult___snd_fst__h32901 = + (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929) ? + int_sqrt_fNext_18$D_OUT[347:232] : + s__h32985 ; + assign _theResult___snd_fst__h33301 = + (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964) ? + int_sqrt_fNext_19$D_OUT[347:232] : + s__h33385 ; + assign _theResult___snd_fst__h33701 = + (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999) ? + int_sqrt_fNext_20$D_OUT[347:232] : + s__h33785 ; + assign _theResult___snd_fst__h34101 = + (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034) ? + int_sqrt_fNext_21$D_OUT[347:232] : + s__h34185 ; + assign _theResult___snd_fst__h34501 = + (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069) ? + int_sqrt_fNext_22$D_OUT[347:232] : + s__h34585 ; + assign _theResult___snd_fst__h34901 = + (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104) ? + int_sqrt_fNext_23$D_OUT[347:232] : + s__h34985 ; + assign _theResult___snd_fst__h35301 = + (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139) ? + int_sqrt_fNext_24$D_OUT[347:232] : + s__h35385 ; + assign _theResult___snd_fst__h35701 = + (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174) ? + int_sqrt_fNext_25$D_OUT[347:232] : + s__h35785 ; + assign _theResult___snd_fst__h36101 = + (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209) ? + int_sqrt_fNext_26$D_OUT[347:232] : + s__h36185 ; + assign _theResult___snd_fst__h36501 = + (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244) ? + int_sqrt_fNext_27$D_OUT[347:232] : + s__h36585 ; + assign _theResult___snd_fst__h36901 = + (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279) ? + int_sqrt_fNext_28$D_OUT[347:232] : + s__h36985 ; + assign _theResult___snd_fst__h37301 = + (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314) ? + int_sqrt_fNext_29$D_OUT[347:232] : + s__h37385 ; + assign _theResult___snd_fst__h37701 = + (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349) ? + int_sqrt_fNext_30$D_OUT[347:232] : + s__h37785 ; + assign _theResult___snd_fst__h38101 = + (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384) ? + int_sqrt_fNext_31$D_OUT[347:232] : + s__h38185 ; + assign _theResult___snd_fst__h38501 = + (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419) ? + int_sqrt_fNext_32$D_OUT[347:232] : + s__h38585 ; + assign _theResult___snd_fst__h38901 = + (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454) ? + int_sqrt_fNext_33$D_OUT[347:232] : + s__h38985 ; + assign _theResult___snd_fst__h39301 = + (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489) ? + int_sqrt_fNext_34$D_OUT[347:232] : + s__h39385 ; + assign _theResult___snd_fst__h39701 = + (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524) ? + int_sqrt_fNext_35$D_OUT[347:232] : + s__h39785 ; + assign _theResult___snd_fst__h40101 = + (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559) ? + int_sqrt_fNext_36$D_OUT[347:232] : + s__h40185 ; + assign _theResult___snd_fst__h40501 = + (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594) ? + int_sqrt_fNext_37$D_OUT[347:232] : + s__h40585 ; + assign _theResult___snd_fst__h40901 = + (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629) ? + int_sqrt_fNext_38$D_OUT[347:232] : + s__h40985 ; + assign _theResult___snd_fst__h41301 = + (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664) ? + int_sqrt_fNext_39$D_OUT[347:232] : + s__h41385 ; + assign _theResult___snd_fst__h41701 = + (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699) ? + int_sqrt_fNext_40$D_OUT[347:232] : + s__h41785 ; + assign _theResult___snd_fst__h42101 = + (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734) ? + int_sqrt_fNext_41$D_OUT[347:232] : + s__h42185 ; + assign _theResult___snd_fst__h42501 = + (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769) ? + int_sqrt_fNext_42$D_OUT[347:232] : + s__h42585 ; + assign _theResult___snd_fst__h42901 = + (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804) ? + int_sqrt_fNext_43$D_OUT[347:232] : + s__h42985 ; + assign _theResult___snd_fst__h43301 = + (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839) ? + int_sqrt_fNext_44$D_OUT[347:232] : + s__h43385 ; + assign _theResult___snd_fst__h43701 = + (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874) ? + int_sqrt_fNext_45$D_OUT[347:232] : + s__h43785 ; + assign _theResult___snd_fst__h44101 = + (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909) ? + int_sqrt_fNext_46$D_OUT[347:232] : + s__h44185 ; + assign _theResult___snd_fst__h44501 = + (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944) ? + int_sqrt_fNext_47$D_OUT[347:232] : + s__h44585 ; + assign _theResult___snd_fst__h44901 = + (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979) ? + int_sqrt_fNext_48$D_OUT[347:232] : + s__h44985 ; + assign _theResult___snd_fst__h45301 = + (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014) ? + int_sqrt_fNext_49$D_OUT[347:232] : + s__h45385 ; + assign _theResult___snd_fst__h45701 = + (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049) ? + int_sqrt_fNext_50$D_OUT[347:232] : + s__h45785 ; + assign _theResult___snd_fst__h46101 = + (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084) ? + int_sqrt_fNext_51$D_OUT[347:232] : + s__h46185 ; + assign _theResult___snd_fst__h46501 = + (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119) ? + int_sqrt_fNext_52$D_OUT[347:232] : + s__h46585 ; + assign _theResult___snd_fst__h46901 = + (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154) ? + int_sqrt_fNext_53$D_OUT[347:232] : + s__h46985 ; + assign _theResult___snd_fst__h47301 = + (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189) ? + int_sqrt_fNext_54$D_OUT[347:232] : + s__h47385 ; + assign _theResult___snd_fst__h47701 = + (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224) ? + int_sqrt_fNext_55$D_OUT[347:232] : + s__h47785 ; + assign _theResult___snd_fst__h48101 = + (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259) ? + int_sqrt_fNext_56$D_OUT[347:232] : + s__h48185 ; + assign _theResult___snd_fst__h48501 = + (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0 || + int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294) ? + int_sqrt_fNext_57$D_OUT[347:232] : + s__h48585 ; + assign _theResult___snd_fst__h75372 = + { IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7[1], + { sfdin__h75260[5:0], 52'd0 } != 58'd0 } ; + assign _theResult___snd_snd__h25377 = + int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 ? + r__h25394 : + r__h25386 ; + assign _theResult___snd_snd__h25777 = + int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 ? + r__h25794 : + r__h25786 ; + assign _theResult___snd_snd__h26177 = + int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 ? + r__h26194 : + r__h26186 ; + assign _theResult___snd_snd__h26577 = + int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 ? + r__h26594 : + r__h26586 ; + assign _theResult___snd_snd__h26977 = + int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 ? + r__h26994 : + r__h26986 ; + assign _theResult___snd_snd__h27377 = + int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 ? + r__h27394 : + r__h27386 ; + assign _theResult___snd_snd__h27777 = + int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 ? + r__h27794 : + r__h27786 ; + assign _theResult___snd_snd__h28177 = + int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 ? + r__h28194 : + r__h28186 ; + assign _theResult___snd_snd__h28577 = + int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 ? + r__h28594 : + r__h28586 ; + assign _theResult___snd_snd__h28977 = + int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 ? + r__h28994 : + r__h28986 ; + assign _theResult___snd_snd__h29377 = + int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 ? + r__h29394 : + r__h29386 ; + assign _theResult___snd_snd__h29777 = + int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 ? + r__h29794 : + r__h29786 ; + assign _theResult___snd_snd__h30177 = + int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 ? + r__h30194 : + r__h30186 ; + assign _theResult___snd_snd__h30577 = + int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 ? + r__h30594 : + r__h30586 ; + assign _theResult___snd_snd__h30977 = + int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 ? + r__h30994 : + r__h30986 ; + assign _theResult___snd_snd__h31377 = + int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 ? + r__h31394 : + r__h31386 ; + assign _theResult___snd_snd__h31777 = + int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 ? + r__h31794 : + r__h31786 ; + assign _theResult___snd_snd__h32177 = + int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 ? + r__h32194 : + r__h32186 ; + assign _theResult___snd_snd__h32577 = + int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 ? + r__h32594 : + r__h32586 ; + assign _theResult___snd_snd__h32977 = + int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 ? + r__h32994 : + r__h32986 ; + assign _theResult___snd_snd__h33377 = + int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 ? + r__h33394 : + r__h33386 ; + assign _theResult___snd_snd__h33777 = + int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 ? + r__h33794 : + r__h33786 ; + assign _theResult___snd_snd__h34177 = + int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 ? + r__h34194 : + r__h34186 ; + assign _theResult___snd_snd__h34577 = + int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 ? + r__h34594 : + r__h34586 ; + assign _theResult___snd_snd__h34977 = + int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 ? + r__h34994 : + r__h34986 ; + assign _theResult___snd_snd__h35377 = + int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 ? + r__h35394 : + r__h35386 ; + assign _theResult___snd_snd__h35777 = + int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 ? + r__h35794 : + r__h35786 ; + assign _theResult___snd_snd__h36177 = + int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 ? + r__h36194 : + r__h36186 ; + assign _theResult___snd_snd__h36577 = + int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 ? + r__h36594 : + r__h36586 ; + assign _theResult___snd_snd__h36977 = + int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 ? + r__h36994 : + r__h36986 ; + assign _theResult___snd_snd__h37377 = + int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 ? + r__h37394 : + r__h37386 ; + assign _theResult___snd_snd__h37777 = + int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 ? + r__h37794 : + r__h37786 ; + assign _theResult___snd_snd__h38177 = + int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 ? + r__h38194 : + r__h38186 ; + assign _theResult___snd_snd__h38577 = + int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 ? + r__h38594 : + r__h38586 ; + assign _theResult___snd_snd__h38977 = + int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 ? + r__h38994 : + r__h38986 ; + assign _theResult___snd_snd__h39377 = + int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 ? + r__h39394 : + r__h39386 ; + assign _theResult___snd_snd__h39777 = + int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 ? + r__h39794 : + r__h39786 ; + assign _theResult___snd_snd__h40177 = + int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 ? + r__h40194 : + r__h40186 ; + assign _theResult___snd_snd__h40577 = + int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 ? + r__h40594 : + r__h40586 ; + assign _theResult___snd_snd__h40977 = + int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 ? + r__h40994 : + r__h40986 ; + assign _theResult___snd_snd__h41377 = + int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 ? + r__h41394 : + r__h41386 ; + assign _theResult___snd_snd__h41777 = + int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 ? + r__h41794 : + r__h41786 ; + assign _theResult___snd_snd__h42177 = + int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 ? + r__h42194 : + r__h42186 ; + assign _theResult___snd_snd__h42577 = + int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 ? + r__h42594 : + r__h42586 ; + assign _theResult___snd_snd__h42977 = + int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 ? + r__h42994 : + r__h42986 ; + assign _theResult___snd_snd__h43377 = + int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 ? + r__h43394 : + r__h43386 ; + assign _theResult___snd_snd__h43777 = + int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 ? + r__h43794 : + r__h43786 ; + assign _theResult___snd_snd__h44177 = + int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 ? + r__h44194 : + r__h44186 ; + assign _theResult___snd_snd__h44577 = + int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 ? + r__h44594 : + r__h44586 ; + assign _theResult___snd_snd__h44977 = + int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 ? + r__h44994 : + r__h44986 ; + assign _theResult___snd_snd__h45377 = + int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 ? + r__h45394 : + r__h45386 ; + assign _theResult___snd_snd__h45777 = + int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 ? + r__h45794 : + r__h45786 ; + assign _theResult___snd_snd__h46177 = + int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 ? + r__h46194 : + r__h46186 ; + assign _theResult___snd_snd__h46577 = + int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 ? + r__h46594 : + r__h46586 ; + assign _theResult___snd_snd__h46977 = + int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 ? + r__h46994 : + r__h46986 ; + assign _theResult___snd_snd__h47377 = + int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 ? + r__h47394 : + r__h47386 ; + assign _theResult___snd_snd__h47777 = + int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 ? + r__h47794 : + r__h47786 ; + assign _theResult___snd_snd__h48177 = + int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 ? + r__h48194 : + r__h48186 ; + assign _theResult___snd_snd__h48577 = + int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 ? + r__h48594 : + r__h48586 ; + assign b___1__h16687 = 116'h40000000000000000000000000000 >> x__h24992 ; + assign b__h25374 = { 2'd0, int_sqrt_fFirst$D_OUT[115:2] } ; + assign b__h25774 = { 2'd0, int_sqrt_fNext_0$D_OUT[115:2] } ; + assign b__h26174 = { 2'd0, int_sqrt_fNext_1$D_OUT[115:2] } ; + assign b__h26574 = { 2'd0, int_sqrt_fNext_2$D_OUT[115:2] } ; + assign b__h26974 = { 2'd0, int_sqrt_fNext_3$D_OUT[115:2] } ; + assign b__h27374 = { 2'd0, int_sqrt_fNext_4$D_OUT[115:2] } ; + assign b__h27774 = { 2'd0, int_sqrt_fNext_5$D_OUT[115:2] } ; + assign b__h28174 = { 2'd0, int_sqrt_fNext_6$D_OUT[115:2] } ; + assign b__h28574 = { 2'd0, int_sqrt_fNext_7$D_OUT[115:2] } ; + assign b__h28974 = { 2'd0, int_sqrt_fNext_8$D_OUT[115:2] } ; + assign b__h29374 = { 2'd0, int_sqrt_fNext_9$D_OUT[115:2] } ; + assign b__h29774 = { 2'd0, int_sqrt_fNext_10$D_OUT[115:2] } ; + assign b__h30174 = { 2'd0, int_sqrt_fNext_11$D_OUT[115:2] } ; + assign b__h30574 = { 2'd0, int_sqrt_fNext_12$D_OUT[115:2] } ; + assign b__h30974 = { 2'd0, int_sqrt_fNext_13$D_OUT[115:2] } ; + assign b__h31374 = { 2'd0, int_sqrt_fNext_14$D_OUT[115:2] } ; + assign b__h31774 = { 2'd0, int_sqrt_fNext_15$D_OUT[115:2] } ; + assign b__h32174 = { 2'd0, int_sqrt_fNext_16$D_OUT[115:2] } ; + assign b__h32574 = { 2'd0, int_sqrt_fNext_17$D_OUT[115:2] } ; + assign b__h32974 = { 2'd0, int_sqrt_fNext_18$D_OUT[115:2] } ; + assign b__h33374 = { 2'd0, int_sqrt_fNext_19$D_OUT[115:2] } ; + assign b__h33774 = { 2'd0, int_sqrt_fNext_20$D_OUT[115:2] } ; + assign b__h34174 = { 2'd0, int_sqrt_fNext_21$D_OUT[115:2] } ; + assign b__h34574 = { 2'd0, int_sqrt_fNext_22$D_OUT[115:2] } ; + assign b__h34974 = { 2'd0, int_sqrt_fNext_23$D_OUT[115:2] } ; + assign b__h35374 = { 2'd0, int_sqrt_fNext_24$D_OUT[115:2] } ; + assign b__h35774 = { 2'd0, int_sqrt_fNext_25$D_OUT[115:2] } ; + assign b__h36174 = { 2'd0, int_sqrt_fNext_26$D_OUT[115:2] } ; + assign b__h36574 = { 2'd0, int_sqrt_fNext_27$D_OUT[115:2] } ; + assign b__h36974 = { 2'd0, int_sqrt_fNext_28$D_OUT[115:2] } ; + assign b__h37374 = { 2'd0, int_sqrt_fNext_29$D_OUT[115:2] } ; + assign b__h37774 = { 2'd0, int_sqrt_fNext_30$D_OUT[115:2] } ; + assign b__h38174 = { 2'd0, int_sqrt_fNext_31$D_OUT[115:2] } ; + assign b__h38574 = { 2'd0, int_sqrt_fNext_32$D_OUT[115:2] } ; + assign b__h38974 = { 2'd0, int_sqrt_fNext_33$D_OUT[115:2] } ; + assign b__h39374 = { 2'd0, int_sqrt_fNext_34$D_OUT[115:2] } ; + assign b__h39774 = { 2'd0, int_sqrt_fNext_35$D_OUT[115:2] } ; + assign b__h40174 = { 2'd0, int_sqrt_fNext_36$D_OUT[115:2] } ; + assign b__h40574 = { 2'd0, int_sqrt_fNext_37$D_OUT[115:2] } ; + assign b__h40974 = { 2'd0, int_sqrt_fNext_38$D_OUT[115:2] } ; + assign b__h41374 = { 2'd0, int_sqrt_fNext_39$D_OUT[115:2] } ; + assign b__h41774 = { 2'd0, int_sqrt_fNext_40$D_OUT[115:2] } ; + assign b__h42174 = { 2'd0, int_sqrt_fNext_41$D_OUT[115:2] } ; + assign b__h42574 = { 2'd0, int_sqrt_fNext_42$D_OUT[115:2] } ; + assign b__h42974 = { 2'd0, int_sqrt_fNext_43$D_OUT[115:2] } ; + assign b__h43374 = { 2'd0, int_sqrt_fNext_44$D_OUT[115:2] } ; + assign b__h43774 = { 2'd0, int_sqrt_fNext_45$D_OUT[115:2] } ; + assign b__h44174 = { 2'd0, int_sqrt_fNext_46$D_OUT[115:2] } ; + assign b__h44574 = { 2'd0, int_sqrt_fNext_47$D_OUT[115:2] } ; + assign b__h44974 = { 2'd0, int_sqrt_fNext_48$D_OUT[115:2] } ; + assign b__h45374 = { 2'd0, int_sqrt_fNext_49$D_OUT[115:2] } ; + assign b__h45774 = { 2'd0, int_sqrt_fNext_50$D_OUT[115:2] } ; + assign b__h46174 = { 2'd0, int_sqrt_fNext_51$D_OUT[115:2] } ; + assign b__h46574 = { 2'd0, int_sqrt_fNext_52$D_OUT[115:2] } ; + assign b__h46974 = { 2'd0, int_sqrt_fNext_53$D_OUT[115:2] } ; + assign b__h47374 = { 2'd0, int_sqrt_fNext_54$D_OUT[115:2] } ; + assign b__h47774 = { 2'd0, int_sqrt_fNext_55$D_OUT[115:2] } ; + assign b__h48174 = { 2'd0, int_sqrt_fNext_56$D_OUT[115:2] } ; + assign b__h48574 = { 2'd0, int_sqrt_fNext_57$D_OUT[115:2] } ; + assign b__h48712 = + int_sqrt_fNext_58$D_OUT[464] ? + int_sqrt_fNext_58$D_OUT[463:348] : + 116'd0 ; + assign din_inc___2_exp__h76519 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; + assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 = + fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; + assign fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 = + fpu_fState_S3$D_OUT[121:111] - 11'd1023 ; + assign guard__h66951 = x__h75654 ; + assign int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 = + int_sqrt_fFirst$D_OUT[347:232] < sum__h25372 ; + assign int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 = + int_sqrt_fNext_0$D_OUT[347:232] < sum__h25772 ; + assign int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 = + int_sqrt_fNext_10$D_OUT[347:232] < sum__h29772 ; + assign int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 = + int_sqrt_fNext_11$D_OUT[347:232] < sum__h30172 ; + assign int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 = + int_sqrt_fNext_12$D_OUT[347:232] < sum__h30572 ; + assign int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 = + int_sqrt_fNext_13$D_OUT[347:232] < sum__h30972 ; + assign int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 = + int_sqrt_fNext_14$D_OUT[347:232] < sum__h31372 ; + assign int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 = + int_sqrt_fNext_15$D_OUT[347:232] < sum__h31772 ; + assign int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 = + int_sqrt_fNext_16$D_OUT[347:232] < sum__h32172 ; + assign int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 = + int_sqrt_fNext_17$D_OUT[347:232] < sum__h32572 ; + assign int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 = + int_sqrt_fNext_18$D_OUT[347:232] < sum__h32972 ; + assign int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 = + int_sqrt_fNext_19$D_OUT[347:232] < sum__h33372 ; + assign int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 = + int_sqrt_fNext_1$D_OUT[347:232] < sum__h26172 ; + assign int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 = + int_sqrt_fNext_20$D_OUT[347:232] < sum__h33772 ; + assign int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 = + int_sqrt_fNext_21$D_OUT[347:232] < sum__h34172 ; + assign int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 = + int_sqrt_fNext_22$D_OUT[347:232] < sum__h34572 ; + assign int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 = + int_sqrt_fNext_23$D_OUT[347:232] < sum__h34972 ; + assign int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 = + int_sqrt_fNext_24$D_OUT[347:232] < sum__h35372 ; + assign int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 = + int_sqrt_fNext_25$D_OUT[347:232] < sum__h35772 ; + assign int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 = + int_sqrt_fNext_26$D_OUT[347:232] < sum__h36172 ; + assign int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 = + int_sqrt_fNext_27$D_OUT[347:232] < sum__h36572 ; + assign int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 = + int_sqrt_fNext_28$D_OUT[347:232] < sum__h36972 ; + assign int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 = + int_sqrt_fNext_29$D_OUT[347:232] < sum__h37372 ; + assign int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 = + int_sqrt_fNext_2$D_OUT[347:232] < sum__h26572 ; + assign int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 = + int_sqrt_fNext_30$D_OUT[347:232] < sum__h37772 ; + assign int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 = + int_sqrt_fNext_31$D_OUT[347:232] < sum__h38172 ; + assign int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 = + int_sqrt_fNext_32$D_OUT[347:232] < sum__h38572 ; + assign int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 = + int_sqrt_fNext_33$D_OUT[347:232] < sum__h38972 ; + assign int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 = + int_sqrt_fNext_34$D_OUT[347:232] < sum__h39372 ; + assign int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 = + int_sqrt_fNext_35$D_OUT[347:232] < sum__h39772 ; + assign int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 = + int_sqrt_fNext_36$D_OUT[347:232] < sum__h40172 ; + assign int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 = + int_sqrt_fNext_37$D_OUT[347:232] < sum__h40572 ; + assign int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 = + int_sqrt_fNext_38$D_OUT[347:232] < sum__h40972 ; + assign int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 = + int_sqrt_fNext_39$D_OUT[347:232] < sum__h41372 ; + assign int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 = + int_sqrt_fNext_3$D_OUT[347:232] < sum__h26972 ; + assign int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 = + int_sqrt_fNext_40$D_OUT[347:232] < sum__h41772 ; + assign int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 = + int_sqrt_fNext_41$D_OUT[347:232] < sum__h42172 ; + assign int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 = + int_sqrt_fNext_42$D_OUT[347:232] < sum__h42572 ; + assign int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 = + int_sqrt_fNext_43$D_OUT[347:232] < sum__h42972 ; + assign int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 = + int_sqrt_fNext_44$D_OUT[347:232] < sum__h43372 ; + assign int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 = + int_sqrt_fNext_45$D_OUT[347:232] < sum__h43772 ; + assign int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 = + int_sqrt_fNext_46$D_OUT[347:232] < sum__h44172 ; + assign int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 = + int_sqrt_fNext_47$D_OUT[347:232] < sum__h44572 ; + assign int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 = + int_sqrt_fNext_48$D_OUT[347:232] < sum__h44972 ; + assign int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 = + int_sqrt_fNext_49$D_OUT[347:232] < sum__h45372 ; + assign int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 = + int_sqrt_fNext_4$D_OUT[347:232] < sum__h27372 ; + assign int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 = + int_sqrt_fNext_50$D_OUT[347:232] < sum__h45772 ; + assign int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 = + int_sqrt_fNext_51$D_OUT[347:232] < sum__h46172 ; + assign int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 = + int_sqrt_fNext_52$D_OUT[347:232] < sum__h46572 ; + assign int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 = + int_sqrt_fNext_53$D_OUT[347:232] < sum__h46972 ; + assign int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 = + int_sqrt_fNext_54$D_OUT[347:232] < sum__h47372 ; + assign int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 = + int_sqrt_fNext_55$D_OUT[347:232] < sum__h47772 ; + assign int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 = + int_sqrt_fNext_56$D_OUT[347:232] < sum__h48172 ; + assign int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 = + int_sqrt_fNext_57$D_OUT[347:232] < sum__h48572 ; + assign int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 = + int_sqrt_fNext_5$D_OUT[347:232] < sum__h27772 ; + assign int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 = + int_sqrt_fNext_6$D_OUT[347:232] < sum__h28172 ; + assign int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 = + int_sqrt_fNext_7$D_OUT[347:232] < sum__h28572 ; + assign int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 = + int_sqrt_fNext_8$D_OUT[347:232] < sum__h28972 ; + assign int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 = + int_sqrt_fNext_9$D_OUT[347:232] < sum__h29372 ; + assign out_exp__h76431 = + fpu_fState_S4$D_OUT[2] ? + _theResult___exp__h76428 : + fpu_fState_S4$D_OUT[64:54] ; + assign out_sfd__h76432 = + fpu_fState_S4$D_OUT[2] ? + _theResult___sfd__h76429 : + fpu_fState_S4$D_OUT[53:2] ; + assign r__h25386 = r__h25394 + int_sqrt_fFirst$D_OUT[115:0] ; + assign r__h25394 = { 1'd0, int_sqrt_fFirst$D_OUT[231:117] } ; + assign r__h25786 = r__h25794 + int_sqrt_fNext_0$D_OUT[115:0] ; + assign r__h25794 = { 1'd0, int_sqrt_fNext_0$D_OUT[231:117] } ; + assign r__h26186 = r__h26194 + int_sqrt_fNext_1$D_OUT[115:0] ; + assign r__h26194 = { 1'd0, int_sqrt_fNext_1$D_OUT[231:117] } ; + assign r__h26586 = r__h26594 + int_sqrt_fNext_2$D_OUT[115:0] ; + assign r__h26594 = { 1'd0, int_sqrt_fNext_2$D_OUT[231:117] } ; + assign r__h26986 = r__h26994 + int_sqrt_fNext_3$D_OUT[115:0] ; + assign r__h26994 = { 1'd0, int_sqrt_fNext_3$D_OUT[231:117] } ; + assign r__h27386 = r__h27394 + int_sqrt_fNext_4$D_OUT[115:0] ; + assign r__h27394 = { 1'd0, int_sqrt_fNext_4$D_OUT[231:117] } ; + assign r__h27786 = r__h27794 + int_sqrt_fNext_5$D_OUT[115:0] ; + assign r__h27794 = { 1'd0, int_sqrt_fNext_5$D_OUT[231:117] } ; + assign r__h28186 = r__h28194 + int_sqrt_fNext_6$D_OUT[115:0] ; + assign r__h28194 = { 1'd0, int_sqrt_fNext_6$D_OUT[231:117] } ; + assign r__h28586 = r__h28594 + int_sqrt_fNext_7$D_OUT[115:0] ; + assign r__h28594 = { 1'd0, int_sqrt_fNext_7$D_OUT[231:117] } ; + assign r__h28986 = r__h28994 + int_sqrt_fNext_8$D_OUT[115:0] ; + assign r__h28994 = { 1'd0, int_sqrt_fNext_8$D_OUT[231:117] } ; + assign r__h29386 = r__h29394 + int_sqrt_fNext_9$D_OUT[115:0] ; + assign r__h29394 = { 1'd0, int_sqrt_fNext_9$D_OUT[231:117] } ; + assign r__h29786 = r__h29794 + int_sqrt_fNext_10$D_OUT[115:0] ; + assign r__h29794 = { 1'd0, int_sqrt_fNext_10$D_OUT[231:117] } ; + assign r__h30186 = r__h30194 + int_sqrt_fNext_11$D_OUT[115:0] ; + assign r__h30194 = { 1'd0, int_sqrt_fNext_11$D_OUT[231:117] } ; + assign r__h30586 = r__h30594 + int_sqrt_fNext_12$D_OUT[115:0] ; + assign r__h30594 = { 1'd0, int_sqrt_fNext_12$D_OUT[231:117] } ; + assign r__h30986 = r__h30994 + int_sqrt_fNext_13$D_OUT[115:0] ; + assign r__h30994 = { 1'd0, int_sqrt_fNext_13$D_OUT[231:117] } ; + assign r__h31386 = r__h31394 + int_sqrt_fNext_14$D_OUT[115:0] ; + assign r__h31394 = { 1'd0, int_sqrt_fNext_14$D_OUT[231:117] } ; + assign r__h31786 = r__h31794 + int_sqrt_fNext_15$D_OUT[115:0] ; + assign r__h31794 = { 1'd0, int_sqrt_fNext_15$D_OUT[231:117] } ; + assign r__h32186 = r__h32194 + int_sqrt_fNext_16$D_OUT[115:0] ; + assign r__h32194 = { 1'd0, int_sqrt_fNext_16$D_OUT[231:117] } ; + assign r__h32586 = r__h32594 + int_sqrt_fNext_17$D_OUT[115:0] ; + assign r__h32594 = { 1'd0, int_sqrt_fNext_17$D_OUT[231:117] } ; + assign r__h32986 = r__h32994 + int_sqrt_fNext_18$D_OUT[115:0] ; + assign r__h32994 = { 1'd0, int_sqrt_fNext_18$D_OUT[231:117] } ; + assign r__h33386 = r__h33394 + int_sqrt_fNext_19$D_OUT[115:0] ; + assign r__h33394 = { 1'd0, int_sqrt_fNext_19$D_OUT[231:117] } ; + assign r__h33786 = r__h33794 + int_sqrt_fNext_20$D_OUT[115:0] ; + assign r__h33794 = { 1'd0, int_sqrt_fNext_20$D_OUT[231:117] } ; + assign r__h34186 = r__h34194 + int_sqrt_fNext_21$D_OUT[115:0] ; + assign r__h34194 = { 1'd0, int_sqrt_fNext_21$D_OUT[231:117] } ; + assign r__h34586 = r__h34594 + int_sqrt_fNext_22$D_OUT[115:0] ; + assign r__h34594 = { 1'd0, int_sqrt_fNext_22$D_OUT[231:117] } ; + assign r__h34986 = r__h34994 + int_sqrt_fNext_23$D_OUT[115:0] ; + assign r__h34994 = { 1'd0, int_sqrt_fNext_23$D_OUT[231:117] } ; + assign r__h35386 = r__h35394 + int_sqrt_fNext_24$D_OUT[115:0] ; + assign r__h35394 = { 1'd0, int_sqrt_fNext_24$D_OUT[231:117] } ; + assign r__h35786 = r__h35794 + int_sqrt_fNext_25$D_OUT[115:0] ; + assign r__h35794 = { 1'd0, int_sqrt_fNext_25$D_OUT[231:117] } ; + assign r__h36186 = r__h36194 + int_sqrt_fNext_26$D_OUT[115:0] ; + assign r__h36194 = { 1'd0, int_sqrt_fNext_26$D_OUT[231:117] } ; + assign r__h36586 = r__h36594 + int_sqrt_fNext_27$D_OUT[115:0] ; + assign r__h36594 = { 1'd0, int_sqrt_fNext_27$D_OUT[231:117] } ; + assign r__h36986 = r__h36994 + int_sqrt_fNext_28$D_OUT[115:0] ; + assign r__h36994 = { 1'd0, int_sqrt_fNext_28$D_OUT[231:117] } ; + assign r__h37386 = r__h37394 + int_sqrt_fNext_29$D_OUT[115:0] ; + assign r__h37394 = { 1'd0, int_sqrt_fNext_29$D_OUT[231:117] } ; + assign r__h37786 = r__h37794 + int_sqrt_fNext_30$D_OUT[115:0] ; + assign r__h37794 = { 1'd0, int_sqrt_fNext_30$D_OUT[231:117] } ; + assign r__h38186 = r__h38194 + int_sqrt_fNext_31$D_OUT[115:0] ; + assign r__h38194 = { 1'd0, int_sqrt_fNext_31$D_OUT[231:117] } ; + assign r__h38586 = r__h38594 + int_sqrt_fNext_32$D_OUT[115:0] ; + assign r__h38594 = { 1'd0, int_sqrt_fNext_32$D_OUT[231:117] } ; + assign r__h38986 = r__h38994 + int_sqrt_fNext_33$D_OUT[115:0] ; + assign r__h38994 = { 1'd0, int_sqrt_fNext_33$D_OUT[231:117] } ; + assign r__h39386 = r__h39394 + int_sqrt_fNext_34$D_OUT[115:0] ; + assign r__h39394 = { 1'd0, int_sqrt_fNext_34$D_OUT[231:117] } ; + assign r__h39786 = r__h39794 + int_sqrt_fNext_35$D_OUT[115:0] ; + assign r__h39794 = { 1'd0, int_sqrt_fNext_35$D_OUT[231:117] } ; + assign r__h40186 = r__h40194 + int_sqrt_fNext_36$D_OUT[115:0] ; + assign r__h40194 = { 1'd0, int_sqrt_fNext_36$D_OUT[231:117] } ; + assign r__h40586 = r__h40594 + int_sqrt_fNext_37$D_OUT[115:0] ; + assign r__h40594 = { 1'd0, int_sqrt_fNext_37$D_OUT[231:117] } ; + assign r__h40986 = r__h40994 + int_sqrt_fNext_38$D_OUT[115:0] ; + assign r__h40994 = { 1'd0, int_sqrt_fNext_38$D_OUT[231:117] } ; + assign r__h41386 = r__h41394 + int_sqrt_fNext_39$D_OUT[115:0] ; + assign r__h41394 = { 1'd0, int_sqrt_fNext_39$D_OUT[231:117] } ; + assign r__h41786 = r__h41794 + int_sqrt_fNext_40$D_OUT[115:0] ; + assign r__h41794 = { 1'd0, int_sqrt_fNext_40$D_OUT[231:117] } ; + assign r__h42186 = r__h42194 + int_sqrt_fNext_41$D_OUT[115:0] ; + assign r__h42194 = { 1'd0, int_sqrt_fNext_41$D_OUT[231:117] } ; + assign r__h42586 = r__h42594 + int_sqrt_fNext_42$D_OUT[115:0] ; + assign r__h42594 = { 1'd0, int_sqrt_fNext_42$D_OUT[231:117] } ; + assign r__h42986 = r__h42994 + int_sqrt_fNext_43$D_OUT[115:0] ; + assign r__h42994 = { 1'd0, int_sqrt_fNext_43$D_OUT[231:117] } ; + assign r__h43386 = r__h43394 + int_sqrt_fNext_44$D_OUT[115:0] ; + assign r__h43394 = { 1'd0, int_sqrt_fNext_44$D_OUT[231:117] } ; + assign r__h43786 = r__h43794 + int_sqrt_fNext_45$D_OUT[115:0] ; + assign r__h43794 = { 1'd0, int_sqrt_fNext_45$D_OUT[231:117] } ; + assign r__h44186 = r__h44194 + int_sqrt_fNext_46$D_OUT[115:0] ; + assign r__h44194 = { 1'd0, int_sqrt_fNext_46$D_OUT[231:117] } ; + assign r__h44586 = r__h44594 + int_sqrt_fNext_47$D_OUT[115:0] ; + assign r__h44594 = { 1'd0, int_sqrt_fNext_47$D_OUT[231:117] } ; + assign r__h44986 = r__h44994 + int_sqrt_fNext_48$D_OUT[115:0] ; + assign r__h44994 = { 1'd0, int_sqrt_fNext_48$D_OUT[231:117] } ; + assign r__h45386 = r__h45394 + int_sqrt_fNext_49$D_OUT[115:0] ; + assign r__h45394 = { 1'd0, int_sqrt_fNext_49$D_OUT[231:117] } ; + assign r__h45786 = r__h45794 + int_sqrt_fNext_50$D_OUT[115:0] ; + assign r__h45794 = { 1'd0, int_sqrt_fNext_50$D_OUT[231:117] } ; + assign r__h46186 = r__h46194 + int_sqrt_fNext_51$D_OUT[115:0] ; + assign r__h46194 = { 1'd0, int_sqrt_fNext_51$D_OUT[231:117] } ; + assign r__h46586 = r__h46594 + int_sqrt_fNext_52$D_OUT[115:0] ; + assign r__h46594 = { 1'd0, int_sqrt_fNext_52$D_OUT[231:117] } ; + assign r__h46986 = r__h46994 + int_sqrt_fNext_53$D_OUT[115:0] ; + assign r__h46994 = { 1'd0, int_sqrt_fNext_53$D_OUT[231:117] } ; + assign r__h47386 = r__h47394 + int_sqrt_fNext_54$D_OUT[115:0] ; + assign r__h47394 = { 1'd0, int_sqrt_fNext_54$D_OUT[231:117] } ; + assign r__h47786 = r__h47794 + int_sqrt_fNext_55$D_OUT[115:0] ; + assign r__h47794 = { 1'd0, int_sqrt_fNext_55$D_OUT[231:117] } ; + assign r__h48186 = r__h48194 + int_sqrt_fNext_56$D_OUT[115:0] ; + assign r__h48194 = { 1'd0, int_sqrt_fNext_56$D_OUT[231:117] } ; + assign r__h48586 = r__h48594 + int_sqrt_fNext_57$D_OUT[115:0] ; + assign r__h48594 = { 1'd0, int_sqrt_fNext_57$D_OUT[231:117] } ; + assign result__h66451 = { int_sqrt_fResponse$D_OUT[59:2], 1'd1 } ; + assign s__h25385 = int_sqrt_fFirst$D_OUT[347:232] - sum__h25372 ; + assign s__h25785 = int_sqrt_fNext_0$D_OUT[347:232] - sum__h25772 ; + assign s__h26185 = int_sqrt_fNext_1$D_OUT[347:232] - sum__h26172 ; + assign s__h26585 = int_sqrt_fNext_2$D_OUT[347:232] - sum__h26572 ; + assign s__h26985 = int_sqrt_fNext_3$D_OUT[347:232] - sum__h26972 ; + assign s__h27385 = int_sqrt_fNext_4$D_OUT[347:232] - sum__h27372 ; + assign s__h27785 = int_sqrt_fNext_5$D_OUT[347:232] - sum__h27772 ; + assign s__h28185 = int_sqrt_fNext_6$D_OUT[347:232] - sum__h28172 ; + assign s__h28585 = int_sqrt_fNext_7$D_OUT[347:232] - sum__h28572 ; + assign s__h28985 = int_sqrt_fNext_8$D_OUT[347:232] - sum__h28972 ; + assign s__h29385 = int_sqrt_fNext_9$D_OUT[347:232] - sum__h29372 ; + assign s__h29785 = int_sqrt_fNext_10$D_OUT[347:232] - sum__h29772 ; + assign s__h30185 = int_sqrt_fNext_11$D_OUT[347:232] - sum__h30172 ; + assign s__h30585 = int_sqrt_fNext_12$D_OUT[347:232] - sum__h30572 ; + assign s__h30985 = int_sqrt_fNext_13$D_OUT[347:232] - sum__h30972 ; + assign s__h31385 = int_sqrt_fNext_14$D_OUT[347:232] - sum__h31372 ; + assign s__h31785 = int_sqrt_fNext_15$D_OUT[347:232] - sum__h31772 ; + assign s__h32185 = int_sqrt_fNext_16$D_OUT[347:232] - sum__h32172 ; + assign s__h32585 = int_sqrt_fNext_17$D_OUT[347:232] - sum__h32572 ; + assign s__h32985 = int_sqrt_fNext_18$D_OUT[347:232] - sum__h32972 ; + assign s__h33385 = int_sqrt_fNext_19$D_OUT[347:232] - sum__h33372 ; + assign s__h33785 = int_sqrt_fNext_20$D_OUT[347:232] - sum__h33772 ; + assign s__h34185 = int_sqrt_fNext_21$D_OUT[347:232] - sum__h34172 ; + assign s__h34585 = int_sqrt_fNext_22$D_OUT[347:232] - sum__h34572 ; + assign s__h34985 = int_sqrt_fNext_23$D_OUT[347:232] - sum__h34972 ; + assign s__h35385 = int_sqrt_fNext_24$D_OUT[347:232] - sum__h35372 ; + assign s__h35785 = int_sqrt_fNext_25$D_OUT[347:232] - sum__h35772 ; + assign s__h36185 = int_sqrt_fNext_26$D_OUT[347:232] - sum__h36172 ; + assign s__h36585 = int_sqrt_fNext_27$D_OUT[347:232] - sum__h36572 ; + assign s__h36985 = int_sqrt_fNext_28$D_OUT[347:232] - sum__h36972 ; + assign s__h37385 = int_sqrt_fNext_29$D_OUT[347:232] - sum__h37372 ; + assign s__h37785 = int_sqrt_fNext_30$D_OUT[347:232] - sum__h37772 ; + assign s__h38185 = int_sqrt_fNext_31$D_OUT[347:232] - sum__h38172 ; + assign s__h38585 = int_sqrt_fNext_32$D_OUT[347:232] - sum__h38572 ; + assign s__h38985 = int_sqrt_fNext_33$D_OUT[347:232] - sum__h38972 ; + assign s__h39385 = int_sqrt_fNext_34$D_OUT[347:232] - sum__h39372 ; + assign s__h39785 = int_sqrt_fNext_35$D_OUT[347:232] - sum__h39772 ; + assign s__h40185 = int_sqrt_fNext_36$D_OUT[347:232] - sum__h40172 ; + assign s__h40585 = int_sqrt_fNext_37$D_OUT[347:232] - sum__h40572 ; + assign s__h40985 = int_sqrt_fNext_38$D_OUT[347:232] - sum__h40972 ; + assign s__h41385 = int_sqrt_fNext_39$D_OUT[347:232] - sum__h41372 ; + assign s__h41785 = int_sqrt_fNext_40$D_OUT[347:232] - sum__h41772 ; + assign s__h42185 = int_sqrt_fNext_41$D_OUT[347:232] - sum__h42172 ; + assign s__h42585 = int_sqrt_fNext_42$D_OUT[347:232] - sum__h42572 ; + assign s__h42985 = int_sqrt_fNext_43$D_OUT[347:232] - sum__h42972 ; + assign s__h43385 = int_sqrt_fNext_44$D_OUT[347:232] - sum__h43372 ; + assign s__h43785 = int_sqrt_fNext_45$D_OUT[347:232] - sum__h43772 ; + assign s__h44185 = int_sqrt_fNext_46$D_OUT[347:232] - sum__h44172 ; + assign s__h44585 = int_sqrt_fNext_47$D_OUT[347:232] - sum__h44572 ; + assign s__h44985 = int_sqrt_fNext_48$D_OUT[347:232] - sum__h44972 ; + assign s__h45385 = int_sqrt_fNext_49$D_OUT[347:232] - sum__h45372 ; + assign s__h45785 = int_sqrt_fNext_50$D_OUT[347:232] - sum__h45772 ; + assign s__h46185 = int_sqrt_fNext_51$D_OUT[347:232] - sum__h46172 ; + assign s__h46585 = int_sqrt_fNext_52$D_OUT[347:232] - sum__h46572 ; + assign s__h46985 = int_sqrt_fNext_53$D_OUT[347:232] - sum__h46972 ; + assign s__h47385 = int_sqrt_fNext_54$D_OUT[347:232] - sum__h47372 ; + assign s__h47785 = int_sqrt_fNext_55$D_OUT[347:232] - sum__h47772 ; + assign s__h48185 = int_sqrt_fNext_56$D_OUT[347:232] - sum__h48172 ; + assign s__h48585 = int_sqrt_fNext_57$D_OUT[347:232] - sum__h48572 ; + assign sfd___1__h65692 = { 1'd0, sfd__h49938[57:1] } ; + assign sfd__h49936 = { value__h58164, 4'd0 } ; + assign sfd__h49938 = sfd__h49936 << x__h65722 ; + assign sfd__h49989 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; + assign sfd__h75932 = + { 1'b0, + fpu_fState_S4$D_OUT[64:54] != 11'd0, + fpu_fState_S4$D_OUT[53:2] } + + 54'd1 ; + assign sfdin__h75260 = + fpu_fState_S3$D_OUT[58] ? + _theResult___snd__h75283 : + _theResult___snd__h75298 ; + assign sum__h25372 = + int_sqrt_fFirst$D_OUT[231:116] + int_sqrt_fFirst$D_OUT[115:0] ; + assign sum__h25772 = + int_sqrt_fNext_0$D_OUT[231:116] + int_sqrt_fNext_0$D_OUT[115:0] ; + assign sum__h26172 = + int_sqrt_fNext_1$D_OUT[231:116] + int_sqrt_fNext_1$D_OUT[115:0] ; + assign sum__h26572 = + int_sqrt_fNext_2$D_OUT[231:116] + int_sqrt_fNext_2$D_OUT[115:0] ; + assign sum__h26972 = + int_sqrt_fNext_3$D_OUT[231:116] + int_sqrt_fNext_3$D_OUT[115:0] ; + assign sum__h27372 = + int_sqrt_fNext_4$D_OUT[231:116] + int_sqrt_fNext_4$D_OUT[115:0] ; + assign sum__h27772 = + int_sqrt_fNext_5$D_OUT[231:116] + int_sqrt_fNext_5$D_OUT[115:0] ; + assign sum__h28172 = + int_sqrt_fNext_6$D_OUT[231:116] + int_sqrt_fNext_6$D_OUT[115:0] ; + assign sum__h28572 = + int_sqrt_fNext_7$D_OUT[231:116] + int_sqrt_fNext_7$D_OUT[115:0] ; + assign sum__h28972 = + int_sqrt_fNext_8$D_OUT[231:116] + int_sqrt_fNext_8$D_OUT[115:0] ; + assign sum__h29372 = + int_sqrt_fNext_9$D_OUT[231:116] + int_sqrt_fNext_9$D_OUT[115:0] ; + assign sum__h29772 = + int_sqrt_fNext_10$D_OUT[231:116] + + int_sqrt_fNext_10$D_OUT[115:0] ; + assign sum__h30172 = + int_sqrt_fNext_11$D_OUT[231:116] + + int_sqrt_fNext_11$D_OUT[115:0] ; + assign sum__h30572 = + int_sqrt_fNext_12$D_OUT[231:116] + + int_sqrt_fNext_12$D_OUT[115:0] ; + assign sum__h30972 = + int_sqrt_fNext_13$D_OUT[231:116] + + int_sqrt_fNext_13$D_OUT[115:0] ; + assign sum__h31372 = + int_sqrt_fNext_14$D_OUT[231:116] + + int_sqrt_fNext_14$D_OUT[115:0] ; + assign sum__h31772 = + int_sqrt_fNext_15$D_OUT[231:116] + + int_sqrt_fNext_15$D_OUT[115:0] ; + assign sum__h32172 = + int_sqrt_fNext_16$D_OUT[231:116] + + int_sqrt_fNext_16$D_OUT[115:0] ; + assign sum__h32572 = + int_sqrt_fNext_17$D_OUT[231:116] + + int_sqrt_fNext_17$D_OUT[115:0] ; + assign sum__h32972 = + int_sqrt_fNext_18$D_OUT[231:116] + + int_sqrt_fNext_18$D_OUT[115:0] ; + assign sum__h33372 = + int_sqrt_fNext_19$D_OUT[231:116] + + int_sqrt_fNext_19$D_OUT[115:0] ; + assign sum__h33772 = + int_sqrt_fNext_20$D_OUT[231:116] + + int_sqrt_fNext_20$D_OUT[115:0] ; + assign sum__h34172 = + int_sqrt_fNext_21$D_OUT[231:116] + + int_sqrt_fNext_21$D_OUT[115:0] ; + assign sum__h34572 = + int_sqrt_fNext_22$D_OUT[231:116] + + int_sqrt_fNext_22$D_OUT[115:0] ; + assign sum__h34972 = + int_sqrt_fNext_23$D_OUT[231:116] + + int_sqrt_fNext_23$D_OUT[115:0] ; + assign sum__h35372 = + int_sqrt_fNext_24$D_OUT[231:116] + + int_sqrt_fNext_24$D_OUT[115:0] ; + assign sum__h35772 = + int_sqrt_fNext_25$D_OUT[231:116] + + int_sqrt_fNext_25$D_OUT[115:0] ; + assign sum__h36172 = + int_sqrt_fNext_26$D_OUT[231:116] + + int_sqrt_fNext_26$D_OUT[115:0] ; + assign sum__h36572 = + int_sqrt_fNext_27$D_OUT[231:116] + + int_sqrt_fNext_27$D_OUT[115:0] ; + assign sum__h36972 = + int_sqrt_fNext_28$D_OUT[231:116] + + int_sqrt_fNext_28$D_OUT[115:0] ; + assign sum__h37372 = + int_sqrt_fNext_29$D_OUT[231:116] + + int_sqrt_fNext_29$D_OUT[115:0] ; + assign sum__h37772 = + int_sqrt_fNext_30$D_OUT[231:116] + + int_sqrt_fNext_30$D_OUT[115:0] ; + assign sum__h38172 = + int_sqrt_fNext_31$D_OUT[231:116] + + int_sqrt_fNext_31$D_OUT[115:0] ; + assign sum__h38572 = + int_sqrt_fNext_32$D_OUT[231:116] + + int_sqrt_fNext_32$D_OUT[115:0] ; + assign sum__h38972 = + int_sqrt_fNext_33$D_OUT[231:116] + + int_sqrt_fNext_33$D_OUT[115:0] ; + assign sum__h39372 = + int_sqrt_fNext_34$D_OUT[231:116] + + int_sqrt_fNext_34$D_OUT[115:0] ; + assign sum__h39772 = + int_sqrt_fNext_35$D_OUT[231:116] + + int_sqrt_fNext_35$D_OUT[115:0] ; + assign sum__h40172 = + int_sqrt_fNext_36$D_OUT[231:116] + + int_sqrt_fNext_36$D_OUT[115:0] ; + assign sum__h40572 = + int_sqrt_fNext_37$D_OUT[231:116] + + int_sqrt_fNext_37$D_OUT[115:0] ; + assign sum__h40972 = + int_sqrt_fNext_38$D_OUT[231:116] + + int_sqrt_fNext_38$D_OUT[115:0] ; + assign sum__h41372 = + int_sqrt_fNext_39$D_OUT[231:116] + + int_sqrt_fNext_39$D_OUT[115:0] ; + assign sum__h41772 = + int_sqrt_fNext_40$D_OUT[231:116] + + int_sqrt_fNext_40$D_OUT[115:0] ; + assign sum__h42172 = + int_sqrt_fNext_41$D_OUT[231:116] + + int_sqrt_fNext_41$D_OUT[115:0] ; + assign sum__h42572 = + int_sqrt_fNext_42$D_OUT[231:116] + + int_sqrt_fNext_42$D_OUT[115:0] ; + assign sum__h42972 = + int_sqrt_fNext_43$D_OUT[231:116] + + int_sqrt_fNext_43$D_OUT[115:0] ; + assign sum__h43372 = + int_sqrt_fNext_44$D_OUT[231:116] + + int_sqrt_fNext_44$D_OUT[115:0] ; + assign sum__h43772 = + int_sqrt_fNext_45$D_OUT[231:116] + + int_sqrt_fNext_45$D_OUT[115:0] ; + assign sum__h44172 = + int_sqrt_fNext_46$D_OUT[231:116] + + int_sqrt_fNext_46$D_OUT[115:0] ; + assign sum__h44572 = + int_sqrt_fNext_47$D_OUT[231:116] + + int_sqrt_fNext_47$D_OUT[115:0] ; + assign sum__h44972 = + int_sqrt_fNext_48$D_OUT[231:116] + + int_sqrt_fNext_48$D_OUT[115:0] ; + assign sum__h45372 = + int_sqrt_fNext_49$D_OUT[231:116] + + int_sqrt_fNext_49$D_OUT[115:0] ; + assign sum__h45772 = + int_sqrt_fNext_50$D_OUT[231:116] + + int_sqrt_fNext_50$D_OUT[115:0] ; + assign sum__h46172 = + int_sqrt_fNext_51$D_OUT[231:116] + + int_sqrt_fNext_51$D_OUT[115:0] ; + assign sum__h46572 = + int_sqrt_fNext_52$D_OUT[231:116] + + int_sqrt_fNext_52$D_OUT[115:0] ; + assign sum__h46972 = + int_sqrt_fNext_53$D_OUT[231:116] + + int_sqrt_fNext_53$D_OUT[115:0] ; + assign sum__h47372 = + int_sqrt_fNext_54$D_OUT[231:116] + + int_sqrt_fNext_54$D_OUT[115:0] ; + assign sum__h47772 = + int_sqrt_fNext_55$D_OUT[231:116] + + int_sqrt_fNext_55$D_OUT[115:0] ; + assign sum__h48172 = + int_sqrt_fNext_56$D_OUT[231:116] + + int_sqrt_fNext_56$D_OUT[115:0] ; + assign sum__h48572 = + int_sqrt_fNext_57$D_OUT[231:116] + + int_sqrt_fNext_57$D_OUT[115:0] ; + assign value_BIT_52___h58260 = fpu_fOperand_S0$D_OUT[65:55] != 11'd0 ; + assign value__h58164 = + { 1'b0, value_BIT_52___h58260, fpu_fOperand_S0$D_OUT[54:3] } ; + assign x__h24992 = + IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237[0] ? + IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 + + 7'd1 : + IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 ; + assign x__h402 = + int_sqrt_fRequest$D_OUT[115] ? + 116'h40000000000000000000000000000 : + b___1__h16687 ; + assign x__h57541 = x__h57559 + 13'd1024 ; + assign x__h57559 = + { IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9[11], + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 } ; + assign x__h65683 = + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[0] ? + sfd__h49938 : + sfd___1__h65692 ; + assign x__h65722 = + IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 - + 6'd1 ; + assign x__h66665 = + int_sqrt_fResponse$D_OUT[0] ? + result__h66451 : + int_sqrt_fResponse$D_OUT[59:1] ; + assign x__h75654 = + (fpu_fState_S3$D_OUT[58] && + IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == + 12'd1023) ? + 2'd3 : + _theResult___snd_fst__h75372 ; + always@(fpu_fState_S4$D_OUT or out_sfd__h76432 or _theResult___sfd__h76429) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + fpu_fState_S4$D_OUT[53:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + out_sfd__h76432; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = + _theResult___sfd__h76429; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___sfd__h76429) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + fpu_fState_S4$D_OUT[53:2]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = + _theResult___sfd__h76429; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or + _theResult___sfd__h76429) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_sfd__h76507 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; + 3'd1: + _theResult___fst_sfd__h76507 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; + 3'd2: + _theResult___fst_sfd__h76507 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[53:2] : + _theResult___sfd__h76429; + 3'd3: + _theResult___fst_sfd__h76507 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[53:2] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___sfd__h76429 : + fpu_fState_S4$D_OUT[53:2]); + 3'd4: _theResult___fst_sfd__h76507 = fpu_fState_S4$D_OUT[53:2]; + default: _theResult___fst_sfd__h76507 = 52'd0; + endcase + end + always@(fpu_fState_S4$D_OUT or out_exp__h76431 or _theResult___exp__h76428) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = + fpu_fState_S4$D_OUT[64:54]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = + out_exp__h76431; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = + _theResult___exp__h76428; + endcase + end + always@(fpu_fState_S4$D_OUT or _theResult___exp__h76428) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = + fpu_fState_S4$D_OUT[64:54]; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = + _theResult___exp__h76428; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 or + _theResult___exp__h76428) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + _theResult___fst_exp__h76506 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3; + 3'd1: + _theResult___fst_exp__h76506 = + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4; + 3'd2: + _theResult___fst_exp__h76506 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:54] : + _theResult___exp__h76428; + 3'd3: + _theResult___fst_exp__h76506 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:54] : + (fpu_fState_S4$D_OUT[65] ? + _theResult___exp__h76428 : + fpu_fState_S4$D_OUT[64:54]); + 3'd4: _theResult___fst_exp__h76506 = fpu_fState_S4$D_OUT[64:54]; + default: _theResult___fst_exp__h76506 = 11'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2, 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = + fpu_fState_S4$D_OUT[65]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = + fpu_fState_S4$D_OUT[68:66] == 3'd4 && + fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd2: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? + fpu_fState_S4$D_OUT[64:2] : + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; + 3'd3: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[64:2] : + (fpu_fState_S4$D_OUT[65] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : + fpu_fState_S4$D_OUT[64:2]); + 3'd4: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = + fpu_fState_S4$D_OUT[64:2]; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = 63'd0; + endcase + end + always@(fpu_fState_S4$D_OUT) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01, 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = + fpu_fState_S4$D_OUT[65]; + 2'd3: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = + fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'b0, 2'b01: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[64:2]; + 2'b10: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + fpu_fState_S4$D_OUT[2] ? + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : + fpu_fState_S4$D_OUT[64:2]; + 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; + endcase + end + always@(fpu_fState_S4$D_OUT or + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) + begin + case (fpu_fState_S4$D_OUT[1:0]) + 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = 63'd0; + 2'b01, 2'b10, 2'b11: + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = + IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; + endcase + end + always@(fpu_fState_S4$D_OUT or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 or + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14) + begin + case (fpu_fState_S4$D_OUT[68:66]) + 3'd0: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = + { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 }; + 3'd1: + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = + (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? + fpu_fState_S4$D_OUT[65:2] : + { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || + fpu_fState_S4$D_OUT[1:0] == 2'b10 || + fpu_fState_S4$D_OUT[1:0] == 2'b11) && + fpu_fState_S4$D_OUT[65], + CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 }; + default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = + { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10, + CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 }; + endcase + end endmodule // mkDoubleSqrt diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v index 7242060..9d6c366 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v index ccb122d..e6946a8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v index 31207ea..25e8f29 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v index d9cea29..6f1d821 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -786,8 +786,8 @@ module mkFetchStage(CLK, out_fifo_enqueueElement_1_dummy_1_0$wget, out_fifo_enqueueFifo_lat_0$whas, out_fifo_enqueueFifo_lat_1$whas, - pc_reg_dummy_1_0$whas, - pc_reg_lat_0$whas; + pc_reg_lat_0$whas, + pc_reg_lat_1$whas; // register decode_epoch reg decode_epoch; @@ -4818,7 +4818,7 @@ module mkFetchStage(CLK, // inlined wires assign pc_reg_lat_0$whas = EN_start || WILL_FIRE_RL_doFetch1 ; - assign pc_reg_dummy_1_0$whas = + assign pc_reg_lat_1$whas = WILL_FIRE_RL_doDecode && SEL_ARR_f32d_data_0_678_BITS_3_TO_0_679_f32d_d_ETC___d4684 && IF_SEL_ARR_instdata_data_0_686_BITS_195_TO_194_ETC___d5447 ; @@ -9130,7 +9130,7 @@ module mkFetchStage(CLK, // submodule pc_reg_dummy2_1 assign pc_reg_dummy2_1$D_IN = 1'd1 ; - assign pc_reg_dummy2_1$EN = pc_reg_dummy_1_0$whas ; + assign pc_reg_dummy2_1$EN = pc_reg_lat_1$whas ; // submodule pc_reg_dummy2_2 assign pc_reg_dummy2_2$D_IN = 1'd1 ; @@ -11527,7 +11527,7 @@ module mkFetchStage(CLK, assign IF_pc_reg_dummy2_0_read__063_AND_pc_reg_dummy2_ETC___d3337 = x__h115849 + 64'd4 ; assign IF_pc_reg_lat_1_whas_THEN_pc_reg_lat_1_wget_EL_ETC___d9 = - pc_reg_dummy_1_0$whas ? + pc_reg_lat_1$whas ? upd__h1659 : (pc_reg_lat_0$whas ? upd__h1686 : pc_reg_rl) ; assign IF_perfReqQ_enqReq_lat_1_whas__977_THEN_perfRe_ETC___d2986 = diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v index 19077ae..9bec235 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v index 1ac4e8b..3999df6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v index 15d044c..2a255b9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v index 582c46c..5c24b1f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v index a99ba17..a94e505 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v index 8f2496d..b420b9a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v index 633084f..f9897e7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v index fb6650c..ab96233 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v index 0f647fc..87e4954 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v index a18b0ec..434f48e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v index 5290f98..ba18f4f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v index 3234ef8..cc3465d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v index 8337f28..c5a0864 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v index 6cbc0b2..805dcc5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index b2795ea..41a36dc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index 1c6cfe3..f15ec88 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -10516,75 +10516,6 @@ module mkLLPipeline(CLK, IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3399; endcase end - always@(way__h173542 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 or - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626) - begin - case (way__h173542) - 4'd0: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311; - 4'd1: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336; - 4'd2: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352; - 4'd3: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380; - 4'd4: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399; - 4'd5: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415; - 4'd6: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430; - 4'd7: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462; - 4'd8: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482; - 4'd9: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501; - 4'd10: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517; - 4'd11: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538; - 4'd12: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556; - 4'd13: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572; - 4'd14: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587; - 4'd15: - SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = - IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626; - endcase - end always@(way__h173542 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3218 or IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3224 or @@ -10654,6 +10585,75 @@ module mkLLPipeline(CLK, IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d3308; endcase end + always@(way__h173542 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587 or + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626) + begin + case (way__h173542) + 4'd0: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2311; + 4'd1: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2336; + 4'd2: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2352; + 4'd3: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2380; + 4'd4: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2399; + 4'd5: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2415; + 4'd6: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2430; + 4'd7: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2462; + 4'd8: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2482; + 4'd9: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2501; + 4'd10: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2517; + 4'd11: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2538; + 4'd12: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2556; + 4'd13: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2572; + 4'd14: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2587; + 4'd15: + SEL_ARR_IF_m_pipe_enq2Mat_dummy2_1_read__576_A_ETC___d3111 = + IF_m_pipe_enq2Mat_dummy2_1_read__576_AND_m_pip_ETC___d2626; + endcase + end always@(way__h173542 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3406 or IF_IF_m_pipe_enq2Mat_lat_0_whas__77_THEN_NOT_m_ETC___d3411 or diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v index 4b0453f..b4fa4a6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index 68735ad..63a9d74 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v index b0ef48d..08033b6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v index b257c36..b7a1045 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v index 2eea032..0848cfa 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v index 7254a62..3e2332b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v index 62600d8..8ce1ce4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v index 7ef963e..086d61c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v index a186981..a7de61e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index 382f1e2..e4d4458 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -1347,9 +1347,9 @@ module mkP3_Core(CLK, .axi_out_tlast(tv_xactor$axi_out_tlast)); // rule RL_rl_once - assign CAN_FIRE_RL_rl_once = WILL_FIRE_RL_rl_once ; - assign WILL_FIRE_RL_rl_once = + assign CAN_FIRE_RL_rl_once = corew$RDY_cpu_reset_server_request_put && !rg_once ; + assign WILL_FIRE_RL_rl_once = CAN_FIRE_RL_rl_once ; // rule RL_rl_reset_response assign CAN_FIRE_RL_rl_reset_response = @@ -1637,7 +1637,7 @@ module mkP3_Core(CLK, assign corew$set_verbosity_verbosity = 4'h0 ; assign corew$EN_set_verbosity = 1'b0 ; assign corew$EN_set_htif_addrs = 1'b0 ; - assign corew$EN_cpu_reset_server_request_put = WILL_FIRE_RL_rl_once ; + assign corew$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; assign corew$EN_cpu_reset_server_response_get = corew$RDY_cpu_reset_server_response_get ; assign corew$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v index 7490ccc..7dfaf3e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index d8462cb..1e25443 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -2114,7 +2114,7 @@ module mkProc(CLK, EN_hart0_server_reset_response_get ; // action method start - assign RDY_start = mmioPlatform_state == 2'd0 ; + assign RDY_start = CAN_FIRE_start ; assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ; assign WILL_FIRE_start = EN_start ; @@ -5967,6 +5967,27 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end + always@(mmioPlatform_curReq or + result__h46297 or + result__h46324 or result__h46351 or result__h46378) + begin + case (mmioPlatform_curReq[2:0]) + 3'h0: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46297; + 3'h2: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46324; + 3'h4: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46351; + 3'h6: + IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + result__h46378; + default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = + 64'd0; + endcase + end always@(mmioPlatform_curReq or result__h46064 or result__h46091 or @@ -6002,27 +6023,6 @@ module mkProc(CLK, result__h46253; endcase end - always@(mmioPlatform_curReq or - result__h46297 or - result__h46324 or result__h46351 or result__h46378) - begin - case (mmioPlatform_curReq[2:0]) - 3'h0: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46297; - 3'h2: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46324; - 3'h4: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46351; - 3'h6: - IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46378; - default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - 64'd0; - endcase - end always@(mmioPlatform_curReq or result__h46418 or result__h46445) begin case (mmioPlatform_curReq[2:0]) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v index a181d0f..955c79f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v index 9192168..0399a9b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v index 7b123fe..473ebaa 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v index bc0bb5b..3e76786 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v index 6484f82..c07ff78 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // @@ -15638,71 +15638,6 @@ module mkReservationStationAlu(CLK, m_data_15[1]; endcase end - always@(idx__h168545 or - m_data_0 or - m_data_1 or - m_data_2 or - m_data_3 or - m_data_4 or - m_data_5 or - m_data_6 or - m_data_7 or - m_data_8 or - m_data_9 or - m_data_10 or - m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) - begin - case (idx__h168545) - 4'd0: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_0[72]; - 4'd1: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_1[72]; - 4'd2: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_2[72]; - 4'd3: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_3[72]; - 4'd4: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_4[72]; - 4'd5: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_5[72]; - 4'd6: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_6[72]; - 4'd7: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_7[72]; - 4'd8: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_8[72]; - 4'd9: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_9[72]; - 4'd10: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_10[72]; - 4'd11: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_11[72]; - 4'd12: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_12[72]; - 4'd13: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_13[72]; - 4'd14: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_14[72]; - 4'd15: - SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = - m_data_15[72]; - endcase - end always@(idx__h168545 or m_data_0 or m_data_1 or @@ -15768,6 +15703,71 @@ module mkReservationStationAlu(CLK, m_data_15[70]; endcase end + always@(idx__h168545 or + m_data_0 or + m_data_1 or + m_data_2 or + m_data_3 or + m_data_4 or + m_data_5 or + m_data_6 or + m_data_7 or + m_data_8 or + m_data_9 or + m_data_10 or + m_data_11 or m_data_12 or m_data_13 or m_data_14 or m_data_15) + begin + case (idx__h168545) + 4'd0: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_0[72]; + 4'd1: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_1[72]; + 4'd2: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_2[72]; + 4'd3: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_3[72]; + 4'd4: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_4[72]; + 4'd5: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_5[72]; + 4'd6: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_6[72]; + 4'd7: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_7[72]; + 4'd8: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_8[72]; + 4'd9: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_9[72]; + 4'd10: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_10[72]; + 4'd11: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_11[72]; + 4'd12: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_12[72]; + 4'd13: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_13[72]; + 4'd14: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_14[72]; + 4'd15: + SEL_ARR_m_data_0_208_BIT_72_770_m_data_1_210_B_ETC___d1787 = + m_data_15[72]; + endcase + end always@(idx__h168545 or m_data_0 or m_data_1 or diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v index b21ff7c..35e774f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v index 62c6ac0..7350806 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v index 5153b0f..2725b41 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v index 46f17d4..6bc3736 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v index 6c29b38..e1af2db 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v index 4071131..2aafd79 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v index a2dfe07..5662f10 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v index 689b342..f161a85 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v index ea8ce28..cc2c578 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v index 4437b39..fd3654a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v index a0aef54..1762326 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v b/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v index 4ce5fb1..d07abc0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTV_Xactor.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v index a049da6..d7059a8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v index 6cef5a7..f4f9439 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v index 7ab9bb7..417af0c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v index 3ca27d9..a3dc704 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v index 9ec85ca..b602264 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v index fe0dcca..b530943 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v index c47f51b..062a838 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v index 2ffba0b..fcd8244 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v index b645a07..e98a4f4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v index 8d04782..1e08888 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v index 76da3ab..b9f2cd4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v index edefcc7..1c8195c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // // diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v b/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v index 9e73d6c..da452c1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_getControlFlow.v @@ -1,5 +1,5 @@ // -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// Generated by Bluespec Compiler, version 2017.07.A (build 4f360250d, 2017-07-21) // // //