From 812c96136023d6f3f681d65dd0cb6746efe5ebf8 Mon Sep 17 00:00:00 2001 From: gameboo Date: Tue, 27 Apr 2021 01:27:52 +0100 Subject: [PATCH 01/35] Introduce the WindCoreInterface --- .gitmodules | 3 + .../Makefile | 17 ++ builds/Resources/Include_Common.mk | 4 +- libs/WindCoreInterface | 1 + src_Core/Core/CoreW.bsv | 166 +++++++++++------- 5 files changed, 129 insertions(+), 62 deletions(-) create mode 160000 libs/WindCoreInterface diff --git a/.gitmodules b/.gitmodules index 9f26513..76c0b05 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,6 @@ [submodule "libs/RISCV_HPM_Events"] path = libs/RISCV_HPM_Events url = https://github.com/CTSRD-CHERI/RISCV_HPM_Events.git +[submodule "libs/WindCoreInterface"] + path = libs/WindCoreInterface + url = https://github.com/CTSRD-CHERI/WindCoreInterface.git diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile index 5ef62de..9653706 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile @@ -11,6 +11,23 @@ EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/B # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler +BSC_COMPILATION_FLAGS += \ + -D RV64 \ + -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ + -D SV39 \ + -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ + -D SHIFT_BARREL \ + -D MULT_SYNTH \ + -D Near_Mem_Caches \ + -D FABRIC64 \ + -D CheriBusBytes=8 \ + -D CheriMasterIDWidth=1 \ + -D CheriTransactionIDWidth=5 \ + -D CAP128 -D BLUESIM \ + -D MEM64 \ + -D RISCV \ + -D INCLUDE_GDB_CONTROL + # Default ISA test TEST ?= rv64ui-p-add diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index c7f0d1e..29462d5 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -56,11 +56,13 @@ TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueUtils:$(REPO)/libs/BlueStuff/BlueBasics +WINDCOREIFC_DIRS = $(REPO)/libs/WindCoreInterface + TAGCONTROLLER_DIRS = $(REPO)/libs/TagController/TagController:$(REPO)/libs/TagController/TagController/CacheCore RISCV_HPM_Events_DIR = $(REPO)/libs/RISCV_HPM_Events -BSC_PATH = $(BLUESTUFF_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+ +BSC_PATH = $(BLUESTUFF_DIRS):$(WINDCOREIFC_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+ # ---------------- # Top-level file and module diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface new file mode 160000 index 0000000..dbcabbf --- /dev/null +++ b/libs/WindCoreInterface @@ -0,0 +1 @@ +Subproject commit dbcabbf45e0940e6f53224af2e9bc3715e728212 diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 9d058d6..a958543 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -46,6 +46,7 @@ package CoreW; // BSV library imports import Vector :: *; +import FIFO :: *; import FIFOF :: *; import GetPut :: *; import ClientServer :: *; @@ -84,9 +85,9 @@ import SoC_Map :: *; import Debug_Module :: *; `endif -import CoreW_IFC :: *; -import Proc_IFC :: *; -import Proc :: *; +import WindCoreInterface :: *; +import Proc_IFC :: *; +import Proc :: *; import PLIC :: *; import PLIC_16_CoreNumX2_7 :: *; @@ -110,9 +111,16 @@ import DM_CPU_Req_Rsp ::*; // ================================================================ // The Core module -(* synthesize *) +//(* synthesize *) module mkCoreW #(Reset dm_power_on_reset) - (CoreW_IFC #(N_External_Interrupt_Sources)); + (WindCoreLo #( // AXI manager 0 port parameters + TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + // AXI manager 1 port parameters + , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + // AXI subordinate 0 port parameters + , t_s_mid, t_s_addr, t_s_data, 0, 0, 0, 0, 0 + // Number of interrupt lines + , N_External_Interrupt_Sources)); // ================================================================ // Notes on 'reset' @@ -201,8 +209,9 @@ module mkCoreW #(Reset dm_power_on_reset) PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7; `ifdef INCLUDE_GDB_CONTROL + let dbg_reset <- mkReset (0, True, clk, reset_by dm_power_on_reset); // Debug Module - Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dm_power_on_reset); + Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dbg_reset.new_rst); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -423,78 +432,110 @@ module mkCoreW #(Reset dm_power_on_reset) endrule // ================================================================ - // INTERFACE + // Connect external debug module interface - // ---------------------------------------------------------------- - // Debugging: set core's verbosity, htif addrs + let f_dbg_reqs <- mkFIFO1; + let f_dbg_rsps <- mkFIFO1; + let f_dbg_rst_reqs <- mkFIFO1; + let f_dbg_rst_rsps <- mkFIFO1; - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - // Warning: ignoring logdelay - proc.set_verbosity (verbosity); - endmethod + rule rl_debug_module_req; + case (f_dbg_reqs.first) matches + tagged ReadReq {.rd_addr}: debug_module.dmi.read_addr (rd_addr); + tagged WriteReq {.wr_addr, .wr_data}: + debug_module.dmi.write (wr_addr, wr_data); + tagged ResetReq: dbg_reset.assertReset; + endcase + f_dbg_reqs.deq; + endrule - // ---------------------------------------------------------------- - // Start + rule rl_debug_module_rsp; + let x <- debug_module.dmi.read_data; + f_dbg_rsps.enq (ReadRsp(x)); + endrule - method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); + rule rl_debug_module_reset_req; + let _ <- debug_module.ndm_reset_client.request.get; + f_dbg_rst_reqs.enq(?); + endrule + + rule rl_debug_module_reset_rsp; + debug_module.ndm_reset_client.response.put(True); + f_dbg_rst_rsps.deq; + endrule + + // ================================================================ + // Connect external interrupts to the PLIC and Proc + + Vector #(t_n_irq, SetClear) irq_ifc; + for (Integer i = 0; i < valueof(t_n_irq); i = i + 1) begin + irq_ifc [i] = interface SetClear; + method set = plic.v_sources[i].m_interrupt_req(True); + method clear = plic.v_sources[i].m_interrupt_req(False); + endinterface; + end + + let nmirq_ifc = interface SetClear; + // TODO: fixup; passing const False for now + method set = proc.non_maskable_interrupt_req (False); + method clear = proc.non_maskable_interrupt_req (False); + endinterface; + + // ================================================================ + // Connect other control and status signals + + let f_ctrl_reqs <- mkFIFO1; + let f_ctrl_rsps <- mkFIFO1; + + function do_release = action plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base), zeroExtend (rangeTop(soc_map.m_plic_addr_range))); + proc.start ( True, soc_map_struct.pc_reset_value, 0, 0); + //proc.set_verbosity (verbosity); + endaction; - let pc = soc_map_struct.pc_reset_value; - proc.start (is_running, pc, tohost_addr, fromhost_addr); + rule rl_ctrl_req; + case (f_ctrl_reqs.first) matches + tagged ReleaseReq: do_release; + tagged StatusReq: $display ("StatusReq not supported in Toooba"); + endcase + f_ctrl_reqs.deq; + endrule -`ifdef INCLUDE_GDB_CONTROL - // Save for potential future use by rl_dm_harts_reset - rg_tohost_addr <= tohost_addr; - rg_fromhost_addr <= fromhost_addr; -`endif + rule rl_ctrl_rsp; + f_ctrl_rsps.enq (StatusRsp(?)); + endrule - $display ("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - cur_cycle, pc, tohost_addr, fromhost_addr); - endmethod + // ================================================================ + // INTERFACE - // ---------------------------------------------------------------- - // AXI4 Fabric interfaces + // debug related signals + // --------------------- + interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps); + interface debugModuleResetClient = toGPClient (f_dbg_rst_reqs, f_dbg_rst_rsps); + // interrupt related signals + // ------------------------- + interface irq = irq_ifc; + interface nmirq = nmirq_ifc; + + // other control and status signals + // -------------------------------- + interface controlStatusServer = toGPServer (f_ctrl_reqs, f_ctrl_rsps); + + // memory interfaces + // ----------------- // Cached master to Fabric master interface - interface cpu_imem_master = tagController.master; - + interface manager_0 = tagController.master; // Uncached master to Fabric master interface - interface cpu_dmem_master = prepend_AXI4_Master_id(0, zero_AXI4_Master_user(uncached_mem_shim.master)); - - // ---------------------------------------------------------------- - // External interrupt sources - - interface core_external_interrupt_sources = plic.v_sources; - - // ---------------------------------------------------------------- - // Non-maskable interrupt request - - method Action nmi_req (Bool set_not_clear); - // TODO: fixup; passing const False for now - proc.non_maskable_interrupt_req (False); - endmethod - + interface manager_1 = extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0); + // TODO: + interface subordinate_0 = culDeSac; +/* `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server = proc.rvfi_dii_server; `endif -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // Optional DM interfaces - - // ---------------- - // DMI (Debug Module Interface) facing remote debugger - - interface DMI dmi = debug_module.dmi; - - // ---------------- - // Facing Platform - - // Non-Debug-Module Reset (reset all except DM) - interface Client ndm_reset_client = debug_module.ndm_reset_client; -`endif - `ifdef INCLUDE_TANDEM_VERIF // ---------------------------------------------------------------- // Optional TV interface @@ -506,9 +547,11 @@ module mkCoreW #(Reset dm_power_on_reset) endmethod endinterface `endif +*/ endmodule: mkCoreW +/* (* synthesize *) module mkCoreW_Synth #(Reset dm_power_on_reset) (CoreW_IFC_Synth #(N_External_Interrupt_Sources)); @@ -533,6 +576,7 @@ module mkCoreW_Synth #(Reset dm_power_on_reset) interface tv_verifier_info_get = core.tv_verifier_info_get; `endif endmodule +*/ // ================================================================ // 2x3 Fabric for this Core From b9ee27f39029c9951cb956dc4739384c50c02efe Mon Sep 17 00:00:00 2001 From: gameboo Date: Wed, 28 Apr 2021 08:25:27 +0100 Subject: [PATCH 02/35] Update to WindCoreMid + Bump WindCoreInterface --- libs/WindCoreInterface | 2 +- src_Core/Core/CoreW.bsv | 149 +++++++++++++++++++--------------------- 2 files changed, 71 insertions(+), 80 deletions(-) diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index dbcabbf..74b8743 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit dbcabbf45e0940e6f53224af2e9bc3715e728212 +Subproject commit 74b87433524be9c28d545d370c3812100bc56232 diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index a958543..e68bbf5 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -111,16 +111,30 @@ import DM_CPU_Req_Rsp ::*; // ================================================================ // The Core module +typedef WindCoreMid #( // AXI manager 0 port parameters + TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + // AXI manager 1 port parameters + , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + // AXI subordinate 0 port parameters + , 0, 0, 0, 0, 0, 0, 0, 0 + // Number of interrupt lines + , N_External_Interrupt_Sources) WindCoreMidIfc; + //(* synthesize *) -module mkCoreW #(Reset dm_power_on_reset) - (WindCoreLo #( // AXI manager 0 port parameters - TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 - // AXI manager 1 port parameters - , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 - // AXI subordinate 0 port parameters - , t_s_mid, t_s_addr, t_s_data, 0, 0, 0, 0, 0 - // Number of interrupt lines - , N_External_Interrupt_Sources)); +module mkCoreW (WindCoreMidIfc); + Reset dfltRst <- exposeCurrentReset; + Reset otherRst = ?; + match {.fromDbgReset, .ifc} <- mkCoreResetHelper ( dfltRst + , reset_by otherRst ); + otherRst <- mkResetEither (dfltRst, fromDbgReset); + return ifc; +endmodule + +// The interface to this module is a convenience to avoid exposing the reset +// hacks to the nicer outer interface, and not have to use a large amount of +// reset_by to decouple the debug module from the rest... +module mkCoreResetHelper #(Reset toDbgReset) + (Tuple2#(Reset, WindCoreMidIfc)); // ================================================================ // Notes on 'reset' @@ -129,7 +143,7 @@ module mkCoreW #(Reset dm_power_on_reset) // 'non-debug-module reset', or 'ndm-reset': it resets everything // in mkCoreW other than the optional RISC-V Debug Module (DM). - // DM is reset ONLY by 'dm_power_on_reset' (parameter of this module). + // DM is reset ONLY by 'toDbgReset' (parameter of this module). // This is expected to be performed exactly once, on power-up. // Note: DM has an internal functionality that the DM spec calls @@ -209,9 +223,8 @@ module mkCoreW #(Reset dm_power_on_reset) PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7; `ifdef INCLUDE_GDB_CONTROL - let dbg_reset <- mkReset (0, True, clk, reset_by dm_power_on_reset); // Debug Module - Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dbg_reset.new_rst); + Debug_Module_IFC debug_module <- mkDebug_Module (reset_by toDbgReset); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -436,15 +449,12 @@ module mkCoreW #(Reset dm_power_on_reset) let f_dbg_reqs <- mkFIFO1; let f_dbg_rsps <- mkFIFO1; - let f_dbg_rst_reqs <- mkFIFO1; - let f_dbg_rst_rsps <- mkFIFO1; rule rl_debug_module_req; case (f_dbg_reqs.first) matches tagged ReadReq {.rd_addr}: debug_module.dmi.read_addr (rd_addr); tagged WriteReq {.wr_addr, .wr_data}: debug_module.dmi.write (wr_addr, wr_data); - tagged ResetReq: dbg_reset.assertReset; endcase f_dbg_reqs.deq; endrule @@ -454,32 +464,36 @@ module mkCoreW #(Reset dm_power_on_reset) f_dbg_rsps.enq (ReadRsp(x)); endrule - rule rl_debug_module_reset_req; + let fromDbgReset <- mkReset (0, False, clk); + rule rl_debug_module_send_reset; let _ <- debug_module.ndm_reset_client.request.get; - f_dbg_rst_reqs.enq(?); - endrule - - rule rl_debug_module_reset_rsp; - debug_module.ndm_reset_client.response.put(True); - f_dbg_rst_rsps.deq; + fromDbgReset.assertReset; endrule // ================================================================ // Connect external interrupts to the PLIC and Proc - Vector #(t_n_irq, SetClear) irq_ifc; - for (Integer i = 0; i < valueof(t_n_irq); i = i + 1) begin - irq_ifc [i] = interface SetClear; - method set = plic.v_sources[i].m_interrupt_req(True); - method clear = plic.v_sources[i].m_interrupt_req(False); + Vector #(N_External_Interrupt_Sources, Reg #(Bool)) irq_reg + <- replicateM (mkReg (False)); + Vector #(N_External_Interrupt_Sources, Put #(Bool)) irq_ifc; + for (Integer i = 0; i < valueof (N_External_Interrupt_Sources); i = i + 1) begin + irq_ifc [i] = interface Put; + method put = writeReg (irq_reg[i]); endinterface; + rule rl_connect_irq; + plic.v_sources[i].m_interrupt_req (irq_reg[i]); + endrule end - let nmirq_ifc = interface SetClear; - // TODO: fixup; passing const False for now - method set = proc.non_maskable_interrupt_req (False); - method clear = proc.non_maskable_interrupt_req (False); + let nmirq_reg <- mkReg (False); + let nmirq_ifc = interface Put; + method put = writeReg (nmirq_reg); endinterface; + rule rl_connect_nmirq; + // TODO: fixup; passing const False for now + //proc.non_maskable_interrupt_req (False); + proc.non_maskable_interrupt_req (nmirq_reg); + endrule // ================================================================ // Connect other control and status signals @@ -490,7 +504,7 @@ module mkCoreW #(Reset dm_power_on_reset) function do_release = action plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base), zeroExtend (rangeTop(soc_map.m_plic_addr_range))); - proc.start ( True, soc_map_struct.pc_reset_value, 0, 0); + proc.start (True, soc_map_struct.pc_reset_value, 0, 0); //proc.set_verbosity (verbosity); endaction; @@ -509,28 +523,31 @@ module mkCoreW #(Reset dm_power_on_reset) // ================================================================ // INTERFACE - // debug related signals - // --------------------- - interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps); - interface debugModuleResetClient = toGPClient (f_dbg_rst_reqs, f_dbg_rst_rsps); + let ifc = interface WindCoreMidIfc; + // debug related signals + // --------------------- + interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps); - // interrupt related signals - // ------------------------- - interface irq = irq_ifc; - interface nmirq = nmirq_ifc; + // interrupt related signals + // ------------------------- + interface irq = irq_ifc; + interface nmirq = nmirq_ifc; - // other control and status signals - // -------------------------------- - interface controlStatusServer = toGPServer (f_ctrl_reqs, f_ctrl_rsps); + // other control and status signals + // -------------------------------- + interface controlStatusServer = toGPServer (f_ctrl_reqs, f_ctrl_rsps); + + // memory interfaces + // ----------------- + // Cached master to Fabric master interface + interface manager_0 = tagController.master; + // Uncached master to Fabric master interface + interface manager_1 = + extendIDFields (zeroMasterUserFields (uncached_mem_shim.master), 0); + // TODO: + interface subordinate_0 = culDeSac; + endinterface; - // memory interfaces - // ----------------- - // Cached master to Fabric master interface - interface manager_0 = tagController.master; - // Uncached master to Fabric master interface - interface manager_1 = extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0); - // TODO: - interface subordinate_0 = culDeSac; /* `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server = proc.rvfi_dii_server; @@ -549,34 +566,8 @@ module mkCoreW #(Reset dm_power_on_reset) `endif */ -endmodule: mkCoreW - -/* -(* synthesize *) -module mkCoreW_Synth #(Reset dm_power_on_reset) - (CoreW_IFC_Synth #(N_External_Interrupt_Sources)); - let core <- mkCoreW (dm_power_on_reset); - let cpu_imem_master_sig <- toAXI4_Master_Sig (core.cpu_imem_master); - let cpu_dmem_master_sig <- toAXI4_Master_Sig (core.cpu_dmem_master); - - method set_verbosity = core.set_verbosity; - method start = core.start; - interface cpu_imem_master = cpu_imem_master_sig; - interface cpu_dmem_master = cpu_dmem_master_sig; - interface core_external_interrupt_sources = core.core_external_interrupt_sources; - method nmi_req = core.nmi_req; -`ifdef RVFI_DII - interface rvfi_dii_server = core.rvfi_dii_server; -`endif -`ifdef INCLUDE_GDB_CONTROL - interface dmi = core.dmi; - interface ndm_reset_client = core.ndm_reset_client; -`endif -`ifdef INCLUDE_TANDEM_VERIF - interface tv_verifier_info_get = core.tv_verifier_info_get; -`endif -endmodule -*/ + return tuple2 (fromDbgReset.new_rst, ifc); +endmodule: mkCoreResetHelper // ================================================================ // 2x3 Fabric for this Core From 72320b32b28af10285edf6f1fd80a0281974d17a Mon Sep 17 00:00:00 2001 From: gameboo Date: Wed, 28 Apr 2021 17:43:47 +0100 Subject: [PATCH 03/35] Update to AXI lite for debug module port --- libs/WindCoreInterface | 2 +- src_Core/Core/CoreW.bsv | 62 ++++----- src_Core/Core/CoreW_IFC.bsv | 204 ------------------------------ src_Testbench/SoC/SoC_Top.bsv | 37 ++---- src_Testbench/Top/Top_HW_Side.bsv | 57 ++------- 5 files changed, 59 insertions(+), 303 deletions(-) delete mode 100644 src_Core/Core/CoreW_IFC.bsv diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 74b8743..112cf18 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 74b87433524be9c28d545d370c3812100bc56232 +Subproject commit 112cf18a33edfb7402782bcf297aa3d179f7e81a diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index e68bbf5..eb7c781 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -60,7 +60,8 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; import AXI4 :: *; -import AXI4_Utils :: *; +import AXI4Lite :: *; +import SourceSink :: *; import TagControllerAXI :: *; import CacheCore :: *; @@ -118,15 +119,18 @@ typedef WindCoreMid #( // AXI manager 0 port parameters // AXI subordinate 0 port parameters , 0, 0, 0, 0, 0, 0, 0, 0 // Number of interrupt lines - , N_External_Interrupt_Sources) WindCoreMidIfc; + , t_n_irq) CoreW_IFC #(numeric type t_n_irq); //(* synthesize *) -module mkCoreW (WindCoreMidIfc); - Reset dfltRst <- exposeCurrentReset; - Reset otherRst = ?; - match {.fromDbgReset, .ifc} <- mkCoreResetHelper ( dfltRst - , reset_by otherRst ); - otherRst <- mkResetEither (dfltRst, fromDbgReset); +module mkCoreW (CoreW_IFC #(t_n_irq)); + Clock clk <- exposeCurrentClock; + Reset rst <- exposeCurrentReset; + let newRst <- mkReset (0, True, clk, reset_by rst); + match {.otherRst, .ifc} <- mkCoreResetHelper ( rst + , reset_by newRst.new_rst); + rule rl_forward_debug_reset (otherRst); + newRst.assertReset; + endrule return ifc; endmodule @@ -134,7 +138,7 @@ endmodule // hacks to the nicer outer interface, and not have to use a large amount of // reset_by to decouple the debug module from the rest... module mkCoreResetHelper #(Reset toDbgReset) - (Tuple2#(Reset, WindCoreMidIfc)); + (Tuple2#(PulseWire, CoreW_IFC #(t_n_irq))); // ================================================================ // Notes on 'reset' @@ -447,36 +451,36 @@ module mkCoreResetHelper #(Reset toDbgReset) // ================================================================ // Connect external debug module interface - let f_dbg_reqs <- mkFIFO1; - let f_dbg_rsps <- mkFIFO1; + let dbgShim <- mkAXI4LiteShim (reset_by toDbgReset); - rule rl_debug_module_req; - case (f_dbg_reqs.first) matches - tagged ReadReq {.rd_addr}: debug_module.dmi.read_addr (rd_addr); - tagged WriteReq {.wr_addr, .wr_data}: - debug_module.dmi.write (wr_addr, wr_data); - endcase - f_dbg_reqs.deq; + rule rl_debug_module_read_req; + let arFlit <- get (dbgShim.master.ar); + debug_module.dmi.read_addr (arFlit.araddr); endrule - - rule rl_debug_module_rsp; + rule rl_debug_module_read_rsp; let x <- debug_module.dmi.read_data; - f_dbg_rsps.enq (ReadRsp(x)); + dbgShim.master.r.put(AXI4Lite_RFlit { rdata: x, rresp: OKAY, ruser: ?}); + endrule + rule rl_debug_module_write_req; + let awFlit <- get (dbgShim.master.aw); + let wFlit <- get (dbgShim.master.w); + dbgShim.master.b.put(defaultValue); + debug_module.dmi.write (awFlit.awaddr, wFlit.wdata); endrule - let fromDbgReset <- mkReset (0, False, clk); + let fromDbgReset <- mkPulseWire (reset_by toDbgReset); rule rl_debug_module_send_reset; let _ <- debug_module.ndm_reset_client.request.get; - fromDbgReset.assertReset; + fromDbgReset.send; endrule // ================================================================ // Connect external interrupts to the PLIC and Proc - Vector #(N_External_Interrupt_Sources, Reg #(Bool)) irq_reg + Vector #(t_n_irq, Reg #(Bool)) irq_reg <- replicateM (mkReg (False)); - Vector #(N_External_Interrupt_Sources, Put #(Bool)) irq_ifc; - for (Integer i = 0; i < valueof (N_External_Interrupt_Sources); i = i + 1) begin + Vector #(t_n_irq, Put #(Bool)) irq_ifc; + for (Integer i = 0; i < valueof (t_n_irq); i = i + 1) begin irq_ifc [i] = interface Put; method put = writeReg (irq_reg[i]); endinterface; @@ -523,10 +527,10 @@ module mkCoreResetHelper #(Reset toDbgReset) // ================================================================ // INTERFACE - let ifc = interface WindCoreMidIfc; + let ifc = interface CoreW_IFC; // debug related signals // --------------------- - interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps); + interface debug_subordinate = dbgShim.slave; // interrupt related signals // ------------------------- @@ -566,7 +570,7 @@ module mkCoreResetHelper #(Reset toDbgReset) `endif */ - return tuple2 (fromDbgReset.new_rst, ifc); + return tuple2 (fromDbgReset, ifc); endmodule: mkCoreResetHelper // ================================================================ diff --git a/src_Core/Core/CoreW_IFC.bsv b/src_Core/Core/CoreW_IFC.bsv deleted file mode 100644 index ff6a4c3..0000000 --- a/src_Core/Core/CoreW_IFC.bsv +++ /dev/null @@ -1,204 +0,0 @@ -// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved. -// -//- -// RVFI_DII + CHERI modifications: -// Copyright (c) 2020 Alexandre Joannou -// Copyright (c) 2020 Peter Rugg -// Copyright (c) 2020 Jonathan Woodruff -// All rights reserved. -// -// This software was developed by SRI International and the University of -// Cambridge Computer Laboratory (Department of Computer Science and -// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the -// DARPA SSITH research programme. -// -// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). -//- - -package CoreW_IFC; - -// ================================================================ -// This package defines the interface of a CoreW module which -// contains: -// - mkProc (the RISC-V CPU; this a variant of MIT's RISCY-OOO mkProc) -// Note: MIT's RISCY-OOO internally has a 'mkCore' and hence this -// interface and its module is called 'CoreW', to disambiguate. -// - mkFabric_2x3 -// - mkNear_Mem_IO_AXI4 -// - mkPLIC_16_CoreNumX2_7 -// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF) -// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL) - -// ================================================================ -// BSV library imports - -import Vector :: *; -import GetPut :: *; -import ClientServer :: *; - -// ---------------- -// BSV additional libs -import AXI4 :: *; - -// ================================================================ -// Project imports - -// Main fabric -import Fabric_Defs :: *; - -// External interrupt request interface -import PLIC :: *; - -`ifdef INCLUDE_GDB_CONTROL -import Debug_Module :: *; -`endif - -`ifdef RVFI_DII -import ProcTypes :: *; -`endif - -`ifdef INCLUDE_TANDEM_VERIF -import ProcTypes :: *; -import Trace_Data2 :: *; -import TV_Info :: *; -`endif - -// ================================================================ -// The CoreW interface - -interface CoreW_IFC #(numeric type t_n_interrupt_sources); - - // ---------------------------------------------------------------- - // Debugging: set core's verbosity - - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - - // ---------------------------------------------------------------- - // Start - - method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); - - // ---------------------------------------------------------------- - // AXI4 Fabric interfaces - - // CPU IMem to Fabric master interface - interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_imem_master; - - // CPU DMem to Fabric master interface - interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_dmem_master; - - // ---------------------------------------------------------------- - // External interrupt sources - - interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources; - - // ---------------------------------------------------------------- - // Non-maskable interrupt request - - (* always_ready, always_enabled *) - method Action nmi_req (Bool set_not_clear); - -`ifdef RVFI_DII - interface Toooba_RVFI_DII_Server rvfi_dii_server; -`endif - -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // Optional Debug Module interfaces - - // ---------------- - // DMI (Debug Module Interface) facing remote debugger - - interface DMI dmi; - - // ---------------- - // Facing Platform - // Non-Debug-Module Reset (reset all except DM) - - interface Client #(Bool, Bool) ndm_reset_client; -`endif - -`ifdef INCLUDE_TANDEM_VERIF - // ---------------------------------------------------------------- - // Optional Tandem Verifier interface output tuples (n,vb), - // where 'vb' is a vector of bytes - // with relevant bytes in locations [0]..[n-1] - - interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get; -`endif - -endinterface - -// ================================================================ -// The Synthesizable CoreW interface (same with Synth AXI) - -interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources); - - // ---------------------------------------------------------------- - // Debugging: set core's verbosity - - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); - - // ---------------------------------------------------------------- - // Start - - method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr); - - // ---------------------------------------------------------------- - // AXI4 Fabric interfaces - - // CPU IMem to Fabric master interface - interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_imem_master; - - // CPU DMem to Fabric master interface - interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, - 0, 0, 0, 0, 0) cpu_dmem_master; - - // ---------------------------------------------------------------- - // External interrupt sources - - interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources; - - // ---------------------------------------------------------------- - // Non-maskable interrupt request - - (* always_ready, always_enabled *) - method Action nmi_req (Bool set_not_clear); - -`ifdef RVFI_DII - interface Toooba_RVFI_DII_Server rvfi_dii_server; -`endif - -`ifdef INCLUDE_GDB_CONTROL - // ---------------------------------------------------------------- - // Optional Debug Module interfaces - - // ---------------- - // DMI (Debug Module Interface) facing remote debugger - - interface DMI dmi; - - // ---------------- - // Facing Platform - // Non-Debug-Module Reset (reset all except DM) - - interface Client #(Bool, Bool) ndm_reset_client; -`endif - -`ifdef INCLUDE_TANDEM_VERIF - // ---------------------------------------------------------------- - // Optional Tandem Verifier interface output tuples (n,vb), - // where 'vb' is a vector of bytes - // with relevant bytes in locations [0]..[n-1] - - interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get; -`endif - -endinterface - -// ================================================================ - -endpackage diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index e854d53..daf6de8 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -47,6 +47,7 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Routable :: *; import AXI4 :: *; +import AXI4Lite :: *; // ================================================================ // Project imports @@ -56,7 +57,7 @@ import SoC_Map :: *; // SoC components (CPU, mem, and IPs) -import CoreW_IFC :: *; +import WindCoreInterface :: *; import CoreW :: *; import PLIC :: *; // For interface to PLIC interrupt sources, in CoreW_IFC @@ -90,15 +91,9 @@ import Debug_Module :: *; // The outermost interface of the SoC interface SoC_Top_IFC; - // Set core's verbosity - method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay); `ifdef INCLUDE_GDB_CONTROL - // DMI (Debug Module Interface) facing remote debugger - interface DMI dmi; - - // Non-Debug-Module Reset (reset all except DM) - interface Client #(Bool, Bool) ndm_reset_client; + interface AXI4Lite_Slave #(7, 32, 0, 0, 0, 0, 0) debug_subordinate; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -148,7 +143,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) // Core: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) // The Debug Module has its own RST_N reset signal (which comes // from outside this module as a paramter) - CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW (dm_power_on_reset); + CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW; // SoC Boot ROM Boot_ROM_IFC boot_rom <- mkBoot_ROM; @@ -179,10 +174,10 @@ module mkSoC_Top #(Reset dm_power_on_reset) master_vector = newVector; // CPU IMem master to fabric - master_vector[imem_master_num] = corew.cpu_imem_master; + master_vector[imem_master_num] = corew.manager_0; // CPU DMem master to fabric - master_vector[dmem_master_num] = corew.cpu_dmem_master; + master_vector[dmem_master_num] = corew.manager_1; // ---------------- // SoC fabric slave connections @@ -232,21 +227,21 @@ module mkSoC_Top #(Reset dm_power_on_reset) Bool intr = uart0.intr; // UART - corew.core_external_interrupt_sources [irq_num_uart0].m_interrupt_req (intr); + corew.irq [irq_num_uart0].put (intr); Integer last_irq_num = irq_num_uart0; `ifdef INCLUDE_ACCEL0 Bool intr_accel0 = accel0.interrupt_req; - corew.core_external_interrupt_sources [irq_num_accel0].m_interrupt_req (intr_accel0); + corew.irq [irq_num_accel0].put (intr_accel0); last_irq_num = irq_num_accel0; `endif // Tie off remaining interrupt request lines (1..N) for (Integer j = last_irq_num + 1; j < valueOf (N_External_Interrupt_Sources); j = j + 1) - corew.core_external_interrupt_sources [j].m_interrupt_req (False); + corew.irq [j].put (False); // Non-maskable interrupt request. [Tie-off; TODO: connect to genuine sources] - corew.nmi_req (False); + corew.nmirq.put (False); endrule // ================================================================ @@ -314,17 +309,9 @@ module mkSoC_Top #(Reset dm_power_on_reset) // ================================================================ // INTERFACE - method Action set_verbosity (Bit #(4) new_verbosity, Bit #(64) logdelay); - corew.set_verbosity (new_verbosity, logdelay); - endmethod - // To external controller (E.g., GDB) `ifdef INCLUDE_GDB_CONTROL - // DMI (Debug Module Interface) facing remote debugger - interface DMI dmi = corew.dmi; - - // Non-Debug-Module Reset (reset all except DM) - interface Client ndm_reset_client = corew.ndm_reset_client; + interface debug_subordinate = corew.debug_subordinate; `endif `ifdef INCLUDE_TANDEM_VERIF @@ -352,7 +339,7 @@ module mkSoC_Top #(Reset dm_power_on_reset) Bool watch_tohost = (tohost_addr != 0); mem0_controller.set_watch_tohost (watch_tohost, tohost_addr); Bool is_running = True; - corew.start (is_running, tohost_addr, fromhost_addr); + corew.controlStatusServer.request.put (ReleaseReq); $display ("%0d: %m.method start (tohost %0h, fromhost %0h)", cur_cycle, tohost_addr, fromhost_addr); endmethod diff --git a/src_Testbench/Top/Top_HW_Side.bsv b/src_Testbench/Top/Top_HW_Side.bsv index cc95e98..c93b966 100644 --- a/src_Testbench/Top/Top_HW_Side.bsv +++ b/src_Testbench/Top/Top_HW_Side.bsv @@ -51,6 +51,9 @@ import GetPut_Aux :: *; // ================================================================ // Project imports +import WindCoreInterface :: *; +import AXI4Lite :: *; +import SourceSink :: *; import ISA_Decls :: *; import TV_Info :: *; import SoC_Top :: *; @@ -104,16 +107,7 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); // - on power-on, and // - when the Debug Module requests an NDM reset (for non-DebugModule). -`ifdef INCLUDE_GDB_CONTROL - let clk <- exposeCurrentClock; - Bool initial_reset_val = False; - Integer ndm_reset_duration = 10; // NOTE: assuming 10 cycle reset enough for NDM - let ndm_reset_controller <- mkReset(ndm_reset_duration, initial_reset_val, clk); - - let ndm_reset <- mkResetEither (power_on_reset, ndm_reset_controller.new_rst); -`else let ndm_reset = power_on_reset; -`endif // ================================================================ // STATE @@ -140,7 +134,6 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); Bool v2 <- $test$plusargs ("v2"); Bit #(4) verbosity = ((v2 ? 2 : (v1 ? 1 : 0))); Bit #(64) logdelay = 0; // # of instructions after which to set verbosity - soc_top.set_verbosity (verbosity, logdelay); // ---------------- // Load optional tohost and fromhost addrs from symbol-table file @@ -165,36 +158,6 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); endfunction // ================================================================ - -`ifdef INCLUDE_GDB_CONTROL - // ================================================================ - // NDM reset from DM - - Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); - - rule rl_ndm_reset (rg_ndm_reset_delay == 0); - let x <- soc_top.ndm_reset_client.request.get; - ndm_reset_controller.assertReset; - rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 200); // NOTE: heuristic - - $display ("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - cur_cycle, ndm_reset_duration); - endrule - - rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); - if (rg_ndm_reset_delay == 1) begin - fa_reset_actions; - Bool is_running = True; - soc_top.ndm_reset_client.response.put (is_running); - $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - cur_cycle); - end - rg_ndm_reset_delay <= rg_ndm_reset_delay - 1; - endrule - // ================================================================ -`endif - - // ================================================================ // BEHAVIOR Reg #(Bool) rg_banner_printed <- mkReg (False); @@ -376,7 +339,8 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); rule rl_handle_external_req_read_request (req.op == external_control_req_op_read_control_fabric); f_external_control_reqs.deq; - soc_top.dmi.read_addr (truncate (req.arg1)); + soc_top.debug_subordinate.ar.put(AXI4Lite_ARFlit { araddr: truncate (req.arg1) + , arprot: ?, aruser: ? }); if (dmi_verbosity != 0) begin $display ("%0d: %m.rl_handle_external_req_read_request", cur_cycle); $display (" ", fshow (req)); @@ -384,8 +348,8 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); endrule rule rl_handle_external_req_read_response; - let x <- soc_top.dmi.read_data; - let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: signExtend (x)}; + let x <- get (soc_top.debug_subordinate.r); + let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: signExtend (x.rdata)}; f_external_control_rsps.enq (rsp); if (dmi_verbosity != 0) begin $display ("%0d: %m.rl_handle_external_req_read_response", cur_cycle); @@ -395,7 +359,10 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); rule rl_handle_external_req_write (req.op == external_control_req_op_write_control_fabric); f_external_control_reqs.deq; - soc_top.dmi.write (truncate (req.arg1), truncate (req.arg2)); + soc_top.debug_subordinate.aw.put(AXI4Lite_AWFlit { awaddr: truncate (req.arg1) + , awprot: ?, awuser: ? }); + soc_top.debug_subordinate.w.put(AXI4Lite_WFlit { wdata: truncate (req.arg2) + , wstrb: ~0, wuser: ? }); // let rsp = Control_Rsp {status: external_control_rsp_status_ok, result: 0}; // f_external_control_rsps.enq (rsp); if (dmi_verbosity != 0) begin @@ -404,6 +371,8 @@ module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server); end endrule + rule rl_drain_debug_write_rsps; soc_top.debug_subordinate.b.drop; endrule + rule rl_handle_external_req_err ( (req.op != external_control_req_op_read_control_fabric) && (req.op != external_control_req_op_write_control_fabric)); f_external_control_reqs.deq; From 45135a0beead477b2efc321753fa579264e8b6ef Mon Sep 17 00:00:00 2001 From: gameboo Date: Fri, 28 May 2021 18:32:25 +0100 Subject: [PATCH 04/35] Don't assume a XILINX tool flow --- src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv | 3 +++ src_Core/RISCY_OOO/fpgautils/lib/SyncFifo.bsv | 2 ++ src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv | 3 +++ src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv | 3 +++ src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv | 8 ++++++++ 5 files changed, 19 insertions(+) diff --git a/src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv b/src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv index c104a73..1fdc68a 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/ResetGuard.bsv @@ -28,6 +28,9 @@ interface ResetGuard; endinterface `ifdef BSIM +`define NO_XILINX +`endif +`ifdef NO_XILINX module mkResetGuard(ResetGuard); Reg#(Bool) ready <- mkReg(False); diff --git a/src_Core/RISCY_OOO/fpgautils/lib/SyncFifo.bsv b/src_Core/RISCY_OOO/fpgautils/lib/SyncFifo.bsv index e780722..d91de68 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/SyncFifo.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/SyncFifo.bsv @@ -24,7 +24,9 @@ import Clocks::*; import FIFOF::*; import Assert::*; +`ifdef USE_CONNECTAL_BRAM_SYNC_FIFO import ConnectalBramFifo::*; +`endif import BRAMFIFO::*; import XilinxSyncFifo::*; import ResetGuard::*; diff --git a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv index e48b711..d6e8d6f 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv @@ -124,6 +124,9 @@ module mkXilinxIntDiv(XilinxIntDiv#(tagT)) provisos ( Bits#(tagT, tagSz), Add#(tagSz, a__, 8) ); `ifdef BSIM +`define NO_XILINX +`endif +`ifdef NO_XILINX IntDivUnsignedImport divIfc <- mkIntDivUnsignedSim; `else IntDivUnsignedImport divIfc <- mkIntDivUnsignedImport; diff --git a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv index 1a91dc1..5986cb3 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv @@ -110,6 +110,9 @@ module mkXilinxIntMul(XilinxIntMul#(tagT)) provisos( // different multilpliers: WaitAutoReset is not needed, since mul is a // pipeline with fixed latency `ifdef BSIM +`define NO_XILINX +`endif +`ifdef NO_XILINX IntMulImport mulSigned <- mkIntMulSim(Signed); IntMulImport mulUnsigned <- mkIntMulSim(Unsigned); IntMulImport mulSignedUnsigned <- mkIntMulSim(SignedUnsigned); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv index d84e1ae..b2315af 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv @@ -79,10 +79,18 @@ `define LOG_L2_TLB_4KB_WAYS 2 // L2 4KB TLB log ways (4 ways) // FMA bookkeeping FIFO: add 1 to allow simultaneous enq/deq +`ifdef USE_XILINX_FPU `define BOOKKEEPING_FP_FMA_SIZE TAdd#(`XILINX_FP_FMA_LATENCY, 1) +`else +`define BOOKKEEPING_FP_FMA_SIZE 4 +`endif // INT MUL bookkeeping FIFO: add 1 to allow simultaneous enq/deq, another 1 // because of internal flow control in MUL unit +`ifdef USE_XILINX_FPU `define BOOKKEEPING_INT_MUL_SIZE TAdd#(`XILINX_INT_MUL_LATENCY, 2) +`else +`define BOOKKEEPING_INT_MUL_SIZE 4 +`endif // non-blocking DTLB `define DTLB_REQ_NUM 4 From e51f7e2680886ec366dc058a7af2765d09d77e6c Mon Sep 17 00:00:00 2001 From: gameboo Date: Fri, 28 May 2021 18:40:21 +0100 Subject: [PATCH 05/35] Bump WindCoreInterface --- libs/WindCoreInterface | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 112cf18..237f28e 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 112cf18a33edfb7402782bcf297aa3d179f7e81a +Subproject commit 237f28e3e4c3ea51d4b93476246cf8880f660d36 From b32da9034b23e8b83c01329268d3f52694e6b5ee Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 1 Jul 2021 15:06:51 +0100 Subject: [PATCH 06/35] Fix addr to DM_addr convertion (pointed out by jrtc27) --- src_Core/Core/CoreW.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index eb7c781..f1c7970 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -455,7 +455,7 @@ module mkCoreResetHelper #(Reset toDbgReset) rule rl_debug_module_read_req; let arFlit <- get (dbgShim.master.ar); - debug_module.dmi.read_addr (arFlit.araddr); + debug_module.dmi.read_addr (truncate (arFlit.araddr >> 2)); endrule rule rl_debug_module_read_rsp; let x <- debug_module.dmi.read_data; @@ -465,7 +465,7 @@ module mkCoreResetHelper #(Reset toDbgReset) let awFlit <- get (dbgShim.master.aw); let wFlit <- get (dbgShim.master.w); dbgShim.master.b.put(defaultValue); - debug_module.dmi.write (awFlit.awaddr, wFlit.wdata); + debug_module.dmi.write (truncate (awFlit.awaddr >> 2), wFlit.wdata); endrule let fromDbgReset <- mkPulseWire (reset_by toDbgReset); From a954fd5b38a699cd56f74f1933e1ce6fc6469c41 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Sat, 7 Aug 2021 12:07:20 +0100 Subject: [PATCH 07/35] Use NonPipelined dividers + update "reset_by" in CoreW --- src_Core/Core/CoreW.bsv | 22 ++++++++++------- .../RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv | 24 +++++++++++-------- src_Core/RISCY_OOO/procs/lib/Fpu.bsv | 8 ++++--- 3 files changed, 32 insertions(+), 22 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index f1c7970..639da69 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -224,7 +224,7 @@ module mkCoreResetHelper #(Reset toDbgReset) `endif // PLIC (Platform-Level Interrupt Controller) - PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7; + PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7 (reset_by all_harts_reset); `ifdef INCLUDE_GDB_CONTROL // Debug Module @@ -279,8 +279,8 @@ module mkCoreResetHelper #(Reset toDbgReset) // ================================================================ // Direct DM-to-CPU connections for run-control and other misc requests - mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server); - mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req); + mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server, reset_by toDbgReset); + mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req, reset_by toDbgReset); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -361,15 +361,15 @@ module mkCoreResetHelper #(Reset toDbgReset) // BEGIN SECTION: DM, no TV // Connect DM's GPR interface directly to CPU - mkConnection (debug_module.harts_gpr_mem_client, proc.harts_gpr_mem_server); + mkConnection (debug_module.harts_gpr_mem_client, proc.harts_gpr_mem_server, reset_by toDbgReset); `ifdef ISA_F_OR_D // Connect DM's FPR interface directly to CPU - mkConnection (debug_module.harts_fpr_mem_client, proc.harts_fpr_mem_server); + mkConnection (debug_module.harts_fpr_mem_client, proc.harts_fpr_mem_server, reset_by toDbgReset); `endif // Connect DM's CSR interface directly to CPU - mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server); + mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server, reset_by toDbgReset); // DM's bus master is directly the bus master let dm_master_local = debug_module.master; @@ -430,7 +430,7 @@ module mkCoreResetHelper #(Reset toDbgReset) return res; endfunction - mkAXI4Bus (route_2x3, master_vector, slave_vector); + mkAXI4Bus (route_2x3, master_vector, slave_vector, reset_by all_harts_reset); // ================================================================ // Connect external interrupt lines from PLIC to CPU @@ -469,8 +469,12 @@ module mkCoreResetHelper #(Reset toDbgReset) endrule let fromDbgReset <- mkPulseWire (reset_by toDbgReset); - rule rl_debug_module_send_reset; - let _ <- debug_module.ndm_reset_client.request.get; + Reg #(UInt #(8)) ndm_reset_delay <- mkReg (0, reset_by toDbgReset); + Reg #(Bool) ndm_reset_restart_running <- mkReg (True, reset_by toDbgReset); + rule rl_debug_module_send_reset (ndm_reset_delay == 0); + let restartRunning <- debug_module.ndm_reset_client.request.get; + ndm_reset_delay <= 110; + ndm_reset_restart_running <= restartRunning; fromDbgReset.send; endrule diff --git a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv index d6e8d6f..e93e1f1 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv @@ -2,6 +2,9 @@ import FIFOF::*; import FIFO::*; import WaitAutoReset::*; +import NonPipelinedMath::*; +import ClientServer::*; +import GetPut::*; export XilinxIntDiv(..); export mkXilinxIntDiv; @@ -70,22 +73,23 @@ module mkIntDivUnsignedSim(IntDivUnsignedImport); FIFO#(Bit#(64)) divisorQ <- mkFIFO; FIFOF#(Tuple2#(Bit#(128), IntDivUser)) respQ <- mkSizedFIFOF(2); + FIFO#(IntDivUser) userFF <- mkFIFO; + Server#(Tuple2#(UInt#(128),UInt#(64)),Tuple2#(UInt#(64),UInt#(64))) + nonpipediv <- mkNonPipelinedDividerBlah (4); + rule compute; dividendQ.deq; divisorQ.deq; let {dividend, user} = dividendQ.first; let divisor = divisorQ.first; + nonpipediv.request.put(tuple2(unpack(zeroExtend(dividend)), unpack(divisor))); + userFF.enq(user); + endrule - // Be careful to avoid divide-by-zero in bluesim's C++, which turns - // res = cond ? exp1 : exp2 - // into - // tmp1 = exp1; tmp2 = exp2; res = cond ? tmp1 : tmp2 - // so we must give a fake non-zero input even if it looks unused. - UInt#(64) a = unpack(dividend); - UInt#(64) b = divisor == 0 ? 1 : unpack(divisor); - Bit#(64) q = divisor == 0 ? maxBound : pack(a / b); - Bit#(64) r = divisor == 0 ? dividend : pack(a % b); - respQ.enq(tuple2({q, r}, user)); + rule getResult; + let {qq, rr} <- nonpipediv.response.get; + let user <- toGet(userFF).get; + respQ.enq(tuple2({pack(qq), pack(rr)}, user)); endrule method Action enqDividend(Bit#(64) dividend, IntDivUser user); diff --git a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv index d7ff598..95b478a 100644 --- a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv @@ -48,8 +48,9 @@ import FIFO::*; import FIFOF::*; import ClientServer::*; import GetPut::*; -import Divide::*; -import SquareRoot::*; +//import Divide::*; +//import SquareRoot::*; +import NonPipelinedMath :: *; import FloatingPoint::*; import XilinxFpu::*; import HasSpecBits::*; @@ -95,7 +96,8 @@ module mkDoubleDiv(Server#(Tuple3#(Double, Double, FpuRoundMode), Tuple2#(Double `ifdef USE_XILINX_FPU let fpu <- mkXilinxFpDiv; `else - let int_div <- mkNonPipelinedDivider(3); // [sizhuo] size in RVFpu: 2 + //let int_div <- mkDivider(1); // [sizhuo] size in RVFpu: 2 + let int_div <- mkNonPipelinedDividerBlah(3); let fpu <- mkFloatingPointDivider(int_div); `endif return fpu; From 2c450aea8cc996834f74109e8cc6e7815f00228a Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 9 Sep 2021 10:57:25 +0100 Subject: [PATCH 08/35] Some reset adjustments --- src_Core/Core/CoreW.bsv | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 639da69..c73d9a4 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -126,8 +126,8 @@ module mkCoreW (CoreW_IFC #(t_n_irq)); Clock clk <- exposeCurrentClock; Reset rst <- exposeCurrentReset; let newRst <- mkReset (0, True, clk, reset_by rst); - match {.otherRst, .ifc} <- mkCoreResetHelper ( rst - , reset_by newRst.new_rst); + match {.otherRst, .ifc} <- mkCoreW_reset ( rst + , reset_by newRst.new_rst); rule rl_forward_debug_reset (otherRst); newRst.assertReset; endrule @@ -137,8 +137,8 @@ endmodule // The interface to this module is a convenience to avoid exposing the reset // hacks to the nicer outer interface, and not have to use a large amount of // reset_by to decouple the debug module from the rest... -module mkCoreResetHelper #(Reset toDbgReset) - (Tuple2#(PulseWire, CoreW_IFC #(t_n_irq))); +module mkCoreW_reset #(Reset toDbgReset) + (Tuple2#(PulseWire, CoreW_IFC #(t_n_irq))); // ================================================================ // Notes on 'reset' @@ -244,6 +244,7 @@ module mkCoreResetHelper #(Reset toDbgReset) // ================================================================ // Hart-reset from DM + Bool start_running = False; `ifdef INCLUDE_GDB_CONTROL Reg #(Bit #(8)) rg_harts_reset_delay <- mkReg (0); Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0); @@ -262,11 +263,10 @@ module mkCoreResetHelper #(Reset toDbgReset) rule rl_dm_harts_reset_wait (rg_harts_reset_delay != 0); if (rg_harts_reset_delay == 1) begin let pc = soc_map_struct.pc_reset_value; - Bool is_running = True; - proc.start (is_running, pc, rg_tohost_addr, rg_fromhost_addr); + proc.start (start_running, pc, rg_tohost_addr, rg_fromhost_addr); // We reset all the harts, so we indicate this to the DM, even though it's possible only one hart was requested to reset for (Integer core = 0; core < valueOf(CoreNum); core = core + 1) - debug_module.harts_reset_client[core].response.put (is_running); + debug_module.harts_reset_client[core].response.put (start_running); $display ("%0d: %m.rl_dm_harts_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr); end @@ -274,6 +274,15 @@ module mkCoreResetHelper #(Reset toDbgReset) endrule `endif + // ================================================================ + // Start the proc a suitable time after a PoR + UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew + Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait); + rule rl_step_0 (rg_corew_start_after_por != 0); + let n = rg_corew_start_after_por - 1; + rg_corew_start_after_por <= n; + if (n==0) do_release(start_running); + endrule `ifdef INCLUDE_GDB_CONTROL // ================================================================ @@ -470,7 +479,7 @@ module mkCoreResetHelper #(Reset toDbgReset) let fromDbgReset <- mkPulseWire (reset_by toDbgReset); Reg #(UInt #(8)) ndm_reset_delay <- mkReg (0, reset_by toDbgReset); - Reg #(Bool) ndm_reset_restart_running <- mkReg (True, reset_by toDbgReset); + Reg #(Bool) ndm_reset_restart_running <- mkReg (False, reset_by toDbgReset); rule rl_debug_module_send_reset (ndm_reset_delay == 0); let restartRunning <- debug_module.ndm_reset_client.request.get; ndm_reset_delay <= 110; @@ -575,7 +584,7 @@ module mkCoreResetHelper #(Reset toDbgReset) */ return tuple2 (fromDbgReset, ifc); -endmodule: mkCoreResetHelper +endmodule: mkCoreW_reset // ================================================================ // 2x3 Fabric for this Core From a65c93ee9899183dfd1b5574be2331b3375f36c6 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Tue, 14 Sep 2021 11:05:50 +0100 Subject: [PATCH 09/35] Update resetting in coreW --- src_Core/Core/CoreW.bsv | 43 ++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index c73d9a4..8e3e844 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -137,7 +137,7 @@ endmodule // The interface to this module is a convenience to avoid exposing the reset // hacks to the nicer outer interface, and not have to use a large amount of // reset_by to decouple the debug module from the rest... -module mkCoreW_reset #(Reset toDbgReset) +module mkCoreW_reset #(Reset porReset) (Tuple2#(PulseWire, CoreW_IFC #(t_n_irq))); // ================================================================ @@ -147,7 +147,7 @@ module mkCoreW_reset #(Reset toDbgReset) // 'non-debug-module reset', or 'ndm-reset': it resets everything // in mkCoreW other than the optional RISC-V Debug Module (DM). - // DM is reset ONLY by 'toDbgReset' (parameter of this module). + // DM is reset ONLY by 'porReset' (parameter of this module). // This is expected to be performed exactly once, on power-up. // Note: DM has an internal functionality that the DM spec calls @@ -228,7 +228,7 @@ module mkCoreW_reset #(Reset toDbgReset) `ifdef INCLUDE_GDB_CONTROL // Debug Module - Debug_Module_IFC debug_module <- mkDebug_Module (reset_by toDbgReset); + Debug_Module_IFC debug_module <- mkDebug_Module (reset_by porReset); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -252,22 +252,21 @@ module mkCoreW_reset #(Reset toDbgReset) for (Integer core = 0; core < valueOf(CoreNum); core = core + 1) rule rl_dm_harts_reset (rg_harts_reset_delay == 0); - let x <- debug_module.harts_reset_client[core].request.get; - dm_harts_reset_controller[core].assertReset; - rg_harts_reset_delay <= fromInteger (hart_reset_duration + 200); // NOTE: heuristic - - $display ("%0d: %m.rl_dm_harts_reset: asserting harts reset for %0d cycles", + let x <- debug_module.harts_reset_client[core].request.get; + dm_harts_reset_controller[core].assertReset; + rg_harts_reset_delay <= fromInteger (hart_reset_duration + 200); // NOTE: heuristic + $display ("%0d: %m.rl_dm_harts_reset: asserting harts reset for %0d cycles", cur_cycle, hart_reset_duration); - endrule + endrule rule rl_dm_harts_reset_wait (rg_harts_reset_delay != 0); if (rg_harts_reset_delay == 1) begin let pc = soc_map_struct.pc_reset_value; - proc.start (start_running, pc, rg_tohost_addr, rg_fromhost_addr); + proc.start (start_running, pc, rg_tohost_addr, rg_fromhost_addr); // We reset all the harts, so we indicate this to the DM, even though it's possible only one hart was requested to reset for (Integer core = 0; core < valueOf(CoreNum); core = core + 1) - debug_module.harts_reset_client[core].response.put (start_running); - $display ("%0d: %m.rl_dm_harts_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", + debug_module.harts_reset_client[core].response.put (start_running); + $display ("%0d: %m.rl_dm_harts_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr); end rg_harts_reset_delay <= rg_harts_reset_delay - 1; @@ -277,7 +276,7 @@ module mkCoreW_reset #(Reset toDbgReset) // ================================================================ // Start the proc a suitable time after a PoR UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew - Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait); + Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait, reset_by porReset); rule rl_step_0 (rg_corew_start_after_por != 0); let n = rg_corew_start_after_por - 1; rg_corew_start_after_por <= n; @@ -288,8 +287,8 @@ module mkCoreW_reset #(Reset toDbgReset) // ================================================================ // Direct DM-to-CPU connections for run-control and other misc requests - mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server, reset_by toDbgReset); - mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req, reset_by toDbgReset); + mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server, reset_by porReset); + mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req, reset_by porReset); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -370,15 +369,15 @@ module mkCoreW_reset #(Reset toDbgReset) // BEGIN SECTION: DM, no TV // Connect DM's GPR interface directly to CPU - mkConnection (debug_module.harts_gpr_mem_client, proc.harts_gpr_mem_server, reset_by toDbgReset); + mkConnection (debug_module.harts_gpr_mem_client, proc.harts_gpr_mem_server, reset_by porReset); `ifdef ISA_F_OR_D // Connect DM's FPR interface directly to CPU - mkConnection (debug_module.harts_fpr_mem_client, proc.harts_fpr_mem_server, reset_by toDbgReset); + mkConnection (debug_module.harts_fpr_mem_client, proc.harts_fpr_mem_server, reset_by porReset); `endif // Connect DM's CSR interface directly to CPU - mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server, reset_by toDbgReset); + mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server, reset_by porReset); // DM's bus master is directly the bus master let dm_master_local = debug_module.master; @@ -460,7 +459,7 @@ module mkCoreW_reset #(Reset toDbgReset) // ================================================================ // Connect external debug module interface - let dbgShim <- mkAXI4LiteShim (reset_by toDbgReset); + let dbgShim <- mkAXI4LiteShim (reset_by porReset); rule rl_debug_module_read_req; let arFlit <- get (dbgShim.master.ar); @@ -477,9 +476,9 @@ module mkCoreW_reset #(Reset toDbgReset) debug_module.dmi.write (truncate (awFlit.awaddr >> 2), wFlit.wdata); endrule - let fromDbgReset <- mkPulseWire (reset_by toDbgReset); - Reg #(UInt #(8)) ndm_reset_delay <- mkReg (0, reset_by toDbgReset); - Reg #(Bool) ndm_reset_restart_running <- mkReg (False, reset_by toDbgReset); + let fromDbgReset <- mkPulseWire (reset_by porReset); + Reg #(UInt #(8)) ndm_reset_delay <- mkReg (0, reset_by porReset); + Reg #(Bool) ndm_reset_restart_running <- mkReg (False, reset_by porReset); rule rl_debug_module_send_reset (ndm_reset_delay == 0); let restartRunning <- debug_module.ndm_reset_client.request.get; ndm_reset_delay <= 110; From bb62b703c8c901f08ee30c55f09a400c72fb6a2e Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 30 Sep 2021 13:30:12 +0100 Subject: [PATCH 10/35] Address some rebase nonsense --- README.md | 2 +- src_Core/Core/CoreW.bsv | 30 ++++++++++++++++++++---------- src_SSITH_P3/src_BSV/P3_Core.bsv | 1 - src_Testbench/SoC/SoC_Top.bsv | 2 +- 4 files changed, 22 insertions(+), 13 deletions(-) diff --git a/README.md b/README.md index 72e657c..adbf59b 100644 --- a/README.md +++ b/README.md @@ -92,7 +92,7 @@ library RTL can be found in the directory `src_bsc_lib_RTL`. **Bluespec BSV** source code (which was used to generate the Verilog RTL) can be found in: - `src_Core/`, for the CPU core, with sub-directories: - - `Core/`: the top-level of the CPU Core (specifically, the files CoreW_IFC.bsv and CoreW.bsv) + - `Core/`: the top-level of the CPU Core (specifically, CoreW.bsv) - `CPU/`: more CPU core sources - `RISCY_OOO/`: the bulk of the code, taken from MIT's riscy-ooo design, with local modifications. - `ISA/`: generic types/constants/functions for the RISC-V ISA (not CPU-implementation-specific) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 8e3e844..00627f1 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -112,8 +112,10 @@ import DM_CPU_Req_Rsp ::*; // ================================================================ // The Core module -typedef WindCoreMid #( // AXI manager 0 port parameters - TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 +typedef WindCoreMid #( // AXI lite subordinate control port parameters + 21, 32, 0, 0, 0, 0, 0 + // AXI manager 0 port parameters + , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI manager 1 port parameters , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI subordinate 0 port parameters @@ -241,6 +243,13 @@ module mkCoreW_reset #(Reset porReset) TV_Encode_IFC tv_encode <- mkTV_Encode; `endif + function do_release (restartRunning) = action + plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base), + zeroExtend (rangeTop(soc_map.m_plic_addr_range))); + proc.start (restartRunning, soc_map_struct.pc_reset_value, 0, 0); + //proc.set_verbosity (verbosity); + endaction; + // ================================================================ // Hart-reset from DM @@ -485,6 +494,14 @@ module mkCoreW_reset #(Reset porReset) ndm_reset_restart_running <= restartRunning; fromDbgReset.send; endrule + rule rl_debug_module_count_reset_delay (ndm_reset_delay > 1); + ndm_reset_delay <= ndm_reset_delay - 1; + endrule + rule rl_debug_module_ack_reset (ndm_reset_delay == 1); + debug_module.ndm_reset_client.response.put (ndm_reset_restart_running); + do_release (ndm_reset_restart_running); + ndm_reset_delay <= 0; + endrule // ================================================================ // Connect external interrupts to the PLIC and Proc @@ -517,16 +534,9 @@ module mkCoreW_reset #(Reset porReset) let f_ctrl_reqs <- mkFIFO1; let f_ctrl_rsps <- mkFIFO1; - function do_release = action - plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base), - zeroExtend (rangeTop(soc_map.m_plic_addr_range))); - proc.start (True, soc_map_struct.pc_reset_value, 0, 0); - //proc.set_verbosity (verbosity); - endaction; - rule rl_ctrl_req; case (f_ctrl_reqs.first) matches - tagged ReleaseReq: do_release; + tagged ReleaseReq: do_release (False); tagged StatusReq: $display ("StatusReq not supported in Toooba"); endcase f_ctrl_reqs.deq; diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index ef5be3e..6567511 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -44,7 +44,6 @@ import Fabric_Defs :: *; import PowerOnReset :: *; // The basic core -import CoreW_IFC :: *; import CoreW :: *; // External interrupt request interface diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index daf6de8..414c3a7 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -59,7 +59,7 @@ import SoC_Map :: *; import WindCoreInterface :: *; import CoreW :: *; -import PLIC :: *; // For interface to PLIC interrupt sources, in CoreW_IFC +import PLIC :: *; import Boot_ROM :: *; import Mem_Controller :: *; From e4bdbfc98ac09eef750408b672ea6845526f8b23 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Sat, 2 Oct 2021 17:29:10 +0100 Subject: [PATCH 11/35] Bump BlueStuff + add outter subordinate trafic as master to internal bus --- libs/BlueStuff | 2 +- libs/TagController | 2 +- libs/WindCoreInterface | 2 +- libs/cheri-cap-lib | 2 +- src_Core/CPU/MMIO_AXI4_Adapter.bsv | 12 +-- src_Core/CPU/Proc_IFC.bsv | 12 +-- src_Core/Core/CoreW.bsv | 75 ++++++++++++------- src_Core/Core/Fabric_Defs.bsv | 16 ++-- src_Core/Debug_Module/DM_System_Bus.bsv | 12 +-- src_Core/Debug_Module/Debug_Module.bsv | 6 +- src_Core/PLIC/PLIC.bsv | 4 +- .../RISCY_OOO/procs/lib/LLCDmaConnect.bsv | 17 ++--- 12 files changed, 89 insertions(+), 73 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 8a36aa9..7e3686c 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 8a36aa9af4d35851053b6f474b959a340e9a72c7 +Subproject commit 7e3686c5dc361a7125e859cf60c609596a1a9b83 diff --git a/libs/TagController b/libs/TagController index 2e2198b..99c43e8 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 2e2198b05f3c7cea61d690e3aa438211d0de9e8d +Subproject commit 99c43e81384741ae11e098a63514a78bd43637e2 diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 237f28e..946b4ec 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 237f28e3e4c3ea51d4b93476246cf8880f660d36 +Subproject commit 946b4ecc178a5a3ccade790765c53dcb18db386e diff --git a/libs/cheri-cap-lib b/libs/cheri-cap-lib index b80c1b3..806b687 160000 --- a/libs/cheri-cap-lib +++ b/libs/cheri-cap-lib @@ -1 +1 @@ -Subproject commit b80c1b3c5977b3aad0cf38125788566458e01493 +Subproject commit 806b687e8a7613f68151032965349b164b34713e diff --git a/src_Core/CPU/MMIO_AXI4_Adapter.bsv b/src_Core/CPU/MMIO_AXI4_Adapter.bsv index 633f61b..694c637 100644 --- a/src_Core/CPU/MMIO_AXI4_Adapter.bsv +++ b/src_Core/CPU/MMIO_AXI4_Adapter.bsv @@ -66,9 +66,9 @@ interface MMIO_AXI4_Adapter_IFC; interface Server #(MMIOCRq, MMIODataPRs) core_side; // Fabric master interface for IO - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) mmio_master; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) mmio_master; endinterface // ================================================================ @@ -127,7 +127,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC); // necessary; the AXI4 fabric should return a DECERR for illegal // addrs; but not all AXI4 fabrics do the right thing. if (soc_map.m_is_IO_addr (req.addr, False)) begin - let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_2x3_default_mid, + let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_corew_bus_default_mid, araddr: req.addr, arlen: (burst) ? 1:0, // burst len = arlen+1 arsize: size, @@ -220,8 +220,8 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC); // on first flit... // ================ if (first) begin - AXI4_AWFlit #(Wd_MId_2x3, Wd_Addr, Wd_AW_User) - mem_req_wr_addr = AXI4_AWFlit {awid: fabric_2x3_default_mid, + AXI4_AWFlit #(Wd_CoreW_Bus_MId, Wd_Addr, Wd_AW_User) + mem_req_wr_addr = AXI4_AWFlit {awid: fabric_corew_bus_default_mid, awaddr: req.addr, awlen: (burst) ? 1:0, // burst len = awlen+1 awsize: size, diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 2aaedd0..4b2697f 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -72,9 +72,9 @@ interface Proc_IFC; Wd_AR_User, Wd_R_User) master0; // Fabric master interface for IO (from MMIOPlatform) - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master1; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) master1; // ---------------- // External interrupts @@ -99,9 +99,9 @@ interface Proc_IFC; // ---------------- // Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory) - interface AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) debug_module_mem_server; + interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) debug_module_mem_server; `ifdef RVFI_DII interface Toooba_RVFI_DII_Server rvfi_dii_server; diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 00627f1..5431624 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -115,11 +115,11 @@ import DM_CPU_Req_Rsp ::*; typedef WindCoreMid #( // AXI lite subordinate control port parameters 21, 32, 0, 0, 0, 0, 0 // AXI manager 0 port parameters - , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI manager 1 port parameters - , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 + , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI subordinate 0 port parameters - , 0, 0, 0, 0, 0, 0, 0, 0 + , 4, 32, 128, 0, 0, 0, 0, 0 // Number of interrupt lines , t_n_irq) CoreW_IFC #(numeric type t_n_irq); @@ -200,14 +200,16 @@ module mkCoreW_reset #(Reset porReset) Proc_IFC proc <- mkProc (reset_by all_harts_reset); // handle uncached interface - let proc_uncached = prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); + let proc_uncached = + prepend_AXI4_Master_id (0, zero_AXI4_Master_user (proc.master1)); // Bridge for uncached expernal bus transactions. let uncached_mem_shim <- mkAXI4ShimFF(reset_by all_harts_reset); // handle cached interface // AXI4 tagController - TagControllerAXI#(Wd_MId, Wd_Addr, Wd_Data) tagController <- mkTagControllerAXI(reset_by all_harts_reset); // TODO double check if reseting like this is good enough - mkConnection(proc.master0, tagController.slave, reset_by all_harts_reset); + TagControllerAXI #(Wd_MId, Wd_Addr, Wd_Data) + tagController <- mkTagControllerAXI (reset_by all_harts_reset); // TODO double check if reseting like this is good enough + mkConnection (proc.master0, tagController.slave, reset_by all_harts_reset); `ifdef PERFORMANCE_MONITORING rule report_tagController_events; EventsCacheCore cache_core_evts = tagController.events; @@ -412,30 +414,44 @@ module mkCoreW_reset #(Reset porReset) // ================================================================ - // Connect the local 2x3 fabric + // new internal AXI4 manager from interace subordinate port + AXI4_Shim #(4, 32, Wd_Data, 0, 0, 0, 0, 0) + subShim <- mkAXI4Shim; + AXI4_Slave #( 4, 32, 128, 0, 0, 0, 0, 0) + outerSubIfc <- toWider_AXI4_Slave (subShim.slave); + AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) innerSubIfc = + prepend_AXI4_Master_addr (0 , zero_AXI4_Master_user (subShim.master)); - // Masters on the local 2x3 fabric - Vector#(Num_Masters_2x3, AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User)) - master_vector = newVector; + // ================================================================ + // Connect the local bus + + // Masters on the local bus + Vector #( CoreW_Bus_Num_Masters + , AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User)) + master_vector = newVector; //let master_vector = newVector; master_vector[cpu_uncached_master_num] = proc_uncached; master_vector[debug_module_sba_master_num] = dm_master_local; + master_vector[sub_ifc_master_num] = innerSubIfc; - // Slaves on the local 2x3 fabric + // Slaves on the local bus // default slave is forwarded out directly to the Core interface - Vector#(Num_Slaves_2x3, AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User)) - slave_vector = newVector; + Vector #( CoreW_Bus_Num_Slaves + , AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User)) + slave_vector = newVector; //let slave_vector = newVector; slave_vector[default_slave_num] = uncached_mem_shim.slave; slave_vector[llc_slave_num] = proc.debug_module_mem_server; slave_vector[plic_slave_num] = zero_AXI4_Slave_user (plic.axi4_slave); - function Vector#(Num_Slaves_2x3, Bool) route_2x3 (Bit#(Wd_Addr) addr); - Vector#(Num_Slaves_2x3, Bool) res = replicate(False); + function Vector #(CoreW_Bus_Num_Slaves, Bool) route (Bit #(Wd_Addr) addr); + Vector #(CoreW_Bus_Num_Slaves, Bool) res = replicate(False); if (inRange(soc_map.m_mem0_controller_addr_range, addr)) res[llc_slave_num] = True; else if (inRange(soc_map.m_plic_addr_range, addr)) @@ -447,7 +463,7 @@ module mkCoreW_reset #(Reset porReset) return res; endfunction - mkAXI4Bus (route_2x3, master_vector, slave_vector, reset_by all_harts_reset); + mkAXI4Bus (route, master_vector, slave_vector, reset_by all_harts_reset); // ================================================================ // Connect external interrupt lines from PLIC to CPU @@ -568,10 +584,10 @@ module mkCoreW_reset #(Reset porReset) // Cached master to Fabric master interface interface manager_0 = tagController.master; // Uncached master to Fabric master interface - interface manager_1 = - extendIDFields (zeroMasterUserFields (uncached_mem_shim.master), 0); + interface manager_1 = prepend_AXI4_Master_id + (0, zero_AXI4_Master_user (uncached_mem_shim.master)); // TODO: - interface subordinate_0 = culDeSac; + interface subordinate_0 = outerSubIfc; endinterface; /* @@ -596,21 +612,22 @@ module mkCoreW_reset #(Reset porReset) endmodule: mkCoreW_reset // ================================================================ -// 2x3 Fabric for this Core +// internal bus for this Core // Masters: CPU DMem, Debug Module System Bus Access, External access // ---------------- // Fabric port numbers for masters -Master_Num_2x3 cpu_uncached_master_num = 0; -Master_Num_2x3 debug_module_sba_master_num = 1; +CoreW_Bus_Master_Num cpu_uncached_master_num = 0; +CoreW_Bus_Master_Num debug_module_sba_master_num = 1; +CoreW_Bus_Master_Num sub_ifc_master_num = 2; // ---------------- // Fabric port numbers for slaves -Slave_Num_2x3 default_slave_num = 0; // for I/O, uncached memory, etc. -Slave_Num_2x3 plic_slave_num = 1; // PLIC mem-mapped registers -Slave_Num_2x3 llc_slave_num = 2; // Normal cached memory (connects to coherent Last-Level Cache) +CoreW_Bus_Slave_Num default_slave_num = 0; // for I/O, uncached memory, etc. +CoreW_Bus_Slave_Num plic_slave_num = 1; // PLIC mem-mapped registers +CoreW_Bus_Slave_Num llc_slave_num = 2; // Normal cached memory (connects to coherent Last-Level Cache) // ================================================================ diff --git a/src_Core/Core/Fabric_Defs.bsv b/src_Core/Core/Fabric_Defs.bsv index c9cdb1a..9443091 100644 --- a/src_Core/Core/Fabric_Defs.bsv +++ b/src_Core/Core/Fabric_Defs.bsv @@ -35,17 +35,17 @@ import ISA_Decls_CHERI :: *; // ================================================================ // Core local Fabric parameters -typedef 2 Num_Masters_2x3; -typedef 3 Num_Slaves_2x3; +typedef 3 CoreW_Bus_Num_Masters; +typedef 3 CoreW_Bus_Num_Slaves; -typedef Bit#(TLog #(Num_Masters_2x3)) Master_Num_2x3; -typedef Bit#(TLog #(Num_Slaves_2x3)) Slave_Num_2x3; +typedef Bit#(TLog #(CoreW_Bus_Num_Masters)) CoreW_Bus_Master_Num; +typedef Bit#(TLog #(CoreW_Bus_Num_Slaves)) CoreW_Bus_Slave_Num; // ---------------- // Width of fabric 'Id' buses -typedef 4 Wd_MId_2x3; -typedef TAdd#(Wd_MId_2x3, TLog#(Num_Masters_2x3)) Wd_SId_2x3; -typedef Wd_SId_2x3 Wd_MId; +typedef 4 Wd_CoreW_Bus_MId; +typedef TAdd#(Wd_CoreW_Bus_MId, TLog#(CoreW_Bus_Num_Masters)) Wd_CoreW_Bus_SId; +typedef Wd_CoreW_Bus_SId Wd_MId; // ---------------- // Width of fabric 'addr' buses @@ -104,7 +104,7 @@ Integer zlsbs_aligned_fabric_addr = valueOf (ZLSBs_Aligned_Fabric_Addr); // ================================================================ // AXI4 defaults for this project -Bit#(Wd_MId_2x3) fabric_2x3_default_mid = 0; +Bit#(Wd_CoreW_Bus_MId) fabric_corew_bus_default_mid = 0; Bit#(Wd_MId) fabric_default_mid = 0; AXI4_Burst fabric_default_burst = INCR; AXI4_Lock fabric_default_lock = NORMAL; diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index 08417d2..be7a24a 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -54,9 +54,9 @@ interface DM_System_Bus_IFC; // ---------------- // Facing System - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ @@ -283,7 +283,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); function Action fa_fabric_send_read_req (Bit #(64) addr64); action Fabric_Addr fabric_addr = truncate (addr64); - let rda = AXI4_ARFlit {arid: fabric_2x3_default_mid, + let rda = AXI4_ARFlit {arid: fabric_corew_bus_default_mid, araddr: fabric_addr, arlen: 0, // burst len = arlen+1 arsize: fn_DM_sbaccess_to_AXI4_Size (rg_sbcs_sbaccess), @@ -318,13 +318,13 @@ module mkDM_System_Bus (DM_System_Bus_IFC); .fabric_data, .fabric_strb, .fabric_size} = fn_to_fabric_write_fields (rg_sbcs_sbaccess, sbaddress, data64); - + // fabric_addr is always fabric-data-width aligned // fabric_data is properly lane-adjusted // fabric_strb identifies the lanes to be written // awsize is always the fabric width - let wra = AXI4_AWFlit {awid: fabric_2x3_default_mid, + let wra = AXI4_AWFlit {awid: fabric_corew_bus_default_mid, awaddr: fabric_addr, awlen: 0, // burst len = awlen+1 awsize: fabric_size, diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 9c17d71..90f1981 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -136,9 +136,9 @@ interface Debug_Module_IFC; interface Client #(Bool, Bool) ndm_reset_client; // Read/Write RISC-V memory - interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master; + interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ diff --git a/src_Core/PLIC/PLIC.bsv b/src_Core/PLIC/PLIC.bsv index 6dc3da9..95670d9 100644 --- a/src_Core/PLIC/PLIC.bsv +++ b/src_Core/PLIC/PLIC.bsv @@ -98,8 +98,8 @@ interface PLIC_IFC #(numeric type t_n_external_sources, method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim); // Memory-mapped access - interface AXI4_Slave #( Wd_SId_2x3, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) - axi4_slave; + interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , 0, 0, 0, 0, 0) axi4_slave; // sources interface Vector #(t_n_external_sources, PLIC_Source_IFC) v_sources; diff --git a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv index 916c602..0c9d13f 100644 --- a/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv +++ b/src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv @@ -127,15 +127,14 @@ endfunction // ================================================================ -module mkLLCDmaConnect #( - DmaServer#(LLCDmaReqId) llc, - // MemLoaderMemClient memLoader, // REPLACED BY AXI4_Slave_interface - Vector#(CoreNum, TlbMemClient) tlb -)(AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User)) provisos ( - Alias#(dmaRqT, DmaRq#(LLCDmaReqId)) -); +module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc + // REPLACED BY AXI4_Slave_interface + //, MemLoaderMemClient memLoader + , Vector#(CoreNum, TlbMemClient) tlb ) + (AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User)) + provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId))); Bool verbose = False; Integer verbosity = 0; From 47930189da9c31689974fff67a4a2c56e880f23a Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Sun, 3 Oct 2021 14:26:05 +0100 Subject: [PATCH 12/35] Bump BlueStuff + assume external subordinate_0 parameters that match internal bus --- src_Core/Core/CoreW.bsv | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index 5431624..da92cda 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -119,7 +119,9 @@ typedef WindCoreMid #( // AXI lite subordinate control port parameters // AXI manager 1 port parameters , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0 // AXI subordinate 0 port parameters - , 4, 32, 128, 0, 0, 0, 0, 0 + , Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data + , Wd_AW_User, Wd_W_User, Wd_B_User + , Wd_AR_User, Wd_R_User // Number of interrupt lines , t_n_irq) CoreW_IFC #(numeric type t_n_irq); @@ -415,14 +417,7 @@ module mkCoreW_reset #(Reset porReset) // ================================================================ // new internal AXI4 manager from interace subordinate port - AXI4_Shim #(4, 32, Wd_Data, 0, 0, 0, 0, 0) - subShim <- mkAXI4Shim; - AXI4_Slave #( 4, 32, 128, 0, 0, 0, 0, 0) - outerSubIfc <- toWider_AXI4_Slave (subShim.slave); - AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data - , Wd_AW_User, Wd_W_User, Wd_B_User - , Wd_AR_User, Wd_R_User) innerSubIfc = - prepend_AXI4_Master_addr (0 , zero_AXI4_Master_user (subShim.master)); + let subShim <- mkAXI4Shim; // ================================================================ // Connect the local bus @@ -436,7 +431,7 @@ module mkCoreW_reset #(Reset porReset) //let master_vector = newVector; master_vector[cpu_uncached_master_num] = proc_uncached; master_vector[debug_module_sba_master_num] = dm_master_local; - master_vector[sub_ifc_master_num] = innerSubIfc; + master_vector[sub_ifc_master_num] = subShim.master; // Slaves on the local bus // default slave is forwarded out directly to the Core interface @@ -586,8 +581,7 @@ module mkCoreW_reset #(Reset porReset) // Uncached master to Fabric master interface interface manager_1 = prepend_AXI4_Master_id (0, zero_AXI4_Master_user (uncached_mem_shim.master)); - // TODO: - interface subordinate_0 = outerSubIfc; + interface subordinate_0 = subShim.slave; endinterface; /* From f292c5196d32951a7773d6e263c63d8db6e2227c Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Mon, 11 Oct 2021 12:03:47 +0100 Subject: [PATCH 13/35] Rename master_xactor to axiShim in DM_System_Bus --- src_Core/Debug_Module/DM_System_Bus.bsv | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index be7a24a..bf77653 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -197,8 +197,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------------------------------------------------------- // Interface to memory fabric - let master_xactor <- mkAXI4ShimFF; - + let axiShim <- mkAXI4ShimFF; // ---------------------------------------------------------------- // System Bus state @@ -294,7 +293,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); arqos: fabric_default_qos, arregion: fabric_default_region, aruser: fabric_default_aruser}; - master_xactor.slave.ar.put(rda); + axiShim.slave.ar.put(rda); // Save read-address for byte-lane extraction from later response // (since rg_sbaddress may be incremented by then). @@ -335,13 +334,13 @@ module mkDM_System_Bus (DM_System_Bus_IFC); awqos: fabric_default_qos, awregion: fabric_default_region, awuser: fabric_default_awuser}; - master_xactor.slave.aw.put(wra); + axiShim.slave.aw.put(wra); let wrd = AXI4_WFlit {wdata: fabric_data, wstrb: fabric_strb, wlast: True, wuser: fabric_default_wuser}; - master_xactor.slave.w.put(wrd); + axiShim.slave.w.put(wrd); if (verbosity != 0) begin $display (" DM_System_Bus.fa_fabric_send_write_req:"); @@ -507,7 +506,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); (* descending_urgency = "rl_sb_read_finish, write" *) rule rl_sb_read_finish ( (rg_sb_state == SB_READ_FINISH) && (rg_sbcs_sberror == DM_SBERROR_NONE)); - let rdr <- get(master_xactor.slave.r); + let rdr <- get(axiShim.slave.r); if (verbosity != 0) $display ("DM_System_Bus.rule_sb_read_finish: rdr = ", fshow (rdr)); @@ -588,7 +587,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // Consume write-responses rule rl_sb_write_response; - let wrr <- get(master_xactor.slave.b); + let wrr <- get(axiShim.slave.b); if (wrr.bresp != OKAY) rg_sbcs_sberror <= DM_SBERROR_OTHER; endrule @@ -597,7 +596,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // INTERFACE method Action reset; - master_xactor.clear; + axiShim.clear; rg_sb_state <= SB_NOTBUSY; @@ -678,7 +677,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------- // Facing System - interface master = master_xactor.master; + interface master = axiShim.master; endmodule // ================================================================ From 947cf8ed7b7d336aaa8124b841a2af0ea7daccc7 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Mon, 11 Oct 2021 12:30:35 +0100 Subject: [PATCH 14/35] NonPipelined API update --- src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/Fpu.bsv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv index e93e1f1..ed8587e 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv @@ -75,7 +75,7 @@ module mkIntDivUnsignedSim(IntDivUnsignedImport); FIFO#(IntDivUser) userFF <- mkFIFO; Server#(Tuple2#(UInt#(128),UInt#(64)),Tuple2#(UInt#(64),UInt#(64))) - nonpipediv <- mkNonPipelinedDividerBlah (4); + nonpipediv <- mkNonPipelinedDivider (4); rule compute; dividendQ.deq; diff --git a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv index 95b478a..fd61e18 100644 --- a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv @@ -97,7 +97,7 @@ module mkDoubleDiv(Server#(Tuple3#(Double, Double, FpuRoundMode), Tuple2#(Double let fpu <- mkXilinxFpDiv; `else //let int_div <- mkDivider(1); // [sizhuo] size in RVFpu: 2 - let int_div <- mkNonPipelinedDividerBlah(3); + let int_div <- mkNonPipelinedDivider(3); let fpu <- mkFloatingPointDivider(int_div); `endif return fpu; From 26fd0e5849b1d55605c91af1c5b8ebec22b1d361 Mon Sep 17 00:00:00 2001 From: gameboo Date: Mon, 21 Feb 2022 20:02:07 +0000 Subject: [PATCH 15/35] Bump BlueStuff + TagController + BSV-RVFI-DII --- libs/BlueStuff | 2 +- libs/TagController | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 7e3686c..75b798d 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 7e3686c5dc361a7125e859cf60c609596a1a9b83 +Subproject commit 75b798dcb50870b7e934687c880531c54c652a37 diff --git a/libs/TagController b/libs/TagController index 99c43e8..2e2198b 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 99c43e81384741ae11e098a63514a78bd43637e2 +Subproject commit 2e2198b05f3c7cea61d690e3aa438211d0de9e8d From effbbff97886206e475e3abbf1bc6552a5ba8f2d Mon Sep 17 00:00:00 2001 From: gameboo Date: Thu, 31 Mar 2022 09:44:18 +0000 Subject: [PATCH 16/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 75b798d..8041329 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 75b798dcb50870b7e934687c880531c54c652a37 +Subproject commit 8041329c831a35cdc083400b5ed55277a63af7c3 From 33313901fa376af32f7a44a4116fdfb21c095f31 Mon Sep 17 00:00:00 2001 From: gameboo Date: Thu, 12 May 2022 10:48:33 +0000 Subject: [PATCH 17/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 8041329..c8be83d 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 8041329c831a35cdc083400b5ed55277a63af7c3 +Subproject commit c8be83d4c6ad6e914c3c760eb3391d0f50d9c7be From 6b51139c9ac4a2e898e74d098ff18467f9f25b50 Mon Sep 17 00:00:00 2001 From: gameboo Date: Wed, 18 May 2022 10:39:44 +0000 Subject: [PATCH 18/35] Update ack --- src_Core/CPU/Proc_IFC.bsv | 9 ++++++++- src_Core/Core/CoreW.bsv | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index 4b2697f..abadfba 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -2,7 +2,7 @@ // //- // RVFI_DII + CHERI modifications: -// Copyright (c) 2020 Alexandre Joannou +// Copyright (c) 2020-2022 Alexandre Joannou // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff // All rights reserved. @@ -13,6 +13,13 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// +// This material is based upon work supported by the DoD Information Analysis +// Center Program Management Office (DoD IAC PMO), sponsored by the Defense +// Technical Information Center (DTIC) under Contract No. FA807518D0004. Any +// opinions, findings and conclusions or recommendations expressed in this +// material are those of the author(s) and do not necessarily reflect the views +// of the Air Force Installation Contracting Agency (AFICA). //- package Proc_IFC; diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index da92cda..d6379ac 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -2,7 +2,7 @@ // //- // RVFI_DII + CHERI modifications: -// Copyright (c) 2020 Alexandre Joannou +// Copyright (c) 2020-2022 Alexandre Joannou // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff // All rights reserved. @@ -13,6 +13,13 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// +// This material is based upon work supported by the DoD Information Analysis +// Center Program Management Office (DoD IAC PMO), sponsored by the Defense +// Technical Information Center (DTIC) under Contract No. FA807518D0004. Any +// opinions, findings and conclusions or recommendations expressed in this +// material are those of the author(s) and do not necessarily reflect the views +// of the Air Force Installation Contracting Agency (AFICA). //- package CoreW; From eefb6c73a159402f72ae5b1d917d38d19ff1e66f Mon Sep 17 00:00:00 2001 From: gameboo Date: Fri, 20 May 2022 09:41:25 +0000 Subject: [PATCH 19/35] Bump BlueStuff and WindCoreInterface --- libs/BlueStuff | 2 +- libs/WindCoreInterface | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index c8be83d..2ffca0b 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit c8be83d4c6ad6e914c3c760eb3391d0f50d9c7be +Subproject commit 2ffca0b2ab20c997d78db7eee9e46f96d5b42a57 diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 946b4ec..81fc7b1 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 946b4ecc178a5a3ccade790765c53dcb18db386e +Subproject commit 81fc7b1512c9a7374285168551a34226456c7c5e From 1d8635f86d52c349a9311543150054c57fa5e30d Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Tue, 28 Jun 2022 11:30:23 +0000 Subject: [PATCH 20/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 2ffca0b..a39795a 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 2ffca0b2ab20c997d78db7eee9e46f96d5b42a57 +Subproject commit a39795a53fac479898e0ecadbc8dd16b668dd20f From e4349261902c57862e0e1fee72899c3d2f0361d7 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Tue, 28 Jun 2022 12:35:30 +0000 Subject: [PATCH 21/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index a39795a..2eca2c2 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit a39795a53fac479898e0ecadbc8dd16b668dd20f +Subproject commit 2eca2c23dc38150f0159cc8e575043cb911a3cf8 From 250d8b5fe0b38e80b589191a83a6f9288f0478d7 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Tue, 28 Jun 2022 16:12:26 +0000 Subject: [PATCH 22/35] Bump submodule. --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 2eca2c2..01b0b5d 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 2eca2c23dc38150f0159cc8e575043cb911a3cf8 +Subproject commit 01b0b5d3a45665e0e39a4631d205bc270e36789a From a4902d842838760e000ebc072025e7ced7cdd79a Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Wed, 29 Jun 2022 15:29:34 +0000 Subject: [PATCH 23/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 01b0b5d..8e5f9bc 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 01b0b5d3a45665e0e39a4631d205bc270e36789a +Subproject commit 8e5f9bc3b3759a00777a6915b5b7871d50d2e8d6 From 77825f5a6ba9b6a31492dd0590172d6dcb16ea1a Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Wed, 29 Jun 2022 16:21:52 +0000 Subject: [PATCH 24/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 8e5f9bc..c2cae9e 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 8e5f9bc3b3759a00777a6915b5b7871d50d2e8d6 +Subproject commit c2cae9ea3ba3f3a99f462e11cef9cde85616f5c4 From 3e1efcc5d975d8c47b5ed20ba4a2b4d6e2a13a1b Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Sat, 9 Jul 2022 13:13:30 +0000 Subject: [PATCH 25/35] Bump BlueStuff TagController WindCoreInterface --- builds/Resources/Include_Common.mk | 7 ++++++- libs/BlueStuff | 2 +- libs/TagController | 2 +- libs/WindCoreInterface | 2 +- 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index 29462d5..19a5fec 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -54,7 +54,12 @@ CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/Core:$(RE TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC -BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueUtils:$(REPO)/libs/BlueStuff/BlueBasics +BLUESTUFFDIR = $(REPO)/libs/BlueStuff +BLUEAXI4DIR = $(BLUESTUFFDIR)/BlueAXI4 +BLUEAXI4DIRS = $(BLUEAXI4DIR):$(BLUEAXI4DIR)/AXI4:$(BLUEAXI4DIR)/AXI4Lite:$(BLUEAXI4DIR)/AXI4Stream:$(BLUEAXI4DIR)/BlueUnixBridges +BLUEBASICSDIR = $(BLUESTUFFDIR)/BlueBasics +BLUEUTILSDIR = $(BLUESTUFFDIR)/BlueUtils +BLUESTUFF_DIRS = $(BLUESTUFFDIR):$(BLUEAXI4DIRS):$(BLUEBASICSDIR):$(BLUEUTILSDIR) WINDCOREIFC_DIRS = $(REPO)/libs/WindCoreInterface diff --git a/libs/BlueStuff b/libs/BlueStuff index c2cae9e..fbd3b9f 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit c2cae9ea3ba3f3a99f462e11cef9cde85616f5c4 +Subproject commit fbd3b9fc685b0e898dde49fb9d8e54d43d9c5e20 diff --git a/libs/TagController b/libs/TagController index 2e2198b..a64b2c8 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 2e2198b05f3c7cea61d690e3aa438211d0de9e8d +Subproject commit a64b2c89252775672e198e89005977dcc25bd1b4 diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 81fc7b1..3845af2 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 81fc7b1512c9a7374285168551a34226456c7c5e +Subproject commit 3845af2b14cd5cd29b220c3e82f77165b0319226 From 59570a4c4317d551cde58507d4e6053f10a43c9c Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Mon, 11 Jul 2022 08:35:18 +0000 Subject: [PATCH 26/35] Bump BlueStuff + TagController + WindCoreInterface --- libs/BlueStuff | 2 +- libs/TagController | 2 +- libs/WindCoreInterface | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index fbd3b9f..f368a0b 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit fbd3b9fc685b0e898dde49fb9d8e54d43d9c5e20 +Subproject commit f368a0ba7f12eb7898d802151c15c4b66019fbe1 diff --git a/libs/TagController b/libs/TagController index a64b2c8..0a70b2f 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit a64b2c89252775672e198e89005977dcc25bd1b4 +Subproject commit 0a70b2f8124e903af8d89a1c5bced7429736aba9 diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 3845af2..6a0c7c6 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 3845af2b14cd5cd29b220c3e82f77165b0319226 +Subproject commit 6a0c7c6c2c433f83270d9f64df196744297fa486 From e6567e20e8a71eaaaa55e7f5b0100077716865ff Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 14 Jul 2022 10:49:39 +0100 Subject: [PATCH 27/35] Bump TagController --- libs/TagController | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/TagController b/libs/TagController index 0a70b2f..a64b2c8 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 0a70b2f8124e903af8d89a1c5bced7429736aba9 +Subproject commit a64b2c89252775672e198e89005977dcc25bd1b4 From f6290abdc97d91bcc744201ca8cfcfbc391b9d44 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 14 Jul 2022 17:02:27 +0100 Subject: [PATCH 28/35] Bump BlueStuff + TagController + WindCoreInterface --- libs/BlueStuff | 2 +- libs/TagController | 2 +- libs/WindCoreInterface | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index f368a0b..7132fdc 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit f368a0ba7f12eb7898d802151c15c4b66019fbe1 +Subproject commit 7132fdc5dd0d2f1dba967ccba56d51ca87cd3652 diff --git a/libs/TagController b/libs/TagController index a64b2c8..801dc98 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit a64b2c89252775672e198e89005977dcc25bd1b4 +Subproject commit 801dc98c360335b058e66c8a88848d78ba213ec8 diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 6a0c7c6..0cd8357 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 6a0c7c6c2c433f83270d9f64df196744297fa486 +Subproject commit 0cd835731fa584ac8e894e45b75cceb154258b1b From 0cf1f0de6edd65b9da01f1a371be86e55d5dd741 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Fri, 15 Jul 2022 14:04:55 +0100 Subject: [PATCH 29/35] Bump BlueStuff + TagController + WindCoreInterface --- libs/BlueStuff | 2 +- libs/TagController | 2 +- libs/WindCoreInterface | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 7132fdc..30d2b89 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 7132fdc5dd0d2f1dba967ccba56d51ca87cd3652 +Subproject commit 30d2b89d9a03896b686a3de5835270795be79124 diff --git a/libs/TagController b/libs/TagController index 801dc98..0af8406 160000 --- a/libs/TagController +++ b/libs/TagController @@ -1 +1 @@ -Subproject commit 801dc98c360335b058e66c8a88848d78ba213ec8 +Subproject commit 0af8406ac66734e4bac4f55904a47dd9dbd4163d diff --git a/libs/WindCoreInterface b/libs/WindCoreInterface index 0cd8357..5af81c8 160000 --- a/libs/WindCoreInterface +++ b/libs/WindCoreInterface @@ -1 +1 @@ -Subproject commit 0cd835731fa584ac8e894e45b75cceb154258b1b +Subproject commit 5af81c8abb25fb81b6cfb56b8ce9562c42eae0a4 From 1fceb8fa72e5113f77f16df28d9034cd17015ef9 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Mon, 25 Jul 2022 11:27:55 +0000 Subject: [PATCH 30/35] Use standard imports as the fixes have been upstreamed. --- src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv | 2 +- src_Core/RISCY_OOO/procs/lib/Fpu.bsv | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv index ed8587e..14d690f 100644 --- a/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv +++ b/src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv @@ -2,7 +2,7 @@ import FIFOF::*; import FIFO::*; import WaitAutoReset::*; -import NonPipelinedMath::*; +import Divide::*; import ClientServer::*; import GetPut::*; diff --git a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv index fd61e18..37e72f0 100644 --- a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv @@ -48,9 +48,8 @@ import FIFO::*; import FIFOF::*; import ClientServer::*; import GetPut::*; -//import Divide::*; -//import SquareRoot::*; -import NonPipelinedMath :: *; +import Divide::*; +import SquareRoot::*; import FloatingPoint::*; import XilinxFpu::*; import HasSpecBits::*; From d7d5446e98e6299c2df4857b11ee87d4d3881a75 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Tue, 2 Aug 2022 10:24:08 +0000 Subject: [PATCH 31/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 30d2b89..16fb83a 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 30d2b89d9a03896b686a3de5835270795be79124 +Subproject commit 16fb83a5c5dcaf1db06bd302da139f17f41bb859 From d82fd285681ca2a459f68e3fccb6f94a601fccb0 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 4 Aug 2022 20:51:10 +0000 Subject: [PATCH 32/35] Bump BlueStuff --- libs/BlueStuff | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/BlueStuff b/libs/BlueStuff index 16fb83a..ea96432 160000 --- a/libs/BlueStuff +++ b/libs/BlueStuff @@ -1 +1 @@ -Subproject commit 16fb83a5c5dcaf1db06bd302da139f17f41bb859 +Subproject commit ea96432eb287a9397dd38636c35e2fac619d5eb8 From a4606c6761fad63525a8c87a1270e5aa9efb8469 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Mon, 15 Aug 2022 16:16:53 +0000 Subject: [PATCH 33/35] Brought the src_SSITH_P3 folder up to date --- src_SSITH_P3/Makefile | 59 ++++++++------- src_SSITH_P3/src_BSV/Giraffe_IFC.bsv | 4 +- src_SSITH_P3/src_BSV/P3_Core.bsv | 106 +++++++++------------------ 3 files changed, 65 insertions(+), 104 deletions(-) diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile index 6715293..4df6e47 100644 --- a/src_SSITH_P3/Makefile +++ b/src_SSITH_P3/Makefile @@ -16,7 +16,7 @@ compile: compile_sim compile_synth # ================================================================ -REPO ?= .. +REPO ?= $(CURDIR)/.. ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ @@ -29,7 +29,7 @@ BSC_COMPILATION_FLAGS += \ -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \ -D CheriBusBytes=8 \ -D CheriMasterIDWidth=1 \ - -D CheriTransactionIDWidth=5 \ + -D CheriTransactionIDWidth=6 \ -D PERFORMANCE_MONITORING \ -D SHIFT_BARREL \ -D MULT_SERIAL \ @@ -62,33 +62,32 @@ CORE_NUM = 2 include $(REPO)/builds/Resources/Include_RISCY_Config.mk -# ================================================================ -# Path to RISCY-OOO sources - -RISCY_HOME ?= ../src_Core/RISCY_OOO - -RISCY_DIRS = $(RISCY_HOME)/procs/RV64G_OOO:$(RISCY_HOME)/procs/lib:$(RISCY_HOME)/coherence/src:$(RISCY_HOME)/fpgautils/lib - -CONNECTAL_DIRS = $(RISCY_HOME)/connectal/bsv:$(RISCY_HOME)/connectal/tests/spi:$(RISCY_HOME)/connectal/lib/bsv - -CHERI_DIRS = $(RISCY_HOME)/../../libs/cheri-cap-lib - -# ALL_RISCY_DIRS = $(RISCY_DIRS) -ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS) - # ================================================================ # Search path for bsc for .bsv files +COREDIR ?= $(REPO) +COREW_DIRS = $(CURDIR)/src_BSV:$(COREDIR)/src_Core/Core:$(COREDIR)/src_Core/CPU:$(COREDIR)/src_Core/ISA:$(COREDIR)/src_Core/PLIC:$(COREDIR)/src_Core/Debug_Module:$(COREDIR)/src_Core/BSV_Additional_Libs:$(COREDIR)/src_Core/RISCY_OOO/procs/RV64G_OOO:$(COREDIR)/src_Core/RISCY_OOO/procs/lib:$(COREDIR)/src_Core/RISCY_OOO/coherence/src:$(COREDIR)/src_Core/RISCY_OOO/fpgautils/lib +WINDCOREIFCDIR ?= $(COREDIR)/libs/WindCoreInterface +CHERICAPLIBDIR ?= $(COREDIR)/libs/cheri-cap-lib +TAGCONTROLLERDIR ?= $(COREDIR)/libs/TagController +RISCVHPMEVENTSDIR ?= $(COREDIR)/libs/RISCV_HPM_Events +TAGCONTROLLER_DIRS = $(TAGCONTROLLERDIR)/TagController:$(TAGCONTROLLERDIR)/TagController/CacheCore +BLUESTUFFDIR ?= $(COREDIR)/libs/BlueStuff +BLUEAXI4DIR = $(BLUESTUFFDIR)/BlueAXI4 +BLUEAXI4DIRS = $(BLUEAXI4DIR):$(BLUEAXI4DIR)/AXI4:$(BLUEAXI4DIR)/AXI4Lite:$(BLUEAXI4DIR)/AXI4Stream:$(BLUEAXI4DIR)/BlueUnixBridges +BLUEUNIXBRIDGESDIR = $(BLUEAXI4DIR)/BlueUnixBridges +BLUEBASICSDIR = $(BLUESTUFFDIR)/BlueBasics +BLUEUTILSDIR = $(BLUESTUFFDIR)/BlueUtils +BLUESTUFF_DIRS = $(BLUESTUFFDIR):$(BLUEAXI4DIRS):$(BLUEBASICSDIR):$(BLUEUTILSDIR):$(BLUESTUFFDIR)/Stratix10ChipID -CONTRIB_DIRS = %/Libraries/Bus -CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/Core:$(REPO)/src_Core/PLIC:$(REPO)/src_Core/Debug_Module:$(REPO)/src_Core/BSV_Additional_Libs - -BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueUtils:$(REPO)/libs/BlueStuff/BlueBasics - -TAGCONTROLLER_DIRS = $(REPO)/libs/TagController/TagController:$(REPO)/libs/TagController/TagController/CacheCore - -RISCV_HPM_Events_DIR = $(REPO)/libs/RISCV_HPM_Events - -BSC_PATH = -p $(CONTRIB_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):src_BSV:$(BLUESTUFF_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+ +# search path for bsc imports +ifdef BSC_CONTRIB_DIR +BSC_CONTRIB_LIB_DIR = $(BSC_CONTRIB_DIR)/lib/Libraries +else +BSC_CONTRIB_LIB_DIR = %/Libraries +endif +BSC_CONTRIB_DIRS = $(BSC_CONTRIB_LIB_DIR)/Bus +BSVPATH = +:$(BSC_CONTRIB_DIRS):$(WINDCOREIFCDIR):$(RISCVHPMEVENTSDIR):$(CHERICAPLIBDIR):$(TAGCONTROLLER_DIRS):$(COREW_DIRS):$(BLUESTUFF_DIRS) +BSC_PATH = -p $(BSVPATH) # ---------------- # Top-level file and module @@ -122,17 +121,17 @@ src_BSV/TagTableStructure.bsv: $(REPO)/libs/TagController/tagsparams.py .PHONY: generate_hpm_vector generate_hpm_vector: GenerateHPMVector.bsv -GenerateHPMVector.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py +GenerateHPMVector.bsv: $(RISCVHPMEVENTSDIR)/parse_counters.py @echo "INFO: Re-generating GenerateHPMVector bluespec file" - $^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -b $@ + $^ $(RISCVHPMEVENTSDIR)/counters.yaml -m ProcTypes -b $@ @echo "INFO: Re-generated GenerateHPMVector bluespec file" .PHONY: stat_counters stat_counters: StatCounters.bsv -StatCounters.bsv: $(RISCV_HPM_Events_DIR)/parse_counters.py +StatCounters.bsv: $(RISCVHPMEVENTSDIR)/parse_counters.py @echo "INFO: Re-generating HPM events struct bluepsec file" - $^ $(RISCV_HPM_Events_DIR)/counters.yaml -m ProcTypes -s $@ + $^ $(RISCVHPMEVENTSDIR)/counters.yaml -m ProcTypes -s $@ @echo "INFO: Re-generated HPM events struct bluespec file" compile_sim: tagsparams stat_counters generate_hpm_vector compile_synth: tagsparams stat_counters generate_hpm_vector diff --git a/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv b/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv index 2eafcff..f9b677d 100644 --- a/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv +++ b/src_SSITH_P3/src_BSV/Giraffe_IFC.bsv @@ -14,8 +14,8 @@ package Giraffe_IFC; -import AXI4 ::*; -import Bus ::*; +import Bus ::*; +import BlueAXI4 ::*; import Connectable ::*; `include "Giraffe.defines" diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 6567511..7f5ff60 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -32,7 +32,9 @@ import Vector :: *; import GetPut_Aux :: *; import Routable :: *; -import AXI4 :: *; +import BlueAXI4 :: *; +import SourceSink :: *; +import WindCoreInterface :: *; import Semi_FIFOF :: *; import Cur_Cycle :: *; @@ -159,67 +161,12 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ // CoreW // CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) - CoreW_IFC #(N_External_Interrupt_Sources) corew <- mkCoreW (dm_power_on_reset, - reset_by ndm_reset); - - // ================================================================ - // Tie-offs (not used in SSITH GFE) - - // Set core's verbosity - rule rl_never (False); - corew.set_verbosity (?, ?); - endrule - - // Tie-offs - rule rl_always (True); - // Non-maskable interrupt request. - corew.nmi_req (False); - endrule + Tuple2 #( PulseWire + , CoreW_IFC #(N_External_Interrupt_Sources)) both + <- mkCoreW_reset (dm_power_on_reset, reset_by ndm_reset); + match {.otherRst, .corew} = both; `ifdef INCLUDE_GDB_CONTROL - // ================================================================ - // NDM reset (reset for non-DebugModule) - - Reg #(Bit #(8)) rg_ndm_reset_delay <- mkReg (0); - Reg #(Bool) rg_running <- mkRegU; - - // Get an NDM-reset request from the Debug Module, assert ndm-reset, - // and then wait for a suitable delay. - rule rl_ndm_reset (rg_ndm_reset_delay == 0); - let x <- corew.ndm_reset_client.request.get; - rg_running <= x; - ndm_reset_controller.assertReset; - rg_ndm_reset_delay <= fromInteger (ndm_reset_duration + 100); // NOTE: heuristic - - $display ("%0d: %m.rl_ndm_reset: asserting NDM reset (for non-DebugModule) for %0d cycles", - cur_cycle, ndm_reset_duration); - endrule - - // Wait for suitable delay, then send ack response to Debug Module for NDM-reset request - rule rl_ndm_reset_wait (rg_ndm_reset_delay != 0); - if (rg_ndm_reset_delay == 1) begin - Bool is_running = rg_running; - // Restart the corew - corew.start (rg_running, 0, 0); - corew.ndm_reset_client.response.put (is_running); - $display ("%0d: %m.rl_ndm_reset_wait: sent NDM reset ack (for non-DebugModule) to Debug Module", - cur_cycle); - end - rg_ndm_reset_delay <= rg_ndm_reset_delay - 1; - endrule - - // ================================================================ - // Start the corew a suitable time after a PoR - UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew - Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait); - rule rl_step_0 (rg_corew_start_after_por != 0); - let n = rg_corew_start_after_por - 1; - rg_corew_start_after_por <= n; - if (n==0) corew.start (True, 0, 0); // initial start leaves proc running - endrule - // ================================================================ - - // ================================================================ // Instantiate JTAG TAP controller, @@ -260,23 +207,40 @@ module mkP3_Core (P3_Core_IFC); w_dmi_rsp_response <= response; endrule - (* preempts = "rl_dmi_req_cpu, rl_dmi_rsp_cpu" *) + (* preempts = "rl_dmi_req_cpu, rl_dmi_read_rsp_cpu" *) rule rl_dmi_req_cpu; match {.addr, .data, .op} = bus_dmi_req.out.first; bus_dmi_req.out.deq; case (op) - 1: corew.dmi.read_addr(addr); + 1: corew.debug_subordinate.ar.put(AXI4Lite_ARFlit { + araddr: zeroExtend (addr) << 2 + , arprot: ? + , aruser: ? + }); 2: begin - corew.dmi.write(addr, data); + corew.debug_subordinate.aw.put(AXI4Lite_AWFlit { + awaddr: zeroExtend (addr) << 2 + , awprot: ? + , awuser: ? + }); + corew.debug_subordinate.w.put(AXI4Lite_WFlit { + wdata: data + , wstrb: ~0 + , wuser: ? + }); bus_dmi_rsp.in.enq(tuple2(?, 0)); end default: bus_dmi_rsp.in.enq(tuple2(?, 2)); endcase endrule - rule rl_dmi_rsp_cpu; - let data <- corew.dmi.read_data; - bus_dmi_rsp.in.enq(tuple2(data, 0)); + rule rl_dmi_read_rsp_cpu; + let rflit <- get (corew.debug_subordinate.r); + bus_dmi_rsp.in.enq(tuple2(rflit.rdata, 0)); + endrule + + rule rl_dmi_write_rsp_drain; + corew.debug_subordinate.b.drop; endrule // ================================================================ @@ -292,8 +256,8 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ // INTERFACE - let master0_sig <- toAXI4_Master_Sig(corew.cpu_imem_master); - let master1_sig <- toAXI4_Master_Sig(corew.cpu_dmem_master); + let master0_sig <- toAXI4_Master_Sig (corew.manager_0); + let master1_sig <- toAXI4_Master_Sig (corew.manager_1); // ---------------------------------------------------------------- // Core CPU interfaces @@ -305,10 +269,8 @@ module mkP3_Core (P3_Core_IFC); // External interrupts method Action interrupt_reqs (Bit #(N_External_Interrupt_Sources) reqs); - for (Integer j = 0; j < valueOf (N_External_Interrupt_Sources); j = j + 1) begin - Bool req_j = unpack (reqs [j]); - corew.core_external_interrupt_sources [j].m_interrupt_req (req_j); - end + for (Integer j = 0; j < valueOf (N_External_Interrupt_Sources); j = j + 1) + corew.irq[j].put (unpack (reqs [j])); endmethod `ifdef INCLUDE_GDB_CONTROL From 95f554dad1c0b6f33c4e1a9bd71584a101025403 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Tue, 16 Aug 2022 12:44:00 +0000 Subject: [PATCH 34/35] removed coreW from component.xml --- src_SSITH_P3/xilinx_ip/component.xml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index d89e99e..bd8f871 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -2236,11 +2236,6 @@ verilogSource IMPORTED_FILE - - ../Verilog_RTL/mkCoreW.v - verilogSource - IMPORTED_FILE - ../Verilog_RTL/mkTagController.v verilogSource From 5bf15adf04f6a91b7f01d16a679751267cf79676 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Wed, 17 Aug 2022 08:41:27 +0000 Subject: [PATCH 35/35] Addressed @francislaus comments --- src_Core/Core/CoreW.bsv | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index d6379ac..af5e7f1 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -258,7 +258,6 @@ module mkCoreW_reset #(Reset porReset) plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base), zeroExtend (rangeTop(soc_map.m_plic_addr_range))); proc.start (restartRunning, soc_map_struct.pc_reset_value, 0, 0); - //proc.set_verbosity (verbosity); endaction; // ================================================================ @@ -435,7 +434,6 @@ module mkCoreW_reset #(Reset porReset) , Wd_AW_User, Wd_W_User, Wd_B_User , Wd_AR_User, Wd_R_User)) master_vector = newVector; - //let master_vector = newVector; master_vector[cpu_uncached_master_num] = proc_uncached; master_vector[debug_module_sba_master_num] = dm_master_local; master_vector[sub_ifc_master_num] = subShim.master; @@ -447,7 +445,6 @@ module mkCoreW_reset #(Reset porReset) , Wd_AW_User, Wd_W_User, Wd_B_User , Wd_AR_User, Wd_R_User)) slave_vector = newVector; - //let slave_vector = newVector; slave_vector[default_slave_num] = uncached_mem_shim.slave; slave_vector[llc_slave_num] = proc.debug_module_mem_server; slave_vector[plic_slave_num] = zero_AXI4_Slave_user (plic.axi4_slave); @@ -541,8 +538,6 @@ module mkCoreW_reset #(Reset porReset) method put = writeReg (nmirq_reg); endinterface; rule rl_connect_nmirq; - // TODO: fixup; passing const False for now - //proc.non_maskable_interrupt_req (False); proc.non_maskable_interrupt_req (nmirq_reg); endrule