From b32da9034b23e8b83c01329268d3f52694e6b5ee Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 1 Jul 2021 15:06:51 +0100 Subject: [PATCH] Fix addr to DM_addr convertion (pointed out by jrtc27) --- src_Core/Core/CoreW.bsv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index eb7c781..f1c7970 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -455,7 +455,7 @@ module mkCoreResetHelper #(Reset toDbgReset) rule rl_debug_module_read_req; let arFlit <- get (dbgShim.master.ar); - debug_module.dmi.read_addr (arFlit.araddr); + debug_module.dmi.read_addr (truncate (arFlit.araddr >> 2)); endrule rule rl_debug_module_read_rsp; let x <- debug_module.dmi.read_data; @@ -465,7 +465,7 @@ module mkCoreResetHelper #(Reset toDbgReset) let awFlit <- get (dbgShim.master.aw); let wFlit <- get (dbgShim.master.w); dbgShim.master.b.put(defaultValue); - debug_module.dmi.write (awFlit.awaddr, wFlit.wdata); + debug_module.dmi.write (truncate (awFlit.awaddr >> 2), wFlit.wdata); endrule let fromDbgReset <- mkPulseWire (reset_by toDbgReset);