From b48a161fdacf2d13d75388d7d8efef6574b497bf Mon Sep 17 00:00:00 2001
From: jon <>
Date: Fri, 25 Jun 2021 17:31:10 +0100
Subject: [PATCH] Experimentally remove repeated write of rg_m_halt_req
 register.

---
 src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
index fe02243..081b156 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
@@ -324,8 +324,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
     );
         fetchStage.pipelines[0].deq;
 `ifdef INCLUDE_GDB_CONTROL
-        fa_step_check;
-
        if (verbosity >= 1) begin
           if (firstTrap == tagged Valid (tagged Interrupt intrDebugHalt))
              $display ("%0d: %m.renameStage.doRenaming_Trap: intrDebugHalt", cur_cycle);