From b6a397df524ca98fdeb2bd3547b8ed97e14af3be Mon Sep 17 00:00:00 2001
From: jon <jonwoodruff@gmail.com>
Date: Tue, 15 Dec 2020 14:49:16 +0000
Subject: [PATCH] Support for ICache stat counters.

---
 libs/TagController                          |  2 +-
 src_Core/CPU/Core.bsv                       |  2 +-
 src_Core/RISCY_OOO/coherence/src/IBank.bsv  | 42 ++++++++++++++++++---
 src_Core/RISCY_OOO/coherence/src/L1Bank.bsv |  2 -
 src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv  |  6 +++
 5 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/libs/TagController b/libs/TagController
index aaa23bc..f4c5348 160000
--- a/libs/TagController
+++ b/libs/TagController
@@ -1 +1 @@
-Subproject commit aaa23bc2469bcde6c6b6e315f94f8ae83c0c14f3
+Subproject commit f4c53481887564f6e8fcb9b8f2bf94f56b7afb07
diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 25544b6..1066279 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1119,7 +1119,7 @@ module mkCore#(CoreId coreId)(Core);
      Vector #(31, Bit #(Report_Width)) mem_core_evts_vec =  to_large_vector (coreFix.memExeIfc.events);
      Vector #(31, Bit #(Report_Width)) other_core_evts_vec = to_large_vector (hpm_core_events_reg);
      Vector #(31, Bit #(Report_Width)) core_evts_vec = unpack(pack(mem_core_evts_vec) | pack(other_core_evts_vec));
-     Vector #(16, Bit #(Report_Width)) imem_evts_vec = replicate (0);//to_large_vector (near_mem.imem.events);
+     Vector #(16, Bit #(Report_Width)) imem_evts_vec = to_large_vector (iMem.events);
      Vector #(16, Bit #(Report_Width)) dmem_evts_vec = to_large_vector (dMem.events);
      Vector #(32, Bit #(Report_Width)) external_evts_vec = replicate (0);//to_large_vector (w_external_evts);
 
diff --git a/src_Core/RISCY_OOO/coherence/src/IBank.bsv b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
index 1fcf4fb..b65da88 100644
--- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
@@ -57,6 +57,10 @@ import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;
 import RandomReplace::*;
+`ifdef PERFORMANCE_MONITORING
+import PerformanceMonitor::*;
+import SpecialWires::*;
+`endif
 
 export ICRqStuck(..);
 export IPRqStuck(..);
@@ -97,6 +101,9 @@ interface IBank#(
     // performance
     method Action setPerfStatus(Bool stats);
     method Data getPerfData(L1IPerfType t);
+`ifdef PERFORMANCE_MONITORING
+    method EventsCache events;
+`endif
 endinterface
 
 module mkIBank#(
@@ -178,32 +185,54 @@ module mkIBank#(
     Bool flushDone = True;
 `endif
 
+    LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer;
 `ifdef PERF_COUNT
     Reg#(Bool) doStats <- mkConfigReg(False);
     Count#(Data) ldCnt <- mkCount(0);
     Count#(Data) ldMissCnt <- mkCount(0);
     Count#(Data) ldMissLat <- mkCount(0);
-
-    LatencyTimer#(cRqNum, 10) latTimer <- mkLatencyTimer;
-
+`endif
+`ifdef PERFORMANCE_MONITORING
+    Array #(Wire #(EventsCache)) perf_events <- mkDWireOR (2, unpack (0));
+    Reg #(EventsCache) perf_events_reg <- mkConfigReg(unpack(0));
+    rule update_events_reg;
+        perf_events_reg <= perf_events[0];
+    endrule
+`endif
     function Action incrReqCnt;
     action
+`ifdef PERF_COUNT
         if(doStats) begin
             ldCnt.incr(1);
         end
+`endif
+`ifdef PERFORMANCE_MONITORING
+        EventsCache events = unpack (0);
+        events.evt_LD = 1;
+        perf_events[0] <= events;
+`endif
+        noAction;
     endaction
     endfunction
 
     function Action incrMissCnt(cRqIdxT idx);
     action
         let lat <- latTimer.done(idx);
+`ifdef PERF_COUNT
         if(doStats) begin
             ldMissLat.incr(zeroExtend(lat));
             ldMissCnt.incr(1);
         end
+`endif
+`ifdef PERFORMANCE_MONITORING
+        EventsCache events = unpack (0);
+        events.evt_LD_MISS_LAT = saturating_truncate(lat);
+        events.evt_LD_MISS = 1;
+        perf_events[1] <= events;
+`endif
+        noAction;
     endaction
     endfunction
-`endif
 
     function tagT getTag(Addr a) = truncateLSB(a);
 
@@ -377,10 +406,8 @@ module mkIBank#(
             fshow(slot), " ; ",
             fshow(cRqToP)
         );
-`ifdef PERF_COUNT
         // performance counter: start miss timer
         latTimer.start(n);
-`endif
     endrule
 
     // last stage of pipeline: process req
@@ -818,6 +845,9 @@ module mkIBank#(
             default: 0;
         endcase);
     endmethod
+`ifdef PERFORMANCE_MONITORING
+    method EventsCache events = perf_events_reg;
+`endif
 endmodule
 
 
diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
index 59dd7a9..4dc503b 100644
--- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
@@ -478,10 +478,8 @@ endfunction
             fshow(slot), " ; ",
             fshow(cRqToP)
         );
-`ifdef PERF_COUNT
         // performance counter: start miss timer
         latTimer.start(n);
-`endif
     endrule
 
     // last stage of pipeline: process req
diff --git a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
index 9edaaaa..8f87367 100644
--- a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
@@ -372,6 +372,9 @@ interface ICoCache;
     method Action flush;
     method Bool flush_done;
     interface Perf#(L1IPerfType) perf;
+`ifdef PERFORMANCE_MONITORING
+    method EventsCache events;
+`endif
 
     interface ChildCacheToParent#(L1Way, void) to_parent;
 
@@ -442,6 +445,9 @@ module mkICoCache(ICoCache);
 `endif
         endmethod
     endinterface
+`ifdef PERFORMANCE_MONITORING
+    method EventsCache events = cache.events;
+`endif
 
     interface to_parent = cache.to_parent;