diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 8b59ae8..b87a303 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -218,6 +218,7 @@ interface Core;
 
 `ifdef PERFORMANCE_MONITORING
     method Action events_llc(EventsCache events);
+    method Action events_tgc(EventsCache events);
 `endif
 endinterface
 
@@ -1111,6 +1112,7 @@ module mkCore#(CoreId coreId)(Core);
      // Performance counters
 
      Reg#(EventsCache) events_llc_reg <- mkRegU;
+     Reg#(EventsCache) events_tgc_reg <- mkRegU;
      rule report_events;
          hpm_core_events[2] <= unpack(pack(commitStage.events));
      endrule
@@ -1123,12 +1125,14 @@ module mkCore#(CoreId coreId)(Core);
      Vector #(16, Bit #(Report_Width)) dmem_evts_vec = to_large_vector (dMem.events);
      Vector #(32, Bit #(Report_Width)) external_evts_vec = replicate (0);//to_large_vector (w_external_evts);
      Vector #(16, Bit #(Report_Width)) llc_evts_vec = to_large_vector (events_llc_reg);
+     Vector #(16, Bit #(Report_Width)) tgc_evts_vec = to_large_vector (events_tgc_reg);
 
      let events = append (null_evt, core_evts_vec);
      events = append (events, imem_evts_vec);
      events = append (events, dmem_evts_vec);
      events = append (events, external_evts_vec);
      events = append (events, llc_evts_vec);
+     events = append (events, tgc_evts_vec);
 
      (* fire_when_enabled, no_implicit_conditions *)
      rule rl_send_perf_evts;
@@ -1530,6 +1534,7 @@ module mkCore#(CoreId coreId)(Core);
 
 `ifdef PERFORMANCE_MONITORING
     method events_llc = events_llc_reg._write;
+    method events_tgc = events_tgc_reg._write;
 `endif
 
 endmodule
diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv
index d65e6e4..e8464b6 100644
--- a/src_Core/CPU/Proc.bsv
+++ b/src_Core/CPU/Proc.bsv
@@ -189,9 +189,11 @@ module mkProc (Proc_IFC);
    endrule
 
 `ifdef PERFORMANCE_MONITORING
+   Reg#(EventsCache) events_tgc_reg <- mkRegU;
    rule broadcastPerfEvents;
        for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin
            core[j].events_llc(llc.events);
+           core[j].events_tgc(events_tgc_reg);
        end
    endrule
 `endif
@@ -356,6 +358,10 @@ module mkProc (Proc_IFC);
     method Bit #(32) hart0_debug_rename = core [0].debugRename;
 `endif
 
+`ifdef PERFORMANCE_MONITORING
+    method events_tgc = events_tgc_reg._write;
+`endif
+
 endmodule: mkProc
 
 // ================================================================
diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv
index d9eaede..61369f5 100644
--- a/src_Core/CPU/Proc_IFC.bsv
+++ b/src_Core/CPU/Proc_IFC.bsv
@@ -32,6 +32,7 @@ import ISA_Decls  :: *;
 import AXI4  :: *;
 import Fabric_Defs :: *;
 import SoC_Map :: *;
+import CCTypes :: *;
 
 `ifdef INCLUDE_GDB_CONTROL
 import DM_CPU_Req_Rsp :: *;
@@ -144,6 +145,10 @@ interface Proc_IFC;
     method Bit #(32) hart0_debug_rename;
 `endif
 
+`ifdef PERFORMANCE_MONITORING
+    method Action events_tgc(EventsCache events);
+`endif
+
 endinterface
 
 // ================================================================
diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index 06e3d4a..0a9e5e4 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -74,6 +74,7 @@ import ProcTypes    :: *;
 // Main fabric
 import Fabric_Defs  :: *;    // for Wd_Id, Wd_Addr, Wd_Data...
 import SoC_Map      :: *;
+import CCTypes      :: *;    // for EventsCache.
 
 `ifdef INCLUDE_GDB_CONTROL
 import Debug_Module  :: *;
@@ -172,6 +173,19 @@ module mkCoreW #(Reset dm_power_on_reset)
    // AXI4 tagController
    TagControllerAXI#(Wd_MId, Wd_Addr, Wd_Data) tagController <- mkTagControllerAXI(reset_by hart0_reset); // TODO double check if reseting like this is good enough
    mkConnection(proc.master0, tagController.slave, reset_by hart0_reset);
+`ifdef PERFORMANCE_MONITORING
+   rule report_tagController_events;
+      Vector#(7, Bit#(1)) evts = tagController.events;
+      EventsCache ce = unpack(0);
+      ce.evt_ST = zeroExtend(evts[0]); // Unsure of mapping from EventsCacheCore to 7-bit vector.
+      ce.evt_ST_MISS = zeroExtend(evts[1]);
+      ce.evt_LD = zeroExtend(evts[2]);
+      ce.evt_LD_MISS = zeroExtend(evts[3]);
+      ce.evt_EVICT = zeroExtend(evts[4]);
+      // SET_TAG_WRITE/READ aren't used in TagCache; tag table data is not tagged.
+      proc.events_tgc(ce);
+   endrule
+`endif
 
    // PLIC (Platform-Level Interrupt Controller)
    PLIC_IFC_16_2_7  plic <- mkPLIC_16_2_7;
diff --git a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
index 8b13ae1..4f69c89 100755
--- a/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
@@ -1041,7 +1041,7 @@ endfunction
 function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
 
 `ifdef PERFORMANCE_MONITORING
-typedef 112 No_Of_Evts;
+typedef 128 No_Of_Evts;
 typedef   8 Report_Width;
 typedef  64 Counter_Width;
 typedef  29 No_Of_Ctrs;