From badf5c8e370aaa6b2ddcdf47951176853d7e0516 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Sun, 5 Jul 2020 21:41:28 +0100 Subject: [PATCH] Include xCHERI in ARCH and build directory names Also use RVFI_DII not RVFIDII in the directory names. This makes everything match Piccolo/Flute rather than having Toooba be a weird, inconsistent and plain wrong. --- .../Makefile | 2 +- .../Mem.hex | 0 .../TagTableStructure.bsv | 0 .../Makefile | 2 +- .../TagTableStructure.bsv | 0 .../Makefile | 2 +- .../TagTableStructure.bsv | 0 src_SSITH_P3/Makefile | 2 +- 8 files changed, 4 insertions(+), 4 deletions(-) rename builds/{RV64ACDFIMSU_Toooba_RVFIDII_verilator => RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator}/Makefile (98%) rename builds/{RV64ACDFIMSU_Toooba_RVFIDII_verilator => RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator}/Mem.hex (100%) rename builds/{RV64ACDFIMSU_Toooba_RVFIDII_verilator => RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator}/TagTableStructure.bsv (100%) rename builds/{RV64ACDFIMSU_Toooba_bluesim => RV64ACDFIMSUxCHERI_Toooba_bluesim}/Makefile (98%) rename builds/{RV64ACDFIMSU_Toooba_bluesim => RV64ACDFIMSUxCHERI_Toooba_bluesim}/TagTableStructure.bsv (100%) rename builds/{RV64ACDFIMSU_Toooba_verilator => RV64ACDFIMSUxCHERI_Toooba_verilator}/Makefile (98%) rename builds/{RV64ACDFIMSU_Toooba_verilator => RV64ACDFIMSUxCHERI_Toooba_verilator}/TagTableStructure.bsv (100%) diff --git a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile similarity index 98% rename from builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile rename to builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile index c965909..e92ce69 100644 --- a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile @@ -20,7 +20,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(RVFI_DII_DIRS):$(CHERI_DIRS) # ================================================================ REPO ?= ../.. -ARCH ?= RV64ACDFIMSU +ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler diff --git a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Mem.hex b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Mem.hex similarity index 100% rename from builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/Mem.hex rename to builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Mem.hex diff --git a/builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/TagTableStructure.bsv b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/TagTableStructure.bsv similarity index 100% rename from builds/RV64ACDFIMSU_Toooba_RVFIDII_verilator/TagTableStructure.bsv rename to builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/TagTableStructure.bsv diff --git a/builds/RV64ACDFIMSU_Toooba_bluesim/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile similarity index 98% rename from builds/RV64ACDFIMSU_Toooba_bluesim/Makefile rename to builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile index 99244e5..ecc3d43 100644 --- a/builds/RV64ACDFIMSU_Toooba_bluesim/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile @@ -18,7 +18,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS) # ================================================================ REPO ?= ../.. -ARCH ?= RV64ACDFIMSU +ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler diff --git a/builds/RV64ACDFIMSU_Toooba_bluesim/TagTableStructure.bsv b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/TagTableStructure.bsv similarity index 100% rename from builds/RV64ACDFIMSU_Toooba_bluesim/TagTableStructure.bsv rename to builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/TagTableStructure.bsv diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Makefile b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile similarity index 98% rename from builds/RV64ACDFIMSU_Toooba_verilator/Makefile rename to builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile index 3292b76..b48118f 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Makefile +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile @@ -18,7 +18,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS) # ================================================================ REPO ?= ../.. -ARCH ?= RV64ACDFIMSU +ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/TagTableStructure.bsv b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/TagTableStructure.bsv similarity index 100% rename from builds/RV64ACDFIMSU_Toooba_verilator/TagTableStructure.bsv rename to builds/RV64ACDFIMSUxCHERI_Toooba_verilator/TagTableStructure.bsv diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile index f1be125..19bd37c 100644 --- a/src_SSITH_P3/Makefile +++ b/src_SSITH_P3/Makefile @@ -16,7 +16,7 @@ compile: compile_sim compile_synth # ================================================================ REPO ?= .. -ARCH ?= RV64ACDFIMSU +ARCH ?= RV64ACDFIMSUxCHERI # ================================================================ # RISC-V config macros passed into Bluespec 'bsc' compiler