From bb557e5e230c479359e95bc0d906bb3bec0ff669 Mon Sep 17 00:00:00 2001 From: Darius Rad Date: Wed, 24 Apr 2019 21:48:33 -0400 Subject: [PATCH] Update compiled output. --- src_SSITH_P3/Verilog_RTL/mkCore.v | 12 +- src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v | 4050 +-------------- src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v | 2052 +------- src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v | 5598 +-------------------- src_SSITH_P3/Verilog_RTL/mkProc.v | 1190 ++--- src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 12 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v | 4050 +-------------- src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v | 2052 +------- src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v | 5598 +-------------------- src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 1190 ++--- 10 files changed, 1386 insertions(+), 24418 deletions(-) diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 0165684..c6c37b4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -9449,6 +9449,7 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9498,6 +9499,7 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9595,6 +9597,7 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9625,6 +9628,7 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -10419,11 +10423,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$RDY_first && IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = @@ -14456,7 +14456,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v index e885e7d..5e92dd3 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v @@ -7,16 +7,15 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 reg -// RDY_response_get O 1 reg +// response_get O 69 +// RDY_response_get O 1 // CLK I 1 clock // RST_N I 1 reset -// request_put I 131 reg +// request_put I 131 // EN_request_put I 1 // EN_response_get I 1 // -// Combinational paths from inputs to outputs: -// EN_response_get -> RDY_request_put +// No combinational paths from inputs to outputs // // @@ -60,4031 +59,44 @@ module mkDoubleDiv(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu_fOperands_S0 - wire [130 : 0] fpu_fOperands_S0$D_IN, fpu_fOperands_S0$D_OUT; - wire fpu_fOperands_S0$CLR, - fpu_fOperands_S0$DEQ, - fpu_fOperands_S0$EMPTY_N, - fpu_fOperands_S0$ENQ, - fpu_fOperands_S0$FULL_N; - - // ports of submodule fpu_fResult_S5 - wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; - wire fpu_fResult_S5$CLR, - fpu_fResult_S5$DEQ, - fpu_fResult_S5$EMPTY_N, - fpu_fResult_S5$ENQ, - fpu_fResult_S5$FULL_N; - - // ports of submodule fpu_fState_S1 - wire [318 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; - wire fpu_fState_S1$CLR, - fpu_fState_S1$DEQ, - fpu_fState_S1$EMPTY_N, - fpu_fState_S1$ENQ, - fpu_fState_S1$FULL_N; - - // ports of submodule fpu_fState_S2 - wire [147 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; - wire fpu_fState_S2$CLR, - fpu_fState_S2$DEQ, - fpu_fState_S2$EMPTY_N, - fpu_fState_S2$ENQ, - fpu_fState_S2$FULL_N; - - // ports of submodule fpu_fState_S3 - wire [194 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; - wire fpu_fState_S3$CLR, - fpu_fState_S3$DEQ, - fpu_fState_S3$EMPTY_N, - fpu_fState_S3$ENQ, - fpu_fState_S3$FULL_N; - - // ports of submodule fpu_fState_S4 - wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; - wire fpu_fState_S4$CLR, - fpu_fState_S4$DEQ, - fpu_fState_S4$EMPTY_N, - fpu_fState_S4$ENQ, - fpu_fState_S4$FULL_N; - - // ports of submodule int_div_fFirst - wire [231 : 0] int_div_fFirst$D_IN, int_div_fFirst$D_OUT; - wire int_div_fFirst$CLR, - int_div_fFirst$DEQ, - int_div_fFirst$EMPTY_N, - int_div_fFirst$ENQ, - int_div_fFirst$FULL_N; - - // ports of submodule int_div_fNext_0 - wire [231 : 0] int_div_fNext_0$D_IN, int_div_fNext_0$D_OUT; - wire int_div_fNext_0$CLR, - int_div_fNext_0$DEQ, - int_div_fNext_0$EMPTY_N, - int_div_fNext_0$ENQ, - int_div_fNext_0$FULL_N; - - // ports of submodule int_div_fNext_1 - wire [231 : 0] int_div_fNext_1$D_IN, int_div_fNext_1$D_OUT; - wire int_div_fNext_1$CLR, - int_div_fNext_1$DEQ, - int_div_fNext_1$EMPTY_N, - int_div_fNext_1$ENQ, - int_div_fNext_1$FULL_N; - - // ports of submodule int_div_fNext_10 - wire [231 : 0] int_div_fNext_10$D_IN, int_div_fNext_10$D_OUT; - wire int_div_fNext_10$CLR, - int_div_fNext_10$DEQ, - int_div_fNext_10$EMPTY_N, - int_div_fNext_10$ENQ, - int_div_fNext_10$FULL_N; - - // ports of submodule int_div_fNext_11 - wire [231 : 0] int_div_fNext_11$D_IN, int_div_fNext_11$D_OUT; - wire int_div_fNext_11$CLR, - int_div_fNext_11$DEQ, - int_div_fNext_11$EMPTY_N, - int_div_fNext_11$ENQ, - int_div_fNext_11$FULL_N; - - // ports of submodule int_div_fNext_12 - wire [231 : 0] int_div_fNext_12$D_IN, int_div_fNext_12$D_OUT; - wire int_div_fNext_12$CLR, - int_div_fNext_12$DEQ, - int_div_fNext_12$EMPTY_N, - int_div_fNext_12$ENQ, - int_div_fNext_12$FULL_N; - - // ports of submodule int_div_fNext_13 - wire [231 : 0] int_div_fNext_13$D_IN, int_div_fNext_13$D_OUT; - wire int_div_fNext_13$CLR, - int_div_fNext_13$DEQ, - int_div_fNext_13$EMPTY_N, - int_div_fNext_13$ENQ, - int_div_fNext_13$FULL_N; - - // ports of submodule int_div_fNext_14 - wire [231 : 0] int_div_fNext_14$D_IN, int_div_fNext_14$D_OUT; - wire int_div_fNext_14$CLR, - int_div_fNext_14$DEQ, - int_div_fNext_14$EMPTY_N, - int_div_fNext_14$ENQ, - int_div_fNext_14$FULL_N; - - // ports of submodule int_div_fNext_15 - wire [231 : 0] int_div_fNext_15$D_IN, int_div_fNext_15$D_OUT; - wire int_div_fNext_15$CLR, - int_div_fNext_15$DEQ, - int_div_fNext_15$EMPTY_N, - int_div_fNext_15$ENQ, - int_div_fNext_15$FULL_N; - - // ports of submodule int_div_fNext_16 - wire [231 : 0] int_div_fNext_16$D_IN, int_div_fNext_16$D_OUT; - wire int_div_fNext_16$CLR, - int_div_fNext_16$DEQ, - int_div_fNext_16$EMPTY_N, - int_div_fNext_16$ENQ, - int_div_fNext_16$FULL_N; - - // ports of submodule int_div_fNext_17 - wire [231 : 0] int_div_fNext_17$D_IN, int_div_fNext_17$D_OUT; - wire int_div_fNext_17$CLR, - int_div_fNext_17$DEQ, - int_div_fNext_17$EMPTY_N, - int_div_fNext_17$ENQ, - int_div_fNext_17$FULL_N; - - // ports of submodule int_div_fNext_18 - wire [231 : 0] int_div_fNext_18$D_IN, int_div_fNext_18$D_OUT; - wire int_div_fNext_18$CLR, - int_div_fNext_18$DEQ, - int_div_fNext_18$EMPTY_N, - int_div_fNext_18$ENQ, - int_div_fNext_18$FULL_N; - - // ports of submodule int_div_fNext_19 - wire [231 : 0] int_div_fNext_19$D_IN, int_div_fNext_19$D_OUT; - wire int_div_fNext_19$CLR, - int_div_fNext_19$DEQ, - int_div_fNext_19$EMPTY_N, - int_div_fNext_19$ENQ, - int_div_fNext_19$FULL_N; - - // ports of submodule int_div_fNext_2 - wire [231 : 0] int_div_fNext_2$D_IN, int_div_fNext_2$D_OUT; - wire int_div_fNext_2$CLR, - int_div_fNext_2$DEQ, - int_div_fNext_2$EMPTY_N, - int_div_fNext_2$ENQ, - int_div_fNext_2$FULL_N; - - // ports of submodule int_div_fNext_20 - wire [231 : 0] int_div_fNext_20$D_IN, int_div_fNext_20$D_OUT; - wire int_div_fNext_20$CLR, - int_div_fNext_20$DEQ, - int_div_fNext_20$EMPTY_N, - int_div_fNext_20$ENQ, - int_div_fNext_20$FULL_N; - - // ports of submodule int_div_fNext_21 - wire [231 : 0] int_div_fNext_21$D_IN, int_div_fNext_21$D_OUT; - wire int_div_fNext_21$CLR, - int_div_fNext_21$DEQ, - int_div_fNext_21$EMPTY_N, - int_div_fNext_21$ENQ, - int_div_fNext_21$FULL_N; - - // ports of submodule int_div_fNext_22 - wire [231 : 0] int_div_fNext_22$D_IN, int_div_fNext_22$D_OUT; - wire int_div_fNext_22$CLR, - int_div_fNext_22$DEQ, - int_div_fNext_22$EMPTY_N, - int_div_fNext_22$ENQ, - int_div_fNext_22$FULL_N; - - // ports of submodule int_div_fNext_23 - wire [231 : 0] int_div_fNext_23$D_IN, int_div_fNext_23$D_OUT; - wire int_div_fNext_23$CLR, - int_div_fNext_23$DEQ, - int_div_fNext_23$EMPTY_N, - int_div_fNext_23$ENQ, - int_div_fNext_23$FULL_N; - - // ports of submodule int_div_fNext_24 - wire [231 : 0] int_div_fNext_24$D_IN, int_div_fNext_24$D_OUT; - wire int_div_fNext_24$CLR, - int_div_fNext_24$DEQ, - int_div_fNext_24$EMPTY_N, - int_div_fNext_24$ENQ, - int_div_fNext_24$FULL_N; - - // ports of submodule int_div_fNext_25 - wire [231 : 0] int_div_fNext_25$D_IN, int_div_fNext_25$D_OUT; - wire int_div_fNext_25$CLR, - int_div_fNext_25$DEQ, - int_div_fNext_25$EMPTY_N, - int_div_fNext_25$ENQ, - int_div_fNext_25$FULL_N; - - // ports of submodule int_div_fNext_26 - wire [231 : 0] int_div_fNext_26$D_IN, int_div_fNext_26$D_OUT; - wire int_div_fNext_26$CLR, - int_div_fNext_26$DEQ, - int_div_fNext_26$EMPTY_N, - int_div_fNext_26$ENQ, - int_div_fNext_26$FULL_N; - - // ports of submodule int_div_fNext_27 - wire [231 : 0] int_div_fNext_27$D_IN, int_div_fNext_27$D_OUT; - wire int_div_fNext_27$CLR, - int_div_fNext_27$DEQ, - int_div_fNext_27$EMPTY_N, - int_div_fNext_27$ENQ, - int_div_fNext_27$FULL_N; - - // ports of submodule int_div_fNext_28 - wire [231 : 0] int_div_fNext_28$D_IN, int_div_fNext_28$D_OUT; - wire int_div_fNext_28$CLR, - int_div_fNext_28$DEQ, - int_div_fNext_28$EMPTY_N, - int_div_fNext_28$ENQ, - int_div_fNext_28$FULL_N; - - // ports of submodule int_div_fNext_29 - wire [231 : 0] int_div_fNext_29$D_IN, int_div_fNext_29$D_OUT; - wire int_div_fNext_29$CLR, - int_div_fNext_29$DEQ, - int_div_fNext_29$EMPTY_N, - int_div_fNext_29$ENQ, - int_div_fNext_29$FULL_N; - - // ports of submodule int_div_fNext_3 - wire [231 : 0] int_div_fNext_3$D_IN, int_div_fNext_3$D_OUT; - wire int_div_fNext_3$CLR, - int_div_fNext_3$DEQ, - int_div_fNext_3$EMPTY_N, - int_div_fNext_3$ENQ, - int_div_fNext_3$FULL_N; - - // ports of submodule int_div_fNext_30 - wire [231 : 0] int_div_fNext_30$D_IN, int_div_fNext_30$D_OUT; - wire int_div_fNext_30$CLR, - int_div_fNext_30$DEQ, - int_div_fNext_30$EMPTY_N, - int_div_fNext_30$ENQ, - int_div_fNext_30$FULL_N; - - // ports of submodule int_div_fNext_31 - wire [231 : 0] int_div_fNext_31$D_IN, int_div_fNext_31$D_OUT; - wire int_div_fNext_31$CLR, - int_div_fNext_31$DEQ, - int_div_fNext_31$EMPTY_N, - int_div_fNext_31$ENQ, - int_div_fNext_31$FULL_N; - - // ports of submodule int_div_fNext_32 - wire [231 : 0] int_div_fNext_32$D_IN, int_div_fNext_32$D_OUT; - wire int_div_fNext_32$CLR, - int_div_fNext_32$DEQ, - int_div_fNext_32$EMPTY_N, - int_div_fNext_32$ENQ, - int_div_fNext_32$FULL_N; - - // ports of submodule int_div_fNext_33 - wire [231 : 0] int_div_fNext_33$D_IN, int_div_fNext_33$D_OUT; - wire int_div_fNext_33$CLR, - int_div_fNext_33$DEQ, - int_div_fNext_33$EMPTY_N, - int_div_fNext_33$ENQ, - int_div_fNext_33$FULL_N; - - // ports of submodule int_div_fNext_34 - wire [231 : 0] int_div_fNext_34$D_IN, int_div_fNext_34$D_OUT; - wire int_div_fNext_34$CLR, - int_div_fNext_34$DEQ, - int_div_fNext_34$EMPTY_N, - int_div_fNext_34$ENQ, - int_div_fNext_34$FULL_N; - - // ports of submodule int_div_fNext_35 - wire [231 : 0] int_div_fNext_35$D_IN, int_div_fNext_35$D_OUT; - wire int_div_fNext_35$CLR, - int_div_fNext_35$DEQ, - int_div_fNext_35$EMPTY_N, - int_div_fNext_35$ENQ, - int_div_fNext_35$FULL_N; - - // ports of submodule int_div_fNext_36 - wire [231 : 0] int_div_fNext_36$D_IN, int_div_fNext_36$D_OUT; - wire int_div_fNext_36$CLR, - int_div_fNext_36$DEQ, - int_div_fNext_36$EMPTY_N, - int_div_fNext_36$ENQ, - int_div_fNext_36$FULL_N; - - // ports of submodule int_div_fNext_37 - wire [231 : 0] int_div_fNext_37$D_IN, int_div_fNext_37$D_OUT; - wire int_div_fNext_37$CLR, - int_div_fNext_37$DEQ, - int_div_fNext_37$EMPTY_N, - int_div_fNext_37$ENQ, - int_div_fNext_37$FULL_N; - - // ports of submodule int_div_fNext_38 - wire [231 : 0] int_div_fNext_38$D_IN, int_div_fNext_38$D_OUT; - wire int_div_fNext_38$CLR, - int_div_fNext_38$DEQ, - int_div_fNext_38$EMPTY_N, - int_div_fNext_38$ENQ, - int_div_fNext_38$FULL_N; - - // ports of submodule int_div_fNext_39 - wire [231 : 0] int_div_fNext_39$D_IN, int_div_fNext_39$D_OUT; - wire int_div_fNext_39$CLR, - int_div_fNext_39$DEQ, - int_div_fNext_39$EMPTY_N, - int_div_fNext_39$ENQ, - int_div_fNext_39$FULL_N; - - // ports of submodule int_div_fNext_4 - wire [231 : 0] int_div_fNext_4$D_IN, int_div_fNext_4$D_OUT; - wire int_div_fNext_4$CLR, - int_div_fNext_4$DEQ, - int_div_fNext_4$EMPTY_N, - int_div_fNext_4$ENQ, - int_div_fNext_4$FULL_N; - - // ports of submodule int_div_fNext_40 - wire [231 : 0] int_div_fNext_40$D_IN, int_div_fNext_40$D_OUT; - wire int_div_fNext_40$CLR, - int_div_fNext_40$DEQ, - int_div_fNext_40$EMPTY_N, - int_div_fNext_40$ENQ, - int_div_fNext_40$FULL_N; - - // ports of submodule int_div_fNext_41 - wire [231 : 0] int_div_fNext_41$D_IN, int_div_fNext_41$D_OUT; - wire int_div_fNext_41$CLR, - int_div_fNext_41$DEQ, - int_div_fNext_41$EMPTY_N, - int_div_fNext_41$ENQ, - int_div_fNext_41$FULL_N; - - // ports of submodule int_div_fNext_42 - wire [231 : 0] int_div_fNext_42$D_IN, int_div_fNext_42$D_OUT; - wire int_div_fNext_42$CLR, - int_div_fNext_42$DEQ, - int_div_fNext_42$EMPTY_N, - int_div_fNext_42$ENQ, - int_div_fNext_42$FULL_N; - - // ports of submodule int_div_fNext_43 - wire [231 : 0] int_div_fNext_43$D_IN, int_div_fNext_43$D_OUT; - wire int_div_fNext_43$CLR, - int_div_fNext_43$DEQ, - int_div_fNext_43$EMPTY_N, - int_div_fNext_43$ENQ, - int_div_fNext_43$FULL_N; - - // ports of submodule int_div_fNext_44 - wire [231 : 0] int_div_fNext_44$D_IN, int_div_fNext_44$D_OUT; - wire int_div_fNext_44$CLR, - int_div_fNext_44$DEQ, - int_div_fNext_44$EMPTY_N, - int_div_fNext_44$ENQ, - int_div_fNext_44$FULL_N; - - // ports of submodule int_div_fNext_45 - wire [231 : 0] int_div_fNext_45$D_IN, int_div_fNext_45$D_OUT; - wire int_div_fNext_45$CLR, - int_div_fNext_45$DEQ, - int_div_fNext_45$EMPTY_N, - int_div_fNext_45$ENQ, - int_div_fNext_45$FULL_N; - - // ports of submodule int_div_fNext_46 - wire [231 : 0] int_div_fNext_46$D_IN, int_div_fNext_46$D_OUT; - wire int_div_fNext_46$CLR, - int_div_fNext_46$DEQ, - int_div_fNext_46$EMPTY_N, - int_div_fNext_46$ENQ, - int_div_fNext_46$FULL_N; - - // ports of submodule int_div_fNext_47 - wire [231 : 0] int_div_fNext_47$D_IN, int_div_fNext_47$D_OUT; - wire int_div_fNext_47$CLR, - int_div_fNext_47$DEQ, - int_div_fNext_47$EMPTY_N, - int_div_fNext_47$ENQ, - int_div_fNext_47$FULL_N; - - // ports of submodule int_div_fNext_48 - wire [231 : 0] int_div_fNext_48$D_IN, int_div_fNext_48$D_OUT; - wire int_div_fNext_48$CLR, - int_div_fNext_48$DEQ, - int_div_fNext_48$EMPTY_N, - int_div_fNext_48$ENQ, - int_div_fNext_48$FULL_N; - - // ports of submodule int_div_fNext_49 - wire [231 : 0] int_div_fNext_49$D_IN, int_div_fNext_49$D_OUT; - wire int_div_fNext_49$CLR, - int_div_fNext_49$DEQ, - int_div_fNext_49$EMPTY_N, - int_div_fNext_49$ENQ, - int_div_fNext_49$FULL_N; - - // ports of submodule int_div_fNext_5 - wire [231 : 0] int_div_fNext_5$D_IN, int_div_fNext_5$D_OUT; - wire int_div_fNext_5$CLR, - int_div_fNext_5$DEQ, - int_div_fNext_5$EMPTY_N, - int_div_fNext_5$ENQ, - int_div_fNext_5$FULL_N; - - // ports of submodule int_div_fNext_50 - wire [231 : 0] int_div_fNext_50$D_IN, int_div_fNext_50$D_OUT; - wire int_div_fNext_50$CLR, - int_div_fNext_50$DEQ, - int_div_fNext_50$EMPTY_N, - int_div_fNext_50$ENQ, - int_div_fNext_50$FULL_N; - - // ports of submodule int_div_fNext_51 - wire [231 : 0] int_div_fNext_51$D_IN, int_div_fNext_51$D_OUT; - wire int_div_fNext_51$CLR, - int_div_fNext_51$DEQ, - int_div_fNext_51$EMPTY_N, - int_div_fNext_51$ENQ, - int_div_fNext_51$FULL_N; - - // ports of submodule int_div_fNext_52 - wire [231 : 0] int_div_fNext_52$D_IN, int_div_fNext_52$D_OUT; - wire int_div_fNext_52$CLR, - int_div_fNext_52$DEQ, - int_div_fNext_52$EMPTY_N, - int_div_fNext_52$ENQ, - int_div_fNext_52$FULL_N; - - // ports of submodule int_div_fNext_53 - wire [231 : 0] int_div_fNext_53$D_IN, int_div_fNext_53$D_OUT; - wire int_div_fNext_53$CLR, - int_div_fNext_53$DEQ, - int_div_fNext_53$EMPTY_N, - int_div_fNext_53$ENQ, - int_div_fNext_53$FULL_N; - - // ports of submodule int_div_fNext_54 - wire [231 : 0] int_div_fNext_54$D_IN, int_div_fNext_54$D_OUT; - wire int_div_fNext_54$CLR, - int_div_fNext_54$DEQ, - int_div_fNext_54$EMPTY_N, - int_div_fNext_54$ENQ, - int_div_fNext_54$FULL_N; - - // ports of submodule int_div_fNext_55 - wire [231 : 0] int_div_fNext_55$D_IN, int_div_fNext_55$D_OUT; - wire int_div_fNext_55$CLR, - int_div_fNext_55$DEQ, - int_div_fNext_55$EMPTY_N, - int_div_fNext_55$ENQ, - int_div_fNext_55$FULL_N; - - // ports of submodule int_div_fNext_56 - wire [231 : 0] int_div_fNext_56$D_IN, int_div_fNext_56$D_OUT; - wire int_div_fNext_56$CLR, - int_div_fNext_56$DEQ, - int_div_fNext_56$EMPTY_N, - int_div_fNext_56$ENQ, - int_div_fNext_56$FULL_N; - - // ports of submodule int_div_fNext_57 - wire [231 : 0] int_div_fNext_57$D_IN, int_div_fNext_57$D_OUT; - wire int_div_fNext_57$CLR, - int_div_fNext_57$DEQ, - int_div_fNext_57$EMPTY_N, - int_div_fNext_57$ENQ, - int_div_fNext_57$FULL_N; - - // ports of submodule int_div_fNext_6 - wire [231 : 0] int_div_fNext_6$D_IN, int_div_fNext_6$D_OUT; - wire int_div_fNext_6$CLR, - int_div_fNext_6$DEQ, - int_div_fNext_6$EMPTY_N, - int_div_fNext_6$ENQ, - int_div_fNext_6$FULL_N; - - // ports of submodule int_div_fNext_7 - wire [231 : 0] int_div_fNext_7$D_IN, int_div_fNext_7$D_OUT; - wire int_div_fNext_7$CLR, - int_div_fNext_7$DEQ, - int_div_fNext_7$EMPTY_N, - int_div_fNext_7$ENQ, - int_div_fNext_7$FULL_N; - - // ports of submodule int_div_fNext_8 - wire [231 : 0] int_div_fNext_8$D_IN, int_div_fNext_8$D_OUT; - wire int_div_fNext_8$CLR, - int_div_fNext_8$DEQ, - int_div_fNext_8$EMPTY_N, - int_div_fNext_8$ENQ, - int_div_fNext_8$FULL_N; - - // ports of submodule int_div_fNext_9 - wire [231 : 0] int_div_fNext_9$D_IN, int_div_fNext_9$D_OUT; - wire int_div_fNext_9$CLR, - int_div_fNext_9$DEQ, - int_div_fNext_9$EMPTY_N, - int_div_fNext_9$ENQ, - int_div_fNext_9$FULL_N; - - // ports of submodule int_div_fRequest - wire [170 : 0] int_div_fRequest$D_IN, int_div_fRequest$D_OUT; - wire int_div_fRequest$CLR, - int_div_fRequest$DEQ, - int_div_fRequest$EMPTY_N, - int_div_fRequest$ENQ, - int_div_fRequest$FULL_N; - - // ports of submodule int_div_fResponse - wire [113 : 0] int_div_fResponse$D_IN, int_div_fResponse$D_OUT; - wire int_div_fResponse$CLR, - int_div_fResponse$DEQ, - int_div_fResponse$EMPTY_N, - int_div_fResponse$ENQ, - int_div_fResponse$FULL_N; + // ports of submodule fpu + wire [130 : 0] fpu$request_put; + wire [68 : 0] fpu$response_get; + wire fpu$EN_request_put, + fpu$EN_response_get, + fpu$RDY_request_put, + fpu$RDY_response_get; // rule scheduling signals - wire CAN_FIRE_RL_fpu_s1_stage, - CAN_FIRE_RL_fpu_s2_stage, - CAN_FIRE_RL_fpu_s3_stage, - CAN_FIRE_RL_fpu_s4_stage, - CAN_FIRE_RL_fpu_s5_stage, - CAN_FIRE_RL_int_div_finish, - CAN_FIRE_RL_int_div_start, - CAN_FIRE_RL_int_div_work, - CAN_FIRE_RL_int_div_work_1, - CAN_FIRE_RL_int_div_work_10, - CAN_FIRE_RL_int_div_work_11, - CAN_FIRE_RL_int_div_work_12, - CAN_FIRE_RL_int_div_work_13, - CAN_FIRE_RL_int_div_work_14, - CAN_FIRE_RL_int_div_work_15, - CAN_FIRE_RL_int_div_work_16, - CAN_FIRE_RL_int_div_work_17, - CAN_FIRE_RL_int_div_work_18, - CAN_FIRE_RL_int_div_work_19, - CAN_FIRE_RL_int_div_work_2, - CAN_FIRE_RL_int_div_work_20, - CAN_FIRE_RL_int_div_work_21, - CAN_FIRE_RL_int_div_work_22, - CAN_FIRE_RL_int_div_work_23, - CAN_FIRE_RL_int_div_work_24, - CAN_FIRE_RL_int_div_work_25, - CAN_FIRE_RL_int_div_work_26, - CAN_FIRE_RL_int_div_work_27, - CAN_FIRE_RL_int_div_work_28, - CAN_FIRE_RL_int_div_work_29, - CAN_FIRE_RL_int_div_work_3, - CAN_FIRE_RL_int_div_work_30, - CAN_FIRE_RL_int_div_work_31, - CAN_FIRE_RL_int_div_work_32, - CAN_FIRE_RL_int_div_work_33, - CAN_FIRE_RL_int_div_work_34, - CAN_FIRE_RL_int_div_work_35, - CAN_FIRE_RL_int_div_work_36, - CAN_FIRE_RL_int_div_work_37, - CAN_FIRE_RL_int_div_work_38, - CAN_FIRE_RL_int_div_work_39, - CAN_FIRE_RL_int_div_work_4, - CAN_FIRE_RL_int_div_work_40, - CAN_FIRE_RL_int_div_work_41, - CAN_FIRE_RL_int_div_work_42, - CAN_FIRE_RL_int_div_work_43, - CAN_FIRE_RL_int_div_work_44, - CAN_FIRE_RL_int_div_work_45, - CAN_FIRE_RL_int_div_work_46, - CAN_FIRE_RL_int_div_work_47, - CAN_FIRE_RL_int_div_work_48, - CAN_FIRE_RL_int_div_work_49, - CAN_FIRE_RL_int_div_work_5, - CAN_FIRE_RL_int_div_work_50, - CAN_FIRE_RL_int_div_work_51, - CAN_FIRE_RL_int_div_work_52, - CAN_FIRE_RL_int_div_work_53, - CAN_FIRE_RL_int_div_work_54, - CAN_FIRE_RL_int_div_work_55, - CAN_FIRE_RL_int_div_work_56, - CAN_FIRE_RL_int_div_work_57, - CAN_FIRE_RL_int_div_work_6, - CAN_FIRE_RL_int_div_work_7, - CAN_FIRE_RL_int_div_work_8, - CAN_FIRE_RL_int_div_work_9, - CAN_FIRE_request_put, + wire CAN_FIRE_request_put, CAN_FIRE_response_get, - WILL_FIRE_RL_fpu_s1_stage, - WILL_FIRE_RL_fpu_s2_stage, - WILL_FIRE_RL_fpu_s3_stage, - WILL_FIRE_RL_fpu_s4_stage, - WILL_FIRE_RL_fpu_s5_stage, - WILL_FIRE_RL_int_div_finish, - WILL_FIRE_RL_int_div_start, - WILL_FIRE_RL_int_div_work, - WILL_FIRE_RL_int_div_work_1, - WILL_FIRE_RL_int_div_work_10, - WILL_FIRE_RL_int_div_work_11, - WILL_FIRE_RL_int_div_work_12, - WILL_FIRE_RL_int_div_work_13, - WILL_FIRE_RL_int_div_work_14, - WILL_FIRE_RL_int_div_work_15, - WILL_FIRE_RL_int_div_work_16, - WILL_FIRE_RL_int_div_work_17, - WILL_FIRE_RL_int_div_work_18, - WILL_FIRE_RL_int_div_work_19, - WILL_FIRE_RL_int_div_work_2, - WILL_FIRE_RL_int_div_work_20, - WILL_FIRE_RL_int_div_work_21, - WILL_FIRE_RL_int_div_work_22, - WILL_FIRE_RL_int_div_work_23, - WILL_FIRE_RL_int_div_work_24, - WILL_FIRE_RL_int_div_work_25, - WILL_FIRE_RL_int_div_work_26, - WILL_FIRE_RL_int_div_work_27, - WILL_FIRE_RL_int_div_work_28, - WILL_FIRE_RL_int_div_work_29, - WILL_FIRE_RL_int_div_work_3, - WILL_FIRE_RL_int_div_work_30, - WILL_FIRE_RL_int_div_work_31, - WILL_FIRE_RL_int_div_work_32, - WILL_FIRE_RL_int_div_work_33, - WILL_FIRE_RL_int_div_work_34, - WILL_FIRE_RL_int_div_work_35, - WILL_FIRE_RL_int_div_work_36, - WILL_FIRE_RL_int_div_work_37, - WILL_FIRE_RL_int_div_work_38, - WILL_FIRE_RL_int_div_work_39, - WILL_FIRE_RL_int_div_work_4, - WILL_FIRE_RL_int_div_work_40, - WILL_FIRE_RL_int_div_work_41, - WILL_FIRE_RL_int_div_work_42, - WILL_FIRE_RL_int_div_work_43, - WILL_FIRE_RL_int_div_work_44, - WILL_FIRE_RL_int_div_work_45, - WILL_FIRE_RL_int_div_work_46, - WILL_FIRE_RL_int_div_work_47, - WILL_FIRE_RL_int_div_work_48, - WILL_FIRE_RL_int_div_work_49, - WILL_FIRE_RL_int_div_work_5, - WILL_FIRE_RL_int_div_work_50, - WILL_FIRE_RL_int_div_work_51, - WILL_FIRE_RL_int_div_work_52, - WILL_FIRE_RL_int_div_work_53, - WILL_FIRE_RL_int_div_work_54, - WILL_FIRE_RL_int_div_work_55, - WILL_FIRE_RL_int_div_work_56, - WILL_FIRE_RL_int_div_work_57, - WILL_FIRE_RL_int_div_work_6, - WILL_FIRE_RL_int_div_work_7, - WILL_FIRE_RL_int_div_work_8, - WILL_FIRE_RL_int_div_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; - // remaining internal signals - reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16; - reg [62 : 0] CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12; - reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, - _theResult___fst_sfd__h37218, - _theResult___fst_sfd__h37707, - _theResult___fst_sfd__h60989; - reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9, - _theResult___fst_exp__h37217, - _theResult___fst_exp__h60988; - reg CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5, - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11; - wire [115 : 0] b__h10163, - b__h10487, - b__h10811, - b__h1091, - b__h11135, - b__h11459, - b__h11783, - b__h12107, - b__h12431, - b__h12755, - b__h13079, - b__h13403, - b__h13727, - b__h14051, - b__h1415, - b__h14375, - b__h14699, - b__h15023, - b__h15347, - b__h15671, - b__h15995, - b__h16319, - b__h16643, - b__h16967, - b__h17291, - b__h1739, - b__h17615, - b__h17939, - b__h18263, - b__h18587, - b__h18911, - b__h19235, - b__h19482, - b__h2063, - b__h2387, - b__h2711, - b__h3035, - b__h3359, - b__h3683, - b__h4007, - b__h4331, - b__h4655, - b__h4979, - b__h5303, - b__h5627, - b__h5951, - b__h6275, - b__h6599, - b__h6923, - b__h7247, - b__h7571, - b__h767, - b__h7895, - b__h8219, - b__h8543, - b__h8867, - b__h9191, - b__h9515, - b__h9839, - value__h19447; - wire [113 : 0] x__h49176; - wire [63 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305, - fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773; - wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7, - IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19, - _theResult____h50063, - _theResult___snd__h52150, - _theResult___snd__h59785, - _theResult___snd__h59800, - _theResult___snd__h59802, - _theResult___snd__h59815, - _theResult___snd__h59821, - _theResult___snd__h59839, - _theResult___snd__h59844, - _theResult___snd_snd_snd__h51398, - b__h378, - int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945, - result__h50077, - result__h50108, - result__h50258, - sfdin__h51553, - sfdin__h59762, - x__h50197, - x__h50487; - wire [56 : 0] value__h50121, x__h49237; - wire [53 : 0] sfd__h60417, value__h49179; - wire [52 : 0] sfdA__h19785, sfdA__h19789, sfdB__h19786, sfdB__h19791; - wire [51 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303, - _theResult___fst_sfd__h60992, - _theResult___sfd__h60911, - _theResult___snd_fst_sfd__h49112, - out_sfd__h60914, - sfd__h36684, - sfd__h36687; - wire [12 : 0] IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205, - value__h49124, - value__h49300; - wire [11 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726; - wire [10 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, - IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, - _theResult___exp__h60910, - _theResult___fst__h49072, - _theResult___fst_exp__h59719, - _theResult___fst_exp__h59722, - _theResult___fst_exp__h59725, - _theResult___fst_exp__h59768, - _theResult___fst_exp__h59771, - _theResult___fst_exp__h59791, - _theResult___fst_exp__h59807, - _theResult___fst_exp__h59846, - _theResult___fst_exp__h59852, - _theResult___fst_exp__h59855, - _theResult___fst_exp__h60991, - _theResult___snd_fst_exp__h49084, - _theResult___snd_fst_exp__h49087, - _theResult___snd_fst_exp__h49111, - din_inc___2_exp__h61001, - fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3, - fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4, - out_exp__h60913, - theResult___fst_exp9725_MINUS_1023__q6, - x__h49291, - x__h50204; - wire [5 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724, - b__h21789, - b__h29207; - wire [4 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765; - wire [1 : 0] IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8, - _theResult___snd_fst__h59874, - guard__h51381, - x__h60140; - wire IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208, - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352, - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441, - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253, - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, - _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351, - fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212, - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, - sfdlsb__h50103; - // action method request_put - assign RDY_request_put = fpu_fOperands_S0$FULL_N ; - assign CAN_FIRE_request_put = fpu_fOperands_S0$FULL_N ; + assign RDY_request_put = fpu$RDY_request_put ; + assign CAN_FIRE_request_put = fpu$RDY_request_put ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu_fResult_S5$D_OUT ; - assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; - assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; + assign response_get = fpu$response_get ; + assign RDY_response_get = fpu$RDY_response_get ; + assign CAN_FIRE_response_get = fpu$RDY_response_get ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu_fOperands_S0 - FIFOL1 #(.width(32'd131)) fpu_fOperands_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fOperands_S0$D_IN), - .ENQ(fpu_fOperands_S0$ENQ), - .DEQ(fpu_fOperands_S0$DEQ), - .CLR(fpu_fOperands_S0$CLR), - .D_OUT(fpu_fOperands_S0$D_OUT), - .FULL_N(fpu_fOperands_S0$FULL_N), - .EMPTY_N(fpu_fOperands_S0$EMPTY_N)); - - // submodule fpu_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fResult_S5$D_IN), - .ENQ(fpu_fResult_S5$ENQ), - .DEQ(fpu_fResult_S5$DEQ), - .CLR(fpu_fResult_S5$CLR), - .D_OUT(fpu_fResult_S5$D_OUT), - .FULL_N(fpu_fResult_S5$FULL_N), - .EMPTY_N(fpu_fResult_S5$EMPTY_N)); - - // submodule fpu_fState_S1 - FIFOL1 #(.width(32'd319)) fpu_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S1$D_IN), - .ENQ(fpu_fState_S1$ENQ), - .DEQ(fpu_fState_S1$DEQ), - .CLR(fpu_fState_S1$CLR), - .D_OUT(fpu_fState_S1$D_OUT), - .FULL_N(fpu_fState_S1$FULL_N), - .EMPTY_N(fpu_fState_S1$EMPTY_N)); - - // submodule fpu_fState_S2 - FIFOL1 #(.width(32'd148)) fpu_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S2$D_IN), - .ENQ(fpu_fState_S2$ENQ), - .DEQ(fpu_fState_S2$DEQ), - .CLR(fpu_fState_S2$CLR), - .D_OUT(fpu_fState_S2$D_OUT), - .FULL_N(fpu_fState_S2$FULL_N), - .EMPTY_N(fpu_fState_S2$EMPTY_N)); - - // submodule fpu_fState_S3 - FIFOL1 #(.width(32'd195)) fpu_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S3$D_IN), - .ENQ(fpu_fState_S3$ENQ), - .DEQ(fpu_fState_S3$DEQ), - .CLR(fpu_fState_S3$CLR), - .D_OUT(fpu_fState_S3$D_OUT), - .FULL_N(fpu_fState_S3$FULL_N), - .EMPTY_N(fpu_fState_S3$EMPTY_N)); - - // submodule fpu_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S4$D_IN), - .ENQ(fpu_fState_S4$ENQ), - .DEQ(fpu_fState_S4$DEQ), - .CLR(fpu_fState_S4$CLR), - .D_OUT(fpu_fState_S4$D_OUT), - .FULL_N(fpu_fState_S4$FULL_N), - .EMPTY_N(fpu_fState_S4$EMPTY_N)); - - // submodule int_div_fFirst - FIFOL1 #(.width(32'd232)) int_div_fFirst(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fFirst$D_IN), - .ENQ(int_div_fFirst$ENQ), - .DEQ(int_div_fFirst$DEQ), - .CLR(int_div_fFirst$CLR), - .D_OUT(int_div_fFirst$D_OUT), - .FULL_N(int_div_fFirst$FULL_N), - .EMPTY_N(int_div_fFirst$EMPTY_N)); - - // submodule int_div_fNext_0 - FIFOL1 #(.width(32'd232)) int_div_fNext_0(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_0$D_IN), - .ENQ(int_div_fNext_0$ENQ), - .DEQ(int_div_fNext_0$DEQ), - .CLR(int_div_fNext_0$CLR), - .D_OUT(int_div_fNext_0$D_OUT), - .FULL_N(int_div_fNext_0$FULL_N), - .EMPTY_N(int_div_fNext_0$EMPTY_N)); - - // submodule int_div_fNext_1 - FIFOL1 #(.width(32'd232)) int_div_fNext_1(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_1$D_IN), - .ENQ(int_div_fNext_1$ENQ), - .DEQ(int_div_fNext_1$DEQ), - .CLR(int_div_fNext_1$CLR), - .D_OUT(int_div_fNext_1$D_OUT), - .FULL_N(int_div_fNext_1$FULL_N), - .EMPTY_N(int_div_fNext_1$EMPTY_N)); - - // submodule int_div_fNext_10 - FIFOL1 #(.width(32'd232)) int_div_fNext_10(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_10$D_IN), - .ENQ(int_div_fNext_10$ENQ), - .DEQ(int_div_fNext_10$DEQ), - .CLR(int_div_fNext_10$CLR), - .D_OUT(int_div_fNext_10$D_OUT), - .FULL_N(int_div_fNext_10$FULL_N), - .EMPTY_N(int_div_fNext_10$EMPTY_N)); - - // submodule int_div_fNext_11 - FIFOL1 #(.width(32'd232)) int_div_fNext_11(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_11$D_IN), - .ENQ(int_div_fNext_11$ENQ), - .DEQ(int_div_fNext_11$DEQ), - .CLR(int_div_fNext_11$CLR), - .D_OUT(int_div_fNext_11$D_OUT), - .FULL_N(int_div_fNext_11$FULL_N), - .EMPTY_N(int_div_fNext_11$EMPTY_N)); - - // submodule int_div_fNext_12 - FIFOL1 #(.width(32'd232)) int_div_fNext_12(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_12$D_IN), - .ENQ(int_div_fNext_12$ENQ), - .DEQ(int_div_fNext_12$DEQ), - .CLR(int_div_fNext_12$CLR), - .D_OUT(int_div_fNext_12$D_OUT), - .FULL_N(int_div_fNext_12$FULL_N), - .EMPTY_N(int_div_fNext_12$EMPTY_N)); - - // submodule int_div_fNext_13 - FIFOL1 #(.width(32'd232)) int_div_fNext_13(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_13$D_IN), - .ENQ(int_div_fNext_13$ENQ), - .DEQ(int_div_fNext_13$DEQ), - .CLR(int_div_fNext_13$CLR), - .D_OUT(int_div_fNext_13$D_OUT), - .FULL_N(int_div_fNext_13$FULL_N), - .EMPTY_N(int_div_fNext_13$EMPTY_N)); - - // submodule int_div_fNext_14 - FIFOL1 #(.width(32'd232)) int_div_fNext_14(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_14$D_IN), - .ENQ(int_div_fNext_14$ENQ), - .DEQ(int_div_fNext_14$DEQ), - .CLR(int_div_fNext_14$CLR), - .D_OUT(int_div_fNext_14$D_OUT), - .FULL_N(int_div_fNext_14$FULL_N), - .EMPTY_N(int_div_fNext_14$EMPTY_N)); - - // submodule int_div_fNext_15 - FIFOL1 #(.width(32'd232)) int_div_fNext_15(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_15$D_IN), - .ENQ(int_div_fNext_15$ENQ), - .DEQ(int_div_fNext_15$DEQ), - .CLR(int_div_fNext_15$CLR), - .D_OUT(int_div_fNext_15$D_OUT), - .FULL_N(int_div_fNext_15$FULL_N), - .EMPTY_N(int_div_fNext_15$EMPTY_N)); - - // submodule int_div_fNext_16 - FIFOL1 #(.width(32'd232)) int_div_fNext_16(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_16$D_IN), - .ENQ(int_div_fNext_16$ENQ), - .DEQ(int_div_fNext_16$DEQ), - .CLR(int_div_fNext_16$CLR), - .D_OUT(int_div_fNext_16$D_OUT), - .FULL_N(int_div_fNext_16$FULL_N), - .EMPTY_N(int_div_fNext_16$EMPTY_N)); - - // submodule int_div_fNext_17 - FIFOL1 #(.width(32'd232)) int_div_fNext_17(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_17$D_IN), - .ENQ(int_div_fNext_17$ENQ), - .DEQ(int_div_fNext_17$DEQ), - .CLR(int_div_fNext_17$CLR), - .D_OUT(int_div_fNext_17$D_OUT), - .FULL_N(int_div_fNext_17$FULL_N), - .EMPTY_N(int_div_fNext_17$EMPTY_N)); - - // submodule int_div_fNext_18 - FIFOL1 #(.width(32'd232)) int_div_fNext_18(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_18$D_IN), - .ENQ(int_div_fNext_18$ENQ), - .DEQ(int_div_fNext_18$DEQ), - .CLR(int_div_fNext_18$CLR), - .D_OUT(int_div_fNext_18$D_OUT), - .FULL_N(int_div_fNext_18$FULL_N), - .EMPTY_N(int_div_fNext_18$EMPTY_N)); - - // submodule int_div_fNext_19 - FIFOL1 #(.width(32'd232)) int_div_fNext_19(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_19$D_IN), - .ENQ(int_div_fNext_19$ENQ), - .DEQ(int_div_fNext_19$DEQ), - .CLR(int_div_fNext_19$CLR), - .D_OUT(int_div_fNext_19$D_OUT), - .FULL_N(int_div_fNext_19$FULL_N), - .EMPTY_N(int_div_fNext_19$EMPTY_N)); - - // submodule int_div_fNext_2 - FIFOL1 #(.width(32'd232)) int_div_fNext_2(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_2$D_IN), - .ENQ(int_div_fNext_2$ENQ), - .DEQ(int_div_fNext_2$DEQ), - .CLR(int_div_fNext_2$CLR), - .D_OUT(int_div_fNext_2$D_OUT), - .FULL_N(int_div_fNext_2$FULL_N), - .EMPTY_N(int_div_fNext_2$EMPTY_N)); - - // submodule int_div_fNext_20 - FIFOL1 #(.width(32'd232)) int_div_fNext_20(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_20$D_IN), - .ENQ(int_div_fNext_20$ENQ), - .DEQ(int_div_fNext_20$DEQ), - .CLR(int_div_fNext_20$CLR), - .D_OUT(int_div_fNext_20$D_OUT), - .FULL_N(int_div_fNext_20$FULL_N), - .EMPTY_N(int_div_fNext_20$EMPTY_N)); - - // submodule int_div_fNext_21 - FIFOL1 #(.width(32'd232)) int_div_fNext_21(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_21$D_IN), - .ENQ(int_div_fNext_21$ENQ), - .DEQ(int_div_fNext_21$DEQ), - .CLR(int_div_fNext_21$CLR), - .D_OUT(int_div_fNext_21$D_OUT), - .FULL_N(int_div_fNext_21$FULL_N), - .EMPTY_N(int_div_fNext_21$EMPTY_N)); - - // submodule int_div_fNext_22 - FIFOL1 #(.width(32'd232)) int_div_fNext_22(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_22$D_IN), - .ENQ(int_div_fNext_22$ENQ), - .DEQ(int_div_fNext_22$DEQ), - .CLR(int_div_fNext_22$CLR), - .D_OUT(int_div_fNext_22$D_OUT), - .FULL_N(int_div_fNext_22$FULL_N), - .EMPTY_N(int_div_fNext_22$EMPTY_N)); - - // submodule int_div_fNext_23 - FIFOL1 #(.width(32'd232)) int_div_fNext_23(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_23$D_IN), - .ENQ(int_div_fNext_23$ENQ), - .DEQ(int_div_fNext_23$DEQ), - .CLR(int_div_fNext_23$CLR), - .D_OUT(int_div_fNext_23$D_OUT), - .FULL_N(int_div_fNext_23$FULL_N), - .EMPTY_N(int_div_fNext_23$EMPTY_N)); - - // submodule int_div_fNext_24 - FIFOL1 #(.width(32'd232)) int_div_fNext_24(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_24$D_IN), - .ENQ(int_div_fNext_24$ENQ), - .DEQ(int_div_fNext_24$DEQ), - .CLR(int_div_fNext_24$CLR), - .D_OUT(int_div_fNext_24$D_OUT), - .FULL_N(int_div_fNext_24$FULL_N), - .EMPTY_N(int_div_fNext_24$EMPTY_N)); - - // submodule int_div_fNext_25 - FIFOL1 #(.width(32'd232)) int_div_fNext_25(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_25$D_IN), - .ENQ(int_div_fNext_25$ENQ), - .DEQ(int_div_fNext_25$DEQ), - .CLR(int_div_fNext_25$CLR), - .D_OUT(int_div_fNext_25$D_OUT), - .FULL_N(int_div_fNext_25$FULL_N), - .EMPTY_N(int_div_fNext_25$EMPTY_N)); - - // submodule int_div_fNext_26 - FIFOL1 #(.width(32'd232)) int_div_fNext_26(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_26$D_IN), - .ENQ(int_div_fNext_26$ENQ), - .DEQ(int_div_fNext_26$DEQ), - .CLR(int_div_fNext_26$CLR), - .D_OUT(int_div_fNext_26$D_OUT), - .FULL_N(int_div_fNext_26$FULL_N), - .EMPTY_N(int_div_fNext_26$EMPTY_N)); - - // submodule int_div_fNext_27 - FIFOL1 #(.width(32'd232)) int_div_fNext_27(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_27$D_IN), - .ENQ(int_div_fNext_27$ENQ), - .DEQ(int_div_fNext_27$DEQ), - .CLR(int_div_fNext_27$CLR), - .D_OUT(int_div_fNext_27$D_OUT), - .FULL_N(int_div_fNext_27$FULL_N), - .EMPTY_N(int_div_fNext_27$EMPTY_N)); - - // submodule int_div_fNext_28 - FIFOL1 #(.width(32'd232)) int_div_fNext_28(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_28$D_IN), - .ENQ(int_div_fNext_28$ENQ), - .DEQ(int_div_fNext_28$DEQ), - .CLR(int_div_fNext_28$CLR), - .D_OUT(int_div_fNext_28$D_OUT), - .FULL_N(int_div_fNext_28$FULL_N), - .EMPTY_N(int_div_fNext_28$EMPTY_N)); - - // submodule int_div_fNext_29 - FIFOL1 #(.width(32'd232)) int_div_fNext_29(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_29$D_IN), - .ENQ(int_div_fNext_29$ENQ), - .DEQ(int_div_fNext_29$DEQ), - .CLR(int_div_fNext_29$CLR), - .D_OUT(int_div_fNext_29$D_OUT), - .FULL_N(int_div_fNext_29$FULL_N), - .EMPTY_N(int_div_fNext_29$EMPTY_N)); - - // submodule int_div_fNext_3 - FIFOL1 #(.width(32'd232)) int_div_fNext_3(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_3$D_IN), - .ENQ(int_div_fNext_3$ENQ), - .DEQ(int_div_fNext_3$DEQ), - .CLR(int_div_fNext_3$CLR), - .D_OUT(int_div_fNext_3$D_OUT), - .FULL_N(int_div_fNext_3$FULL_N), - .EMPTY_N(int_div_fNext_3$EMPTY_N)); - - // submodule int_div_fNext_30 - FIFOL1 #(.width(32'd232)) int_div_fNext_30(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_30$D_IN), - .ENQ(int_div_fNext_30$ENQ), - .DEQ(int_div_fNext_30$DEQ), - .CLR(int_div_fNext_30$CLR), - .D_OUT(int_div_fNext_30$D_OUT), - .FULL_N(int_div_fNext_30$FULL_N), - .EMPTY_N(int_div_fNext_30$EMPTY_N)); - - // submodule int_div_fNext_31 - FIFOL1 #(.width(32'd232)) int_div_fNext_31(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_31$D_IN), - .ENQ(int_div_fNext_31$ENQ), - .DEQ(int_div_fNext_31$DEQ), - .CLR(int_div_fNext_31$CLR), - .D_OUT(int_div_fNext_31$D_OUT), - .FULL_N(int_div_fNext_31$FULL_N), - .EMPTY_N(int_div_fNext_31$EMPTY_N)); - - // submodule int_div_fNext_32 - FIFOL1 #(.width(32'd232)) int_div_fNext_32(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_32$D_IN), - .ENQ(int_div_fNext_32$ENQ), - .DEQ(int_div_fNext_32$DEQ), - .CLR(int_div_fNext_32$CLR), - .D_OUT(int_div_fNext_32$D_OUT), - .FULL_N(int_div_fNext_32$FULL_N), - .EMPTY_N(int_div_fNext_32$EMPTY_N)); - - // submodule int_div_fNext_33 - FIFOL1 #(.width(32'd232)) int_div_fNext_33(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_33$D_IN), - .ENQ(int_div_fNext_33$ENQ), - .DEQ(int_div_fNext_33$DEQ), - .CLR(int_div_fNext_33$CLR), - .D_OUT(int_div_fNext_33$D_OUT), - .FULL_N(int_div_fNext_33$FULL_N), - .EMPTY_N(int_div_fNext_33$EMPTY_N)); - - // submodule int_div_fNext_34 - FIFOL1 #(.width(32'd232)) int_div_fNext_34(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_34$D_IN), - .ENQ(int_div_fNext_34$ENQ), - .DEQ(int_div_fNext_34$DEQ), - .CLR(int_div_fNext_34$CLR), - .D_OUT(int_div_fNext_34$D_OUT), - .FULL_N(int_div_fNext_34$FULL_N), - .EMPTY_N(int_div_fNext_34$EMPTY_N)); - - // submodule int_div_fNext_35 - FIFOL1 #(.width(32'd232)) int_div_fNext_35(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_35$D_IN), - .ENQ(int_div_fNext_35$ENQ), - .DEQ(int_div_fNext_35$DEQ), - .CLR(int_div_fNext_35$CLR), - .D_OUT(int_div_fNext_35$D_OUT), - .FULL_N(int_div_fNext_35$FULL_N), - .EMPTY_N(int_div_fNext_35$EMPTY_N)); - - // submodule int_div_fNext_36 - FIFOL1 #(.width(32'd232)) int_div_fNext_36(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_36$D_IN), - .ENQ(int_div_fNext_36$ENQ), - .DEQ(int_div_fNext_36$DEQ), - .CLR(int_div_fNext_36$CLR), - .D_OUT(int_div_fNext_36$D_OUT), - .FULL_N(int_div_fNext_36$FULL_N), - .EMPTY_N(int_div_fNext_36$EMPTY_N)); - - // submodule int_div_fNext_37 - FIFOL1 #(.width(32'd232)) int_div_fNext_37(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_37$D_IN), - .ENQ(int_div_fNext_37$ENQ), - .DEQ(int_div_fNext_37$DEQ), - .CLR(int_div_fNext_37$CLR), - .D_OUT(int_div_fNext_37$D_OUT), - .FULL_N(int_div_fNext_37$FULL_N), - .EMPTY_N(int_div_fNext_37$EMPTY_N)); - - // submodule int_div_fNext_38 - FIFOL1 #(.width(32'd232)) int_div_fNext_38(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_38$D_IN), - .ENQ(int_div_fNext_38$ENQ), - .DEQ(int_div_fNext_38$DEQ), - .CLR(int_div_fNext_38$CLR), - .D_OUT(int_div_fNext_38$D_OUT), - .FULL_N(int_div_fNext_38$FULL_N), - .EMPTY_N(int_div_fNext_38$EMPTY_N)); - - // submodule int_div_fNext_39 - FIFOL1 #(.width(32'd232)) int_div_fNext_39(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_39$D_IN), - .ENQ(int_div_fNext_39$ENQ), - .DEQ(int_div_fNext_39$DEQ), - .CLR(int_div_fNext_39$CLR), - .D_OUT(int_div_fNext_39$D_OUT), - .FULL_N(int_div_fNext_39$FULL_N), - .EMPTY_N(int_div_fNext_39$EMPTY_N)); - - // submodule int_div_fNext_4 - FIFOL1 #(.width(32'd232)) int_div_fNext_4(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_4$D_IN), - .ENQ(int_div_fNext_4$ENQ), - .DEQ(int_div_fNext_4$DEQ), - .CLR(int_div_fNext_4$CLR), - .D_OUT(int_div_fNext_4$D_OUT), - .FULL_N(int_div_fNext_4$FULL_N), - .EMPTY_N(int_div_fNext_4$EMPTY_N)); - - // submodule int_div_fNext_40 - FIFOL1 #(.width(32'd232)) int_div_fNext_40(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_40$D_IN), - .ENQ(int_div_fNext_40$ENQ), - .DEQ(int_div_fNext_40$DEQ), - .CLR(int_div_fNext_40$CLR), - .D_OUT(int_div_fNext_40$D_OUT), - .FULL_N(int_div_fNext_40$FULL_N), - .EMPTY_N(int_div_fNext_40$EMPTY_N)); - - // submodule int_div_fNext_41 - FIFOL1 #(.width(32'd232)) int_div_fNext_41(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_41$D_IN), - .ENQ(int_div_fNext_41$ENQ), - .DEQ(int_div_fNext_41$DEQ), - .CLR(int_div_fNext_41$CLR), - .D_OUT(int_div_fNext_41$D_OUT), - .FULL_N(int_div_fNext_41$FULL_N), - .EMPTY_N(int_div_fNext_41$EMPTY_N)); - - // submodule int_div_fNext_42 - FIFOL1 #(.width(32'd232)) int_div_fNext_42(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_42$D_IN), - .ENQ(int_div_fNext_42$ENQ), - .DEQ(int_div_fNext_42$DEQ), - .CLR(int_div_fNext_42$CLR), - .D_OUT(int_div_fNext_42$D_OUT), - .FULL_N(int_div_fNext_42$FULL_N), - .EMPTY_N(int_div_fNext_42$EMPTY_N)); - - // submodule int_div_fNext_43 - FIFOL1 #(.width(32'd232)) int_div_fNext_43(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_43$D_IN), - .ENQ(int_div_fNext_43$ENQ), - .DEQ(int_div_fNext_43$DEQ), - .CLR(int_div_fNext_43$CLR), - .D_OUT(int_div_fNext_43$D_OUT), - .FULL_N(int_div_fNext_43$FULL_N), - .EMPTY_N(int_div_fNext_43$EMPTY_N)); - - // submodule int_div_fNext_44 - FIFOL1 #(.width(32'd232)) int_div_fNext_44(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_44$D_IN), - .ENQ(int_div_fNext_44$ENQ), - .DEQ(int_div_fNext_44$DEQ), - .CLR(int_div_fNext_44$CLR), - .D_OUT(int_div_fNext_44$D_OUT), - .FULL_N(int_div_fNext_44$FULL_N), - .EMPTY_N(int_div_fNext_44$EMPTY_N)); - - // submodule int_div_fNext_45 - FIFOL1 #(.width(32'd232)) int_div_fNext_45(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_45$D_IN), - .ENQ(int_div_fNext_45$ENQ), - .DEQ(int_div_fNext_45$DEQ), - .CLR(int_div_fNext_45$CLR), - .D_OUT(int_div_fNext_45$D_OUT), - .FULL_N(int_div_fNext_45$FULL_N), - .EMPTY_N(int_div_fNext_45$EMPTY_N)); - - // submodule int_div_fNext_46 - FIFOL1 #(.width(32'd232)) int_div_fNext_46(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_46$D_IN), - .ENQ(int_div_fNext_46$ENQ), - .DEQ(int_div_fNext_46$DEQ), - .CLR(int_div_fNext_46$CLR), - .D_OUT(int_div_fNext_46$D_OUT), - .FULL_N(int_div_fNext_46$FULL_N), - .EMPTY_N(int_div_fNext_46$EMPTY_N)); - - // submodule int_div_fNext_47 - FIFOL1 #(.width(32'd232)) int_div_fNext_47(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_47$D_IN), - .ENQ(int_div_fNext_47$ENQ), - .DEQ(int_div_fNext_47$DEQ), - .CLR(int_div_fNext_47$CLR), - .D_OUT(int_div_fNext_47$D_OUT), - .FULL_N(int_div_fNext_47$FULL_N), - .EMPTY_N(int_div_fNext_47$EMPTY_N)); - - // submodule int_div_fNext_48 - FIFOL1 #(.width(32'd232)) int_div_fNext_48(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_48$D_IN), - .ENQ(int_div_fNext_48$ENQ), - .DEQ(int_div_fNext_48$DEQ), - .CLR(int_div_fNext_48$CLR), - .D_OUT(int_div_fNext_48$D_OUT), - .FULL_N(int_div_fNext_48$FULL_N), - .EMPTY_N(int_div_fNext_48$EMPTY_N)); - - // submodule int_div_fNext_49 - FIFOL1 #(.width(32'd232)) int_div_fNext_49(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_49$D_IN), - .ENQ(int_div_fNext_49$ENQ), - .DEQ(int_div_fNext_49$DEQ), - .CLR(int_div_fNext_49$CLR), - .D_OUT(int_div_fNext_49$D_OUT), - .FULL_N(int_div_fNext_49$FULL_N), - .EMPTY_N(int_div_fNext_49$EMPTY_N)); - - // submodule int_div_fNext_5 - FIFOL1 #(.width(32'd232)) int_div_fNext_5(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_5$D_IN), - .ENQ(int_div_fNext_5$ENQ), - .DEQ(int_div_fNext_5$DEQ), - .CLR(int_div_fNext_5$CLR), - .D_OUT(int_div_fNext_5$D_OUT), - .FULL_N(int_div_fNext_5$FULL_N), - .EMPTY_N(int_div_fNext_5$EMPTY_N)); - - // submodule int_div_fNext_50 - FIFOL1 #(.width(32'd232)) int_div_fNext_50(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_50$D_IN), - .ENQ(int_div_fNext_50$ENQ), - .DEQ(int_div_fNext_50$DEQ), - .CLR(int_div_fNext_50$CLR), - .D_OUT(int_div_fNext_50$D_OUT), - .FULL_N(int_div_fNext_50$FULL_N), - .EMPTY_N(int_div_fNext_50$EMPTY_N)); - - // submodule int_div_fNext_51 - FIFOL1 #(.width(32'd232)) int_div_fNext_51(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_51$D_IN), - .ENQ(int_div_fNext_51$ENQ), - .DEQ(int_div_fNext_51$DEQ), - .CLR(int_div_fNext_51$CLR), - .D_OUT(int_div_fNext_51$D_OUT), - .FULL_N(int_div_fNext_51$FULL_N), - .EMPTY_N(int_div_fNext_51$EMPTY_N)); - - // submodule int_div_fNext_52 - FIFOL1 #(.width(32'd232)) int_div_fNext_52(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_52$D_IN), - .ENQ(int_div_fNext_52$ENQ), - .DEQ(int_div_fNext_52$DEQ), - .CLR(int_div_fNext_52$CLR), - .D_OUT(int_div_fNext_52$D_OUT), - .FULL_N(int_div_fNext_52$FULL_N), - .EMPTY_N(int_div_fNext_52$EMPTY_N)); - - // submodule int_div_fNext_53 - FIFOL1 #(.width(32'd232)) int_div_fNext_53(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_53$D_IN), - .ENQ(int_div_fNext_53$ENQ), - .DEQ(int_div_fNext_53$DEQ), - .CLR(int_div_fNext_53$CLR), - .D_OUT(int_div_fNext_53$D_OUT), - .FULL_N(int_div_fNext_53$FULL_N), - .EMPTY_N(int_div_fNext_53$EMPTY_N)); - - // submodule int_div_fNext_54 - FIFOL1 #(.width(32'd232)) int_div_fNext_54(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_54$D_IN), - .ENQ(int_div_fNext_54$ENQ), - .DEQ(int_div_fNext_54$DEQ), - .CLR(int_div_fNext_54$CLR), - .D_OUT(int_div_fNext_54$D_OUT), - .FULL_N(int_div_fNext_54$FULL_N), - .EMPTY_N(int_div_fNext_54$EMPTY_N)); - - // submodule int_div_fNext_55 - FIFOL1 #(.width(32'd232)) int_div_fNext_55(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_55$D_IN), - .ENQ(int_div_fNext_55$ENQ), - .DEQ(int_div_fNext_55$DEQ), - .CLR(int_div_fNext_55$CLR), - .D_OUT(int_div_fNext_55$D_OUT), - .FULL_N(int_div_fNext_55$FULL_N), - .EMPTY_N(int_div_fNext_55$EMPTY_N)); - - // submodule int_div_fNext_56 - FIFOL1 #(.width(32'd232)) int_div_fNext_56(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_56$D_IN), - .ENQ(int_div_fNext_56$ENQ), - .DEQ(int_div_fNext_56$DEQ), - .CLR(int_div_fNext_56$CLR), - .D_OUT(int_div_fNext_56$D_OUT), - .FULL_N(int_div_fNext_56$FULL_N), - .EMPTY_N(int_div_fNext_56$EMPTY_N)); - - // submodule int_div_fNext_57 - FIFOL1 #(.width(32'd232)) int_div_fNext_57(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_57$D_IN), - .ENQ(int_div_fNext_57$ENQ), - .DEQ(int_div_fNext_57$DEQ), - .CLR(int_div_fNext_57$CLR), - .D_OUT(int_div_fNext_57$D_OUT), - .FULL_N(int_div_fNext_57$FULL_N), - .EMPTY_N(int_div_fNext_57$EMPTY_N)); - - // submodule int_div_fNext_6 - FIFOL1 #(.width(32'd232)) int_div_fNext_6(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_6$D_IN), - .ENQ(int_div_fNext_6$ENQ), - .DEQ(int_div_fNext_6$DEQ), - .CLR(int_div_fNext_6$CLR), - .D_OUT(int_div_fNext_6$D_OUT), - .FULL_N(int_div_fNext_6$FULL_N), - .EMPTY_N(int_div_fNext_6$EMPTY_N)); - - // submodule int_div_fNext_7 - FIFOL1 #(.width(32'd232)) int_div_fNext_7(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_7$D_IN), - .ENQ(int_div_fNext_7$ENQ), - .DEQ(int_div_fNext_7$DEQ), - .CLR(int_div_fNext_7$CLR), - .D_OUT(int_div_fNext_7$D_OUT), - .FULL_N(int_div_fNext_7$FULL_N), - .EMPTY_N(int_div_fNext_7$EMPTY_N)); - - // submodule int_div_fNext_8 - FIFOL1 #(.width(32'd232)) int_div_fNext_8(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_8$D_IN), - .ENQ(int_div_fNext_8$ENQ), - .DEQ(int_div_fNext_8$DEQ), - .CLR(int_div_fNext_8$CLR), - .D_OUT(int_div_fNext_8$D_OUT), - .FULL_N(int_div_fNext_8$FULL_N), - .EMPTY_N(int_div_fNext_8$EMPTY_N)); - - // submodule int_div_fNext_9 - FIFOL1 #(.width(32'd232)) int_div_fNext_9(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_9$D_IN), - .ENQ(int_div_fNext_9$ENQ), - .DEQ(int_div_fNext_9$DEQ), - .CLR(int_div_fNext_9$CLR), - .D_OUT(int_div_fNext_9$D_OUT), - .FULL_N(int_div_fNext_9$FULL_N), - .EMPTY_N(int_div_fNext_9$EMPTY_N)); - - // submodule int_div_fRequest - FIFOL1 #(.width(32'd171)) int_div_fRequest(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fRequest$D_IN), - .ENQ(int_div_fRequest$ENQ), - .DEQ(int_div_fRequest$DEQ), - .CLR(int_div_fRequest$CLR), - .D_OUT(int_div_fRequest$D_OUT), - .FULL_N(int_div_fRequest$FULL_N), - .EMPTY_N(int_div_fRequest$EMPTY_N)); - - // submodule int_div_fResponse - FIFOL1 #(.width(32'd114)) int_div_fResponse(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fResponse$D_IN), - .ENQ(int_div_fResponse$ENQ), - .DEQ(int_div_fResponse$DEQ), - .CLR(int_div_fResponse$CLR), - .D_OUT(int_div_fResponse$D_OUT), - .FULL_N(int_div_fResponse$FULL_N), - .EMPTY_N(int_div_fResponse$EMPTY_N)); - - // rule RL_fpu_s5_stage - assign CAN_FIRE_RL_fpu_s5_stage = - fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; - - // rule RL_fpu_s4_stage - assign CAN_FIRE_RL_fpu_s4_stage = - fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; - - // rule RL_fpu_s3_stage - assign CAN_FIRE_RL_fpu_s3_stage = - fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && - (fpu_fState_S2$D_OUT[147] || int_div_fResponse$EMPTY_N) ; - assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; - - // rule RL_int_div_finish - assign CAN_FIRE_RL_int_div_finish = - int_div_fNext_57$EMPTY_N && int_div_fResponse$FULL_N ; - assign WILL_FIRE_RL_int_div_finish = CAN_FIRE_RL_int_div_finish ; - - // rule RL_int_div_work_57 - assign CAN_FIRE_RL_int_div_work_57 = - int_div_fNext_56$EMPTY_N && int_div_fNext_57$FULL_N ; - assign WILL_FIRE_RL_int_div_work_57 = CAN_FIRE_RL_int_div_work_57 ; - - // rule RL_int_div_work_56 - assign CAN_FIRE_RL_int_div_work_56 = - int_div_fNext_55$EMPTY_N && int_div_fNext_56$FULL_N ; - assign WILL_FIRE_RL_int_div_work_56 = CAN_FIRE_RL_int_div_work_56 ; - - // rule RL_int_div_work_55 - assign CAN_FIRE_RL_int_div_work_55 = - int_div_fNext_54$EMPTY_N && int_div_fNext_55$FULL_N ; - assign WILL_FIRE_RL_int_div_work_55 = CAN_FIRE_RL_int_div_work_55 ; - - // rule RL_int_div_work_54 - assign CAN_FIRE_RL_int_div_work_54 = - int_div_fNext_53$EMPTY_N && int_div_fNext_54$FULL_N ; - assign WILL_FIRE_RL_int_div_work_54 = CAN_FIRE_RL_int_div_work_54 ; - - // rule RL_int_div_work_53 - assign CAN_FIRE_RL_int_div_work_53 = - int_div_fNext_52$EMPTY_N && int_div_fNext_53$FULL_N ; - assign WILL_FIRE_RL_int_div_work_53 = CAN_FIRE_RL_int_div_work_53 ; - - // rule RL_int_div_work_52 - assign CAN_FIRE_RL_int_div_work_52 = - int_div_fNext_51$EMPTY_N && int_div_fNext_52$FULL_N ; - assign WILL_FIRE_RL_int_div_work_52 = CAN_FIRE_RL_int_div_work_52 ; - - // rule RL_int_div_work_51 - assign CAN_FIRE_RL_int_div_work_51 = - int_div_fNext_50$EMPTY_N && int_div_fNext_51$FULL_N ; - assign WILL_FIRE_RL_int_div_work_51 = CAN_FIRE_RL_int_div_work_51 ; - - // rule RL_int_div_work_50 - assign CAN_FIRE_RL_int_div_work_50 = - int_div_fNext_49$EMPTY_N && int_div_fNext_50$FULL_N ; - assign WILL_FIRE_RL_int_div_work_50 = CAN_FIRE_RL_int_div_work_50 ; - - // rule RL_int_div_work_49 - assign CAN_FIRE_RL_int_div_work_49 = - int_div_fNext_48$EMPTY_N && int_div_fNext_49$FULL_N ; - assign WILL_FIRE_RL_int_div_work_49 = CAN_FIRE_RL_int_div_work_49 ; - - // rule RL_int_div_work_48 - assign CAN_FIRE_RL_int_div_work_48 = - int_div_fNext_47$EMPTY_N && int_div_fNext_48$FULL_N ; - assign WILL_FIRE_RL_int_div_work_48 = CAN_FIRE_RL_int_div_work_48 ; - - // rule RL_int_div_work_47 - assign CAN_FIRE_RL_int_div_work_47 = - int_div_fNext_46$EMPTY_N && int_div_fNext_47$FULL_N ; - assign WILL_FIRE_RL_int_div_work_47 = CAN_FIRE_RL_int_div_work_47 ; - - // rule RL_int_div_work_46 - assign CAN_FIRE_RL_int_div_work_46 = - int_div_fNext_45$EMPTY_N && int_div_fNext_46$FULL_N ; - assign WILL_FIRE_RL_int_div_work_46 = CAN_FIRE_RL_int_div_work_46 ; - - // rule RL_int_div_work_45 - assign CAN_FIRE_RL_int_div_work_45 = - int_div_fNext_44$EMPTY_N && int_div_fNext_45$FULL_N ; - assign WILL_FIRE_RL_int_div_work_45 = CAN_FIRE_RL_int_div_work_45 ; - - // rule RL_int_div_work_44 - assign CAN_FIRE_RL_int_div_work_44 = - int_div_fNext_43$EMPTY_N && int_div_fNext_44$FULL_N ; - assign WILL_FIRE_RL_int_div_work_44 = CAN_FIRE_RL_int_div_work_44 ; - - // rule RL_int_div_work_43 - assign CAN_FIRE_RL_int_div_work_43 = - int_div_fNext_42$EMPTY_N && int_div_fNext_43$FULL_N ; - assign WILL_FIRE_RL_int_div_work_43 = CAN_FIRE_RL_int_div_work_43 ; - - // rule RL_int_div_work_42 - assign CAN_FIRE_RL_int_div_work_42 = - int_div_fNext_41$EMPTY_N && int_div_fNext_42$FULL_N ; - assign WILL_FIRE_RL_int_div_work_42 = CAN_FIRE_RL_int_div_work_42 ; - - // rule RL_int_div_work_41 - assign CAN_FIRE_RL_int_div_work_41 = - int_div_fNext_40$EMPTY_N && int_div_fNext_41$FULL_N ; - assign WILL_FIRE_RL_int_div_work_41 = CAN_FIRE_RL_int_div_work_41 ; - - // rule RL_int_div_work_40 - assign CAN_FIRE_RL_int_div_work_40 = - int_div_fNext_39$EMPTY_N && int_div_fNext_40$FULL_N ; - assign WILL_FIRE_RL_int_div_work_40 = CAN_FIRE_RL_int_div_work_40 ; - - // rule RL_int_div_work_39 - assign CAN_FIRE_RL_int_div_work_39 = - int_div_fNext_38$EMPTY_N && int_div_fNext_39$FULL_N ; - assign WILL_FIRE_RL_int_div_work_39 = CAN_FIRE_RL_int_div_work_39 ; - - // rule RL_int_div_work_38 - assign CAN_FIRE_RL_int_div_work_38 = - int_div_fNext_37$EMPTY_N && int_div_fNext_38$FULL_N ; - assign WILL_FIRE_RL_int_div_work_38 = CAN_FIRE_RL_int_div_work_38 ; - - // rule RL_int_div_work_37 - assign CAN_FIRE_RL_int_div_work_37 = - int_div_fNext_36$EMPTY_N && int_div_fNext_37$FULL_N ; - assign WILL_FIRE_RL_int_div_work_37 = CAN_FIRE_RL_int_div_work_37 ; - - // rule RL_int_div_work_36 - assign CAN_FIRE_RL_int_div_work_36 = - int_div_fNext_35$EMPTY_N && int_div_fNext_36$FULL_N ; - assign WILL_FIRE_RL_int_div_work_36 = CAN_FIRE_RL_int_div_work_36 ; - - // rule RL_int_div_work_35 - assign CAN_FIRE_RL_int_div_work_35 = - int_div_fNext_34$EMPTY_N && int_div_fNext_35$FULL_N ; - assign WILL_FIRE_RL_int_div_work_35 = CAN_FIRE_RL_int_div_work_35 ; - - // rule RL_int_div_work_34 - assign CAN_FIRE_RL_int_div_work_34 = - int_div_fNext_33$EMPTY_N && int_div_fNext_34$FULL_N ; - assign WILL_FIRE_RL_int_div_work_34 = CAN_FIRE_RL_int_div_work_34 ; - - // rule RL_int_div_work_33 - assign CAN_FIRE_RL_int_div_work_33 = - int_div_fNext_32$EMPTY_N && int_div_fNext_33$FULL_N ; - assign WILL_FIRE_RL_int_div_work_33 = CAN_FIRE_RL_int_div_work_33 ; - - // rule RL_int_div_work_32 - assign CAN_FIRE_RL_int_div_work_32 = - int_div_fNext_31$EMPTY_N && int_div_fNext_32$FULL_N ; - assign WILL_FIRE_RL_int_div_work_32 = CAN_FIRE_RL_int_div_work_32 ; - - // rule RL_int_div_work_31 - assign CAN_FIRE_RL_int_div_work_31 = - int_div_fNext_30$EMPTY_N && int_div_fNext_31$FULL_N ; - assign WILL_FIRE_RL_int_div_work_31 = CAN_FIRE_RL_int_div_work_31 ; - - // rule RL_int_div_work_30 - assign CAN_FIRE_RL_int_div_work_30 = - int_div_fNext_29$EMPTY_N && int_div_fNext_30$FULL_N ; - assign WILL_FIRE_RL_int_div_work_30 = CAN_FIRE_RL_int_div_work_30 ; - - // rule RL_int_div_work_29 - assign CAN_FIRE_RL_int_div_work_29 = - int_div_fNext_28$EMPTY_N && int_div_fNext_29$FULL_N ; - assign WILL_FIRE_RL_int_div_work_29 = CAN_FIRE_RL_int_div_work_29 ; - - // rule RL_int_div_work_28 - assign CAN_FIRE_RL_int_div_work_28 = - int_div_fNext_27$EMPTY_N && int_div_fNext_28$FULL_N ; - assign WILL_FIRE_RL_int_div_work_28 = CAN_FIRE_RL_int_div_work_28 ; - - // rule RL_int_div_work_27 - assign CAN_FIRE_RL_int_div_work_27 = - int_div_fNext_26$EMPTY_N && int_div_fNext_27$FULL_N ; - assign WILL_FIRE_RL_int_div_work_27 = CAN_FIRE_RL_int_div_work_27 ; - - // rule RL_int_div_work_26 - assign CAN_FIRE_RL_int_div_work_26 = - int_div_fNext_25$EMPTY_N && int_div_fNext_26$FULL_N ; - assign WILL_FIRE_RL_int_div_work_26 = CAN_FIRE_RL_int_div_work_26 ; - - // rule RL_int_div_work_25 - assign CAN_FIRE_RL_int_div_work_25 = - int_div_fNext_24$EMPTY_N && int_div_fNext_25$FULL_N ; - assign WILL_FIRE_RL_int_div_work_25 = CAN_FIRE_RL_int_div_work_25 ; - - // rule RL_int_div_work_24 - assign CAN_FIRE_RL_int_div_work_24 = - int_div_fNext_23$EMPTY_N && int_div_fNext_24$FULL_N ; - assign WILL_FIRE_RL_int_div_work_24 = CAN_FIRE_RL_int_div_work_24 ; - - // rule RL_int_div_work_23 - assign CAN_FIRE_RL_int_div_work_23 = - int_div_fNext_22$EMPTY_N && int_div_fNext_23$FULL_N ; - assign WILL_FIRE_RL_int_div_work_23 = CAN_FIRE_RL_int_div_work_23 ; - - // rule RL_int_div_work_22 - assign CAN_FIRE_RL_int_div_work_22 = - int_div_fNext_21$EMPTY_N && int_div_fNext_22$FULL_N ; - assign WILL_FIRE_RL_int_div_work_22 = CAN_FIRE_RL_int_div_work_22 ; - - // rule RL_int_div_work_21 - assign CAN_FIRE_RL_int_div_work_21 = - int_div_fNext_20$EMPTY_N && int_div_fNext_21$FULL_N ; - assign WILL_FIRE_RL_int_div_work_21 = CAN_FIRE_RL_int_div_work_21 ; - - // rule RL_int_div_work_20 - assign CAN_FIRE_RL_int_div_work_20 = - int_div_fNext_19$EMPTY_N && int_div_fNext_20$FULL_N ; - assign WILL_FIRE_RL_int_div_work_20 = CAN_FIRE_RL_int_div_work_20 ; - - // rule RL_int_div_work_19 - assign CAN_FIRE_RL_int_div_work_19 = - int_div_fNext_18$EMPTY_N && int_div_fNext_19$FULL_N ; - assign WILL_FIRE_RL_int_div_work_19 = CAN_FIRE_RL_int_div_work_19 ; - - // rule RL_int_div_work_18 - assign CAN_FIRE_RL_int_div_work_18 = - int_div_fNext_17$EMPTY_N && int_div_fNext_18$FULL_N ; - assign WILL_FIRE_RL_int_div_work_18 = CAN_FIRE_RL_int_div_work_18 ; - - // rule RL_int_div_work_17 - assign CAN_FIRE_RL_int_div_work_17 = - int_div_fNext_16$EMPTY_N && int_div_fNext_17$FULL_N ; - assign WILL_FIRE_RL_int_div_work_17 = CAN_FIRE_RL_int_div_work_17 ; - - // rule RL_int_div_work_16 - assign CAN_FIRE_RL_int_div_work_16 = - int_div_fNext_15$EMPTY_N && int_div_fNext_16$FULL_N ; - assign WILL_FIRE_RL_int_div_work_16 = CAN_FIRE_RL_int_div_work_16 ; - - // rule RL_int_div_work_15 - assign CAN_FIRE_RL_int_div_work_15 = - int_div_fNext_14$EMPTY_N && int_div_fNext_15$FULL_N ; - assign WILL_FIRE_RL_int_div_work_15 = CAN_FIRE_RL_int_div_work_15 ; - - // rule RL_int_div_work_14 - assign CAN_FIRE_RL_int_div_work_14 = - int_div_fNext_13$EMPTY_N && int_div_fNext_14$FULL_N ; - assign WILL_FIRE_RL_int_div_work_14 = CAN_FIRE_RL_int_div_work_14 ; - - // rule RL_int_div_work_13 - assign CAN_FIRE_RL_int_div_work_13 = - int_div_fNext_12$EMPTY_N && int_div_fNext_13$FULL_N ; - assign WILL_FIRE_RL_int_div_work_13 = CAN_FIRE_RL_int_div_work_13 ; - - // rule RL_int_div_work_12 - assign CAN_FIRE_RL_int_div_work_12 = - int_div_fNext_11$EMPTY_N && int_div_fNext_12$FULL_N ; - assign WILL_FIRE_RL_int_div_work_12 = CAN_FIRE_RL_int_div_work_12 ; - - // rule RL_int_div_work_11 - assign CAN_FIRE_RL_int_div_work_11 = - int_div_fNext_10$EMPTY_N && int_div_fNext_11$FULL_N ; - assign WILL_FIRE_RL_int_div_work_11 = CAN_FIRE_RL_int_div_work_11 ; - - // rule RL_int_div_work_10 - assign CAN_FIRE_RL_int_div_work_10 = - int_div_fNext_9$EMPTY_N && int_div_fNext_10$FULL_N ; - assign WILL_FIRE_RL_int_div_work_10 = CAN_FIRE_RL_int_div_work_10 ; - - // rule RL_int_div_work_9 - assign CAN_FIRE_RL_int_div_work_9 = - int_div_fNext_8$EMPTY_N && int_div_fNext_9$FULL_N ; - assign WILL_FIRE_RL_int_div_work_9 = CAN_FIRE_RL_int_div_work_9 ; - - // rule RL_int_div_work_8 - assign CAN_FIRE_RL_int_div_work_8 = - int_div_fNext_7$EMPTY_N && int_div_fNext_8$FULL_N ; - assign WILL_FIRE_RL_int_div_work_8 = CAN_FIRE_RL_int_div_work_8 ; - - // rule RL_int_div_work_7 - assign CAN_FIRE_RL_int_div_work_7 = - int_div_fNext_6$EMPTY_N && int_div_fNext_7$FULL_N ; - assign WILL_FIRE_RL_int_div_work_7 = CAN_FIRE_RL_int_div_work_7 ; - - // rule RL_int_div_work_6 - assign CAN_FIRE_RL_int_div_work_6 = - int_div_fNext_5$EMPTY_N && int_div_fNext_6$FULL_N ; - assign WILL_FIRE_RL_int_div_work_6 = CAN_FIRE_RL_int_div_work_6 ; - - // rule RL_int_div_work_5 - assign CAN_FIRE_RL_int_div_work_5 = - int_div_fNext_4$EMPTY_N && int_div_fNext_5$FULL_N ; - assign WILL_FIRE_RL_int_div_work_5 = CAN_FIRE_RL_int_div_work_5 ; - - // rule RL_int_div_work_4 - assign CAN_FIRE_RL_int_div_work_4 = - int_div_fNext_3$EMPTY_N && int_div_fNext_4$FULL_N ; - assign WILL_FIRE_RL_int_div_work_4 = CAN_FIRE_RL_int_div_work_4 ; - - // rule RL_int_div_work_3 - assign CAN_FIRE_RL_int_div_work_3 = - int_div_fNext_2$EMPTY_N && int_div_fNext_3$FULL_N ; - assign WILL_FIRE_RL_int_div_work_3 = CAN_FIRE_RL_int_div_work_3 ; - - // rule RL_int_div_work_2 - assign CAN_FIRE_RL_int_div_work_2 = - int_div_fNext_1$EMPTY_N && int_div_fNext_2$FULL_N ; - assign WILL_FIRE_RL_int_div_work_2 = CAN_FIRE_RL_int_div_work_2 ; - - // rule RL_int_div_work_1 - assign CAN_FIRE_RL_int_div_work_1 = - int_div_fNext_0$EMPTY_N && int_div_fNext_1$FULL_N ; - assign WILL_FIRE_RL_int_div_work_1 = CAN_FIRE_RL_int_div_work_1 ; - - // rule RL_int_div_work - assign CAN_FIRE_RL_int_div_work = - int_div_fFirst$EMPTY_N && int_div_fNext_0$FULL_N ; - assign WILL_FIRE_RL_int_div_work = CAN_FIRE_RL_int_div_work ; - - // rule RL_int_div_start - assign CAN_FIRE_RL_int_div_start = - int_div_fRequest$EMPTY_N && int_div_fFirst$FULL_N ; - assign WILL_FIRE_RL_int_div_start = CAN_FIRE_RL_int_div_start ; - - // rule RL_fpu_s2_stage - assign CAN_FIRE_RL_fpu_s2_stage = - fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && - (fpu_fState_S1$D_OUT[318] || int_div_fRequest$FULL_N) ; - assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; - - // rule RL_fpu_s1_stage - assign CAN_FIRE_RL_fpu_s1_stage = - fpu_fOperands_S0$EMPTY_N && fpu_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; - - // submodule fpu_fOperands_S0 - assign fpu_fOperands_S0$D_IN = request_put ; - assign fpu_fOperands_S0$ENQ = EN_request_put ; - assign fpu_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fOperands_S0$CLR = 1'b0 ; - - // submodule fpu_fResult_S5 - assign fpu_fResult_S5$D_IN = - fpu_fState_S4$D_OUT[138] ? - fpu_fState_S4$D_OUT[137:69] : - { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[65:2] : - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16, - fpu_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h60991 == 11'd2047 && - _theResult___fst_sfd__h60992 == 52'd0, - 1'd0, - fpu_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fResult_S5$DEQ = EN_response_get ; - assign fpu_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_fState_S1 - assign fpu_fState_S1$D_IN = - { fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, - (fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118]) ? - { fpu_fOperands_S0$D_OUT[130:119], sfd__h36684 } : - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54] || - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0), - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, - fpu_fOperands_S0$D_OUT[2:0], - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, - _theResult___snd_fst_exp__h49111, - _theResult___snd_fst_sfd__h49112, - x__h49176, - x__h49237, - x__h49291 } ; - assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S1$CLR = 1'b0 ; - - // submodule fpu_fState_S2 - assign fpu_fState_S2$D_IN = - { fpu_fState_S1$D_OUT[318:182], fpu_fState_S1$D_OUT[10:0] } ; - assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S2$CLR = 1'b0 ; - - // submodule fpu_fState_S3 - assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT[147:11], x__h50487 } ; - assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S3$CLR = 1'b0 ; - - // submodule fpu_fState_S4 - assign fpu_fState_S4$D_IN = - { (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[194] : - fpu_fState_S3$D_OUT[194], - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - fpu_fState_S3$D_OUT[193:130] : - { CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 }) : - fpu_fState_S3$D_OUT[193:130], - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, - fpu_fState_S3$D_OUT[124:122], - fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780, - x__h60140 } ; - assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S4$CLR = 1'b0 ; - - // submodule int_div_fFirst - assign int_div_fFirst$D_IN = - { b__h378, 60'd0, int_div_fRequest$D_OUT[170:57] } ; - assign int_div_fFirst$ENQ = CAN_FIRE_RL_int_div_start ; - assign int_div_fFirst$DEQ = CAN_FIRE_RL_int_div_work ; - assign int_div_fFirst$CLR = 1'b0 ; - - // submodule int_div_fNext_0 - assign int_div_fNext_0$D_IN = - { int_div_fFirst$D_OUT[231:174], - int_div_fFirst$D_OUT[172:116], - !int_div_fFirst$D_OUT[115], - int_div_fFirst$D_OUT[115] ? - { int_div_fFirst$D_OUT[114:0], 1'd0 } + b__h767 : - { int_div_fFirst$D_OUT[114:0], 1'd0 } - b__h767 } ; - assign int_div_fNext_0$ENQ = CAN_FIRE_RL_int_div_work ; - assign int_div_fNext_0$DEQ = CAN_FIRE_RL_int_div_work_1 ; - assign int_div_fNext_0$CLR = 1'b0 ; - - // submodule int_div_fNext_1 - assign int_div_fNext_1$D_IN = - { int_div_fNext_0$D_OUT[231:174], - int_div_fNext_0$D_OUT[172:116], - !int_div_fNext_0$D_OUT[115], - int_div_fNext_0$D_OUT[115] ? - { int_div_fNext_0$D_OUT[114:0], 1'd0 } + b__h1091 : - { int_div_fNext_0$D_OUT[114:0], 1'd0 } - b__h1091 } ; - assign int_div_fNext_1$ENQ = CAN_FIRE_RL_int_div_work_1 ; - assign int_div_fNext_1$DEQ = CAN_FIRE_RL_int_div_work_2 ; - assign int_div_fNext_1$CLR = 1'b0 ; - - // submodule int_div_fNext_10 - assign int_div_fNext_10$D_IN = - { int_div_fNext_9$D_OUT[231:174], - int_div_fNext_9$D_OUT[172:116], - !int_div_fNext_9$D_OUT[115], - int_div_fNext_9$D_OUT[115] ? - { int_div_fNext_9$D_OUT[114:0], 1'd0 } + b__h4007 : - { int_div_fNext_9$D_OUT[114:0], 1'd0 } - b__h4007 } ; - assign int_div_fNext_10$ENQ = CAN_FIRE_RL_int_div_work_10 ; - assign int_div_fNext_10$DEQ = CAN_FIRE_RL_int_div_work_11 ; - assign int_div_fNext_10$CLR = 1'b0 ; - - // submodule int_div_fNext_11 - assign int_div_fNext_11$D_IN = - { int_div_fNext_10$D_OUT[231:174], - int_div_fNext_10$D_OUT[172:116], - !int_div_fNext_10$D_OUT[115], - int_div_fNext_10$D_OUT[115] ? - { int_div_fNext_10$D_OUT[114:0], 1'd0 } + b__h4331 : - { int_div_fNext_10$D_OUT[114:0], 1'd0 } - b__h4331 } ; - assign int_div_fNext_11$ENQ = CAN_FIRE_RL_int_div_work_11 ; - assign int_div_fNext_11$DEQ = CAN_FIRE_RL_int_div_work_12 ; - assign int_div_fNext_11$CLR = 1'b0 ; - - // submodule int_div_fNext_12 - assign int_div_fNext_12$D_IN = - { int_div_fNext_11$D_OUT[231:174], - int_div_fNext_11$D_OUT[172:116], - !int_div_fNext_11$D_OUT[115], - int_div_fNext_11$D_OUT[115] ? - { int_div_fNext_11$D_OUT[114:0], 1'd0 } + b__h4655 : - { int_div_fNext_11$D_OUT[114:0], 1'd0 } - b__h4655 } ; - assign int_div_fNext_12$ENQ = CAN_FIRE_RL_int_div_work_12 ; - assign int_div_fNext_12$DEQ = CAN_FIRE_RL_int_div_work_13 ; - assign int_div_fNext_12$CLR = 1'b0 ; - - // submodule int_div_fNext_13 - assign int_div_fNext_13$D_IN = - { int_div_fNext_12$D_OUT[231:174], - int_div_fNext_12$D_OUT[172:116], - !int_div_fNext_12$D_OUT[115], - int_div_fNext_12$D_OUT[115] ? - { int_div_fNext_12$D_OUT[114:0], 1'd0 } + b__h4979 : - { int_div_fNext_12$D_OUT[114:0], 1'd0 } - b__h4979 } ; - assign int_div_fNext_13$ENQ = CAN_FIRE_RL_int_div_work_13 ; - assign int_div_fNext_13$DEQ = CAN_FIRE_RL_int_div_work_14 ; - assign int_div_fNext_13$CLR = 1'b0 ; - - // submodule int_div_fNext_14 - assign int_div_fNext_14$D_IN = - { int_div_fNext_13$D_OUT[231:174], - int_div_fNext_13$D_OUT[172:116], - !int_div_fNext_13$D_OUT[115], - int_div_fNext_13$D_OUT[115] ? - { int_div_fNext_13$D_OUT[114:0], 1'd0 } + b__h5303 : - { int_div_fNext_13$D_OUT[114:0], 1'd0 } - b__h5303 } ; - assign int_div_fNext_14$ENQ = CAN_FIRE_RL_int_div_work_14 ; - assign int_div_fNext_14$DEQ = CAN_FIRE_RL_int_div_work_15 ; - assign int_div_fNext_14$CLR = 1'b0 ; - - // submodule int_div_fNext_15 - assign int_div_fNext_15$D_IN = - { int_div_fNext_14$D_OUT[231:174], - int_div_fNext_14$D_OUT[172:116], - !int_div_fNext_14$D_OUT[115], - int_div_fNext_14$D_OUT[115] ? - { int_div_fNext_14$D_OUT[114:0], 1'd0 } + b__h5627 : - { int_div_fNext_14$D_OUT[114:0], 1'd0 } - b__h5627 } ; - assign int_div_fNext_15$ENQ = CAN_FIRE_RL_int_div_work_15 ; - assign int_div_fNext_15$DEQ = CAN_FIRE_RL_int_div_work_16 ; - assign int_div_fNext_15$CLR = 1'b0 ; - - // submodule int_div_fNext_16 - assign int_div_fNext_16$D_IN = - { int_div_fNext_15$D_OUT[231:174], - int_div_fNext_15$D_OUT[172:116], - !int_div_fNext_15$D_OUT[115], - int_div_fNext_15$D_OUT[115] ? - { int_div_fNext_15$D_OUT[114:0], 1'd0 } + b__h5951 : - { int_div_fNext_15$D_OUT[114:0], 1'd0 } - b__h5951 } ; - assign int_div_fNext_16$ENQ = CAN_FIRE_RL_int_div_work_16 ; - assign int_div_fNext_16$DEQ = CAN_FIRE_RL_int_div_work_17 ; - assign int_div_fNext_16$CLR = 1'b0 ; - - // submodule int_div_fNext_17 - assign int_div_fNext_17$D_IN = - { int_div_fNext_16$D_OUT[231:174], - int_div_fNext_16$D_OUT[172:116], - !int_div_fNext_16$D_OUT[115], - int_div_fNext_16$D_OUT[115] ? - { int_div_fNext_16$D_OUT[114:0], 1'd0 } + b__h6275 : - { int_div_fNext_16$D_OUT[114:0], 1'd0 } - b__h6275 } ; - assign int_div_fNext_17$ENQ = CAN_FIRE_RL_int_div_work_17 ; - assign int_div_fNext_17$DEQ = CAN_FIRE_RL_int_div_work_18 ; - assign int_div_fNext_17$CLR = 1'b0 ; - - // submodule int_div_fNext_18 - assign int_div_fNext_18$D_IN = - { int_div_fNext_17$D_OUT[231:174], - int_div_fNext_17$D_OUT[172:116], - !int_div_fNext_17$D_OUT[115], - int_div_fNext_17$D_OUT[115] ? - { int_div_fNext_17$D_OUT[114:0], 1'd0 } + b__h6599 : - { int_div_fNext_17$D_OUT[114:0], 1'd0 } - b__h6599 } ; - assign int_div_fNext_18$ENQ = CAN_FIRE_RL_int_div_work_18 ; - assign int_div_fNext_18$DEQ = CAN_FIRE_RL_int_div_work_19 ; - assign int_div_fNext_18$CLR = 1'b0 ; - - // submodule int_div_fNext_19 - assign int_div_fNext_19$D_IN = - { int_div_fNext_18$D_OUT[231:174], - int_div_fNext_18$D_OUT[172:116], - !int_div_fNext_18$D_OUT[115], - int_div_fNext_18$D_OUT[115] ? - { int_div_fNext_18$D_OUT[114:0], 1'd0 } + b__h6923 : - { int_div_fNext_18$D_OUT[114:0], 1'd0 } - b__h6923 } ; - assign int_div_fNext_19$ENQ = CAN_FIRE_RL_int_div_work_19 ; - assign int_div_fNext_19$DEQ = CAN_FIRE_RL_int_div_work_20 ; - assign int_div_fNext_19$CLR = 1'b0 ; - - // submodule int_div_fNext_2 - assign int_div_fNext_2$D_IN = - { int_div_fNext_1$D_OUT[231:174], - int_div_fNext_1$D_OUT[172:116], - !int_div_fNext_1$D_OUT[115], - int_div_fNext_1$D_OUT[115] ? - { int_div_fNext_1$D_OUT[114:0], 1'd0 } + b__h1415 : - { int_div_fNext_1$D_OUT[114:0], 1'd0 } - b__h1415 } ; - assign int_div_fNext_2$ENQ = CAN_FIRE_RL_int_div_work_2 ; - assign int_div_fNext_2$DEQ = CAN_FIRE_RL_int_div_work_3 ; - assign int_div_fNext_2$CLR = 1'b0 ; - - // submodule int_div_fNext_20 - assign int_div_fNext_20$D_IN = - { int_div_fNext_19$D_OUT[231:174], - int_div_fNext_19$D_OUT[172:116], - !int_div_fNext_19$D_OUT[115], - int_div_fNext_19$D_OUT[115] ? - { int_div_fNext_19$D_OUT[114:0], 1'd0 } + b__h7247 : - { int_div_fNext_19$D_OUT[114:0], 1'd0 } - b__h7247 } ; - assign int_div_fNext_20$ENQ = CAN_FIRE_RL_int_div_work_20 ; - assign int_div_fNext_20$DEQ = CAN_FIRE_RL_int_div_work_21 ; - assign int_div_fNext_20$CLR = 1'b0 ; - - // submodule int_div_fNext_21 - assign int_div_fNext_21$D_IN = - { int_div_fNext_20$D_OUT[231:174], - int_div_fNext_20$D_OUT[172:116], - !int_div_fNext_20$D_OUT[115], - int_div_fNext_20$D_OUT[115] ? - { int_div_fNext_20$D_OUT[114:0], 1'd0 } + b__h7571 : - { int_div_fNext_20$D_OUT[114:0], 1'd0 } - b__h7571 } ; - assign int_div_fNext_21$ENQ = CAN_FIRE_RL_int_div_work_21 ; - assign int_div_fNext_21$DEQ = CAN_FIRE_RL_int_div_work_22 ; - assign int_div_fNext_21$CLR = 1'b0 ; - - // submodule int_div_fNext_22 - assign int_div_fNext_22$D_IN = - { int_div_fNext_21$D_OUT[231:174], - int_div_fNext_21$D_OUT[172:116], - !int_div_fNext_21$D_OUT[115], - int_div_fNext_21$D_OUT[115] ? - { int_div_fNext_21$D_OUT[114:0], 1'd0 } + b__h7895 : - { int_div_fNext_21$D_OUT[114:0], 1'd0 } - b__h7895 } ; - assign int_div_fNext_22$ENQ = CAN_FIRE_RL_int_div_work_22 ; - assign int_div_fNext_22$DEQ = CAN_FIRE_RL_int_div_work_23 ; - assign int_div_fNext_22$CLR = 1'b0 ; - - // submodule int_div_fNext_23 - assign int_div_fNext_23$D_IN = - { int_div_fNext_22$D_OUT[231:174], - int_div_fNext_22$D_OUT[172:116], - !int_div_fNext_22$D_OUT[115], - int_div_fNext_22$D_OUT[115] ? - { int_div_fNext_22$D_OUT[114:0], 1'd0 } + b__h8219 : - { int_div_fNext_22$D_OUT[114:0], 1'd0 } - b__h8219 } ; - assign int_div_fNext_23$ENQ = CAN_FIRE_RL_int_div_work_23 ; - assign int_div_fNext_23$DEQ = CAN_FIRE_RL_int_div_work_24 ; - assign int_div_fNext_23$CLR = 1'b0 ; - - // submodule int_div_fNext_24 - assign int_div_fNext_24$D_IN = - { int_div_fNext_23$D_OUT[231:174], - int_div_fNext_23$D_OUT[172:116], - !int_div_fNext_23$D_OUT[115], - int_div_fNext_23$D_OUT[115] ? - { int_div_fNext_23$D_OUT[114:0], 1'd0 } + b__h8543 : - { int_div_fNext_23$D_OUT[114:0], 1'd0 } - b__h8543 } ; - assign int_div_fNext_24$ENQ = CAN_FIRE_RL_int_div_work_24 ; - assign int_div_fNext_24$DEQ = CAN_FIRE_RL_int_div_work_25 ; - assign int_div_fNext_24$CLR = 1'b0 ; - - // submodule int_div_fNext_25 - assign int_div_fNext_25$D_IN = - { int_div_fNext_24$D_OUT[231:174], - int_div_fNext_24$D_OUT[172:116], - !int_div_fNext_24$D_OUT[115], - int_div_fNext_24$D_OUT[115] ? - { int_div_fNext_24$D_OUT[114:0], 1'd0 } + b__h8867 : - { int_div_fNext_24$D_OUT[114:0], 1'd0 } - b__h8867 } ; - assign int_div_fNext_25$ENQ = CAN_FIRE_RL_int_div_work_25 ; - assign int_div_fNext_25$DEQ = CAN_FIRE_RL_int_div_work_26 ; - assign int_div_fNext_25$CLR = 1'b0 ; - - // submodule int_div_fNext_26 - assign int_div_fNext_26$D_IN = - { int_div_fNext_25$D_OUT[231:174], - int_div_fNext_25$D_OUT[172:116], - !int_div_fNext_25$D_OUT[115], - int_div_fNext_25$D_OUT[115] ? - { int_div_fNext_25$D_OUT[114:0], 1'd0 } + b__h9191 : - { int_div_fNext_25$D_OUT[114:0], 1'd0 } - b__h9191 } ; - assign int_div_fNext_26$ENQ = CAN_FIRE_RL_int_div_work_26 ; - assign int_div_fNext_26$DEQ = CAN_FIRE_RL_int_div_work_27 ; - assign int_div_fNext_26$CLR = 1'b0 ; - - // submodule int_div_fNext_27 - assign int_div_fNext_27$D_IN = - { int_div_fNext_26$D_OUT[231:174], - int_div_fNext_26$D_OUT[172:116], - !int_div_fNext_26$D_OUT[115], - int_div_fNext_26$D_OUT[115] ? - { int_div_fNext_26$D_OUT[114:0], 1'd0 } + b__h9515 : - { int_div_fNext_26$D_OUT[114:0], 1'd0 } - b__h9515 } ; - assign int_div_fNext_27$ENQ = CAN_FIRE_RL_int_div_work_27 ; - assign int_div_fNext_27$DEQ = CAN_FIRE_RL_int_div_work_28 ; - assign int_div_fNext_27$CLR = 1'b0 ; - - // submodule int_div_fNext_28 - assign int_div_fNext_28$D_IN = - { int_div_fNext_27$D_OUT[231:174], - int_div_fNext_27$D_OUT[172:116], - !int_div_fNext_27$D_OUT[115], - int_div_fNext_27$D_OUT[115] ? - { int_div_fNext_27$D_OUT[114:0], 1'd0 } + b__h9839 : - { int_div_fNext_27$D_OUT[114:0], 1'd0 } - b__h9839 } ; - assign int_div_fNext_28$ENQ = CAN_FIRE_RL_int_div_work_28 ; - assign int_div_fNext_28$DEQ = CAN_FIRE_RL_int_div_work_29 ; - assign int_div_fNext_28$CLR = 1'b0 ; - - // submodule int_div_fNext_29 - assign int_div_fNext_29$D_IN = - { int_div_fNext_28$D_OUT[231:174], - int_div_fNext_28$D_OUT[172:116], - !int_div_fNext_28$D_OUT[115], - int_div_fNext_28$D_OUT[115] ? - { int_div_fNext_28$D_OUT[114:0], 1'd0 } + b__h10163 : - { int_div_fNext_28$D_OUT[114:0], 1'd0 } - b__h10163 } ; - assign int_div_fNext_29$ENQ = CAN_FIRE_RL_int_div_work_29 ; - assign int_div_fNext_29$DEQ = CAN_FIRE_RL_int_div_work_30 ; - assign int_div_fNext_29$CLR = 1'b0 ; - - // submodule int_div_fNext_3 - assign int_div_fNext_3$D_IN = - { int_div_fNext_2$D_OUT[231:174], - int_div_fNext_2$D_OUT[172:116], - !int_div_fNext_2$D_OUT[115], - int_div_fNext_2$D_OUT[115] ? - { int_div_fNext_2$D_OUT[114:0], 1'd0 } + b__h1739 : - { int_div_fNext_2$D_OUT[114:0], 1'd0 } - b__h1739 } ; - assign int_div_fNext_3$ENQ = CAN_FIRE_RL_int_div_work_3 ; - assign int_div_fNext_3$DEQ = CAN_FIRE_RL_int_div_work_4 ; - assign int_div_fNext_3$CLR = 1'b0 ; - - // submodule int_div_fNext_30 - assign int_div_fNext_30$D_IN = - { int_div_fNext_29$D_OUT[231:174], - int_div_fNext_29$D_OUT[172:116], - !int_div_fNext_29$D_OUT[115], - int_div_fNext_29$D_OUT[115] ? - { int_div_fNext_29$D_OUT[114:0], 1'd0 } + b__h10487 : - { int_div_fNext_29$D_OUT[114:0], 1'd0 } - b__h10487 } ; - assign int_div_fNext_30$ENQ = CAN_FIRE_RL_int_div_work_30 ; - assign int_div_fNext_30$DEQ = CAN_FIRE_RL_int_div_work_31 ; - assign int_div_fNext_30$CLR = 1'b0 ; - - // submodule int_div_fNext_31 - assign int_div_fNext_31$D_IN = - { int_div_fNext_30$D_OUT[231:174], - int_div_fNext_30$D_OUT[172:116], - !int_div_fNext_30$D_OUT[115], - int_div_fNext_30$D_OUT[115] ? - { int_div_fNext_30$D_OUT[114:0], 1'd0 } + b__h10811 : - { int_div_fNext_30$D_OUT[114:0], 1'd0 } - b__h10811 } ; - assign int_div_fNext_31$ENQ = CAN_FIRE_RL_int_div_work_31 ; - assign int_div_fNext_31$DEQ = CAN_FIRE_RL_int_div_work_32 ; - assign int_div_fNext_31$CLR = 1'b0 ; - - // submodule int_div_fNext_32 - assign int_div_fNext_32$D_IN = - { int_div_fNext_31$D_OUT[231:174], - int_div_fNext_31$D_OUT[172:116], - !int_div_fNext_31$D_OUT[115], - int_div_fNext_31$D_OUT[115] ? - { int_div_fNext_31$D_OUT[114:0], 1'd0 } + b__h11135 : - { int_div_fNext_31$D_OUT[114:0], 1'd0 } - b__h11135 } ; - assign int_div_fNext_32$ENQ = CAN_FIRE_RL_int_div_work_32 ; - assign int_div_fNext_32$DEQ = CAN_FIRE_RL_int_div_work_33 ; - assign int_div_fNext_32$CLR = 1'b0 ; - - // submodule int_div_fNext_33 - assign int_div_fNext_33$D_IN = - { int_div_fNext_32$D_OUT[231:174], - int_div_fNext_32$D_OUT[172:116], - !int_div_fNext_32$D_OUT[115], - int_div_fNext_32$D_OUT[115] ? - { int_div_fNext_32$D_OUT[114:0], 1'd0 } + b__h11459 : - { int_div_fNext_32$D_OUT[114:0], 1'd0 } - b__h11459 } ; - assign int_div_fNext_33$ENQ = CAN_FIRE_RL_int_div_work_33 ; - assign int_div_fNext_33$DEQ = CAN_FIRE_RL_int_div_work_34 ; - assign int_div_fNext_33$CLR = 1'b0 ; - - // submodule int_div_fNext_34 - assign int_div_fNext_34$D_IN = - { int_div_fNext_33$D_OUT[231:174], - int_div_fNext_33$D_OUT[172:116], - !int_div_fNext_33$D_OUT[115], - int_div_fNext_33$D_OUT[115] ? - { int_div_fNext_33$D_OUT[114:0], 1'd0 } + b__h11783 : - { int_div_fNext_33$D_OUT[114:0], 1'd0 } - b__h11783 } ; - assign int_div_fNext_34$ENQ = CAN_FIRE_RL_int_div_work_34 ; - assign int_div_fNext_34$DEQ = CAN_FIRE_RL_int_div_work_35 ; - assign int_div_fNext_34$CLR = 1'b0 ; - - // submodule int_div_fNext_35 - assign int_div_fNext_35$D_IN = - { int_div_fNext_34$D_OUT[231:174], - int_div_fNext_34$D_OUT[172:116], - !int_div_fNext_34$D_OUT[115], - int_div_fNext_34$D_OUT[115] ? - { int_div_fNext_34$D_OUT[114:0], 1'd0 } + b__h12107 : - { int_div_fNext_34$D_OUT[114:0], 1'd0 } - b__h12107 } ; - assign int_div_fNext_35$ENQ = CAN_FIRE_RL_int_div_work_35 ; - assign int_div_fNext_35$DEQ = CAN_FIRE_RL_int_div_work_36 ; - assign int_div_fNext_35$CLR = 1'b0 ; - - // submodule int_div_fNext_36 - assign int_div_fNext_36$D_IN = - { int_div_fNext_35$D_OUT[231:174], - int_div_fNext_35$D_OUT[172:116], - !int_div_fNext_35$D_OUT[115], - int_div_fNext_35$D_OUT[115] ? - { int_div_fNext_35$D_OUT[114:0], 1'd0 } + b__h12431 : - { int_div_fNext_35$D_OUT[114:0], 1'd0 } - b__h12431 } ; - assign int_div_fNext_36$ENQ = CAN_FIRE_RL_int_div_work_36 ; - assign int_div_fNext_36$DEQ = CAN_FIRE_RL_int_div_work_37 ; - assign int_div_fNext_36$CLR = 1'b0 ; - - // submodule int_div_fNext_37 - assign int_div_fNext_37$D_IN = - { int_div_fNext_36$D_OUT[231:174], - int_div_fNext_36$D_OUT[172:116], - !int_div_fNext_36$D_OUT[115], - int_div_fNext_36$D_OUT[115] ? - { int_div_fNext_36$D_OUT[114:0], 1'd0 } + b__h12755 : - { int_div_fNext_36$D_OUT[114:0], 1'd0 } - b__h12755 } ; - assign int_div_fNext_37$ENQ = CAN_FIRE_RL_int_div_work_37 ; - assign int_div_fNext_37$DEQ = CAN_FIRE_RL_int_div_work_38 ; - assign int_div_fNext_37$CLR = 1'b0 ; - - // submodule int_div_fNext_38 - assign int_div_fNext_38$D_IN = - { int_div_fNext_37$D_OUT[231:174], - int_div_fNext_37$D_OUT[172:116], - !int_div_fNext_37$D_OUT[115], - int_div_fNext_37$D_OUT[115] ? - { int_div_fNext_37$D_OUT[114:0], 1'd0 } + b__h13079 : - { int_div_fNext_37$D_OUT[114:0], 1'd0 } - b__h13079 } ; - assign int_div_fNext_38$ENQ = CAN_FIRE_RL_int_div_work_38 ; - assign int_div_fNext_38$DEQ = CAN_FIRE_RL_int_div_work_39 ; - assign int_div_fNext_38$CLR = 1'b0 ; - - // submodule int_div_fNext_39 - assign int_div_fNext_39$D_IN = - { int_div_fNext_38$D_OUT[231:174], - int_div_fNext_38$D_OUT[172:116], - !int_div_fNext_38$D_OUT[115], - int_div_fNext_38$D_OUT[115] ? - { int_div_fNext_38$D_OUT[114:0], 1'd0 } + b__h13403 : - { int_div_fNext_38$D_OUT[114:0], 1'd0 } - b__h13403 } ; - assign int_div_fNext_39$ENQ = CAN_FIRE_RL_int_div_work_39 ; - assign int_div_fNext_39$DEQ = CAN_FIRE_RL_int_div_work_40 ; - assign int_div_fNext_39$CLR = 1'b0 ; - - // submodule int_div_fNext_4 - assign int_div_fNext_4$D_IN = - { int_div_fNext_3$D_OUT[231:174], - int_div_fNext_3$D_OUT[172:116], - !int_div_fNext_3$D_OUT[115], - int_div_fNext_3$D_OUT[115] ? - { int_div_fNext_3$D_OUT[114:0], 1'd0 } + b__h2063 : - { int_div_fNext_3$D_OUT[114:0], 1'd0 } - b__h2063 } ; - assign int_div_fNext_4$ENQ = CAN_FIRE_RL_int_div_work_4 ; - assign int_div_fNext_4$DEQ = CAN_FIRE_RL_int_div_work_5 ; - assign int_div_fNext_4$CLR = 1'b0 ; - - // submodule int_div_fNext_40 - assign int_div_fNext_40$D_IN = - { int_div_fNext_39$D_OUT[231:174], - int_div_fNext_39$D_OUT[172:116], - !int_div_fNext_39$D_OUT[115], - int_div_fNext_39$D_OUT[115] ? - { int_div_fNext_39$D_OUT[114:0], 1'd0 } + b__h13727 : - { int_div_fNext_39$D_OUT[114:0], 1'd0 } - b__h13727 } ; - assign int_div_fNext_40$ENQ = CAN_FIRE_RL_int_div_work_40 ; - assign int_div_fNext_40$DEQ = CAN_FIRE_RL_int_div_work_41 ; - assign int_div_fNext_40$CLR = 1'b0 ; - - // submodule int_div_fNext_41 - assign int_div_fNext_41$D_IN = - { int_div_fNext_40$D_OUT[231:174], - int_div_fNext_40$D_OUT[172:116], - !int_div_fNext_40$D_OUT[115], - int_div_fNext_40$D_OUT[115] ? - { int_div_fNext_40$D_OUT[114:0], 1'd0 } + b__h14051 : - { int_div_fNext_40$D_OUT[114:0], 1'd0 } - b__h14051 } ; - assign int_div_fNext_41$ENQ = CAN_FIRE_RL_int_div_work_41 ; - assign int_div_fNext_41$DEQ = CAN_FIRE_RL_int_div_work_42 ; - assign int_div_fNext_41$CLR = 1'b0 ; - - // submodule int_div_fNext_42 - assign int_div_fNext_42$D_IN = - { int_div_fNext_41$D_OUT[231:174], - int_div_fNext_41$D_OUT[172:116], - !int_div_fNext_41$D_OUT[115], - int_div_fNext_41$D_OUT[115] ? - { int_div_fNext_41$D_OUT[114:0], 1'd0 } + b__h14375 : - { int_div_fNext_41$D_OUT[114:0], 1'd0 } - b__h14375 } ; - assign int_div_fNext_42$ENQ = CAN_FIRE_RL_int_div_work_42 ; - assign int_div_fNext_42$DEQ = CAN_FIRE_RL_int_div_work_43 ; - assign int_div_fNext_42$CLR = 1'b0 ; - - // submodule int_div_fNext_43 - assign int_div_fNext_43$D_IN = - { int_div_fNext_42$D_OUT[231:174], - int_div_fNext_42$D_OUT[172:116], - !int_div_fNext_42$D_OUT[115], - int_div_fNext_42$D_OUT[115] ? - { int_div_fNext_42$D_OUT[114:0], 1'd0 } + b__h14699 : - { int_div_fNext_42$D_OUT[114:0], 1'd0 } - b__h14699 } ; - assign int_div_fNext_43$ENQ = CAN_FIRE_RL_int_div_work_43 ; - assign int_div_fNext_43$DEQ = CAN_FIRE_RL_int_div_work_44 ; - assign int_div_fNext_43$CLR = 1'b0 ; - - // submodule int_div_fNext_44 - assign int_div_fNext_44$D_IN = - { int_div_fNext_43$D_OUT[231:174], - int_div_fNext_43$D_OUT[172:116], - !int_div_fNext_43$D_OUT[115], - int_div_fNext_43$D_OUT[115] ? - { int_div_fNext_43$D_OUT[114:0], 1'd0 } + b__h15023 : - { int_div_fNext_43$D_OUT[114:0], 1'd0 } - b__h15023 } ; - assign int_div_fNext_44$ENQ = CAN_FIRE_RL_int_div_work_44 ; - assign int_div_fNext_44$DEQ = CAN_FIRE_RL_int_div_work_45 ; - assign int_div_fNext_44$CLR = 1'b0 ; - - // submodule int_div_fNext_45 - assign int_div_fNext_45$D_IN = - { int_div_fNext_44$D_OUT[231:174], - int_div_fNext_44$D_OUT[172:116], - !int_div_fNext_44$D_OUT[115], - int_div_fNext_44$D_OUT[115] ? - { int_div_fNext_44$D_OUT[114:0], 1'd0 } + b__h15347 : - { int_div_fNext_44$D_OUT[114:0], 1'd0 } - b__h15347 } ; - assign int_div_fNext_45$ENQ = CAN_FIRE_RL_int_div_work_45 ; - assign int_div_fNext_45$DEQ = CAN_FIRE_RL_int_div_work_46 ; - assign int_div_fNext_45$CLR = 1'b0 ; - - // submodule int_div_fNext_46 - assign int_div_fNext_46$D_IN = - { int_div_fNext_45$D_OUT[231:174], - int_div_fNext_45$D_OUT[172:116], - !int_div_fNext_45$D_OUT[115], - int_div_fNext_45$D_OUT[115] ? - { int_div_fNext_45$D_OUT[114:0], 1'd0 } + b__h15671 : - { int_div_fNext_45$D_OUT[114:0], 1'd0 } - b__h15671 } ; - assign int_div_fNext_46$ENQ = CAN_FIRE_RL_int_div_work_46 ; - assign int_div_fNext_46$DEQ = CAN_FIRE_RL_int_div_work_47 ; - assign int_div_fNext_46$CLR = 1'b0 ; - - // submodule int_div_fNext_47 - assign int_div_fNext_47$D_IN = - { int_div_fNext_46$D_OUT[231:174], - int_div_fNext_46$D_OUT[172:116], - !int_div_fNext_46$D_OUT[115], - int_div_fNext_46$D_OUT[115] ? - { int_div_fNext_46$D_OUT[114:0], 1'd0 } + b__h15995 : - { int_div_fNext_46$D_OUT[114:0], 1'd0 } - b__h15995 } ; - assign int_div_fNext_47$ENQ = CAN_FIRE_RL_int_div_work_47 ; - assign int_div_fNext_47$DEQ = CAN_FIRE_RL_int_div_work_48 ; - assign int_div_fNext_47$CLR = 1'b0 ; - - // submodule int_div_fNext_48 - assign int_div_fNext_48$D_IN = - { int_div_fNext_47$D_OUT[231:174], - int_div_fNext_47$D_OUT[172:116], - !int_div_fNext_47$D_OUT[115], - int_div_fNext_47$D_OUT[115] ? - { int_div_fNext_47$D_OUT[114:0], 1'd0 } + b__h16319 : - { int_div_fNext_47$D_OUT[114:0], 1'd0 } - b__h16319 } ; - assign int_div_fNext_48$ENQ = CAN_FIRE_RL_int_div_work_48 ; - assign int_div_fNext_48$DEQ = CAN_FIRE_RL_int_div_work_49 ; - assign int_div_fNext_48$CLR = 1'b0 ; - - // submodule int_div_fNext_49 - assign int_div_fNext_49$D_IN = - { int_div_fNext_48$D_OUT[231:174], - int_div_fNext_48$D_OUT[172:116], - !int_div_fNext_48$D_OUT[115], - int_div_fNext_48$D_OUT[115] ? - { int_div_fNext_48$D_OUT[114:0], 1'd0 } + b__h16643 : - { int_div_fNext_48$D_OUT[114:0], 1'd0 } - b__h16643 } ; - assign int_div_fNext_49$ENQ = CAN_FIRE_RL_int_div_work_49 ; - assign int_div_fNext_49$DEQ = CAN_FIRE_RL_int_div_work_50 ; - assign int_div_fNext_49$CLR = 1'b0 ; - - // submodule int_div_fNext_5 - assign int_div_fNext_5$D_IN = - { int_div_fNext_4$D_OUT[231:174], - int_div_fNext_4$D_OUT[172:116], - !int_div_fNext_4$D_OUT[115], - int_div_fNext_4$D_OUT[115] ? - { int_div_fNext_4$D_OUT[114:0], 1'd0 } + b__h2387 : - { int_div_fNext_4$D_OUT[114:0], 1'd0 } - b__h2387 } ; - assign int_div_fNext_5$ENQ = CAN_FIRE_RL_int_div_work_5 ; - assign int_div_fNext_5$DEQ = CAN_FIRE_RL_int_div_work_6 ; - assign int_div_fNext_5$CLR = 1'b0 ; - - // submodule int_div_fNext_50 - assign int_div_fNext_50$D_IN = - { int_div_fNext_49$D_OUT[231:174], - int_div_fNext_49$D_OUT[172:116], - !int_div_fNext_49$D_OUT[115], - int_div_fNext_49$D_OUT[115] ? - { int_div_fNext_49$D_OUT[114:0], 1'd0 } + b__h16967 : - { int_div_fNext_49$D_OUT[114:0], 1'd0 } - b__h16967 } ; - assign int_div_fNext_50$ENQ = CAN_FIRE_RL_int_div_work_50 ; - assign int_div_fNext_50$DEQ = CAN_FIRE_RL_int_div_work_51 ; - assign int_div_fNext_50$CLR = 1'b0 ; - - // submodule int_div_fNext_51 - assign int_div_fNext_51$D_IN = - { int_div_fNext_50$D_OUT[231:174], - int_div_fNext_50$D_OUT[172:116], - !int_div_fNext_50$D_OUT[115], - int_div_fNext_50$D_OUT[115] ? - { int_div_fNext_50$D_OUT[114:0], 1'd0 } + b__h17291 : - { int_div_fNext_50$D_OUT[114:0], 1'd0 } - b__h17291 } ; - assign int_div_fNext_51$ENQ = CAN_FIRE_RL_int_div_work_51 ; - assign int_div_fNext_51$DEQ = CAN_FIRE_RL_int_div_work_52 ; - assign int_div_fNext_51$CLR = 1'b0 ; - - // submodule int_div_fNext_52 - assign int_div_fNext_52$D_IN = - { int_div_fNext_51$D_OUT[231:174], - int_div_fNext_51$D_OUT[172:116], - !int_div_fNext_51$D_OUT[115], - int_div_fNext_51$D_OUT[115] ? - { int_div_fNext_51$D_OUT[114:0], 1'd0 } + b__h17615 : - { int_div_fNext_51$D_OUT[114:0], 1'd0 } - b__h17615 } ; - assign int_div_fNext_52$ENQ = CAN_FIRE_RL_int_div_work_52 ; - assign int_div_fNext_52$DEQ = CAN_FIRE_RL_int_div_work_53 ; - assign int_div_fNext_52$CLR = 1'b0 ; - - // submodule int_div_fNext_53 - assign int_div_fNext_53$D_IN = - { int_div_fNext_52$D_OUT[231:174], - int_div_fNext_52$D_OUT[172:116], - !int_div_fNext_52$D_OUT[115], - int_div_fNext_52$D_OUT[115] ? - { int_div_fNext_52$D_OUT[114:0], 1'd0 } + b__h17939 : - { int_div_fNext_52$D_OUT[114:0], 1'd0 } - b__h17939 } ; - assign int_div_fNext_53$ENQ = CAN_FIRE_RL_int_div_work_53 ; - assign int_div_fNext_53$DEQ = CAN_FIRE_RL_int_div_work_54 ; - assign int_div_fNext_53$CLR = 1'b0 ; - - // submodule int_div_fNext_54 - assign int_div_fNext_54$D_IN = - { int_div_fNext_53$D_OUT[231:174], - int_div_fNext_53$D_OUT[172:116], - !int_div_fNext_53$D_OUT[115], - int_div_fNext_53$D_OUT[115] ? - { int_div_fNext_53$D_OUT[114:0], 1'd0 } + b__h18263 : - { int_div_fNext_53$D_OUT[114:0], 1'd0 } - b__h18263 } ; - assign int_div_fNext_54$ENQ = CAN_FIRE_RL_int_div_work_54 ; - assign int_div_fNext_54$DEQ = CAN_FIRE_RL_int_div_work_55 ; - assign int_div_fNext_54$CLR = 1'b0 ; - - // submodule int_div_fNext_55 - assign int_div_fNext_55$D_IN = - { int_div_fNext_54$D_OUT[231:174], - int_div_fNext_54$D_OUT[172:116], - !int_div_fNext_54$D_OUT[115], - int_div_fNext_54$D_OUT[115] ? - { int_div_fNext_54$D_OUT[114:0], 1'd0 } + b__h18587 : - { int_div_fNext_54$D_OUT[114:0], 1'd0 } - b__h18587 } ; - assign int_div_fNext_55$ENQ = CAN_FIRE_RL_int_div_work_55 ; - assign int_div_fNext_55$DEQ = CAN_FIRE_RL_int_div_work_56 ; - assign int_div_fNext_55$CLR = 1'b0 ; - - // submodule int_div_fNext_56 - assign int_div_fNext_56$D_IN = - { int_div_fNext_55$D_OUT[231:174], - int_div_fNext_55$D_OUT[172:116], - !int_div_fNext_55$D_OUT[115], - int_div_fNext_55$D_OUT[115] ? - { int_div_fNext_55$D_OUT[114:0], 1'd0 } + b__h18911 : - { int_div_fNext_55$D_OUT[114:0], 1'd0 } - b__h18911 } ; - assign int_div_fNext_56$ENQ = CAN_FIRE_RL_int_div_work_56 ; - assign int_div_fNext_56$DEQ = CAN_FIRE_RL_int_div_work_57 ; - assign int_div_fNext_56$CLR = 1'b0 ; - - // submodule int_div_fNext_57 - assign int_div_fNext_57$D_IN = - { int_div_fNext_56$D_OUT[231:174], - int_div_fNext_56$D_OUT[172:116], - !int_div_fNext_56$D_OUT[115], - int_div_fNext_56$D_OUT[115] ? - { int_div_fNext_56$D_OUT[114:0], 1'd0 } + b__h19235 : - { int_div_fNext_56$D_OUT[114:0], 1'd0 } - b__h19235 } ; - assign int_div_fNext_57$ENQ = CAN_FIRE_RL_int_div_work_57 ; - assign int_div_fNext_57$DEQ = CAN_FIRE_RL_int_div_finish ; - assign int_div_fNext_57$CLR = 1'b0 ; - - // submodule int_div_fNext_6 - assign int_div_fNext_6$D_IN = - { int_div_fNext_5$D_OUT[231:174], - int_div_fNext_5$D_OUT[172:116], - !int_div_fNext_5$D_OUT[115], - int_div_fNext_5$D_OUT[115] ? - { int_div_fNext_5$D_OUT[114:0], 1'd0 } + b__h2711 : - { int_div_fNext_5$D_OUT[114:0], 1'd0 } - b__h2711 } ; - assign int_div_fNext_6$ENQ = CAN_FIRE_RL_int_div_work_6 ; - assign int_div_fNext_6$DEQ = CAN_FIRE_RL_int_div_work_7 ; - assign int_div_fNext_6$CLR = 1'b0 ; - - // submodule int_div_fNext_7 - assign int_div_fNext_7$D_IN = - { int_div_fNext_6$D_OUT[231:174], - int_div_fNext_6$D_OUT[172:116], - !int_div_fNext_6$D_OUT[115], - int_div_fNext_6$D_OUT[115] ? - { int_div_fNext_6$D_OUT[114:0], 1'd0 } + b__h3035 : - { int_div_fNext_6$D_OUT[114:0], 1'd0 } - b__h3035 } ; - assign int_div_fNext_7$ENQ = CAN_FIRE_RL_int_div_work_7 ; - assign int_div_fNext_7$DEQ = CAN_FIRE_RL_int_div_work_8 ; - assign int_div_fNext_7$CLR = 1'b0 ; - - // submodule int_div_fNext_8 - assign int_div_fNext_8$D_IN = - { int_div_fNext_7$D_OUT[231:174], - int_div_fNext_7$D_OUT[172:116], - !int_div_fNext_7$D_OUT[115], - int_div_fNext_7$D_OUT[115] ? - { int_div_fNext_7$D_OUT[114:0], 1'd0 } + b__h3359 : - { int_div_fNext_7$D_OUT[114:0], 1'd0 } - b__h3359 } ; - assign int_div_fNext_8$ENQ = CAN_FIRE_RL_int_div_work_8 ; - assign int_div_fNext_8$DEQ = CAN_FIRE_RL_int_div_work_9 ; - assign int_div_fNext_8$CLR = 1'b0 ; - - // submodule int_div_fNext_9 - assign int_div_fNext_9$D_IN = - { int_div_fNext_8$D_OUT[231:174], - int_div_fNext_8$D_OUT[172:116], - !int_div_fNext_8$D_OUT[115], - int_div_fNext_8$D_OUT[115] ? - { int_div_fNext_8$D_OUT[114:0], 1'd0 } + b__h3683 : - { int_div_fNext_8$D_OUT[114:0], 1'd0 } - b__h3683 } ; - assign int_div_fNext_9$ENQ = CAN_FIRE_RL_int_div_work_9 ; - assign int_div_fNext_9$DEQ = CAN_FIRE_RL_int_div_work_10 ; - assign int_div_fNext_9$CLR = 1'b0 ; - - // submodule int_div_fRequest - assign int_div_fRequest$D_IN = fpu_fState_S1$D_OUT[181:11] ; - assign int_div_fRequest$ENQ = - WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[318] ; - assign int_div_fRequest$DEQ = CAN_FIRE_RL_int_div_start ; - assign int_div_fRequest$CLR = 1'b0 ; - - // submodule int_div_fResponse - assign int_div_fResponse$D_IN = - { IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19[56:0], - value__h19447[114:58] } ; - assign int_div_fResponse$ENQ = CAN_FIRE_RL_int_div_finish ; - assign int_div_fResponse$DEQ = - WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[147] ; - assign int_div_fResponse$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7 = - _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 ? - _theResult___snd__h59844 : - _theResult___snd__h59839 ; - assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 = - sfd__h60417[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h61001, sfd__h60417[52:1] }) : - { IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, - sfd__h60417[51:0] } ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 = - (_theResult___fst_exp__h59725 == 11'd0) ? - 12'd3074 : - { theResult___fst_exp9725_MINUS_1023__q6[10], - theResult___fst_exp9725_MINUS_1023__q6 } ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 = - (sfdin__h51553[57] ? - 6'd0 : - (sfdin__h51553[56] ? - 6'd1 : - (sfdin__h51553[55] ? - 6'd2 : - (sfdin__h51553[54] ? - 6'd3 : - (sfdin__h51553[53] ? - 6'd4 : - (sfdin__h51553[52] ? - 6'd5 : - (sfdin__h51553[51] ? - 6'd6 : - (sfdin__h51553[50] ? - 6'd7 : - (sfdin__h51553[49] ? - 6'd8 : - (sfdin__h51553[48] ? - 6'd9 : - (sfdin__h51553[47] ? - 6'd10 : - (sfdin__h51553[46] ? - 6'd11 : - (sfdin__h51553[45] ? - 6'd12 : - (sfdin__h51553[44] ? - 6'd13 : - (sfdin__h51553[43] ? - 6'd14 : - (sfdin__h51553[42] ? - 6'd15 : - (sfdin__h51553[41] ? - 6'd16 : - (sfdin__h51553[40] ? - 6'd17 : - (sfdin__h51553[39] ? - 6'd18 : - (sfdin__h51553[38] ? - 6'd19 : - (sfdin__h51553[37] ? - 6'd20 : - (sfdin__h51553[36] ? - 6'd21 : - (sfdin__h51553[35] ? - 6'd22 : - (sfdin__h51553[34] ? - 6'd23 : - (sfdin__h51553[33] ? - 6'd24 : - (sfdin__h51553[32] ? - 6'd25 : - (sfdin__h51553[31] ? - 6'd26 : - (sfdin__h51553[30] ? - 6'd27 : - (sfdin__h51553[29] ? - 6'd28 : - (sfdin__h51553[28] ? - 6'd29 : - (sfdin__h51553[27] ? - 6'd30 : - (sfdin__h51553[26] ? - 6'd31 : - (sfdin__h51553[25] ? - 6'd32 : - (sfdin__h51553[24] ? - 6'd33 : - (sfdin__h51553[23] ? - 6'd34 : - (sfdin__h51553[22] ? - 6'd35 : - (sfdin__h51553[21] ? - 6'd36 : - (sfdin__h51553[20] ? - 6'd37 : - (sfdin__h51553[19] ? - 6'd38 : - (sfdin__h51553[18] ? - 6'd39 : - (sfdin__h51553[17] ? - 6'd40 : - (sfdin__h51553[16] ? - 6'd41 : - (sfdin__h51553[15] ? - 6'd42 : - (sfdin__h51553[14] ? - 6'd43 : - (sfdin__h51553[13] ? - 6'd44 : - (sfdin__h51553[12] ? - 6'd45 : - (sfdin__h51553[11] ? - 6'd46 : - (sfdin__h51553[10] ? - 6'd47 : - (sfdin__h51553[9] ? - 6'd48 : - (sfdin__h51553[8] ? - 6'd49 : - (sfdin__h51553[7] ? - 6'd50 : - (sfdin__h51553[6] ? - 6'd51 : - (sfdin__h51553[5] ? - 6'd52 : - (sfdin__h51553[4] ? - 6'd53 : - (sfdin__h51553[3] ? - 6'd54 : - (sfdin__h51553[2] ? - 6'd55 : - (sfdin__h51553[1] ? - 6'd56 : - (sfdin__h51553[0] ? - 6'd57 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 = - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 - - 12'd3074 ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770 = - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 : - { fpu_fState_S3$D_OUT[129:128], - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[127] : - fpu_fState_S3$D_OUT[127], - fpu_fState_S3$D_OUT[126], - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[125] : - fpu_fState_S3$D_OUT[125] } ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 = - (sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h59768, sfdin__h59762[57:6] } ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 = - (((fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3[10]}}, - fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 }) - - { 7'd0, b__h21789 }) - - (((fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4[10]}}, - fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 }) - - { 7'd0, b__h29207 }) ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ - 13'h1000) <= - 13'd5120 ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ - 13'h1000) < - 13'd3020 ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ - 13'h1000) < - 13'd3074 ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 : - CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0) ? - 11'd2047 : - ((fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? - 11'd0 : - _theResult___fst_exp__h37217) ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? - 52'd0 : - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? - _theResult___fst_sfd__h37707 : - _theResult___fst_sfd__h37218) ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54]) ? - { fpu_fOperands_S0$D_OUT[66:55], sfd__h36687 } : - ((fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118]) ? - fpu_fOperands_S0$D_OUT[130:67] : - ((fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54]) ? - fpu_fOperands_S0$D_OUT[66:3] : - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305)) ; - assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 = - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] == 2'b0 && - !fpu_fState_S3$D_OUT[194] : - !fpu_fState_S3$D_OUT[194] ; - assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 = - ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - { fpu_fState_S3$D_OUT[129:128], - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[127], - fpu_fState_S3$D_OUT[126], - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[125] } : - fpu_fState_S3$D_OUT[129:125]) | - { 2'd0, - sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023, - _theResult___fst_exp__h59771 == 11'd0 && guard__h51381 != 2'd0, - sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023 } ; - assign IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 = - (fpu_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h60417[53:52] == 2'b01) ? - 11'd1 : - fpu_fState_S4$D_OUT[64:54] ; - assign IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19 = - int_div_fNext_57$D_OUT[115] ? - int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 - - 58'd1 : - int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 ; - assign IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8 = - sfdin__h59762[5] ? 2'd2 : 2'd0 ; - assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 = - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) ; - assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305 = - { NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 ? - 52'h8000000000000 : - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 } ; - assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334 = - (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 && - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; - assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341 = - (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208) ; - assign _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 = - ({ 6'd0, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ^ - 12'h800) <= - (IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ^ - 12'h800) ; - assign _theResult____h50063 = - (fpu_fState_S2$D_OUT[10:0] < 11'd58) ? - result__h50108 : - result__h50258 ; - assign _theResult___exp__h60910 = - sfd__h60417[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h61001) : - IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 ; - assign _theResult___fst__h49072 = - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 ? - value__h49300[10:0] : - 11'd0 ; - assign _theResult___fst_exp__h59719 = fpu_fState_S3$D_OUT[120:110] - 11'd1 ; - assign _theResult___fst_exp__h59722 = - (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___fst_exp__h59719 : - 11'd2046 ; - assign _theResult___fst_exp__h59725 = - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___fst_exp__h59722 : - fpu_fState_S3$D_OUT[120:110] ; - assign _theResult___fst_exp__h59768 = - sfdin__h51553[57] ? - _theResult___fst_exp__h59791 : - _theResult___fst_exp__h59855 ; - assign _theResult___fst_exp__h59771 = - (sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h59768 ; - assign _theResult___fst_exp__h59791 = - (_theResult___fst_exp__h59725 == 11'd0) ? - 11'd2 : - _theResult___fst_exp__h59725 + 11'd1 ; - assign _theResult___fst_exp__h59807 = - (_theResult___fst_exp__h59725 == 11'd0) ? - 11'd1 : - _theResult___fst_exp__h59725 ; - assign _theResult___fst_exp__h59846 = - _theResult___fst_exp__h59725 - - { 5'd0, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ; - assign _theResult___fst_exp__h59852 = - (!sfdin__h51553[57] && !sfdin__h51553[56] && - !sfdin__h51553[55] && - !sfdin__h51553[54] && - !sfdin__h51553[53] && - !sfdin__h51553[52] && - !sfdin__h51553[51] && - !sfdin__h51553[50] && - !sfdin__h51553[49] && - !sfdin__h51553[48] && - !sfdin__h51553[47] && - !sfdin__h51553[46] && - !sfdin__h51553[45] && - !sfdin__h51553[44] && - !sfdin__h51553[43] && - !sfdin__h51553[42] && - !sfdin__h51553[41] && - !sfdin__h51553[40] && - !sfdin__h51553[39] && - !sfdin__h51553[38] && - !sfdin__h51553[37] && - !sfdin__h51553[36] && - !sfdin__h51553[35] && - !sfdin__h51553[34] && - !sfdin__h51553[33] && - !sfdin__h51553[32] && - !sfdin__h51553[31] && - !sfdin__h51553[30] && - !sfdin__h51553[29] && - !sfdin__h51553[28] && - !sfdin__h51553[27] && - !sfdin__h51553[26] && - !sfdin__h51553[25] && - !sfdin__h51553[24] && - !sfdin__h51553[23] && - !sfdin__h51553[22] && - !sfdin__h51553[21] && - !sfdin__h51553[20] && - !sfdin__h51553[19] && - !sfdin__h51553[18] && - !sfdin__h51553[17] && - !sfdin__h51553[16] && - !sfdin__h51553[15] && - !sfdin__h51553[14] && - !sfdin__h51553[13] && - !sfdin__h51553[12] && - !sfdin__h51553[11] && - !sfdin__h51553[10] && - !sfdin__h51553[9] && - !sfdin__h51553[8] && - !sfdin__h51553[7] && - !sfdin__h51553[6] && - !sfdin__h51553[5] && - !sfdin__h51553[4] && - !sfdin__h51553[3] && - !sfdin__h51553[2] && - !sfdin__h51553[1] && - !sfdin__h51553[0] || - !_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727) ? - 11'd0 : - _theResult___fst_exp__h59846 ; - assign _theResult___fst_exp__h59855 = - (!sfdin__h51553[57] && sfdin__h51553[56]) ? - _theResult___fst_exp__h59807 : - _theResult___fst_exp__h59852 ; - assign _theResult___fst_exp__h60991 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h60988 ; - assign _theResult___fst_sfd__h60992 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h60989 ; - assign _theResult___sfd__h60911 = - sfd__h60417[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h60417[52:1]) : - sfd__h60417[51:0] ; - assign _theResult___snd__h52150 = { fpu_fState_S3$D_OUT[56:0], 1'd0 } ; - assign _theResult___snd__h59785 = { sfdin__h51553[56:0], 1'd0 } ; - assign _theResult___snd__h59800 = - (!sfdin__h51553[57] && sfdin__h51553[56]) ? - _theResult___snd__h59802 : - _theResult___snd__h59815 ; - assign _theResult___snd__h59802 = { sfdin__h51553[55:0], 2'd0 } ; - assign _theResult___snd__h59815 = - (!sfdin__h51553[57] && !sfdin__h51553[56] && - !sfdin__h51553[55] && - !sfdin__h51553[54] && - !sfdin__h51553[53] && - !sfdin__h51553[52] && - !sfdin__h51553[51] && - !sfdin__h51553[50] && - !sfdin__h51553[49] && - !sfdin__h51553[48] && - !sfdin__h51553[47] && - !sfdin__h51553[46] && - !sfdin__h51553[45] && - !sfdin__h51553[44] && - !sfdin__h51553[43] && - !sfdin__h51553[42] && - !sfdin__h51553[41] && - !sfdin__h51553[40] && - !sfdin__h51553[39] && - !sfdin__h51553[38] && - !sfdin__h51553[37] && - !sfdin__h51553[36] && - !sfdin__h51553[35] && - !sfdin__h51553[34] && - !sfdin__h51553[33] && - !sfdin__h51553[32] && - !sfdin__h51553[31] && - !sfdin__h51553[30] && - !sfdin__h51553[29] && - !sfdin__h51553[28] && - !sfdin__h51553[27] && - !sfdin__h51553[26] && - !sfdin__h51553[25] && - !sfdin__h51553[24] && - !sfdin__h51553[23] && - !sfdin__h51553[22] && - !sfdin__h51553[21] && - !sfdin__h51553[20] && - !sfdin__h51553[19] && - !sfdin__h51553[18] && - !sfdin__h51553[17] && - !sfdin__h51553[16] && - !sfdin__h51553[15] && - !sfdin__h51553[14] && - !sfdin__h51553[13] && - !sfdin__h51553[12] && - !sfdin__h51553[11] && - !sfdin__h51553[10] && - !sfdin__h51553[9] && - !sfdin__h51553[8] && - !sfdin__h51553[7] && - !sfdin__h51553[6] && - !sfdin__h51553[5] && - !sfdin__h51553[4] && - !sfdin__h51553[3] && - !sfdin__h51553[2] && - !sfdin__h51553[1] && - !sfdin__h51553[0]) ? - sfdin__h51553 : - _theResult___snd__h59821 ; - assign _theResult___snd__h59821 = - { IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7[55:0], - 2'd0 } ; - assign _theResult___snd__h59839 = - sfdin__h51553 << - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ; - assign _theResult___snd__h59844 = - sfdin__h51553 << - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 ; - assign _theResult___snd_fst__h59874 = - { IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8[1], - { sfdin__h59762[4:0], 52'd0 } != 57'd0 } ; - assign _theResult___snd_fst_exp__h49084 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352) ? - 11'd0 : - value__h49124[10:0] ; - assign _theResult___snd_fst_exp__h49087 = - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? - _theResult___snd_fst_exp__h49084 : - 11'd2046 ; - assign _theResult___snd_fst_exp__h49111 = - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 ? - 11'd0 : - _theResult___snd_fst_exp__h49087 ; - assign _theResult___snd_fst_sfd__h49112 = - (fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? - 52'd0 : - 52'hFFFFFFFFFFFFF ; - assign _theResult___snd_snd_snd__h51398 = - (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___snd__h52150 : - fpu_fState_S3$D_OUT[57:0] ; - assign b__h10163 = { int_div_fNext_28$D_OUT[231:174], 58'd0 } ; - assign b__h10487 = { int_div_fNext_29$D_OUT[231:174], 58'd0 } ; - assign b__h10811 = { int_div_fNext_30$D_OUT[231:174], 58'd0 } ; - assign b__h1091 = { int_div_fNext_0$D_OUT[231:174], 58'd0 } ; - assign b__h11135 = { int_div_fNext_31$D_OUT[231:174], 58'd0 } ; - assign b__h11459 = { int_div_fNext_32$D_OUT[231:174], 58'd0 } ; - assign b__h11783 = { int_div_fNext_33$D_OUT[231:174], 58'd0 } ; - assign b__h12107 = { int_div_fNext_34$D_OUT[231:174], 58'd0 } ; - assign b__h12431 = { int_div_fNext_35$D_OUT[231:174], 58'd0 } ; - assign b__h12755 = { int_div_fNext_36$D_OUT[231:174], 58'd0 } ; - assign b__h13079 = { int_div_fNext_37$D_OUT[231:174], 58'd0 } ; - assign b__h13403 = { int_div_fNext_38$D_OUT[231:174], 58'd0 } ; - assign b__h13727 = { int_div_fNext_39$D_OUT[231:174], 58'd0 } ; - assign b__h14051 = { int_div_fNext_40$D_OUT[231:174], 58'd0 } ; - assign b__h1415 = { int_div_fNext_1$D_OUT[231:174], 58'd0 } ; - assign b__h14375 = { int_div_fNext_41$D_OUT[231:174], 58'd0 } ; - assign b__h14699 = { int_div_fNext_42$D_OUT[231:174], 58'd0 } ; - assign b__h15023 = { int_div_fNext_43$D_OUT[231:174], 58'd0 } ; - assign b__h15347 = { int_div_fNext_44$D_OUT[231:174], 58'd0 } ; - assign b__h15671 = { int_div_fNext_45$D_OUT[231:174], 58'd0 } ; - assign b__h15995 = { int_div_fNext_46$D_OUT[231:174], 58'd0 } ; - assign b__h16319 = { int_div_fNext_47$D_OUT[231:174], 58'd0 } ; - assign b__h16643 = { int_div_fNext_48$D_OUT[231:174], 58'd0 } ; - assign b__h16967 = { int_div_fNext_49$D_OUT[231:174], 58'd0 } ; - assign b__h17291 = { int_div_fNext_50$D_OUT[231:174], 58'd0 } ; - assign b__h1739 = { int_div_fNext_2$D_OUT[231:174], 58'd0 } ; - assign b__h17615 = { int_div_fNext_51$D_OUT[231:174], 58'd0 } ; - assign b__h17939 = { int_div_fNext_52$D_OUT[231:174], 58'd0 } ; - assign b__h18263 = { int_div_fNext_53$D_OUT[231:174], 58'd0 } ; - assign b__h18587 = { int_div_fNext_54$D_OUT[231:174], 58'd0 } ; - assign b__h18911 = { int_div_fNext_55$D_OUT[231:174], 58'd0 } ; - assign b__h19235 = { int_div_fNext_56$D_OUT[231:174], 58'd0 } ; - assign b__h19482 = { int_div_fNext_57$D_OUT[231:174], 58'd0 } ; - assign b__h2063 = { int_div_fNext_3$D_OUT[231:174], 58'd0 } ; - assign b__h21789 = - (fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? - (fpu_fOperands_S0$D_OUT[118] ? - 6'd1 : - (fpu_fOperands_S0$D_OUT[117] ? - 6'd2 : - (fpu_fOperands_S0$D_OUT[116] ? - 6'd3 : - (fpu_fOperands_S0$D_OUT[115] ? - 6'd4 : - (fpu_fOperands_S0$D_OUT[114] ? - 6'd5 : - (fpu_fOperands_S0$D_OUT[113] ? - 6'd6 : - (fpu_fOperands_S0$D_OUT[112] ? - 6'd7 : - (fpu_fOperands_S0$D_OUT[111] ? - 6'd8 : - (fpu_fOperands_S0$D_OUT[110] ? - 6'd9 : - (fpu_fOperands_S0$D_OUT[109] ? - 6'd10 : - (fpu_fOperands_S0$D_OUT[108] ? - 6'd11 : - (fpu_fOperands_S0$D_OUT[107] ? - 6'd12 : - (fpu_fOperands_S0$D_OUT[106] ? - 6'd13 : - (fpu_fOperands_S0$D_OUT[105] ? - 6'd14 : - (fpu_fOperands_S0$D_OUT[104] ? - 6'd15 : - (fpu_fOperands_S0$D_OUT[103] ? - 6'd16 : - (fpu_fOperands_S0$D_OUT[102] ? - 6'd17 : - (fpu_fOperands_S0$D_OUT[101] ? - 6'd18 : - (fpu_fOperands_S0$D_OUT[100] ? - 6'd19 : - (fpu_fOperands_S0$D_OUT[99] ? - 6'd20 : - (fpu_fOperands_S0$D_OUT[98] ? - 6'd21 : - (fpu_fOperands_S0$D_OUT[97] ? - 6'd22 : - (fpu_fOperands_S0$D_OUT[96] ? - 6'd23 : - (fpu_fOperands_S0$D_OUT[95] ? - 6'd24 : - (fpu_fOperands_S0$D_OUT[94] ? - 6'd25 : - (fpu_fOperands_S0$D_OUT[93] ? - 6'd26 : - (fpu_fOperands_S0$D_OUT[92] ? - 6'd27 : - (fpu_fOperands_S0$D_OUT[91] ? - 6'd28 : - (fpu_fOperands_S0$D_OUT[90] ? - 6'd29 : - (fpu_fOperands_S0$D_OUT[89] ? - 6'd30 : - (fpu_fOperands_S0$D_OUT[88] ? - 6'd31 : - (fpu_fOperands_S0$D_OUT[87] ? - 6'd32 : - (fpu_fOperands_S0$D_OUT[86] ? - 6'd33 : - (fpu_fOperands_S0$D_OUT[85] ? - 6'd34 : - (fpu_fOperands_S0$D_OUT[84] ? - 6'd35 : - (fpu_fOperands_S0$D_OUT[83] ? - 6'd36 : - (fpu_fOperands_S0$D_OUT[82] ? - 6'd37 : - (fpu_fOperands_S0$D_OUT[81] ? - 6'd38 : - (fpu_fOperands_S0$D_OUT[80] ? - 6'd39 : - (fpu_fOperands_S0$D_OUT[79] ? - 6'd40 : - (fpu_fOperands_S0$D_OUT[78] ? - 6'd41 : - (fpu_fOperands_S0$D_OUT[77] ? - 6'd42 : - (fpu_fOperands_S0$D_OUT[76] ? - 6'd43 : - (fpu_fOperands_S0$D_OUT[75] ? - 6'd44 : - (fpu_fOperands_S0$D_OUT[74] ? - 6'd45 : - (fpu_fOperands_S0$D_OUT[73] ? - 6'd46 : - (fpu_fOperands_S0$D_OUT[72] ? - 6'd47 : - (fpu_fOperands_S0$D_OUT[71] ? - 6'd48 : - (fpu_fOperands_S0$D_OUT[70] ? - 6'd49 : - (fpu_fOperands_S0$D_OUT[69] ? - 6'd50 : - (fpu_fOperands_S0$D_OUT[68] ? - 6'd51 : - (fpu_fOperands_S0$D_OUT[67] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h2387 = { int_div_fNext_4$D_OUT[231:174], 58'd0 } ; - assign b__h2711 = { int_div_fNext_5$D_OUT[231:174], 58'd0 } ; - assign b__h29207 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? - (fpu_fOperands_S0$D_OUT[54] ? - 6'd1 : - (fpu_fOperands_S0$D_OUT[53] ? - 6'd2 : - (fpu_fOperands_S0$D_OUT[52] ? - 6'd3 : - (fpu_fOperands_S0$D_OUT[51] ? - 6'd4 : - (fpu_fOperands_S0$D_OUT[50] ? - 6'd5 : - (fpu_fOperands_S0$D_OUT[49] ? - 6'd6 : - (fpu_fOperands_S0$D_OUT[48] ? - 6'd7 : - (fpu_fOperands_S0$D_OUT[47] ? - 6'd8 : - (fpu_fOperands_S0$D_OUT[46] ? - 6'd9 : - (fpu_fOperands_S0$D_OUT[45] ? - 6'd10 : - (fpu_fOperands_S0$D_OUT[44] ? - 6'd11 : - (fpu_fOperands_S0$D_OUT[43] ? - 6'd12 : - (fpu_fOperands_S0$D_OUT[42] ? - 6'd13 : - (fpu_fOperands_S0$D_OUT[41] ? - 6'd14 : - (fpu_fOperands_S0$D_OUT[40] ? - 6'd15 : - (fpu_fOperands_S0$D_OUT[39] ? - 6'd16 : - (fpu_fOperands_S0$D_OUT[38] ? - 6'd17 : - (fpu_fOperands_S0$D_OUT[37] ? - 6'd18 : - (fpu_fOperands_S0$D_OUT[36] ? - 6'd19 : - (fpu_fOperands_S0$D_OUT[35] ? - 6'd20 : - (fpu_fOperands_S0$D_OUT[34] ? - 6'd21 : - (fpu_fOperands_S0$D_OUT[33] ? - 6'd22 : - (fpu_fOperands_S0$D_OUT[32] ? - 6'd23 : - (fpu_fOperands_S0$D_OUT[31] ? - 6'd24 : - (fpu_fOperands_S0$D_OUT[30] ? - 6'd25 : - (fpu_fOperands_S0$D_OUT[29] ? - 6'd26 : - (fpu_fOperands_S0$D_OUT[28] ? - 6'd27 : - (fpu_fOperands_S0$D_OUT[27] ? - 6'd28 : - (fpu_fOperands_S0$D_OUT[26] ? - 6'd29 : - (fpu_fOperands_S0$D_OUT[25] ? - 6'd30 : - (fpu_fOperands_S0$D_OUT[24] ? - 6'd31 : - (fpu_fOperands_S0$D_OUT[23] ? - 6'd32 : - (fpu_fOperands_S0$D_OUT[22] ? - 6'd33 : - (fpu_fOperands_S0$D_OUT[21] ? - 6'd34 : - (fpu_fOperands_S0$D_OUT[20] ? - 6'd35 : - (fpu_fOperands_S0$D_OUT[19] ? - 6'd36 : - (fpu_fOperands_S0$D_OUT[18] ? - 6'd37 : - (fpu_fOperands_S0$D_OUT[17] ? - 6'd38 : - (fpu_fOperands_S0$D_OUT[16] ? - 6'd39 : - (fpu_fOperands_S0$D_OUT[15] ? - 6'd40 : - (fpu_fOperands_S0$D_OUT[14] ? - 6'd41 : - (fpu_fOperands_S0$D_OUT[13] ? - 6'd42 : - (fpu_fOperands_S0$D_OUT[12] ? - 6'd43 : - (fpu_fOperands_S0$D_OUT[11] ? - 6'd44 : - (fpu_fOperands_S0$D_OUT[10] ? - 6'd45 : - (fpu_fOperands_S0$D_OUT[9] ? - 6'd46 : - (fpu_fOperands_S0$D_OUT[8] ? - 6'd47 : - (fpu_fOperands_S0$D_OUT[7] ? - 6'd48 : - (fpu_fOperands_S0$D_OUT[6] ? - 6'd49 : - (fpu_fOperands_S0$D_OUT[5] ? - 6'd50 : - (fpu_fOperands_S0$D_OUT[4] ? - 6'd51 : - (fpu_fOperands_S0$D_OUT[3] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h3035 = { int_div_fNext_6$D_OUT[231:174], 58'd0 } ; - assign b__h3359 = { int_div_fNext_7$D_OUT[231:174], 58'd0 } ; - assign b__h3683 = { int_div_fNext_8$D_OUT[231:174], 58'd0 } ; - assign b__h378 = { 1'd0, int_div_fRequest$D_OUT[56:0] } ; - assign b__h4007 = { int_div_fNext_9$D_OUT[231:174], 58'd0 } ; - assign b__h4331 = { int_div_fNext_10$D_OUT[231:174], 58'd0 } ; - assign b__h4655 = { int_div_fNext_11$D_OUT[231:174], 58'd0 } ; - assign b__h4979 = { int_div_fNext_12$D_OUT[231:174], 58'd0 } ; - assign b__h5303 = { int_div_fNext_13$D_OUT[231:174], 58'd0 } ; - assign b__h5627 = { int_div_fNext_14$D_OUT[231:174], 58'd0 } ; - assign b__h5951 = { int_div_fNext_15$D_OUT[231:174], 58'd0 } ; - assign b__h6275 = { int_div_fNext_16$D_OUT[231:174], 58'd0 } ; - assign b__h6599 = { int_div_fNext_17$D_OUT[231:174], 58'd0 } ; - assign b__h6923 = { int_div_fNext_18$D_OUT[231:174], 58'd0 } ; - assign b__h7247 = { int_div_fNext_19$D_OUT[231:174], 58'd0 } ; - assign b__h7571 = { int_div_fNext_20$D_OUT[231:174], 58'd0 } ; - assign b__h767 = { int_div_fFirst$D_OUT[231:174], 58'd0 } ; - assign b__h7895 = { int_div_fNext_21$D_OUT[231:174], 58'd0 } ; - assign b__h8219 = { int_div_fNext_22$D_OUT[231:174], 58'd0 } ; - assign b__h8543 = { int_div_fNext_23$D_OUT[231:174], 58'd0 } ; - assign b__h8867 = { int_div_fNext_24$D_OUT[231:174], 58'd0 } ; - assign b__h9191 = { int_div_fNext_25$D_OUT[231:174], 58'd0 } ; - assign b__h9515 = { int_div_fNext_26$D_OUT[231:174], 58'd0 } ; - assign b__h9839 = { int_div_fNext_27$D_OUT[231:174], 58'd0 } ; - assign din_inc___2_exp__h61001 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; - assign fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 = - fpu_fOperands_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 = - fpu_fOperands_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 ; - assign fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 = - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; - assign fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 = - fpu_fOperands_S0$D_OUT[130] == fpu_fOperands_S0$D_OUT[66] ; - assign fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780 = - { fpu_fState_S3$D_OUT[121], - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 : - ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - { _theResult___fst_exp__h59719, - fpu_fState_S3$D_OUT[109:58] } : - 63'h7FEFFFFFFFFFFFFF) : - fpu_fState_S3$D_OUT[120:58]) } ; - assign guard__h51381 = x__h60140 ; - assign int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 = - int_div_fNext_57$D_OUT[173:116] + - -(~int_div_fNext_57$D_OUT[173:116]) ; - assign out_exp__h60913 = - fpu_fState_S4$D_OUT[2] ? - _theResult___exp__h60910 : - fpu_fState_S4$D_OUT[64:54] ; - assign out_sfd__h60914 = - fpu_fState_S4$D_OUT[2] ? - _theResult___sfd__h60911 : - fpu_fState_S4$D_OUT[53:2] ; - assign result__h50077 = { _theResult____h50063[57:1], 1'd1 } ; - assign result__h50108 = - { 1'd0, - value__h50121[56:1], - value__h50121[0] | sfdlsb__h50103 } ; - assign result__h50258 = - (int_div_fResponse$D_OUT[113:57] == 57'd0) ? 58'd0 : 58'd1 ; - assign sfdA__h19785 = - { fpu_fOperands_S0$D_OUT[129:119] != 11'd0, - fpu_fOperands_S0$D_OUT[118:67] } ; - assign sfdA__h19789 = sfdA__h19785 << b__h21789 ; - assign sfdB__h19786 = - { fpu_fOperands_S0$D_OUT[65:55] != 11'd0, - fpu_fOperands_S0$D_OUT[54:3] } ; - assign sfdB__h19791 = sfdB__h19786 << b__h29207 ; - assign sfd__h36684 = { 1'd1, fpu_fOperands_S0$D_OUT[117:67] } ; - assign sfd__h36687 = { 1'd1, fpu_fOperands_S0$D_OUT[53:3] } ; - assign sfd__h60417 = - { 1'b0, - fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfdin__h51553 = - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___snd_snd_snd__h51398 : - fpu_fState_S3$D_OUT[57:0] ; - assign sfdin__h59762 = - sfdin__h51553[57] ? - _theResult___snd__h59785 : - _theResult___snd__h59800 ; - assign sfdlsb__h50103 = x__h50197 != 58'd0 ; - assign theResult___fst_exp9725_MINUS_1023__q6 = - _theResult___fst_exp__h59725 - 11'd1023 ; - assign value__h19447 = - int_div_fNext_57$D_OUT[115] ? - int_div_fNext_57$D_OUT[115:0] + b__h19482 : - int_div_fNext_57$D_OUT[115:0] ; - assign value__h49124 = - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 + - 13'd1023 ; - assign value__h49179 = { 1'b0, sfdA__h19789 } ; - assign value__h49300 = - 13'd7170 - - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ; - assign value__h50121 = - int_div_fResponse$D_OUT[113:57] >> fpu_fState_S2$D_OUT[10:0] ; - assign x__h49176 = { value__h49179, 60'd0 } ; - assign x__h49237 = { sfdB__h19791, 4'b0 } ; - assign x__h49291 = - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 ? - 11'd0 : - _theResult___fst__h49072 ; - assign x__h50197 = { 1'd0, int_div_fResponse$D_OUT[113:57] } << x__h50204 ; - assign x__h50204 = 11'd58 - fpu_fState_S2$D_OUT[10:0] ; - assign x__h50487 = - (int_div_fResponse$D_OUT[56:0] == 57'd0) ? - _theResult____h50063 : - result__h50077 ; - assign x__h60140 = - (sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h59874 ; - always@(fpu_fState_S4$D_OUT or out_sfd__h60914 or _theResult___sfd__h60911) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - fpu_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - out_sfd__h60914; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - _theResult___sfd__h60911; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___sfd__h60911) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - fpu_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - _theResult___sfd__h60911; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or - _theResult___sfd__h60911) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h60989 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; - 3'd1: - _theResult___fst_sfd__h60989 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; - 3'd2: - _theResult___fst_sfd__h60989 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___sfd__h60911; - 3'd3: - _theResult___fst_sfd__h60989 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[53:2] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___sfd__h60911 : - fpu_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h60989 = fpu_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h60989 = 52'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_exp__h37217 = 11'd2047; - 3'd2: - _theResult___fst_exp__h37217 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 11'd2047 : - 11'd2046; - 3'd3: - _theResult___fst_exp__h37217 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 11'd2046 : - 11'd2047; - 3'd4: _theResult___fst_exp__h37217 = 11'd2046; - default: _theResult___fst_exp__h37217 = 11'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_sfd__h37218 = 52'd0; - 3'd2: - _theResult___fst_sfd__h37218 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - _theResult___fst_sfd__h37218 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'hFFFFFFFFFFFFF : - 52'd0; - 3'd4: _theResult___fst_sfd__h37218 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h37218 = 52'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0: _theResult___fst_sfd__h37707 = 52'd0; - 3'd1: _theResult___fst_sfd__h37707 = 52'd1; - 3'd2: - _theResult___fst_sfd__h37707 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'd1 : - 52'd0; - 3'd3: - _theResult___fst_sfd__h37707 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'd0 : - 52'd1; - default: _theResult___fst_sfd__h37707 = 52'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; - default: CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = - fpu_fOperands_S0$D_OUT[2:0] == 3'd4 && - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; - endcase - end - always@(fpu_fState_S4$D_OUT or out_exp__h60913 or _theResult___exp__h60910) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = - fpu_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = - out_exp__h60913; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = - _theResult___exp__h60910; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___exp__h60910) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = - fpu_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = - _theResult___exp__h60910; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 or - _theResult___exp__h60910) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h60988 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9; - 3'd1: - _theResult___fst_exp__h60988 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10; - 3'd2: - _theResult___fst_exp__h60988 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___exp__h60910; - 3'd3: - _theResult___fst_exp__h60988 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:54] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___exp__h60910 : - fpu_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h60988 = fpu_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h60988 = 11'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = - fpu_fState_S4$D_OUT[65]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = - fpu_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; - 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:2] : - (fpu_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : - fpu_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = - fpu_fState_S4$D_OUT[64:2]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = 63'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = - fpu_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = - fpu_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : - fpu_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = - { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 }; - 3'd1: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[65:2] : - { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_fState_S4$D_OUT[65], - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 }; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = - { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 }; - endcase - end - always@(fpu_fState_S3$D_OUT) - begin - case (fpu_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = - fpu_fState_S3$D_OUT[121]; - default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = - fpu_fState_S3$D_OUT[124:122] == 3'd4 && - fpu_fState_S3$D_OUT[121]; - endcase - end - always@(fpu_fState_S3$D_OUT) - begin - case (fpu_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - 63'h7FF0000000000000; - 3'd2: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - fpu_fState_S3$D_OUT[121] ? - 63'h7FEFFFFFFFFFFFFF : - 63'h7FF0000000000000; - 3'd3: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - fpu_fState_S3$D_OUT[121] ? - 63'h7FF0000000000000 : - 63'h7FEFFFFFFFFFFFFF; - 3'd4: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - 63'h7FEFFFFFFFFFFFFF; - default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = 63'd0; - endcase - end + // submodule fpu + mkXilinxFpDiv fpu(.CLK(CLK), + .RST_N(RST_N), + .request_put(fpu$request_put), + .EN_request_put(fpu$EN_request_put), + .EN_response_get(fpu$EN_response_get), + .RDY_request_put(fpu$RDY_request_put), + .response_get(fpu$response_get), + .RDY_response_get(fpu$RDY_response_get)); + + // submodule fpu + assign fpu$request_put = request_put ; + assign fpu$EN_request_put = EN_request_put ; + assign fpu$EN_response_get = EN_response_get ; endmodule // mkDoubleDiv diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v index de193e3..5d2e0d5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v @@ -7,16 +7,15 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 reg -// RDY_response_get O 1 reg +// response_get O 69 +// RDY_response_get O 1 // CLK I 1 clock // RST_N I 1 reset -// request_put I 196 reg +// request_put I 196 // EN_request_put I 1 // EN_response_get I 1 // -// Combinational paths from inputs to outputs: -// EN_response_get -> RDY_request_put +// No combinational paths from inputs to outputs // // @@ -60,2035 +59,44 @@ module mkDoubleFMA(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu_fOperand_S0 - wire [195 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; - wire fpu_fOperand_S0$CLR, - fpu_fOperand_S0$DEQ, - fpu_fOperand_S0$EMPTY_N, - fpu_fOperand_S0$ENQ, - fpu_fOperand_S0$FULL_N; - - // ports of submodule fpu_fProd_S2 - wire [105 : 0] fpu_fProd_S2$D_IN, fpu_fProd_S2$D_OUT; - wire fpu_fProd_S2$CLR, - fpu_fProd_S2$DEQ, - fpu_fProd_S2$EMPTY_N, - fpu_fProd_S2$ENQ, - fpu_fProd_S2$FULL_N; - - // ports of submodule fpu_fProd_S3 - wire [105 : 0] fpu_fProd_S3$D_IN, fpu_fProd_S3$D_OUT; - wire fpu_fProd_S3$CLR, - fpu_fProd_S3$DEQ, - fpu_fProd_S3$EMPTY_N, - fpu_fProd_S3$ENQ, - fpu_fProd_S3$FULL_N; - - // ports of submodule fpu_fResult_S9 - wire [68 : 0] fpu_fResult_S9$D_IN, fpu_fResult_S9$D_OUT; - wire fpu_fResult_S9$CLR, - fpu_fResult_S9$DEQ, - fpu_fResult_S9$EMPTY_N, - fpu_fResult_S9$ENQ, - fpu_fResult_S9$FULL_N; - - // ports of submodule fpu_fState_S1 - wire [257 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; - wire fpu_fState_S1$CLR, - fpu_fState_S1$DEQ, - fpu_fState_S1$EMPTY_N, - fpu_fState_S1$ENQ, - fpu_fState_S1$FULL_N; - - // ports of submodule fpu_fState_S2 - wire [151 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; - wire fpu_fState_S2$CLR, - fpu_fState_S2$DEQ, - fpu_fState_S2$EMPTY_N, - fpu_fState_S2$ENQ, - fpu_fState_S2$FULL_N; - - // ports of submodule fpu_fState_S3 - wire [151 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; - wire fpu_fState_S3$CLR, - fpu_fState_S3$DEQ, - fpu_fState_S3$EMPTY_N, - fpu_fState_S3$ENQ, - fpu_fState_S3$FULL_N; - - // ports of submodule fpu_fState_S4 - wire [203 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; - wire fpu_fState_S4$CLR, - fpu_fState_S4$DEQ, - fpu_fState_S4$EMPTY_N, - fpu_fState_S4$ENQ, - fpu_fState_S4$FULL_N; - - // ports of submodule fpu_fState_S5 - wire [215 : 0] fpu_fState_S5$D_IN, fpu_fState_S5$D_OUT; - wire fpu_fState_S5$CLR, - fpu_fState_S5$DEQ, - fpu_fState_S5$EMPTY_N, - fpu_fState_S5$ENQ, - fpu_fState_S5$FULL_N; - - // ports of submodule fpu_fState_S6 - wire [202 : 0] fpu_fState_S6$D_IN, fpu_fState_S6$D_OUT; - wire fpu_fState_S6$CLR, - fpu_fState_S6$DEQ, - fpu_fState_S6$EMPTY_N, - fpu_fState_S6$ENQ, - fpu_fState_S6$FULL_N; - - // ports of submodule fpu_fState_S7 - wire [202 : 0] fpu_fState_S7$D_IN, fpu_fState_S7$D_OUT; - wire fpu_fState_S7$CLR, - fpu_fState_S7$DEQ, - fpu_fState_S7$EMPTY_N, - fpu_fState_S7$ENQ, - fpu_fState_S7$FULL_N; - - // ports of submodule fpu_fState_S8 - wire [140 : 0] fpu_fState_S8$D_IN, fpu_fState_S8$D_OUT; - wire fpu_fState_S8$CLR, - fpu_fState_S8$DEQ, - fpu_fState_S8$EMPTY_N, - fpu_fState_S8$ENQ, - fpu_fState_S8$FULL_N; + // ports of submodule fpu + wire [195 : 0] fpu$request_put; + wire [68 : 0] fpu$response_get; + wire fpu$EN_request_put, + fpu$EN_response_get, + fpu$RDY_request_put, + fpu$RDY_response_get; // rule scheduling signals - wire CAN_FIRE_RL_fpu_s1_stage, - CAN_FIRE_RL_fpu_s2_stage, - CAN_FIRE_RL_fpu_s3_stage, - CAN_FIRE_RL_fpu_s4_stage, - CAN_FIRE_RL_fpu_s5_stage, - CAN_FIRE_RL_fpu_s6_stage, - CAN_FIRE_RL_fpu_s7_stage, - CAN_FIRE_RL_fpu_s8_stage, - CAN_FIRE_RL_fpu_s9_stage, - CAN_FIRE_request_put, + wire CAN_FIRE_request_put, CAN_FIRE_response_get, - WILL_FIRE_RL_fpu_s1_stage, - WILL_FIRE_RL_fpu_s2_stage, - WILL_FIRE_RL_fpu_s3_stage, - WILL_FIRE_RL_fpu_s4_stage, - WILL_FIRE_RL_fpu_s5_stage, - WILL_FIRE_RL_fpu_s6_stage, - WILL_FIRE_RL_fpu_s7_stage, - WILL_FIRE_RL_fpu_s8_stage, - WILL_FIRE_RL_fpu_s9_stage, WILL_FIRE_request_put, WILL_FIRE_response_get; - // remaining internal signals - reg [62 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17, - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18, - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19; - reg [51 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1, - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2, - _theResult___fst_sfd__h46438; - reg [10 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11, - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12, - _theResult___fst_exp__h46437; - reg CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14; - wire [139 : 0] IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796; - wire [118 : 0] IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160; - wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4, - _theResult___fst__h20642, - _theResult___snd__h34781, - _theResult___snd__h34795, - _theResult___snd__h34797, - _theResult___snd__h34809, - _theResult___snd__h34815, - _theResult___snd__h34833, - _theResult___snd__h34838, - fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213, - sfdBC__h19477, - sfdin__h34758, - x__h20711; - wire [68 : 0] IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282; - wire [63 : 0] IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137, - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735, - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132, - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737; - wire [56 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9, - _theResult___snd__h45207, - _theResult___snd__h45221, - _theResult___snd__h45223, - _theResult___snd__h45235, - _theResult___snd__h45241, - _theResult___snd__h45259, - _theResult___snd__h45264, - fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816, - guard__h36182, - result__h36187, - sfdA__h35392, - sfdBC__h35393, - sfd__h36934, - sfdin__h45184, - x__h35755, - x__h35759, - x__h36174, - x__h36686, - x__h36695; - wire [53 : 0] sfd__h45855; - wire [52 : 0] x__h18058, x__h18070; - wire [51 : 0] _theResult___fst_sfd__h396, - _theResult___sfd__h46360, - out_sfd__h46363, - sfd__h3208, - sfd__h3211, - sfd__h3214; - wire [12 : 0] IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208, - value__h34698, - value__h45122, - x__h20744, - x__h36286; - wire [11 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663, - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104, - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869; - wire [10 : 0] IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212, - _theResult___exp__h46359, - _theResult___fst_exp__h34764, - _theResult___fst_exp__h34767, - _theResult___fst_exp__h34786, - _theResult___fst_exp__h34801, - _theResult___fst_exp__h34840, - _theResult___fst_exp__h34846, - _theResult___fst_exp__h34849, - _theResult___fst_exp__h45190, - _theResult___fst_exp__h45193, - _theResult___fst_exp__h45212, - _theResult___fst_exp__h45227, - _theResult___fst_exp__h45266, - _theResult___fst_exp__h45272, - _theResult___fst_exp__h45275, - din_exp4681_MINUS_1023__q3, - din_exp__h34681, - din_inc___2_exp__h46444, - fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16, - fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7, - fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6, - out_exp__h46362, - value5122_BITS_10_TO_0_MINUS_1023__q8, - x__h327; - wire [6 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661; - wire [5 : 0] IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102; - wire [4 : 0] IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702, - fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, - fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244; - wire [2 : 0] NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724; - wire [1 : 0] IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5, - IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10, - _theResult___snd_fst__h34866, - _theResult___snd_fst__h45292, - _theResult___snd_snd__h35186, - _theResult___snd_snd_snd__h35184, - guardBC__h19481, - guard__h36938, - x__h35221, - x__h45575; - wire IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123, - IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, - IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717, - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722, - IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, - NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147, - NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, - NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785, - _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664, - _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105, - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209, - fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127, - fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58, - fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56, - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203, - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205, - sfdlsb__h20640; - // action method request_put - assign RDY_request_put = fpu_fOperand_S0$FULL_N ; - assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; + assign RDY_request_put = fpu$RDY_request_put ; + assign CAN_FIRE_request_put = fpu$RDY_request_put ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu_fResult_S9$D_OUT ; - assign RDY_response_get = fpu_fResult_S9$EMPTY_N ; - assign CAN_FIRE_response_get = fpu_fResult_S9$EMPTY_N ; + assign response_get = fpu$response_get ; + assign RDY_response_get = fpu$RDY_response_get ; + assign CAN_FIRE_response_get = fpu$RDY_response_get ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu_fOperand_S0 - FIFOL1 #(.width(32'd196)) fpu_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fOperand_S0$D_IN), - .ENQ(fpu_fOperand_S0$ENQ), - .DEQ(fpu_fOperand_S0$DEQ), - .CLR(fpu_fOperand_S0$CLR), - .D_OUT(fpu_fOperand_S0$D_OUT), - .FULL_N(fpu_fOperand_S0$FULL_N), - .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); + // submodule fpu + mkXilinxFpFma fpu(.CLK(CLK), + .RST_N(RST_N), + .request_put(fpu$request_put), + .EN_request_put(fpu$EN_request_put), + .EN_response_get(fpu$EN_response_get), + .RDY_request_put(fpu$RDY_request_put), + .response_get(fpu$response_get), + .RDY_response_get(fpu$RDY_response_get)); - // submodule fpu_fProd_S2 - FIFOL1 #(.width(32'd106)) fpu_fProd_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fProd_S2$D_IN), - .ENQ(fpu_fProd_S2$ENQ), - .DEQ(fpu_fProd_S2$DEQ), - .CLR(fpu_fProd_S2$CLR), - .D_OUT(fpu_fProd_S2$D_OUT), - .FULL_N(fpu_fProd_S2$FULL_N), - .EMPTY_N(fpu_fProd_S2$EMPTY_N)); - - // submodule fpu_fProd_S3 - FIFOL1 #(.width(32'd106)) fpu_fProd_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fProd_S3$D_IN), - .ENQ(fpu_fProd_S3$ENQ), - .DEQ(fpu_fProd_S3$DEQ), - .CLR(fpu_fProd_S3$CLR), - .D_OUT(fpu_fProd_S3$D_OUT), - .FULL_N(fpu_fProd_S3$FULL_N), - .EMPTY_N(fpu_fProd_S3$EMPTY_N)); - - // submodule fpu_fResult_S9 - FIFOL1 #(.width(32'd69)) fpu_fResult_S9(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fResult_S9$D_IN), - .ENQ(fpu_fResult_S9$ENQ), - .DEQ(fpu_fResult_S9$DEQ), - .CLR(fpu_fResult_S9$CLR), - .D_OUT(fpu_fResult_S9$D_OUT), - .FULL_N(fpu_fResult_S9$FULL_N), - .EMPTY_N(fpu_fResult_S9$EMPTY_N)); - - // submodule fpu_fState_S1 - FIFOL1 #(.width(32'd258)) fpu_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S1$D_IN), - .ENQ(fpu_fState_S1$ENQ), - .DEQ(fpu_fState_S1$DEQ), - .CLR(fpu_fState_S1$CLR), - .D_OUT(fpu_fState_S1$D_OUT), - .FULL_N(fpu_fState_S1$FULL_N), - .EMPTY_N(fpu_fState_S1$EMPTY_N)); - - // submodule fpu_fState_S2 - FIFOL1 #(.width(32'd152)) fpu_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S2$D_IN), - .ENQ(fpu_fState_S2$ENQ), - .DEQ(fpu_fState_S2$DEQ), - .CLR(fpu_fState_S2$CLR), - .D_OUT(fpu_fState_S2$D_OUT), - .FULL_N(fpu_fState_S2$FULL_N), - .EMPTY_N(fpu_fState_S2$EMPTY_N)); - - // submodule fpu_fState_S3 - FIFOL1 #(.width(32'd152)) fpu_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S3$D_IN), - .ENQ(fpu_fState_S3$ENQ), - .DEQ(fpu_fState_S3$DEQ), - .CLR(fpu_fState_S3$CLR), - .D_OUT(fpu_fState_S3$D_OUT), - .FULL_N(fpu_fState_S3$FULL_N), - .EMPTY_N(fpu_fState_S3$EMPTY_N)); - - // submodule fpu_fState_S4 - FIFOL1 #(.width(32'd204)) fpu_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S4$D_IN), - .ENQ(fpu_fState_S4$ENQ), - .DEQ(fpu_fState_S4$DEQ), - .CLR(fpu_fState_S4$CLR), - .D_OUT(fpu_fState_S4$D_OUT), - .FULL_N(fpu_fState_S4$FULL_N), - .EMPTY_N(fpu_fState_S4$EMPTY_N)); - - // submodule fpu_fState_S5 - FIFOL1 #(.width(32'd216)) fpu_fState_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S5$D_IN), - .ENQ(fpu_fState_S5$ENQ), - .DEQ(fpu_fState_S5$DEQ), - .CLR(fpu_fState_S5$CLR), - .D_OUT(fpu_fState_S5$D_OUT), - .FULL_N(fpu_fState_S5$FULL_N), - .EMPTY_N(fpu_fState_S5$EMPTY_N)); - - // submodule fpu_fState_S6 - FIFOL1 #(.width(32'd203)) fpu_fState_S6(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S6$D_IN), - .ENQ(fpu_fState_S6$ENQ), - .DEQ(fpu_fState_S6$DEQ), - .CLR(fpu_fState_S6$CLR), - .D_OUT(fpu_fState_S6$D_OUT), - .FULL_N(fpu_fState_S6$FULL_N), - .EMPTY_N(fpu_fState_S6$EMPTY_N)); - - // submodule fpu_fState_S7 - FIFOL1 #(.width(32'd203)) fpu_fState_S7(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S7$D_IN), - .ENQ(fpu_fState_S7$ENQ), - .DEQ(fpu_fState_S7$DEQ), - .CLR(fpu_fState_S7$CLR), - .D_OUT(fpu_fState_S7$D_OUT), - .FULL_N(fpu_fState_S7$FULL_N), - .EMPTY_N(fpu_fState_S7$EMPTY_N)); - - // submodule fpu_fState_S8 - FIFOL1 #(.width(32'd141)) fpu_fState_S8(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S8$D_IN), - .ENQ(fpu_fState_S8$ENQ), - .DEQ(fpu_fState_S8$DEQ), - .CLR(fpu_fState_S8$CLR), - .D_OUT(fpu_fState_S8$D_OUT), - .FULL_N(fpu_fState_S8$FULL_N), - .EMPTY_N(fpu_fState_S8$EMPTY_N)); - - // rule RL_fpu_s9_stage - assign CAN_FIRE_RL_fpu_s9_stage = - fpu_fState_S8$EMPTY_N && fpu_fResult_S9$FULL_N ; - assign WILL_FIRE_RL_fpu_s9_stage = CAN_FIRE_RL_fpu_s9_stage ; - - // rule RL_fpu_s8_stage - assign CAN_FIRE_RL_fpu_s8_stage = - fpu_fState_S7$EMPTY_N && fpu_fState_S8$FULL_N ; - assign WILL_FIRE_RL_fpu_s8_stage = CAN_FIRE_RL_fpu_s8_stage ; - - // rule RL_fpu_s7_stage - assign CAN_FIRE_RL_fpu_s7_stage = - fpu_fState_S6$EMPTY_N && fpu_fState_S7$FULL_N ; - assign WILL_FIRE_RL_fpu_s7_stage = CAN_FIRE_RL_fpu_s7_stage ; - - // rule RL_fpu_s6_stage - assign CAN_FIRE_RL_fpu_s6_stage = - fpu_fState_S5$EMPTY_N && fpu_fState_S6$FULL_N ; - assign WILL_FIRE_RL_fpu_s6_stage = CAN_FIRE_RL_fpu_s6_stage ; - - // rule RL_fpu_s5_stage - assign CAN_FIRE_RL_fpu_s5_stage = - fpu_fState_S4$EMPTY_N && fpu_fState_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; - - // rule RL_fpu_s4_stage - assign CAN_FIRE_RL_fpu_s4_stage = - fpu_fState_S3$EMPTY_N && fpu_fProd_S3$EMPTY_N && - fpu_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; - - // rule RL_fpu_s3_stage - assign CAN_FIRE_RL_fpu_s3_stage = - fpu_fState_S2$EMPTY_N && fpu_fProd_S2$EMPTY_N && - fpu_fProd_S3$FULL_N && - fpu_fState_S3$FULL_N ; - assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; - - // rule RL_fpu_s2_stage - assign CAN_FIRE_RL_fpu_s2_stage = - fpu_fState_S1$EMPTY_N && fpu_fProd_S2$FULL_N && - fpu_fState_S2$FULL_N ; - assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; - - // rule RL_fpu_s1_stage - assign CAN_FIRE_RL_fpu_s1_stage = - fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; - - // submodule fpu_fOperand_S0 - assign fpu_fOperand_S0$D_IN = request_put ; - assign fpu_fOperand_S0$ENQ = EN_request_put ; - assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_fProd_S2 - assign fpu_fProd_S2$D_IN = - fpu_fState_S1$D_OUT[105:53] * fpu_fState_S1$D_OUT[52:0] ; - assign fpu_fProd_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fProd_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fProd_S2$CLR = 1'b0 ; - - // submodule fpu_fProd_S3 - assign fpu_fProd_S3$D_IN = fpu_fProd_S2$D_OUT ; - assign fpu_fProd_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fProd_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fProd_S3$CLR = 1'b0 ; - - // submodule fpu_fResult_S9 - assign fpu_fResult_S9$D_IN = - fpu_fState_S8$D_OUT[140] ? - fpu_fState_S8$D_OUT[139:71] : - IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 ; - assign fpu_fResult_S9$ENQ = CAN_FIRE_RL_fpu_s9_stage ; - assign fpu_fResult_S9$DEQ = EN_response_get ; - assign fpu_fResult_S9$CLR = 1'b0 ; - - // submodule fpu_fState_S1 - assign fpu_fState_S1$D_IN = - { x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && - !_theResult___fst_sfd__h396[51] || - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperand_S0$D_OUT[118] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54] || - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, - 4'd0, - fpu_fOperand_S0$D_OUT[2:0], - fpu_fOperand_S0$D_OUT[195], - fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 } ; - assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S1$CLR = 1'b0 ; - - // submodule fpu_fState_S2 - assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[257:106] ; - assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S2$CLR = 1'b0 ; - - // submodule fpu_fState_S3 - assign fpu_fState_S3$D_IN = fpu_fState_S2$D_OUT ; - assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S3$CLR = 1'b0 ; - - // submodule fpu_fState_S4 - assign fpu_fState_S4$D_IN = - { fpu_fState_S3$D_OUT[151:87], - IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, - fpu_fState_S3$D_OUT[81:14], - !fpu_fState_S3$D_OUT[151] && fpu_fState_S3$D_OUT[13], - fpu_fState_S3$D_OUT[151] ? - 63'd0 : - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737, - x__h35221 } ; - assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S4$CLR = 1'b0 ; - - // submodule fpu_fState_S5 - assign fpu_fState_S5$D_IN = - { fpu_fState_S4$D_OUT[203:130], - fpu_fState_S4$D_OUT[129] != fpu_fState_S4$D_OUT[65], - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - fpu_fState_S4$D_OUT[65] : - fpu_fState_S4$D_OUT[129], - IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 } ; - assign fpu_fState_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S5$DEQ = CAN_FIRE_RL_fpu_s6_stage ; - assign fpu_fState_S5$CLR = 1'b0 ; - - // submodule fpu_fState_S6 - assign fpu_fState_S6$D_IN = - { fpu_fState_S5$D_OUT[215:127], - fpu_fState_S5$D_OUT[113:57], - x__h36174 } ; - assign fpu_fState_S6$ENQ = CAN_FIRE_RL_fpu_s6_stage ; - assign fpu_fState_S6$DEQ = CAN_FIRE_RL_fpu_s7_stage ; - assign fpu_fState_S6$CLR = 1'b0 ; - - // submodule fpu_fState_S7 - assign fpu_fState_S7$D_IN = - { fpu_fState_S6$D_OUT[202:114], x__h36686, x__h36695 } ; - assign fpu_fState_S7$ENQ = CAN_FIRE_RL_fpu_s7_stage ; - assign fpu_fState_S7$DEQ = CAN_FIRE_RL_fpu_s8_stage ; - assign fpu_fState_S7$CLR = 1'b0 ; - - // submodule fpu_fState_S8 - assign fpu_fState_S8$D_IN = - { fpu_fState_S7$D_OUT[202:138], - fpu_fState_S7$D_OUT[202] ? - fpu_fState_S7$D_OUT[137:133] : - fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, - fpu_fState_S7$D_OUT[132:129], - !fpu_fState_S7$D_OUT[202] && fpu_fState_S7$D_OUT[127], - fpu_fState_S7$D_OUT[202] ? - 63'd0 : - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, - x__h45575, - fpu_fState_S7$D_OUT[128] } ; - assign fpu_fState_S8$ENQ = CAN_FIRE_RL_fpu_s8_stage ; - assign fpu_fState_S8$DEQ = CAN_FIRE_RL_fpu_s9_stage ; - assign fpu_fState_S8$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4 = - _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 ? - _theResult___snd__h34838 : - _theResult___snd__h34833 ; - assign IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9 = - _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 ? - _theResult___snd__h45264 : - _theResult___snd__h45259 ; - assign IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 = - sfd__h45855[53] ? - ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h46444, sfd__h45855[52:1] }) : - { IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, - sfd__h45855[51:0] } ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 = - (din_exp__h34681 == 11'd0) ? - 12'd3074 : - { din_exp4681_MINUS_1023__q3[10], - din_exp4681_MINUS_1023__q3 } ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 = - (sfdBC__h19477[105] ? - 7'd0 : - (sfdBC__h19477[104] ? - 7'd1 : - (sfdBC__h19477[103] ? - 7'd2 : - (sfdBC__h19477[102] ? - 7'd3 : - (sfdBC__h19477[101] ? - 7'd4 : - (sfdBC__h19477[100] ? - 7'd5 : - (sfdBC__h19477[99] ? - 7'd6 : - (sfdBC__h19477[98] ? - 7'd7 : - (sfdBC__h19477[97] ? - 7'd8 : - (sfdBC__h19477[96] ? - 7'd9 : - (sfdBC__h19477[95] ? - 7'd10 : - (sfdBC__h19477[94] ? - 7'd11 : - (sfdBC__h19477[93] ? - 7'd12 : - (sfdBC__h19477[92] ? - 7'd13 : - (sfdBC__h19477[91] ? - 7'd14 : - (sfdBC__h19477[90] ? - 7'd15 : - (sfdBC__h19477[89] ? - 7'd16 : - (sfdBC__h19477[88] ? - 7'd17 : - (sfdBC__h19477[87] ? - 7'd18 : - (sfdBC__h19477[86] ? - 7'd19 : - (sfdBC__h19477[85] ? - 7'd20 : - (sfdBC__h19477[84] ? - 7'd21 : - (sfdBC__h19477[83] ? - 7'd22 : - (sfdBC__h19477[82] ? - 7'd23 : - (sfdBC__h19477[81] ? - 7'd24 : - (sfdBC__h19477[80] ? - 7'd25 : - (sfdBC__h19477[79] ? - 7'd26 : - (sfdBC__h19477[78] ? - 7'd27 : - (sfdBC__h19477[77] ? - 7'd28 : - (sfdBC__h19477[76] ? - 7'd29 : - (sfdBC__h19477[75] ? - 7'd30 : - (sfdBC__h19477[74] ? - 7'd31 : - (sfdBC__h19477[73] ? - 7'd32 : - (sfdBC__h19477[72] ? - 7'd33 : - (sfdBC__h19477[71] ? - 7'd34 : - (sfdBC__h19477[70] ? - 7'd35 : - (sfdBC__h19477[69] ? - 7'd36 : - (sfdBC__h19477[68] ? - 7'd37 : - (sfdBC__h19477[67] ? - 7'd38 : - (sfdBC__h19477[66] ? - 7'd39 : - (sfdBC__h19477[65] ? - 7'd40 : - (sfdBC__h19477[64] ? - 7'd41 : - (sfdBC__h19477[63] ? - 7'd42 : - (sfdBC__h19477[62] ? - 7'd43 : - (sfdBC__h19477[61] ? - 7'd44 : - (sfdBC__h19477[60] ? - 7'd45 : - (sfdBC__h19477[59] ? - 7'd46 : - (sfdBC__h19477[58] ? - 7'd47 : - (sfdBC__h19477[57] ? - 7'd48 : - (sfdBC__h19477[56] ? - 7'd49 : - (sfdBC__h19477[55] ? - 7'd50 : - (sfdBC__h19477[54] ? - 7'd51 : - (sfdBC__h19477[53] ? - 7'd52 : - (sfdBC__h19477[52] ? - 7'd53 : - (sfdBC__h19477[51] ? - 7'd54 : - (sfdBC__h19477[50] ? - 7'd55 : - (sfdBC__h19477[49] ? - 7'd56 : - (sfdBC__h19477[48] ? - 7'd57 : - (sfdBC__h19477[47] ? - 7'd58 : - (sfdBC__h19477[46] ? - 7'd59 : - (sfdBC__h19477[45] ? - 7'd60 : - (sfdBC__h19477[44] ? - 7'd61 : - (sfdBC__h19477[43] ? - 7'd62 : - (sfdBC__h19477[42] ? - 7'd63 : - (sfdBC__h19477[41] ? - 7'd64 : - (sfdBC__h19477[40] ? - 7'd65 : - (sfdBC__h19477[39] ? - 7'd66 : - (sfdBC__h19477[38] ? - 7'd67 : - (sfdBC__h19477[37] ? - 7'd68 : - (sfdBC__h19477[36] ? - 7'd69 : - (sfdBC__h19477[35] ? - 7'd70 : - (sfdBC__h19477[34] ? - 7'd71 : - (sfdBC__h19477[33] ? - 7'd72 : - (sfdBC__h19477[32] ? - 7'd73 : - (sfdBC__h19477[31] ? - 7'd74 : - (sfdBC__h19477[30] ? - 7'd75 : - (sfdBC__h19477[29] ? - 7'd76 : - (sfdBC__h19477[28] ? - 7'd77 : - (sfdBC__h19477[27] ? - 7'd78 : - (sfdBC__h19477[26] ? - 7'd79 : - (sfdBC__h19477[25] ? - 7'd80 : - (sfdBC__h19477[24] ? - 7'd81 : - (sfdBC__h19477[23] ? - 7'd82 : - (sfdBC__h19477[22] ? - 7'd83 : - (sfdBC__h19477[21] ? - 7'd84 : - (sfdBC__h19477[20] ? - 7'd85 : - (sfdBC__h19477[19] ? - 7'd86 : - (sfdBC__h19477[18] ? - 7'd87 : - (sfdBC__h19477[17] ? - 7'd88 : - (sfdBC__h19477[16] ? - 7'd89 : - (sfdBC__h19477[15] ? - 7'd90 : - (sfdBC__h19477[14] ? - 7'd91 : - (sfdBC__h19477[13] ? - 7'd92 : - (sfdBC__h19477[12] ? - 7'd93 : - (sfdBC__h19477[11] ? - 7'd94 : - (sfdBC__h19477[10] ? - 7'd95 : - (sfdBC__h19477[9] ? - 7'd96 : - (sfdBC__h19477[8] ? - 7'd97 : - (sfdBC__h19477[7] ? - 7'd98 : - (sfdBC__h19477[6] ? - 7'd99 : - (sfdBC__h19477[5] ? - 7'd100 : - (sfdBC__h19477[4] ? - 7'd101 : - (sfdBC__h19477[3] ? - 7'd102 : - (sfdBC__h19477[2] ? - 7'd103 : - (sfdBC__h19477[1] ? - 7'd104 : - (sfdBC__h19477[0] ? - 7'd105 : - 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 = - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 - - 12'd3074 ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735 = - (sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h34764, sfdin__h34758[105:54] } ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? - fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194] : - ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 : - fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 : - ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? - 63'h7FF0000000000000 : - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112) ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51]) ? - { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 } : - ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118]) ? - fpu_fOperand_S0$D_OUT[130:67] : - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54]) ? - fpu_fOperand_S0$D_OUT[66:3] : - { NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 })) ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && - !_theResult___fst_sfd__h396[51]) ? - { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], - x__h327, - sfd__h3208 } : - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 ; - assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 = - (sfd__h36934[56] ? - 6'd0 : - (sfd__h36934[55] ? - 6'd1 : - (sfd__h36934[54] ? - 6'd2 : - (sfd__h36934[53] ? - 6'd3 : - (sfd__h36934[52] ? - 6'd4 : - (sfd__h36934[51] ? - 6'd5 : - (sfd__h36934[50] ? - 6'd6 : - (sfd__h36934[49] ? - 6'd7 : - (sfd__h36934[48] ? - 6'd8 : - (sfd__h36934[47] ? - 6'd9 : - (sfd__h36934[46] ? - 6'd10 : - (sfd__h36934[45] ? - 6'd11 : - (sfd__h36934[44] ? - 6'd12 : - (sfd__h36934[43] ? - 6'd13 : - (sfd__h36934[42] ? - 6'd14 : - (sfd__h36934[41] ? - 6'd15 : - (sfd__h36934[40] ? - 6'd16 : - (sfd__h36934[39] ? - 6'd17 : - (sfd__h36934[38] ? - 6'd18 : - (sfd__h36934[37] ? - 6'd19 : - (sfd__h36934[36] ? - 6'd20 : - (sfd__h36934[35] ? - 6'd21 : - (sfd__h36934[34] ? - 6'd22 : - (sfd__h36934[33] ? - 6'd23 : - (sfd__h36934[32] ? - 6'd24 : - (sfd__h36934[31] ? - 6'd25 : - (sfd__h36934[30] ? - 6'd26 : - (sfd__h36934[29] ? - 6'd27 : - (sfd__h36934[28] ? - 6'd28 : - (sfd__h36934[27] ? - 6'd29 : - (sfd__h36934[26] ? - 6'd30 : - (sfd__h36934[25] ? - 6'd31 : - (sfd__h36934[24] ? - 6'd32 : - (sfd__h36934[23] ? - 6'd33 : - (sfd__h36934[22] ? - 6'd34 : - (sfd__h36934[21] ? - 6'd35 : - (sfd__h36934[20] ? - 6'd36 : - (sfd__h36934[19] ? - 6'd37 : - (sfd__h36934[18] ? - 6'd38 : - (sfd__h36934[17] ? - 6'd39 : - (sfd__h36934[16] ? - 6'd40 : - (sfd__h36934[15] ? - 6'd41 : - (sfd__h36934[14] ? - 6'd42 : - (sfd__h36934[13] ? - 6'd43 : - (sfd__h36934[12] ? - 6'd44 : - (sfd__h36934[11] ? - 6'd45 : - (sfd__h36934[10] ? - 6'd46 : - (sfd__h36934[9] ? - 6'd47 : - (sfd__h36934[8] ? - 6'd48 : - (sfd__h36934[7] ? - 6'd49 : - (sfd__h36934[6] ? - 6'd50 : - (sfd__h36934[5] ? - 6'd51 : - (sfd__h36934[4] ? - 6'd52 : - (sfd__h36934[3] ? - 6'd53 : - (sfd__h36934[2] ? - 6'd54 : - (sfd__h36934[1] ? - 6'd55 : - (sfd__h36934[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153 = - (sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h45190, sfdin__h45184[56:5] } ; - assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704 = - (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? - fpu_fState_S3$D_OUT[86] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[4] ; - assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707 = - (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? - fpu_fState_S3$D_OUT[85] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[3] ; - assign IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 = - { NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 : - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 - - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 : - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 - - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, - x__h35755, - x__h35759 } ; - assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 = - (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && - !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ? - 63'h7FF8000000000000 : - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 ; - assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 = - (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperand_S0$D_OUT[118]) ? - { fpu_fOperand_S0$D_OUT[130:119], sfd__h3211 } : - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54]) ? - { fpu_fOperand_S0$D_OUT[66:55], sfd__h3214 } : - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137) ; - assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 = - { ((fpu_fOperand_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15[10]}}, - fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 }) + - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16[10]}}, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 }), - x__h18058, - x__h18070 } ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 = - fpu_fOperand_S0$D_OUT[195] ? - fpu_fOperand_S0$D_OUT[193:131] : - 63'd0 ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 = - x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 && - (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148 = - x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && - !_theResult___fst_sfd__h396[51] || - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperand_S0$D_OUT[118] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54] || - NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62 = - x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51] || - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54] || - x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 || - fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 ; - assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? - (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - 63'd0 : - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735) : - 63'h7FEFFFFFFFFFFFFF ; - assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[83] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[1] ; - assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[82] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[0] ; - assign IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726 = - fpu_fState_S3$D_OUT[151] ? - fpu_fState_S3$D_OUT[86:82] : - { IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, - IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, - NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 } ; - assign IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 = - (fpu_fState_S4$D_OUT[128:118] == 11'd0) ? - 13'd7170 : - { {2{fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7[10]}}, - fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 } ; - assign IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 = - (fpu_fState_S4$D_OUT[64:54] == 11'd0) ? - 13'd7170 : - { {2{fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6[10]}}, - fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 } ; - assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 = - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 - - 12'd3074 ; - assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 = - (value__h45122[10:0] == 11'd0) ? - 12'd3074 : - { value5122_BITS_10_TO_0_MINUS_1023__q8[10], - value5122_BITS_10_TO_0_MINUS_1023__q8 } ; - assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 = - (fpu_fState_S8$D_OUT[65:55] == 11'd0 && - sfd__h45855[53:52] == 2'b01) ? - 11'd1 : - fpu_fState_S8$D_OUT[65:55] ; - assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 = - (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[65:55] : - _theResult___fst_exp__h46437 ; - assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261 = - (fpu_fState_S8$D_OUT[67] && - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == - 11'd0 && - ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h46438) == - 52'd0 && - !fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244[0] && - fpu_fState_S8$D_OUT[0]) ? - fpu_fState_S8$D_OUT[70:68] == 3'd3 : - ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[66] : - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14) ; - assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 = - { IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, - (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[65:3] : - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19, - fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 } ; - assign IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5 = - sfdin__h34758[53] ? 2'd2 : 2'd0 ; - assign IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10 = - sfdin__h45184[4] ? 2'd2 : 2'd0 ; - assign NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 = - (x__h327 != 11'd2047 || !_theResult___fst_sfd__h396[51]) && - (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperand_S0$D_OUT[118]) && - (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperand_S0$D_OUT[54]) && - (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && - !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ; - assign NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124 = - (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperand_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && - (x__h327 != 11'd2047 || _theResult___fst_sfd__h396 != 52'd0 || - (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperand_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperand_S0$D_OUT[54:3] != 52'd0) || - fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) && - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 ; - assign NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 = - fpu_fOperand_S0$D_OUT[130] != fpu_fOperand_S0$D_OUT[66] ; - assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711 = - !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - fpu_fState_S3$D_OUT[84] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[2]) ; - assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 = - { NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 : - fpu_fState_S3$D_OUT[83], - !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 } ; - assign NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 = - !fpu_fState_S4$D_OUT[130] || - (IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 ^ - 13'h1000) > - (IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 ^ - 13'h1000) || - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 == - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 && - sfdBC__h35393 > sfdA__h35392 ; - assign _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 = - ({ 5'd0, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ^ - 12'h800) <= - (IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 = - ({ 6'd0, - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ^ - 12'h800) <= - (IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ^ - 12'h800) ; - assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 = - 13'd7170 - fpu_fState_S3$D_OUT[12:0] ; - assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 = - (_7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ^ - 13'h1000) <= - 13'd4096 ; - assign _theResult___exp__h46359 = - sfd__h45855[53] ? - ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h46444) : - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 ; - assign _theResult___fst__h20642 = - { fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[105:1], - fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[0] | - sfdlsb__h20640 } ; - assign _theResult___fst_exp__h34764 = - sfdBC__h19477[105] ? - _theResult___fst_exp__h34786 : - _theResult___fst_exp__h34849 ; - assign _theResult___fst_exp__h34767 = - (sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h34764 ; - assign _theResult___fst_exp__h34786 = - (din_exp__h34681 == 11'd0) ? 11'd2 : din_exp__h34681 + 11'd1 ; - assign _theResult___fst_exp__h34801 = - (din_exp__h34681 == 11'd0) ? 11'd1 : din_exp__h34681 ; - assign _theResult___fst_exp__h34840 = - din_exp__h34681 - - { 4'd0, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ; - assign _theResult___fst_exp__h34846 = - (!sfdBC__h19477[105] && !sfdBC__h19477[104] && - !sfdBC__h19477[103] && - !sfdBC__h19477[102] && - !sfdBC__h19477[101] && - !sfdBC__h19477[100] && - !sfdBC__h19477[99] && - !sfdBC__h19477[98] && - !sfdBC__h19477[97] && - !sfdBC__h19477[96] && - !sfdBC__h19477[95] && - !sfdBC__h19477[94] && - !sfdBC__h19477[93] && - !sfdBC__h19477[92] && - !sfdBC__h19477[91] && - !sfdBC__h19477[90] && - !sfdBC__h19477[89] && - !sfdBC__h19477[88] && - !sfdBC__h19477[87] && - !sfdBC__h19477[86] && - !sfdBC__h19477[85] && - !sfdBC__h19477[84] && - !sfdBC__h19477[83] && - !sfdBC__h19477[82] && - !sfdBC__h19477[81] && - !sfdBC__h19477[80] && - !sfdBC__h19477[79] && - !sfdBC__h19477[78] && - !sfdBC__h19477[77] && - !sfdBC__h19477[76] && - !sfdBC__h19477[75] && - !sfdBC__h19477[74] && - !sfdBC__h19477[73] && - !sfdBC__h19477[72] && - !sfdBC__h19477[71] && - !sfdBC__h19477[70] && - !sfdBC__h19477[69] && - !sfdBC__h19477[68] && - !sfdBC__h19477[67] && - !sfdBC__h19477[66] && - !sfdBC__h19477[65] && - !sfdBC__h19477[64] && - !sfdBC__h19477[63] && - !sfdBC__h19477[62] && - !sfdBC__h19477[61] && - !sfdBC__h19477[60] && - !sfdBC__h19477[59] && - !sfdBC__h19477[58] && - !sfdBC__h19477[57] && - !sfdBC__h19477[56] && - !sfdBC__h19477[55] && - !sfdBC__h19477[54] && - !sfdBC__h19477[53] && - !sfdBC__h19477[52] && - !sfdBC__h19477[51] && - !sfdBC__h19477[50] && - !sfdBC__h19477[49] && - !sfdBC__h19477[48] && - !sfdBC__h19477[47] && - !sfdBC__h19477[46] && - !sfdBC__h19477[45] && - !sfdBC__h19477[44] && - !sfdBC__h19477[43] && - !sfdBC__h19477[42] && - !sfdBC__h19477[41] && - !sfdBC__h19477[40] && - !sfdBC__h19477[39] && - !sfdBC__h19477[38] && - !sfdBC__h19477[37] && - !sfdBC__h19477[36] && - !sfdBC__h19477[35] && - !sfdBC__h19477[34] && - !sfdBC__h19477[33] && - !sfdBC__h19477[32] && - !sfdBC__h19477[31] && - !sfdBC__h19477[30] && - !sfdBC__h19477[29] && - !sfdBC__h19477[28] && - !sfdBC__h19477[27] && - !sfdBC__h19477[26] && - !sfdBC__h19477[25] && - !sfdBC__h19477[24] && - !sfdBC__h19477[23] && - !sfdBC__h19477[22] && - !sfdBC__h19477[21] && - !sfdBC__h19477[20] && - !sfdBC__h19477[19] && - !sfdBC__h19477[18] && - !sfdBC__h19477[17] && - !sfdBC__h19477[16] && - !sfdBC__h19477[15] && - !sfdBC__h19477[14] && - !sfdBC__h19477[13] && - !sfdBC__h19477[12] && - !sfdBC__h19477[11] && - !sfdBC__h19477[10] && - !sfdBC__h19477[9] && - !sfdBC__h19477[8] && - !sfdBC__h19477[7] && - !sfdBC__h19477[6] && - !sfdBC__h19477[5] && - !sfdBC__h19477[4] && - !sfdBC__h19477[3] && - !sfdBC__h19477[2] && - !sfdBC__h19477[1] && - !sfdBC__h19477[0] || - !_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664) ? - 11'd0 : - _theResult___fst_exp__h34840 ; - assign _theResult___fst_exp__h34849 = - (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? - _theResult___fst_exp__h34801 : - _theResult___fst_exp__h34846 ; - assign _theResult___fst_exp__h45190 = - sfd__h36934[56] ? - _theResult___fst_exp__h45212 : - _theResult___fst_exp__h45275 ; - assign _theResult___fst_exp__h45193 = - (sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h45190 ; - assign _theResult___fst_exp__h45212 = - (value__h45122[10:0] == 11'd0) ? - 11'd2 : - value__h45122[10:0] + 11'd1 ; - assign _theResult___fst_exp__h45227 = - (value__h45122[10:0] == 11'd0) ? 11'd1 : value__h45122[10:0] ; - assign _theResult___fst_exp__h45266 = - value__h45122[10:0] - - { 5'd0, - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ; - assign _theResult___fst_exp__h45272 = - (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && - !sfd__h36934[53] && - !sfd__h36934[52] && - !sfd__h36934[51] && - !sfd__h36934[50] && - !sfd__h36934[49] && - !sfd__h36934[48] && - !sfd__h36934[47] && - !sfd__h36934[46] && - !sfd__h36934[45] && - !sfd__h36934[44] && - !sfd__h36934[43] && - !sfd__h36934[42] && - !sfd__h36934[41] && - !sfd__h36934[40] && - !sfd__h36934[39] && - !sfd__h36934[38] && - !sfd__h36934[37] && - !sfd__h36934[36] && - !sfd__h36934[35] && - !sfd__h36934[34] && - !sfd__h36934[33] && - !sfd__h36934[32] && - !sfd__h36934[31] && - !sfd__h36934[30] && - !sfd__h36934[29] && - !sfd__h36934[28] && - !sfd__h36934[27] && - !sfd__h36934[26] && - !sfd__h36934[25] && - !sfd__h36934[24] && - !sfd__h36934[23] && - !sfd__h36934[22] && - !sfd__h36934[21] && - !sfd__h36934[20] && - !sfd__h36934[19] && - !sfd__h36934[18] && - !sfd__h36934[17] && - !sfd__h36934[16] && - !sfd__h36934[15] && - !sfd__h36934[14] && - !sfd__h36934[13] && - !sfd__h36934[12] && - !sfd__h36934[11] && - !sfd__h36934[10] && - !sfd__h36934[9] && - !sfd__h36934[8] && - !sfd__h36934[7] && - !sfd__h36934[6] && - !sfd__h36934[5] && - !sfd__h36934[4] && - !sfd__h36934[3] && - !sfd__h36934[2] && - !sfd__h36934[1] && - !sfd__h36934[0] || - !_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105) ? - 11'd0 : - _theResult___fst_exp__h45266 ; - assign _theResult___fst_exp__h45275 = - (!sfd__h36934[56] && sfd__h36934[55]) ? - _theResult___fst_exp__h45227 : - _theResult___fst_exp__h45272 ; - assign _theResult___fst_sfd__h396 = - fpu_fOperand_S0$D_OUT[195] ? - fpu_fOperand_S0$D_OUT[182:131] : - 52'd0 ; - assign _theResult___sfd__h46360 = - sfd__h45855[53] ? - ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? - 52'd0 : - sfd__h45855[52:1]) : - sfd__h45855[51:0] ; - assign _theResult___snd__h34781 = { sfdBC__h19477[104:0], 1'd0 } ; - assign _theResult___snd__h34795 = - (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? - _theResult___snd__h34797 : - _theResult___snd__h34809 ; - assign _theResult___snd__h34797 = { sfdBC__h19477[103:0], 2'd0 } ; - assign _theResult___snd__h34809 = - (!sfdBC__h19477[105] && !sfdBC__h19477[104] && - !sfdBC__h19477[103] && - !sfdBC__h19477[102] && - !sfdBC__h19477[101] && - !sfdBC__h19477[100] && - !sfdBC__h19477[99] && - !sfdBC__h19477[98] && - !sfdBC__h19477[97] && - !sfdBC__h19477[96] && - !sfdBC__h19477[95] && - !sfdBC__h19477[94] && - !sfdBC__h19477[93] && - !sfdBC__h19477[92] && - !sfdBC__h19477[91] && - !sfdBC__h19477[90] && - !sfdBC__h19477[89] && - !sfdBC__h19477[88] && - !sfdBC__h19477[87] && - !sfdBC__h19477[86] && - !sfdBC__h19477[85] && - !sfdBC__h19477[84] && - !sfdBC__h19477[83] && - !sfdBC__h19477[82] && - !sfdBC__h19477[81] && - !sfdBC__h19477[80] && - !sfdBC__h19477[79] && - !sfdBC__h19477[78] && - !sfdBC__h19477[77] && - !sfdBC__h19477[76] && - !sfdBC__h19477[75] && - !sfdBC__h19477[74] && - !sfdBC__h19477[73] && - !sfdBC__h19477[72] && - !sfdBC__h19477[71] && - !sfdBC__h19477[70] && - !sfdBC__h19477[69] && - !sfdBC__h19477[68] && - !sfdBC__h19477[67] && - !sfdBC__h19477[66] && - !sfdBC__h19477[65] && - !sfdBC__h19477[64] && - !sfdBC__h19477[63] && - !sfdBC__h19477[62] && - !sfdBC__h19477[61] && - !sfdBC__h19477[60] && - !sfdBC__h19477[59] && - !sfdBC__h19477[58] && - !sfdBC__h19477[57] && - !sfdBC__h19477[56] && - !sfdBC__h19477[55] && - !sfdBC__h19477[54] && - !sfdBC__h19477[53] && - !sfdBC__h19477[52] && - !sfdBC__h19477[51] && - !sfdBC__h19477[50] && - !sfdBC__h19477[49] && - !sfdBC__h19477[48] && - !sfdBC__h19477[47] && - !sfdBC__h19477[46] && - !sfdBC__h19477[45] && - !sfdBC__h19477[44] && - !sfdBC__h19477[43] && - !sfdBC__h19477[42] && - !sfdBC__h19477[41] && - !sfdBC__h19477[40] && - !sfdBC__h19477[39] && - !sfdBC__h19477[38] && - !sfdBC__h19477[37] && - !sfdBC__h19477[36] && - !sfdBC__h19477[35] && - !sfdBC__h19477[34] && - !sfdBC__h19477[33] && - !sfdBC__h19477[32] && - !sfdBC__h19477[31] && - !sfdBC__h19477[30] && - !sfdBC__h19477[29] && - !sfdBC__h19477[28] && - !sfdBC__h19477[27] && - !sfdBC__h19477[26] && - !sfdBC__h19477[25] && - !sfdBC__h19477[24] && - !sfdBC__h19477[23] && - !sfdBC__h19477[22] && - !sfdBC__h19477[21] && - !sfdBC__h19477[20] && - !sfdBC__h19477[19] && - !sfdBC__h19477[18] && - !sfdBC__h19477[17] && - !sfdBC__h19477[16] && - !sfdBC__h19477[15] && - !sfdBC__h19477[14] && - !sfdBC__h19477[13] && - !sfdBC__h19477[12] && - !sfdBC__h19477[11] && - !sfdBC__h19477[10] && - !sfdBC__h19477[9] && - !sfdBC__h19477[8] && - !sfdBC__h19477[7] && - !sfdBC__h19477[6] && - !sfdBC__h19477[5] && - !sfdBC__h19477[4] && - !sfdBC__h19477[3] && - !sfdBC__h19477[2] && - !sfdBC__h19477[1] && - !sfdBC__h19477[0]) ? - sfdBC__h19477 : - _theResult___snd__h34815 ; - assign _theResult___snd__h34815 = - { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4[103:0], - 2'd0 } ; - assign _theResult___snd__h34833 = - sfdBC__h19477 << - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ; - assign _theResult___snd__h34838 = - sfdBC__h19477 << - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 ; - assign _theResult___snd__h45207 = { sfd__h36934[55:0], 1'd0 } ; - assign _theResult___snd__h45221 = - (!sfd__h36934[56] && sfd__h36934[55]) ? - _theResult___snd__h45223 : - _theResult___snd__h45235 ; - assign _theResult___snd__h45223 = { sfd__h36934[54:0], 2'd0 } ; - assign _theResult___snd__h45235 = - (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && - !sfd__h36934[53] && - !sfd__h36934[52] && - !sfd__h36934[51] && - !sfd__h36934[50] && - !sfd__h36934[49] && - !sfd__h36934[48] && - !sfd__h36934[47] && - !sfd__h36934[46] && - !sfd__h36934[45] && - !sfd__h36934[44] && - !sfd__h36934[43] && - !sfd__h36934[42] && - !sfd__h36934[41] && - !sfd__h36934[40] && - !sfd__h36934[39] && - !sfd__h36934[38] && - !sfd__h36934[37] && - !sfd__h36934[36] && - !sfd__h36934[35] && - !sfd__h36934[34] && - !sfd__h36934[33] && - !sfd__h36934[32] && - !sfd__h36934[31] && - !sfd__h36934[30] && - !sfd__h36934[29] && - !sfd__h36934[28] && - !sfd__h36934[27] && - !sfd__h36934[26] && - !sfd__h36934[25] && - !sfd__h36934[24] && - !sfd__h36934[23] && - !sfd__h36934[22] && - !sfd__h36934[21] && - !sfd__h36934[20] && - !sfd__h36934[19] && - !sfd__h36934[18] && - !sfd__h36934[17] && - !sfd__h36934[16] && - !sfd__h36934[15] && - !sfd__h36934[14] && - !sfd__h36934[13] && - !sfd__h36934[12] && - !sfd__h36934[11] && - !sfd__h36934[10] && - !sfd__h36934[9] && - !sfd__h36934[8] && - !sfd__h36934[7] && - !sfd__h36934[6] && - !sfd__h36934[5] && - !sfd__h36934[4] && - !sfd__h36934[3] && - !sfd__h36934[2] && - !sfd__h36934[1] && - !sfd__h36934[0]) ? - sfd__h36934 : - _theResult___snd__h45241 ; - assign _theResult___snd__h45241 = - { IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9[54:0], - 2'd0 } ; - assign _theResult___snd__h45259 = - sfd__h36934 << - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ; - assign _theResult___snd__h45264 = - sfd__h36934 << - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 ; - assign _theResult___snd_fst__h34866 = - { IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5[1], - { sfdin__h34758[52:0], 52'd0 } != 105'd0 } ; - assign _theResult___snd_fst__h45292 = - { IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10[1], - { sfdin__h45184[3:0], 52'd0 } != 56'd0 } ; - assign _theResult___snd_snd__h35186 = - (fpu_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; - assign _theResult___snd_snd_snd__h35184 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - _theResult___snd_snd__h35186 : - guardBC__h19481 ; - assign din_exp4681_MINUS_1023__q3 = din_exp__h34681 - 11'd1023 ; - assign din_exp__h34681 = - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? - value__h34698[10:0] : - 11'd0 ; - assign din_inc___2_exp__h46444 = fpu_fState_S8$D_OUT[65:55] + 11'd1 ; - assign fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 = - fpu_fOperand_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 = - fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 = - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 = - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || - x__h327 == 11'd0 && _theResult___fst_sfd__h396 == 52'd0 && - (fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) && - fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 ; - assign fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 = - (fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) == - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 ; - assign fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213 = - fpu_fProd_S3$D_OUT >> - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; - assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 = - (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; - assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 = - (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; - assign fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702 = - fpu_fState_S3$D_OUT[86:82] | - { 2'd0, - sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023, - _theResult___fst_exp__h34767 == 11'd0 && - guardBC__h19481 != 2'd0, - sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023 } ; - assign fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 = - fpu_fState_S4$D_OUT[128:118] - 11'd1023 ; - assign fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 = - fpu_fState_S4$D_OUT[64:54] - 11'd1023 ; - assign fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816 = - fpu_fState_S5$D_OUT[56:0] >> fpu_fState_S5$D_OUT[126:114] ; - assign fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143 = - fpu_fState_S7$D_OUT[137:133] | - { 2'd0, - sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023, - _theResult___fst_exp__h45193 == 11'd0 && guard__h36938 != 2'd0, - sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023 } ; - assign fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 = - fpu_fState_S8$D_OUT[75:71] | - { 2'd0, - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == - 11'd2047 && - ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h46438) == - 52'd0, - 1'd0, - fpu_fState_S8$D_OUT[65:55] != 11'd2047 && - fpu_fState_S8$D_OUT[2:1] != 2'b0 } ; - assign guardBC__h19481 = - (sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h34866 ; - assign guard__h36182 = fpu_fState_S5$D_OUT[56:0] << x__h36286 ; - assign guard__h36938 = - (sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h45292 ; - assign out_exp__h46362 = - fpu_fState_S8$D_OUT[3] ? - _theResult___exp__h46359 : - fpu_fState_S8$D_OUT[65:55] ; - assign out_sfd__h46363 = - fpu_fState_S8$D_OUT[3] ? - _theResult___sfd__h46360 : - fpu_fState_S8$D_OUT[54:3] ; - assign result__h36187 = - { fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[56:1], - fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[0] | - guard__h36182 != 57'd0 } ; - assign sfdA__h35392 = - { 1'b0, - fpu_fState_S4$D_OUT[128:118] != 11'd0, - fpu_fState_S4$D_OUT[117:66], - 3'b0 } ; - assign sfdBC__h19477 = - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? - fpu_fProd_S3$D_OUT : - _theResult___fst__h20642 ; - assign sfdBC__h35393 = - { 1'b0, - fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:0], - 1'b0 } ; - assign sfd__h3208 = { 1'd1, _theResult___fst_sfd__h396[50:0] } ; - assign sfd__h3211 = { 1'd1, fpu_fOperand_S0$D_OUT[117:67] } ; - assign sfd__h3214 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h36934 = - fpu_fState_S7$D_OUT[128] ? - fpu_fState_S7$D_OUT[56:0] : - fpu_fState_S7$D_OUT[113:57] ; - assign sfd__h45855 = - { 1'b0, - fpu_fState_S8$D_OUT[65:55] != 11'd0, - fpu_fState_S8$D_OUT[54:3] } + - 54'd1 ; - assign sfdin__h34758 = - sfdBC__h19477[105] ? - _theResult___snd__h34781 : - _theResult___snd__h34795 ; - assign sfdin__h45184 = - sfd__h36934[56] ? - _theResult___snd__h45207 : - _theResult___snd__h45221 ; - assign sfdlsb__h20640 = x__h20711 != 106'd0 ; - assign value5122_BITS_10_TO_0_MINUS_1023__q8 = - value__h45122[10:0] - 11'd1023 ; - assign value__h34698 = fpu_fState_S3$D_OUT[12:0] + 13'd1023 ; - assign value__h45122 = fpu_fState_S7$D_OUT[126:114] + 13'd1023 ; - assign x__h18058 = - { fpu_fOperand_S0$D_OUT[129:119] != 11'd0, - fpu_fOperand_S0$D_OUT[118:67] } ; - assign x__h18070 = - { fpu_fOperand_S0$D_OUT[65:55] != 11'd0, - fpu_fOperand_S0$D_OUT[54:3] } ; - assign x__h20711 = fpu_fProd_S3$D_OUT << x__h20744 ; - assign x__h20744 = - 13'd106 - - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; - assign x__h327 = - fpu_fOperand_S0$D_OUT[195] ? - fpu_fOperand_S0$D_OUT[193:183] : - 11'd0 ; - assign x__h35221 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? - _theResult___snd_snd_snd__h35184 : - 2'd3 ; - assign x__h35755 = - { 1'b0, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - { fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:0], - 1'b0 } : - { fpu_fState_S4$D_OUT[128:118] != 11'd0, - fpu_fState_S4$D_OUT[117:66], - 3'b0 } } ; - assign x__h35759 = - { 1'b0, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - { fpu_fState_S4$D_OUT[128:118] != 11'd0, - fpu_fState_S4$D_OUT[117:66], - 3'b0 } : - { fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:0], - 1'b0 } } ; - assign x__h36174 = - fpu_fState_S5$D_OUT[215] ? - fpu_fState_S5$D_OUT[56:0] : - (((fpu_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? - result__h36187 : - ((fpu_fState_S5$D_OUT[56:0] == 57'd0) ? - fpu_fState_S5$D_OUT[56:0] : - 57'd1)) ; - assign x__h36286 = 13'd57 - fpu_fState_S5$D_OUT[126:114] ; - assign x__h36686 = fpu_fState_S6$D_OUT[113:57] + fpu_fState_S6$D_OUT[56:0] ; - assign x__h36695 = fpu_fState_S6$D_OUT[113:57] - fpu_fState_S6$D_OUT[56:0] ; - assign x__h45575 = fpu_fState_S7$D_OUT[202] ? 2'd0 : guard__h36938 ; - always@(fpu_fState_S8$D_OUT or out_sfd__h46363 or _theResult___sfd__h46360) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = - fpu_fState_S8$D_OUT[54:3]; - 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = - out_sfd__h46363; - 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = - _theResult___sfd__h46360; - endcase - end - always@(fpu_fState_S8$D_OUT or _theResult___sfd__h46360) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = - fpu_fState_S8$D_OUT[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = - _theResult___sfd__h46360; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 or - _theResult___sfd__h46360) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_sfd__h46438 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1; - 3'd1: - _theResult___fst_sfd__h46438 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2; - 3'd2: - _theResult___fst_sfd__h46438 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? - fpu_fState_S8$D_OUT[54:3] : - _theResult___sfd__h46360; - 3'd3: - _theResult___fst_sfd__h46438 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[54:3] : - (fpu_fState_S8$D_OUT[66] ? - _theResult___sfd__h46360 : - fpu_fState_S8$D_OUT[54:3]); - 3'd4: _theResult___fst_sfd__h46438 = fpu_fState_S8$D_OUT[54:3]; - default: _theResult___fst_sfd__h46438 = 52'd0; - endcase - end - always@(fpu_fState_S8$D_OUT or out_exp__h46362 or _theResult___exp__h46359) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = - fpu_fState_S8$D_OUT[65:55]; - 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = - out_exp__h46362; - 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = - _theResult___exp__h46359; - endcase - end - always@(fpu_fState_S8$D_OUT or _theResult___exp__h46359) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = - fpu_fState_S8$D_OUT[65:55]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = - _theResult___exp__h46359; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 or - _theResult___exp__h46359) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_exp__h46437 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11; - 3'd1: - _theResult___fst_exp__h46437 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12; - 3'd2: - _theResult___fst_exp__h46437 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? - fpu_fState_S8$D_OUT[65:55] : - _theResult___exp__h46359; - 3'd3: - _theResult___fst_exp__h46437 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[65:55] : - (fpu_fState_S8$D_OUT[66] ? - _theResult___exp__h46359 : - fpu_fState_S8$D_OUT[65:55]); - 3'd4: _theResult___fst_exp__h46437 = fpu_fState_S8$D_OUT[65:55]; - default: _theResult___fst_exp__h46437 = 11'd0; - endcase - end - always@(fpu_fState_S8$D_OUT) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = - fpu_fState_S8$D_OUT[66]; - 2'd3: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = - fpu_fState_S8$D_OUT[2:1] == 2'b11 && fpu_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13; - 3'd1: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[66] : - (fpu_fState_S8$D_OUT[2:1] == 2'b01 || - fpu_fState_S8$D_OUT[2:1] == 2'b10 || - fpu_fState_S8$D_OUT[2:1] == 2'b11) && - fpu_fState_S8$D_OUT[66]; - 3'd2, 3'd3: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - fpu_fState_S8$D_OUT[66]; - default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - fpu_fState_S8$D_OUT[70:68] == 3'd4 && - fpu_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = - fpu_fState_S8$D_OUT[65:3]; - 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = - fpu_fState_S8$D_OUT[3] ? - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : - fpu_fState_S8$D_OUT[65:3]; - 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; - endcase - end - always@(fpu_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = - fpu_fState_S8$D_OUT[65:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 or - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17; - 3'd1: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18; - 3'd2: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? - fpu_fState_S8$D_OUT[65:3] : - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; - 3'd3: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[65:3] : - (fpu_fState_S8$D_OUT[66] ? - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : - fpu_fState_S8$D_OUT[65:3]); - 3'd4: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - fpu_fState_S8$D_OUT[65:3]; - default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = 63'd0; - endcase - end + // submodule fpu + assign fpu$request_put = request_put ; + assign fpu$EN_request_put = EN_request_put ; + assign fpu$EN_response_get = EN_response_get ; endmodule // mkDoubleFMA diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v index 9ba65dd..8b1becd 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v @@ -7,16 +7,15 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 reg -// RDY_response_get O 1 reg +// response_get O 69 +// RDY_response_get O 1 // CLK I 1 clock // RST_N I 1 reset -// request_put I 67 reg +// request_put I 67 // EN_request_put I 1 // EN_response_get I 1 // -// Combinational paths from inputs to outputs: -// EN_response_get -> RDY_request_put +// No combinational paths from inputs to outputs // // @@ -60,5579 +59,44 @@ module mkDoubleSqrt(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu_fOperand_S0 - wire [66 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; - wire fpu_fOperand_S0$CLR, - fpu_fOperand_S0$DEQ, - fpu_fOperand_S0$EMPTY_N, - fpu_fOperand_S0$ENQ, - fpu_fOperand_S0$FULL_N; - - // ports of submodule fpu_fResult_S5 - wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; - wire fpu_fResult_S5$CLR, - fpu_fResult_S5$DEQ, - fpu_fResult_S5$EMPTY_N, - fpu_fResult_S5$ENQ, - fpu_fResult_S5$FULL_N; - - // ports of submodule fpu_fState_S1 - wire [194 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; - wire fpu_fState_S1$CLR, - fpu_fState_S1$DEQ, - fpu_fState_S1$EMPTY_N, - fpu_fState_S1$ENQ, - fpu_fState_S1$FULL_N; - - // ports of submodule fpu_fState_S2 - wire [136 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; - wire fpu_fState_S2$CLR, - fpu_fState_S2$DEQ, - fpu_fState_S2$EMPTY_N, - fpu_fState_S2$ENQ, - fpu_fState_S2$FULL_N; - - // ports of submodule fpu_fState_S3 - wire [195 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; - wire fpu_fState_S3$CLR, - fpu_fState_S3$DEQ, - fpu_fState_S3$EMPTY_N, - fpu_fState_S3$ENQ, - fpu_fState_S3$FULL_N; - - // ports of submodule fpu_fState_S4 - wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; - wire fpu_fState_S4$CLR, - fpu_fState_S4$DEQ, - fpu_fState_S4$EMPTY_N, - fpu_fState_S4$ENQ, - fpu_fState_S4$FULL_N; - - // ports of submodule int_sqrt_fFirst - wire [464 : 0] int_sqrt_fFirst$D_IN, int_sqrt_fFirst$D_OUT; - wire int_sqrt_fFirst$CLR, - int_sqrt_fFirst$DEQ, - int_sqrt_fFirst$EMPTY_N, - int_sqrt_fFirst$ENQ, - int_sqrt_fFirst$FULL_N; - - // ports of submodule int_sqrt_fNext_0 - wire [464 : 0] int_sqrt_fNext_0$D_IN, int_sqrt_fNext_0$D_OUT; - wire int_sqrt_fNext_0$CLR, - int_sqrt_fNext_0$DEQ, - int_sqrt_fNext_0$EMPTY_N, - int_sqrt_fNext_0$ENQ, - int_sqrt_fNext_0$FULL_N; - - // ports of submodule int_sqrt_fNext_1 - wire [464 : 0] int_sqrt_fNext_1$D_IN, int_sqrt_fNext_1$D_OUT; - wire int_sqrt_fNext_1$CLR, - int_sqrt_fNext_1$DEQ, - int_sqrt_fNext_1$EMPTY_N, - int_sqrt_fNext_1$ENQ, - int_sqrt_fNext_1$FULL_N; - - // ports of submodule int_sqrt_fNext_10 - wire [464 : 0] int_sqrt_fNext_10$D_IN, int_sqrt_fNext_10$D_OUT; - wire int_sqrt_fNext_10$CLR, - int_sqrt_fNext_10$DEQ, - int_sqrt_fNext_10$EMPTY_N, - int_sqrt_fNext_10$ENQ, - int_sqrt_fNext_10$FULL_N; - - // ports of submodule int_sqrt_fNext_11 - wire [464 : 0] int_sqrt_fNext_11$D_IN, int_sqrt_fNext_11$D_OUT; - wire int_sqrt_fNext_11$CLR, - int_sqrt_fNext_11$DEQ, - int_sqrt_fNext_11$EMPTY_N, - int_sqrt_fNext_11$ENQ, - int_sqrt_fNext_11$FULL_N; - - // ports of submodule int_sqrt_fNext_12 - wire [464 : 0] int_sqrt_fNext_12$D_IN, int_sqrt_fNext_12$D_OUT; - wire int_sqrt_fNext_12$CLR, - int_sqrt_fNext_12$DEQ, - int_sqrt_fNext_12$EMPTY_N, - int_sqrt_fNext_12$ENQ, - int_sqrt_fNext_12$FULL_N; - - // ports of submodule int_sqrt_fNext_13 - wire [464 : 0] int_sqrt_fNext_13$D_IN, int_sqrt_fNext_13$D_OUT; - wire int_sqrt_fNext_13$CLR, - int_sqrt_fNext_13$DEQ, - int_sqrt_fNext_13$EMPTY_N, - int_sqrt_fNext_13$ENQ, - int_sqrt_fNext_13$FULL_N; - - // ports of submodule int_sqrt_fNext_14 - wire [464 : 0] int_sqrt_fNext_14$D_IN, int_sqrt_fNext_14$D_OUT; - wire int_sqrt_fNext_14$CLR, - int_sqrt_fNext_14$DEQ, - int_sqrt_fNext_14$EMPTY_N, - int_sqrt_fNext_14$ENQ, - int_sqrt_fNext_14$FULL_N; - - // ports of submodule int_sqrt_fNext_15 - wire [464 : 0] int_sqrt_fNext_15$D_IN, int_sqrt_fNext_15$D_OUT; - wire int_sqrt_fNext_15$CLR, - int_sqrt_fNext_15$DEQ, - int_sqrt_fNext_15$EMPTY_N, - int_sqrt_fNext_15$ENQ, - int_sqrt_fNext_15$FULL_N; - - // ports of submodule int_sqrt_fNext_16 - wire [464 : 0] int_sqrt_fNext_16$D_IN, int_sqrt_fNext_16$D_OUT; - wire int_sqrt_fNext_16$CLR, - int_sqrt_fNext_16$DEQ, - int_sqrt_fNext_16$EMPTY_N, - int_sqrt_fNext_16$ENQ, - int_sqrt_fNext_16$FULL_N; - - // ports of submodule int_sqrt_fNext_17 - wire [464 : 0] int_sqrt_fNext_17$D_IN, int_sqrt_fNext_17$D_OUT; - wire int_sqrt_fNext_17$CLR, - int_sqrt_fNext_17$DEQ, - int_sqrt_fNext_17$EMPTY_N, - int_sqrt_fNext_17$ENQ, - int_sqrt_fNext_17$FULL_N; - - // ports of submodule int_sqrt_fNext_18 - wire [464 : 0] int_sqrt_fNext_18$D_IN, int_sqrt_fNext_18$D_OUT; - wire int_sqrt_fNext_18$CLR, - int_sqrt_fNext_18$DEQ, - int_sqrt_fNext_18$EMPTY_N, - int_sqrt_fNext_18$ENQ, - int_sqrt_fNext_18$FULL_N; - - // ports of submodule int_sqrt_fNext_19 - wire [464 : 0] int_sqrt_fNext_19$D_IN, int_sqrt_fNext_19$D_OUT; - wire int_sqrt_fNext_19$CLR, - int_sqrt_fNext_19$DEQ, - int_sqrt_fNext_19$EMPTY_N, - int_sqrt_fNext_19$ENQ, - int_sqrt_fNext_19$FULL_N; - - // ports of submodule int_sqrt_fNext_2 - wire [464 : 0] int_sqrt_fNext_2$D_IN, int_sqrt_fNext_2$D_OUT; - wire int_sqrt_fNext_2$CLR, - int_sqrt_fNext_2$DEQ, - int_sqrt_fNext_2$EMPTY_N, - int_sqrt_fNext_2$ENQ, - int_sqrt_fNext_2$FULL_N; - - // ports of submodule int_sqrt_fNext_20 - wire [464 : 0] int_sqrt_fNext_20$D_IN, int_sqrt_fNext_20$D_OUT; - wire int_sqrt_fNext_20$CLR, - int_sqrt_fNext_20$DEQ, - int_sqrt_fNext_20$EMPTY_N, - int_sqrt_fNext_20$ENQ, - int_sqrt_fNext_20$FULL_N; - - // ports of submodule int_sqrt_fNext_21 - wire [464 : 0] int_sqrt_fNext_21$D_IN, int_sqrt_fNext_21$D_OUT; - wire int_sqrt_fNext_21$CLR, - int_sqrt_fNext_21$DEQ, - int_sqrt_fNext_21$EMPTY_N, - int_sqrt_fNext_21$ENQ, - int_sqrt_fNext_21$FULL_N; - - // ports of submodule int_sqrt_fNext_22 - wire [464 : 0] int_sqrt_fNext_22$D_IN, int_sqrt_fNext_22$D_OUT; - wire int_sqrt_fNext_22$CLR, - int_sqrt_fNext_22$DEQ, - int_sqrt_fNext_22$EMPTY_N, - int_sqrt_fNext_22$ENQ, - int_sqrt_fNext_22$FULL_N; - - // ports of submodule int_sqrt_fNext_23 - wire [464 : 0] int_sqrt_fNext_23$D_IN, int_sqrt_fNext_23$D_OUT; - wire int_sqrt_fNext_23$CLR, - int_sqrt_fNext_23$DEQ, - int_sqrt_fNext_23$EMPTY_N, - int_sqrt_fNext_23$ENQ, - int_sqrt_fNext_23$FULL_N; - - // ports of submodule int_sqrt_fNext_24 - wire [464 : 0] int_sqrt_fNext_24$D_IN, int_sqrt_fNext_24$D_OUT; - wire int_sqrt_fNext_24$CLR, - int_sqrt_fNext_24$DEQ, - int_sqrt_fNext_24$EMPTY_N, - int_sqrt_fNext_24$ENQ, - int_sqrt_fNext_24$FULL_N; - - // ports of submodule int_sqrt_fNext_25 - wire [464 : 0] int_sqrt_fNext_25$D_IN, int_sqrt_fNext_25$D_OUT; - wire int_sqrt_fNext_25$CLR, - int_sqrt_fNext_25$DEQ, - int_sqrt_fNext_25$EMPTY_N, - int_sqrt_fNext_25$ENQ, - int_sqrt_fNext_25$FULL_N; - - // ports of submodule int_sqrt_fNext_26 - wire [464 : 0] int_sqrt_fNext_26$D_IN, int_sqrt_fNext_26$D_OUT; - wire int_sqrt_fNext_26$CLR, - int_sqrt_fNext_26$DEQ, - int_sqrt_fNext_26$EMPTY_N, - int_sqrt_fNext_26$ENQ, - int_sqrt_fNext_26$FULL_N; - - // ports of submodule int_sqrt_fNext_27 - wire [464 : 0] int_sqrt_fNext_27$D_IN, int_sqrt_fNext_27$D_OUT; - wire int_sqrt_fNext_27$CLR, - int_sqrt_fNext_27$DEQ, - int_sqrt_fNext_27$EMPTY_N, - int_sqrt_fNext_27$ENQ, - int_sqrt_fNext_27$FULL_N; - - // ports of submodule int_sqrt_fNext_28 - wire [464 : 0] int_sqrt_fNext_28$D_IN, int_sqrt_fNext_28$D_OUT; - wire int_sqrt_fNext_28$CLR, - int_sqrt_fNext_28$DEQ, - int_sqrt_fNext_28$EMPTY_N, - int_sqrt_fNext_28$ENQ, - int_sqrt_fNext_28$FULL_N; - - // ports of submodule int_sqrt_fNext_29 - wire [464 : 0] int_sqrt_fNext_29$D_IN, int_sqrt_fNext_29$D_OUT; - wire int_sqrt_fNext_29$CLR, - int_sqrt_fNext_29$DEQ, - int_sqrt_fNext_29$EMPTY_N, - int_sqrt_fNext_29$ENQ, - int_sqrt_fNext_29$FULL_N; - - // ports of submodule int_sqrt_fNext_3 - wire [464 : 0] int_sqrt_fNext_3$D_IN, int_sqrt_fNext_3$D_OUT; - wire int_sqrt_fNext_3$CLR, - int_sqrt_fNext_3$DEQ, - int_sqrt_fNext_3$EMPTY_N, - int_sqrt_fNext_3$ENQ, - int_sqrt_fNext_3$FULL_N; - - // ports of submodule int_sqrt_fNext_30 - wire [464 : 0] int_sqrt_fNext_30$D_IN, int_sqrt_fNext_30$D_OUT; - wire int_sqrt_fNext_30$CLR, - int_sqrt_fNext_30$DEQ, - int_sqrt_fNext_30$EMPTY_N, - int_sqrt_fNext_30$ENQ, - int_sqrt_fNext_30$FULL_N; - - // ports of submodule int_sqrt_fNext_31 - wire [464 : 0] int_sqrt_fNext_31$D_IN, int_sqrt_fNext_31$D_OUT; - wire int_sqrt_fNext_31$CLR, - int_sqrt_fNext_31$DEQ, - int_sqrt_fNext_31$EMPTY_N, - int_sqrt_fNext_31$ENQ, - int_sqrt_fNext_31$FULL_N; - - // ports of submodule int_sqrt_fNext_32 - wire [464 : 0] int_sqrt_fNext_32$D_IN, int_sqrt_fNext_32$D_OUT; - wire int_sqrt_fNext_32$CLR, - int_sqrt_fNext_32$DEQ, - int_sqrt_fNext_32$EMPTY_N, - int_sqrt_fNext_32$ENQ, - int_sqrt_fNext_32$FULL_N; - - // ports of submodule int_sqrt_fNext_33 - wire [464 : 0] int_sqrt_fNext_33$D_IN, int_sqrt_fNext_33$D_OUT; - wire int_sqrt_fNext_33$CLR, - int_sqrt_fNext_33$DEQ, - int_sqrt_fNext_33$EMPTY_N, - int_sqrt_fNext_33$ENQ, - int_sqrt_fNext_33$FULL_N; - - // ports of submodule int_sqrt_fNext_34 - wire [464 : 0] int_sqrt_fNext_34$D_IN, int_sqrt_fNext_34$D_OUT; - wire int_sqrt_fNext_34$CLR, - int_sqrt_fNext_34$DEQ, - int_sqrt_fNext_34$EMPTY_N, - int_sqrt_fNext_34$ENQ, - int_sqrt_fNext_34$FULL_N; - - // ports of submodule int_sqrt_fNext_35 - wire [464 : 0] int_sqrt_fNext_35$D_IN, int_sqrt_fNext_35$D_OUT; - wire int_sqrt_fNext_35$CLR, - int_sqrt_fNext_35$DEQ, - int_sqrt_fNext_35$EMPTY_N, - int_sqrt_fNext_35$ENQ, - int_sqrt_fNext_35$FULL_N; - - // ports of submodule int_sqrt_fNext_36 - wire [464 : 0] int_sqrt_fNext_36$D_IN, int_sqrt_fNext_36$D_OUT; - wire int_sqrt_fNext_36$CLR, - int_sqrt_fNext_36$DEQ, - int_sqrt_fNext_36$EMPTY_N, - int_sqrt_fNext_36$ENQ, - int_sqrt_fNext_36$FULL_N; - - // ports of submodule int_sqrt_fNext_37 - wire [464 : 0] int_sqrt_fNext_37$D_IN, int_sqrt_fNext_37$D_OUT; - wire int_sqrt_fNext_37$CLR, - int_sqrt_fNext_37$DEQ, - int_sqrt_fNext_37$EMPTY_N, - int_sqrt_fNext_37$ENQ, - int_sqrt_fNext_37$FULL_N; - - // ports of submodule int_sqrt_fNext_38 - wire [464 : 0] int_sqrt_fNext_38$D_IN, int_sqrt_fNext_38$D_OUT; - wire int_sqrt_fNext_38$CLR, - int_sqrt_fNext_38$DEQ, - int_sqrt_fNext_38$EMPTY_N, - int_sqrt_fNext_38$ENQ, - int_sqrt_fNext_38$FULL_N; - - // ports of submodule int_sqrt_fNext_39 - wire [464 : 0] int_sqrt_fNext_39$D_IN, int_sqrt_fNext_39$D_OUT; - wire int_sqrt_fNext_39$CLR, - int_sqrt_fNext_39$DEQ, - int_sqrt_fNext_39$EMPTY_N, - int_sqrt_fNext_39$ENQ, - int_sqrt_fNext_39$FULL_N; - - // ports of submodule int_sqrt_fNext_4 - wire [464 : 0] int_sqrt_fNext_4$D_IN, int_sqrt_fNext_4$D_OUT; - wire int_sqrt_fNext_4$CLR, - int_sqrt_fNext_4$DEQ, - int_sqrt_fNext_4$EMPTY_N, - int_sqrt_fNext_4$ENQ, - int_sqrt_fNext_4$FULL_N; - - // ports of submodule int_sqrt_fNext_40 - wire [464 : 0] int_sqrt_fNext_40$D_IN, int_sqrt_fNext_40$D_OUT; - wire int_sqrt_fNext_40$CLR, - int_sqrt_fNext_40$DEQ, - int_sqrt_fNext_40$EMPTY_N, - int_sqrt_fNext_40$ENQ, - int_sqrt_fNext_40$FULL_N; - - // ports of submodule int_sqrt_fNext_41 - wire [464 : 0] int_sqrt_fNext_41$D_IN, int_sqrt_fNext_41$D_OUT; - wire int_sqrt_fNext_41$CLR, - int_sqrt_fNext_41$DEQ, - int_sqrt_fNext_41$EMPTY_N, - int_sqrt_fNext_41$ENQ, - int_sqrt_fNext_41$FULL_N; - - // ports of submodule int_sqrt_fNext_42 - wire [464 : 0] int_sqrt_fNext_42$D_IN, int_sqrt_fNext_42$D_OUT; - wire int_sqrt_fNext_42$CLR, - int_sqrt_fNext_42$DEQ, - int_sqrt_fNext_42$EMPTY_N, - int_sqrt_fNext_42$ENQ, - int_sqrt_fNext_42$FULL_N; - - // ports of submodule int_sqrt_fNext_43 - wire [464 : 0] int_sqrt_fNext_43$D_IN, int_sqrt_fNext_43$D_OUT; - wire int_sqrt_fNext_43$CLR, - int_sqrt_fNext_43$DEQ, - int_sqrt_fNext_43$EMPTY_N, - int_sqrt_fNext_43$ENQ, - int_sqrt_fNext_43$FULL_N; - - // ports of submodule int_sqrt_fNext_44 - wire [464 : 0] int_sqrt_fNext_44$D_IN, int_sqrt_fNext_44$D_OUT; - wire int_sqrt_fNext_44$CLR, - int_sqrt_fNext_44$DEQ, - int_sqrt_fNext_44$EMPTY_N, - int_sqrt_fNext_44$ENQ, - int_sqrt_fNext_44$FULL_N; - - // ports of submodule int_sqrt_fNext_45 - wire [464 : 0] int_sqrt_fNext_45$D_IN, int_sqrt_fNext_45$D_OUT; - wire int_sqrt_fNext_45$CLR, - int_sqrt_fNext_45$DEQ, - int_sqrt_fNext_45$EMPTY_N, - int_sqrt_fNext_45$ENQ, - int_sqrt_fNext_45$FULL_N; - - // ports of submodule int_sqrt_fNext_46 - wire [464 : 0] int_sqrt_fNext_46$D_IN, int_sqrt_fNext_46$D_OUT; - wire int_sqrt_fNext_46$CLR, - int_sqrt_fNext_46$DEQ, - int_sqrt_fNext_46$EMPTY_N, - int_sqrt_fNext_46$ENQ, - int_sqrt_fNext_46$FULL_N; - - // ports of submodule int_sqrt_fNext_47 - wire [464 : 0] int_sqrt_fNext_47$D_IN, int_sqrt_fNext_47$D_OUT; - wire int_sqrt_fNext_47$CLR, - int_sqrt_fNext_47$DEQ, - int_sqrt_fNext_47$EMPTY_N, - int_sqrt_fNext_47$ENQ, - int_sqrt_fNext_47$FULL_N; - - // ports of submodule int_sqrt_fNext_48 - wire [464 : 0] int_sqrt_fNext_48$D_IN, int_sqrt_fNext_48$D_OUT; - wire int_sqrt_fNext_48$CLR, - int_sqrt_fNext_48$DEQ, - int_sqrt_fNext_48$EMPTY_N, - int_sqrt_fNext_48$ENQ, - int_sqrt_fNext_48$FULL_N; - - // ports of submodule int_sqrt_fNext_49 - wire [464 : 0] int_sqrt_fNext_49$D_IN, int_sqrt_fNext_49$D_OUT; - wire int_sqrt_fNext_49$CLR, - int_sqrt_fNext_49$DEQ, - int_sqrt_fNext_49$EMPTY_N, - int_sqrt_fNext_49$ENQ, - int_sqrt_fNext_49$FULL_N; - - // ports of submodule int_sqrt_fNext_5 - wire [464 : 0] int_sqrt_fNext_5$D_IN, int_sqrt_fNext_5$D_OUT; - wire int_sqrt_fNext_5$CLR, - int_sqrt_fNext_5$DEQ, - int_sqrt_fNext_5$EMPTY_N, - int_sqrt_fNext_5$ENQ, - int_sqrt_fNext_5$FULL_N; - - // ports of submodule int_sqrt_fNext_50 - wire [464 : 0] int_sqrt_fNext_50$D_IN, int_sqrt_fNext_50$D_OUT; - wire int_sqrt_fNext_50$CLR, - int_sqrt_fNext_50$DEQ, - int_sqrt_fNext_50$EMPTY_N, - int_sqrt_fNext_50$ENQ, - int_sqrt_fNext_50$FULL_N; - - // ports of submodule int_sqrt_fNext_51 - wire [464 : 0] int_sqrt_fNext_51$D_IN, int_sqrt_fNext_51$D_OUT; - wire int_sqrt_fNext_51$CLR, - int_sqrt_fNext_51$DEQ, - int_sqrt_fNext_51$EMPTY_N, - int_sqrt_fNext_51$ENQ, - int_sqrt_fNext_51$FULL_N; - - // ports of submodule int_sqrt_fNext_52 - wire [464 : 0] int_sqrt_fNext_52$D_IN, int_sqrt_fNext_52$D_OUT; - wire int_sqrt_fNext_52$CLR, - int_sqrt_fNext_52$DEQ, - int_sqrt_fNext_52$EMPTY_N, - int_sqrt_fNext_52$ENQ, - int_sqrt_fNext_52$FULL_N; - - // ports of submodule int_sqrt_fNext_53 - wire [464 : 0] int_sqrt_fNext_53$D_IN, int_sqrt_fNext_53$D_OUT; - wire int_sqrt_fNext_53$CLR, - int_sqrt_fNext_53$DEQ, - int_sqrt_fNext_53$EMPTY_N, - int_sqrt_fNext_53$ENQ, - int_sqrt_fNext_53$FULL_N; - - // ports of submodule int_sqrt_fNext_54 - wire [464 : 0] int_sqrt_fNext_54$D_IN, int_sqrt_fNext_54$D_OUT; - wire int_sqrt_fNext_54$CLR, - int_sqrt_fNext_54$DEQ, - int_sqrt_fNext_54$EMPTY_N, - int_sqrt_fNext_54$ENQ, - int_sqrt_fNext_54$FULL_N; - - // ports of submodule int_sqrt_fNext_55 - wire [464 : 0] int_sqrt_fNext_55$D_IN, int_sqrt_fNext_55$D_OUT; - wire int_sqrt_fNext_55$CLR, - int_sqrt_fNext_55$DEQ, - int_sqrt_fNext_55$EMPTY_N, - int_sqrt_fNext_55$ENQ, - int_sqrt_fNext_55$FULL_N; - - // ports of submodule int_sqrt_fNext_56 - wire [464 : 0] int_sqrt_fNext_56$D_IN, int_sqrt_fNext_56$D_OUT; - wire int_sqrt_fNext_56$CLR, - int_sqrt_fNext_56$DEQ, - int_sqrt_fNext_56$EMPTY_N, - int_sqrt_fNext_56$ENQ, - int_sqrt_fNext_56$FULL_N; - - // ports of submodule int_sqrt_fNext_57 - wire [464 : 0] int_sqrt_fNext_57$D_IN, int_sqrt_fNext_57$D_OUT; - wire int_sqrt_fNext_57$CLR, - int_sqrt_fNext_57$DEQ, - int_sqrt_fNext_57$EMPTY_N, - int_sqrt_fNext_57$ENQ, - int_sqrt_fNext_57$FULL_N; - - // ports of submodule int_sqrt_fNext_58 - wire [464 : 0] int_sqrt_fNext_58$D_IN, int_sqrt_fNext_58$D_OUT; - wire int_sqrt_fNext_58$CLR, - int_sqrt_fNext_58$DEQ, - int_sqrt_fNext_58$EMPTY_N, - int_sqrt_fNext_58$ENQ, - int_sqrt_fNext_58$FULL_N; - - // ports of submodule int_sqrt_fNext_6 - wire [464 : 0] int_sqrt_fNext_6$D_IN, int_sqrt_fNext_6$D_OUT; - wire int_sqrt_fNext_6$CLR, - int_sqrt_fNext_6$DEQ, - int_sqrt_fNext_6$EMPTY_N, - int_sqrt_fNext_6$ENQ, - int_sqrt_fNext_6$FULL_N; - - // ports of submodule int_sqrt_fNext_7 - wire [464 : 0] int_sqrt_fNext_7$D_IN, int_sqrt_fNext_7$D_OUT; - wire int_sqrt_fNext_7$CLR, - int_sqrt_fNext_7$DEQ, - int_sqrt_fNext_7$EMPTY_N, - int_sqrt_fNext_7$ENQ, - int_sqrt_fNext_7$FULL_N; - - // ports of submodule int_sqrt_fNext_8 - wire [464 : 0] int_sqrt_fNext_8$D_IN, int_sqrt_fNext_8$D_OUT; - wire int_sqrt_fNext_8$CLR, - int_sqrt_fNext_8$DEQ, - int_sqrt_fNext_8$EMPTY_N, - int_sqrt_fNext_8$ENQ, - int_sqrt_fNext_8$FULL_N; - - // ports of submodule int_sqrt_fNext_9 - wire [464 : 0] int_sqrt_fNext_9$D_IN, int_sqrt_fNext_9$D_OUT; - wire int_sqrt_fNext_9$CLR, - int_sqrt_fNext_9$DEQ, - int_sqrt_fNext_9$EMPTY_N, - int_sqrt_fNext_9$ENQ, - int_sqrt_fNext_9$FULL_N; - - // ports of submodule int_sqrt_fRequest - wire [115 : 0] int_sqrt_fRequest$D_IN, int_sqrt_fRequest$D_OUT; - wire int_sqrt_fRequest$CLR, - int_sqrt_fRequest$DEQ, - int_sqrt_fRequest$EMPTY_N, - int_sqrt_fRequest$ENQ, - int_sqrt_fRequest$FULL_N; - - // ports of submodule int_sqrt_fResponse - wire [116 : 0] int_sqrt_fResponse$D_IN, int_sqrt_fResponse$D_OUT; - wire int_sqrt_fResponse$CLR, - int_sqrt_fResponse$DEQ, - int_sqrt_fResponse$EMPTY_N, - int_sqrt_fResponse$ENQ, - int_sqrt_fResponse$FULL_N; + // ports of submodule fpu + wire [68 : 0] fpu$response_get; + wire [66 : 0] fpu$request_put; + wire fpu$EN_request_put, + fpu$EN_response_get, + fpu$RDY_request_put, + fpu$RDY_response_get; // rule scheduling signals - wire CAN_FIRE_RL_fpu_s1_stage, - CAN_FIRE_RL_fpu_s2_stage, - CAN_FIRE_RL_fpu_s3_stage, - CAN_FIRE_RL_fpu_s4_stage, - CAN_FIRE_RL_fpu_s5_stage, - CAN_FIRE_RL_int_sqrt_finish, - CAN_FIRE_RL_int_sqrt_start, - CAN_FIRE_RL_int_sqrt_work, - CAN_FIRE_RL_int_sqrt_work_1, - CAN_FIRE_RL_int_sqrt_work_10, - CAN_FIRE_RL_int_sqrt_work_11, - CAN_FIRE_RL_int_sqrt_work_12, - CAN_FIRE_RL_int_sqrt_work_13, - CAN_FIRE_RL_int_sqrt_work_14, - CAN_FIRE_RL_int_sqrt_work_15, - CAN_FIRE_RL_int_sqrt_work_16, - CAN_FIRE_RL_int_sqrt_work_17, - CAN_FIRE_RL_int_sqrt_work_18, - CAN_FIRE_RL_int_sqrt_work_19, - CAN_FIRE_RL_int_sqrt_work_2, - CAN_FIRE_RL_int_sqrt_work_20, - CAN_FIRE_RL_int_sqrt_work_21, - CAN_FIRE_RL_int_sqrt_work_22, - CAN_FIRE_RL_int_sqrt_work_23, - CAN_FIRE_RL_int_sqrt_work_24, - CAN_FIRE_RL_int_sqrt_work_25, - CAN_FIRE_RL_int_sqrt_work_26, - CAN_FIRE_RL_int_sqrt_work_27, - CAN_FIRE_RL_int_sqrt_work_28, - CAN_FIRE_RL_int_sqrt_work_29, - CAN_FIRE_RL_int_sqrt_work_3, - CAN_FIRE_RL_int_sqrt_work_30, - CAN_FIRE_RL_int_sqrt_work_31, - CAN_FIRE_RL_int_sqrt_work_32, - CAN_FIRE_RL_int_sqrt_work_33, - CAN_FIRE_RL_int_sqrt_work_34, - CAN_FIRE_RL_int_sqrt_work_35, - CAN_FIRE_RL_int_sqrt_work_36, - CAN_FIRE_RL_int_sqrt_work_37, - CAN_FIRE_RL_int_sqrt_work_38, - CAN_FIRE_RL_int_sqrt_work_39, - CAN_FIRE_RL_int_sqrt_work_4, - CAN_FIRE_RL_int_sqrt_work_40, - CAN_FIRE_RL_int_sqrt_work_41, - CAN_FIRE_RL_int_sqrt_work_42, - CAN_FIRE_RL_int_sqrt_work_43, - CAN_FIRE_RL_int_sqrt_work_44, - CAN_FIRE_RL_int_sqrt_work_45, - CAN_FIRE_RL_int_sqrt_work_46, - CAN_FIRE_RL_int_sqrt_work_47, - CAN_FIRE_RL_int_sqrt_work_48, - CAN_FIRE_RL_int_sqrt_work_49, - CAN_FIRE_RL_int_sqrt_work_5, - CAN_FIRE_RL_int_sqrt_work_50, - CAN_FIRE_RL_int_sqrt_work_51, - CAN_FIRE_RL_int_sqrt_work_52, - CAN_FIRE_RL_int_sqrt_work_53, - CAN_FIRE_RL_int_sqrt_work_54, - CAN_FIRE_RL_int_sqrt_work_55, - CAN_FIRE_RL_int_sqrt_work_56, - CAN_FIRE_RL_int_sqrt_work_57, - CAN_FIRE_RL_int_sqrt_work_58, - CAN_FIRE_RL_int_sqrt_work_6, - CAN_FIRE_RL_int_sqrt_work_7, - CAN_FIRE_RL_int_sqrt_work_8, - CAN_FIRE_RL_int_sqrt_work_9, - CAN_FIRE_request_put, + wire CAN_FIRE_request_put, CAN_FIRE_response_get, - WILL_FIRE_RL_fpu_s1_stage, - WILL_FIRE_RL_fpu_s2_stage, - WILL_FIRE_RL_fpu_s3_stage, - WILL_FIRE_RL_fpu_s4_stage, - WILL_FIRE_RL_fpu_s5_stage, - WILL_FIRE_RL_int_sqrt_finish, - WILL_FIRE_RL_int_sqrt_start, - WILL_FIRE_RL_int_sqrt_work, - WILL_FIRE_RL_int_sqrt_work_1, - WILL_FIRE_RL_int_sqrt_work_10, - WILL_FIRE_RL_int_sqrt_work_11, - WILL_FIRE_RL_int_sqrt_work_12, - WILL_FIRE_RL_int_sqrt_work_13, - WILL_FIRE_RL_int_sqrt_work_14, - WILL_FIRE_RL_int_sqrt_work_15, - WILL_FIRE_RL_int_sqrt_work_16, - WILL_FIRE_RL_int_sqrt_work_17, - WILL_FIRE_RL_int_sqrt_work_18, - WILL_FIRE_RL_int_sqrt_work_19, - WILL_FIRE_RL_int_sqrt_work_2, - WILL_FIRE_RL_int_sqrt_work_20, - WILL_FIRE_RL_int_sqrt_work_21, - WILL_FIRE_RL_int_sqrt_work_22, - WILL_FIRE_RL_int_sqrt_work_23, - WILL_FIRE_RL_int_sqrt_work_24, - WILL_FIRE_RL_int_sqrt_work_25, - WILL_FIRE_RL_int_sqrt_work_26, - WILL_FIRE_RL_int_sqrt_work_27, - WILL_FIRE_RL_int_sqrt_work_28, - WILL_FIRE_RL_int_sqrt_work_29, - WILL_FIRE_RL_int_sqrt_work_3, - WILL_FIRE_RL_int_sqrt_work_30, - WILL_FIRE_RL_int_sqrt_work_31, - WILL_FIRE_RL_int_sqrt_work_32, - WILL_FIRE_RL_int_sqrt_work_33, - WILL_FIRE_RL_int_sqrt_work_34, - WILL_FIRE_RL_int_sqrt_work_35, - WILL_FIRE_RL_int_sqrt_work_36, - WILL_FIRE_RL_int_sqrt_work_37, - WILL_FIRE_RL_int_sqrt_work_38, - WILL_FIRE_RL_int_sqrt_work_39, - WILL_FIRE_RL_int_sqrt_work_4, - WILL_FIRE_RL_int_sqrt_work_40, - WILL_FIRE_RL_int_sqrt_work_41, - WILL_FIRE_RL_int_sqrt_work_42, - WILL_FIRE_RL_int_sqrt_work_43, - WILL_FIRE_RL_int_sqrt_work_44, - WILL_FIRE_RL_int_sqrt_work_45, - WILL_FIRE_RL_int_sqrt_work_46, - WILL_FIRE_RL_int_sqrt_work_47, - WILL_FIRE_RL_int_sqrt_work_48, - WILL_FIRE_RL_int_sqrt_work_49, - WILL_FIRE_RL_int_sqrt_work_5, - WILL_FIRE_RL_int_sqrt_work_50, - WILL_FIRE_RL_int_sqrt_work_51, - WILL_FIRE_RL_int_sqrt_work_52, - WILL_FIRE_RL_int_sqrt_work_53, - WILL_FIRE_RL_int_sqrt_work_54, - WILL_FIRE_RL_int_sqrt_work_55, - WILL_FIRE_RL_int_sqrt_work_56, - WILL_FIRE_RL_int_sqrt_work_57, - WILL_FIRE_RL_int_sqrt_work_58, - WILL_FIRE_RL_int_sqrt_work_6, - WILL_FIRE_RL_int_sqrt_work_7, - WILL_FIRE_RL_int_sqrt_work_8, - WILL_FIRE_RL_int_sqrt_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; - // remaining internal signals - reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15; - reg [62 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11; - reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, - _theResult___fst_sfd__h76507; - reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4, - _theResult___fst_exp__h76506; - reg CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10; - wire [194 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477; - wire [115 : 0] _theResult___snd_fst__h25299, - _theResult___snd_fst__h25701, - _theResult___snd_fst__h26101, - _theResult___snd_fst__h26501, - _theResult___snd_fst__h26901, - _theResult___snd_fst__h27301, - _theResult___snd_fst__h27701, - _theResult___snd_fst__h28101, - _theResult___snd_fst__h28501, - _theResult___snd_fst__h28901, - _theResult___snd_fst__h29301, - _theResult___snd_fst__h29701, - _theResult___snd_fst__h30101, - _theResult___snd_fst__h30501, - _theResult___snd_fst__h30901, - _theResult___snd_fst__h31301, - _theResult___snd_fst__h31701, - _theResult___snd_fst__h32101, - _theResult___snd_fst__h32501, - _theResult___snd_fst__h32901, - _theResult___snd_fst__h33301, - _theResult___snd_fst__h33701, - _theResult___snd_fst__h34101, - _theResult___snd_fst__h34501, - _theResult___snd_fst__h34901, - _theResult___snd_fst__h35301, - _theResult___snd_fst__h35701, - _theResult___snd_fst__h36101, - _theResult___snd_fst__h36501, - _theResult___snd_fst__h36901, - _theResult___snd_fst__h37301, - _theResult___snd_fst__h37701, - _theResult___snd_fst__h38101, - _theResult___snd_fst__h38501, - _theResult___snd_fst__h38901, - _theResult___snd_fst__h39301, - _theResult___snd_fst__h39701, - _theResult___snd_fst__h40101, - _theResult___snd_fst__h40501, - _theResult___snd_fst__h40901, - _theResult___snd_fst__h41301, - _theResult___snd_fst__h41701, - _theResult___snd_fst__h42101, - _theResult___snd_fst__h42501, - _theResult___snd_fst__h42901, - _theResult___snd_fst__h43301, - _theResult___snd_fst__h43701, - _theResult___snd_fst__h44101, - _theResult___snd_fst__h44501, - _theResult___snd_fst__h44901, - _theResult___snd_fst__h45301, - _theResult___snd_fst__h45701, - _theResult___snd_fst__h46101, - _theResult___snd_fst__h46501, - _theResult___snd_fst__h46901, - _theResult___snd_fst__h47301, - _theResult___snd_fst__h47701, - _theResult___snd_fst__h48101, - _theResult___snd_fst__h48501, - _theResult___snd_snd__h25377, - _theResult___snd_snd__h25777, - _theResult___snd_snd__h26177, - _theResult___snd_snd__h26577, - _theResult___snd_snd__h26977, - _theResult___snd_snd__h27377, - _theResult___snd_snd__h27777, - _theResult___snd_snd__h28177, - _theResult___snd_snd__h28577, - _theResult___snd_snd__h28977, - _theResult___snd_snd__h29377, - _theResult___snd_snd__h29777, - _theResult___snd_snd__h30177, - _theResult___snd_snd__h30577, - _theResult___snd_snd__h30977, - _theResult___snd_snd__h31377, - _theResult___snd_snd__h31777, - _theResult___snd_snd__h32177, - _theResult___snd_snd__h32577, - _theResult___snd_snd__h32977, - _theResult___snd_snd__h33377, - _theResult___snd_snd__h33777, - _theResult___snd_snd__h34177, - _theResult___snd_snd__h34577, - _theResult___snd_snd__h34977, - _theResult___snd_snd__h35377, - _theResult___snd_snd__h35777, - _theResult___snd_snd__h36177, - _theResult___snd_snd__h36577, - _theResult___snd_snd__h36977, - _theResult___snd_snd__h37377, - _theResult___snd_snd__h37777, - _theResult___snd_snd__h38177, - _theResult___snd_snd__h38577, - _theResult___snd_snd__h38977, - _theResult___snd_snd__h39377, - _theResult___snd_snd__h39777, - _theResult___snd_snd__h40177, - _theResult___snd_snd__h40577, - _theResult___snd_snd__h40977, - _theResult___snd_snd__h41377, - _theResult___snd_snd__h41777, - _theResult___snd_snd__h42177, - _theResult___snd_snd__h42577, - _theResult___snd_snd__h42977, - _theResult___snd_snd__h43377, - _theResult___snd_snd__h43777, - _theResult___snd_snd__h44177, - _theResult___snd_snd__h44577, - _theResult___snd_snd__h44977, - _theResult___snd_snd__h45377, - _theResult___snd_snd__h45777, - _theResult___snd_snd__h46177, - _theResult___snd_snd__h46577, - _theResult___snd_snd__h46977, - _theResult___snd_snd__h47377, - _theResult___snd_snd__h47777, - _theResult___snd_snd__h48177, - _theResult___snd_snd__h48577, - b___1__h16687, - b__h25374, - b__h25774, - b__h26174, - b__h26574, - b__h26974, - b__h27374, - b__h27774, - b__h28174, - b__h28574, - b__h28974, - b__h29374, - b__h29774, - b__h30174, - b__h30574, - b__h30974, - b__h31374, - b__h31774, - b__h32174, - b__h32574, - b__h32974, - b__h33374, - b__h33774, - b__h34174, - b__h34574, - b__h34974, - b__h35374, - b__h35774, - b__h36174, - b__h36574, - b__h36974, - b__h37374, - b__h37774, - b__h38174, - b__h38574, - b__h38974, - b__h39374, - b__h39774, - b__h40174, - b__h40574, - b__h40974, - b__h41374, - b__h41774, - b__h42174, - b__h42574, - b__h42974, - b__h43374, - b__h43774, - b__h44174, - b__h44574, - b__h44974, - b__h45374, - b__h45774, - b__h46174, - b__h46574, - b__h46974, - b__h47374, - b__h47774, - b__h48174, - b__h48574, - b__h48712, - r__h25386, - r__h25394, - r__h25786, - r__h25794, - r__h26186, - r__h26194, - r__h26586, - r__h26594, - r__h26986, - r__h26994, - r__h27386, - r__h27394, - r__h27786, - r__h27794, - r__h28186, - r__h28194, - r__h28586, - r__h28594, - r__h28986, - r__h28994, - r__h29386, - r__h29394, - r__h29786, - r__h29794, - r__h30186, - r__h30194, - r__h30586, - r__h30594, - r__h30986, - r__h30994, - r__h31386, - r__h31394, - r__h31786, - r__h31794, - r__h32186, - r__h32194, - r__h32586, - r__h32594, - r__h32986, - r__h32994, - r__h33386, - r__h33394, - r__h33786, - r__h33794, - r__h34186, - r__h34194, - r__h34586, - r__h34594, - r__h34986, - r__h34994, - r__h35386, - r__h35394, - r__h35786, - r__h35794, - r__h36186, - r__h36194, - r__h36586, - r__h36594, - r__h36986, - r__h36994, - r__h37386, - r__h37394, - r__h37786, - r__h37794, - r__h38186, - r__h38194, - r__h38586, - r__h38594, - r__h38986, - r__h38994, - r__h39386, - r__h39394, - r__h39786, - r__h39794, - r__h40186, - r__h40194, - r__h40586, - r__h40594, - r__h40986, - r__h40994, - r__h41386, - r__h41394, - r__h41786, - r__h41794, - r__h42186, - r__h42194, - r__h42586, - r__h42594, - r__h42986, - r__h42994, - r__h43386, - r__h43394, - r__h43786, - r__h43794, - r__h44186, - r__h44194, - r__h44586, - r__h44594, - r__h44986, - r__h44994, - r__h45386, - r__h45394, - r__h45786, - r__h45794, - r__h46186, - r__h46194, - r__h46586, - r__h46594, - r__h46986, - r__h46994, - r__h47386, - r__h47394, - r__h47786, - r__h47794, - r__h48186, - r__h48194, - r__h48586, - r__h48594, - s__h25385, - s__h25785, - s__h26185, - s__h26585, - s__h26985, - s__h27385, - s__h27785, - s__h28185, - s__h28585, - s__h28985, - s__h29385, - s__h29785, - s__h30185, - s__h30585, - s__h30985, - s__h31385, - s__h31785, - s__h32185, - s__h32585, - s__h32985, - s__h33385, - s__h33785, - s__h34185, - s__h34585, - s__h34985, - s__h35385, - s__h35785, - s__h36185, - s__h36585, - s__h36985, - s__h37385, - s__h37785, - s__h38185, - s__h38585, - s__h38985, - s__h39385, - s__h39785, - s__h40185, - s__h40585, - s__h40985, - s__h41385, - s__h41785, - s__h42185, - s__h42585, - s__h42985, - s__h43385, - s__h43785, - s__h44185, - s__h44585, - s__h44985, - s__h45385, - s__h45785, - s__h46185, - s__h46585, - s__h46985, - s__h47385, - s__h47785, - s__h48185, - s__h48585, - sum__h25372, - sum__h25772, - sum__h26172, - sum__h26572, - sum__h26972, - sum__h27372, - sum__h27772, - sum__h28172, - sum__h28572, - sum__h28972, - sum__h29372, - sum__h29772, - sum__h30172, - sum__h30572, - sum__h30972, - sum__h31372, - sum__h31772, - sum__h32172, - sum__h32572, - sum__h32972, - sum__h33372, - sum__h33772, - sum__h34172, - sum__h34572, - sum__h34972, - sum__h35372, - sum__h35772, - sum__h36172, - sum__h36572, - sum__h36972, - sum__h37372, - sum__h37772, - sum__h38172, - sum__h38572, - sum__h38972, - sum__h39372, - sum__h39772, - sum__h40172, - sum__h40572, - sum__h40972, - sum__h41372, - sum__h41772, - sum__h42172, - sum__h42572, - sum__h42972, - sum__h43372, - sum__h43772, - sum__h44172, - sum__h44572, - sum__h44972, - sum__h45372, - sum__h45772, - sum__h46172, - sum__h46572, - sum__h46972, - sum__h47372, - sum__h47772, - sum__h48172, - sum__h48572, - x__h402; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866, - IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820; - wire [58 : 0] IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6, - _theResult___snd__h75283, - _theResult___snd__h75298, - _theResult___snd__h75300, - _theResult___snd__h75313, - _theResult___snd__h75319, - _theResult___snd__h75337, - _theResult___snd__h75342, - result__h66451, - sfdin__h75260, - x__h66665; - wire [57 : 0] sfd___1__h65692, sfd__h49936, sfd__h49938, x__h65683; - wire [53 : 0] sfd__h75932, value__h58164; - wire [51 : 0] _theResult___fst_sfd__h76510, - _theResult___sfd__h76429, - out_sfd__h76432, - sfd__h49989; - wire [12 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460, - x__h57541, - x__h57559; - wire [11 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9, - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531, - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774; - wire [10 : 0] IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, - _theResult___exp__h76428, - _theResult___fst_exp__h75266, - _theResult___fst_exp__h75269, - _theResult___fst_exp__h75289, - _theResult___fst_exp__h75305, - _theResult___fst_exp__h75344, - _theResult___fst_exp__h75350, - _theResult___fst_exp__h75353, - _theResult___fst_exp__h76509, - din_inc___2_exp__h76519, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8, - fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5, - out_exp__h76431; - wire [6 : 0] IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237, - x__h24992; - wire [5 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458, - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772, - x__h65722; - wire [2 : 0] IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813; - wire [1 : 0] IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7, - _theResult___snd_fst__h75372, - guard__h66951, - x__h75654; - wire _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775, - int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264, - int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299, - int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649, - int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684, - int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719, - int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754, - int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789, - int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824, - int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859, - int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894, - int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929, - int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964, - int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334, - int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999, - int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034, - int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069, - int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104, - int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139, - int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174, - int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209, - int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244, - int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279, - int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314, - int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369, - int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349, - int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384, - int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419, - int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454, - int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489, - int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524, - int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559, - int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594, - int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629, - int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664, - int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404, - int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699, - int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734, - int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769, - int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804, - int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839, - int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874, - int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909, - int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944, - int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979, - int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014, - int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439, - int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049, - int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084, - int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119, - int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154, - int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189, - int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224, - int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259, - int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294, - int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474, - int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509, - int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544, - int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579, - int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614, - value_BIT_52___h58260; - // action method request_put - assign RDY_request_put = fpu_fOperand_S0$FULL_N ; - assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; + assign RDY_request_put = fpu$RDY_request_put ; + assign CAN_FIRE_request_put = fpu$RDY_request_put ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu_fResult_S5$D_OUT ; - assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; - assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; + assign response_get = fpu$response_get ; + assign RDY_response_get = fpu$RDY_response_get ; + assign CAN_FIRE_response_get = fpu$RDY_response_get ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu_fOperand_S0 - FIFOL1 #(.width(32'd67)) fpu_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fOperand_S0$D_IN), - .ENQ(fpu_fOperand_S0$ENQ), - .DEQ(fpu_fOperand_S0$DEQ), - .CLR(fpu_fOperand_S0$CLR), - .D_OUT(fpu_fOperand_S0$D_OUT), - .FULL_N(fpu_fOperand_S0$FULL_N), - .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); - - // submodule fpu_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fResult_S5$D_IN), - .ENQ(fpu_fResult_S5$ENQ), - .DEQ(fpu_fResult_S5$DEQ), - .CLR(fpu_fResult_S5$CLR), - .D_OUT(fpu_fResult_S5$D_OUT), - .FULL_N(fpu_fResult_S5$FULL_N), - .EMPTY_N(fpu_fResult_S5$EMPTY_N)); - - // submodule fpu_fState_S1 - FIFOL1 #(.width(32'd195)) fpu_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S1$D_IN), - .ENQ(fpu_fState_S1$ENQ), - .DEQ(fpu_fState_S1$DEQ), - .CLR(fpu_fState_S1$CLR), - .D_OUT(fpu_fState_S1$D_OUT), - .FULL_N(fpu_fState_S1$FULL_N), - .EMPTY_N(fpu_fState_S1$EMPTY_N)); - - // submodule fpu_fState_S2 - FIFOL1 #(.width(32'd137)) fpu_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S2$D_IN), - .ENQ(fpu_fState_S2$ENQ), - .DEQ(fpu_fState_S2$DEQ), - .CLR(fpu_fState_S2$CLR), - .D_OUT(fpu_fState_S2$D_OUT), - .FULL_N(fpu_fState_S2$FULL_N), - .EMPTY_N(fpu_fState_S2$EMPTY_N)); - - // submodule fpu_fState_S3 - FIFOL1 #(.width(32'd196)) fpu_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S3$D_IN), - .ENQ(fpu_fState_S3$ENQ), - .DEQ(fpu_fState_S3$DEQ), - .CLR(fpu_fState_S3$CLR), - .D_OUT(fpu_fState_S3$D_OUT), - .FULL_N(fpu_fState_S3$FULL_N), - .EMPTY_N(fpu_fState_S3$EMPTY_N)); - - // submodule fpu_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S4$D_IN), - .ENQ(fpu_fState_S4$ENQ), - .DEQ(fpu_fState_S4$DEQ), - .CLR(fpu_fState_S4$CLR), - .D_OUT(fpu_fState_S4$D_OUT), - .FULL_N(fpu_fState_S4$FULL_N), - .EMPTY_N(fpu_fState_S4$EMPTY_N)); - - // submodule int_sqrt_fFirst - FIFOL1 #(.width(32'd465)) int_sqrt_fFirst(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fFirst$D_IN), - .ENQ(int_sqrt_fFirst$ENQ), - .DEQ(int_sqrt_fFirst$DEQ), - .CLR(int_sqrt_fFirst$CLR), - .D_OUT(int_sqrt_fFirst$D_OUT), - .FULL_N(int_sqrt_fFirst$FULL_N), - .EMPTY_N(int_sqrt_fFirst$EMPTY_N)); - - // submodule int_sqrt_fNext_0 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_0(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_0$D_IN), - .ENQ(int_sqrt_fNext_0$ENQ), - .DEQ(int_sqrt_fNext_0$DEQ), - .CLR(int_sqrt_fNext_0$CLR), - .D_OUT(int_sqrt_fNext_0$D_OUT), - .FULL_N(int_sqrt_fNext_0$FULL_N), - .EMPTY_N(int_sqrt_fNext_0$EMPTY_N)); - - // submodule int_sqrt_fNext_1 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_1(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_1$D_IN), - .ENQ(int_sqrt_fNext_1$ENQ), - .DEQ(int_sqrt_fNext_1$DEQ), - .CLR(int_sqrt_fNext_1$CLR), - .D_OUT(int_sqrt_fNext_1$D_OUT), - .FULL_N(int_sqrt_fNext_1$FULL_N), - .EMPTY_N(int_sqrt_fNext_1$EMPTY_N)); - - // submodule int_sqrt_fNext_10 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_10(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_10$D_IN), - .ENQ(int_sqrt_fNext_10$ENQ), - .DEQ(int_sqrt_fNext_10$DEQ), - .CLR(int_sqrt_fNext_10$CLR), - .D_OUT(int_sqrt_fNext_10$D_OUT), - .FULL_N(int_sqrt_fNext_10$FULL_N), - .EMPTY_N(int_sqrt_fNext_10$EMPTY_N)); - - // submodule int_sqrt_fNext_11 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_11(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_11$D_IN), - .ENQ(int_sqrt_fNext_11$ENQ), - .DEQ(int_sqrt_fNext_11$DEQ), - .CLR(int_sqrt_fNext_11$CLR), - .D_OUT(int_sqrt_fNext_11$D_OUT), - .FULL_N(int_sqrt_fNext_11$FULL_N), - .EMPTY_N(int_sqrt_fNext_11$EMPTY_N)); - - // submodule int_sqrt_fNext_12 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_12(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_12$D_IN), - .ENQ(int_sqrt_fNext_12$ENQ), - .DEQ(int_sqrt_fNext_12$DEQ), - .CLR(int_sqrt_fNext_12$CLR), - .D_OUT(int_sqrt_fNext_12$D_OUT), - .FULL_N(int_sqrt_fNext_12$FULL_N), - .EMPTY_N(int_sqrt_fNext_12$EMPTY_N)); - - // submodule int_sqrt_fNext_13 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_13(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_13$D_IN), - .ENQ(int_sqrt_fNext_13$ENQ), - .DEQ(int_sqrt_fNext_13$DEQ), - .CLR(int_sqrt_fNext_13$CLR), - .D_OUT(int_sqrt_fNext_13$D_OUT), - .FULL_N(int_sqrt_fNext_13$FULL_N), - .EMPTY_N(int_sqrt_fNext_13$EMPTY_N)); - - // submodule int_sqrt_fNext_14 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_14(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_14$D_IN), - .ENQ(int_sqrt_fNext_14$ENQ), - .DEQ(int_sqrt_fNext_14$DEQ), - .CLR(int_sqrt_fNext_14$CLR), - .D_OUT(int_sqrt_fNext_14$D_OUT), - .FULL_N(int_sqrt_fNext_14$FULL_N), - .EMPTY_N(int_sqrt_fNext_14$EMPTY_N)); - - // submodule int_sqrt_fNext_15 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_15(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_15$D_IN), - .ENQ(int_sqrt_fNext_15$ENQ), - .DEQ(int_sqrt_fNext_15$DEQ), - .CLR(int_sqrt_fNext_15$CLR), - .D_OUT(int_sqrt_fNext_15$D_OUT), - .FULL_N(int_sqrt_fNext_15$FULL_N), - .EMPTY_N(int_sqrt_fNext_15$EMPTY_N)); - - // submodule int_sqrt_fNext_16 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_16(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_16$D_IN), - .ENQ(int_sqrt_fNext_16$ENQ), - .DEQ(int_sqrt_fNext_16$DEQ), - .CLR(int_sqrt_fNext_16$CLR), - .D_OUT(int_sqrt_fNext_16$D_OUT), - .FULL_N(int_sqrt_fNext_16$FULL_N), - .EMPTY_N(int_sqrt_fNext_16$EMPTY_N)); - - // submodule int_sqrt_fNext_17 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_17(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_17$D_IN), - .ENQ(int_sqrt_fNext_17$ENQ), - .DEQ(int_sqrt_fNext_17$DEQ), - .CLR(int_sqrt_fNext_17$CLR), - .D_OUT(int_sqrt_fNext_17$D_OUT), - .FULL_N(int_sqrt_fNext_17$FULL_N), - .EMPTY_N(int_sqrt_fNext_17$EMPTY_N)); - - // submodule int_sqrt_fNext_18 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_18(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_18$D_IN), - .ENQ(int_sqrt_fNext_18$ENQ), - .DEQ(int_sqrt_fNext_18$DEQ), - .CLR(int_sqrt_fNext_18$CLR), - .D_OUT(int_sqrt_fNext_18$D_OUT), - .FULL_N(int_sqrt_fNext_18$FULL_N), - .EMPTY_N(int_sqrt_fNext_18$EMPTY_N)); - - // submodule int_sqrt_fNext_19 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_19(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_19$D_IN), - .ENQ(int_sqrt_fNext_19$ENQ), - .DEQ(int_sqrt_fNext_19$DEQ), - .CLR(int_sqrt_fNext_19$CLR), - .D_OUT(int_sqrt_fNext_19$D_OUT), - .FULL_N(int_sqrt_fNext_19$FULL_N), - .EMPTY_N(int_sqrt_fNext_19$EMPTY_N)); - - // submodule int_sqrt_fNext_2 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_2(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_2$D_IN), - .ENQ(int_sqrt_fNext_2$ENQ), - .DEQ(int_sqrt_fNext_2$DEQ), - .CLR(int_sqrt_fNext_2$CLR), - .D_OUT(int_sqrt_fNext_2$D_OUT), - .FULL_N(int_sqrt_fNext_2$FULL_N), - .EMPTY_N(int_sqrt_fNext_2$EMPTY_N)); - - // submodule int_sqrt_fNext_20 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_20(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_20$D_IN), - .ENQ(int_sqrt_fNext_20$ENQ), - .DEQ(int_sqrt_fNext_20$DEQ), - .CLR(int_sqrt_fNext_20$CLR), - .D_OUT(int_sqrt_fNext_20$D_OUT), - .FULL_N(int_sqrt_fNext_20$FULL_N), - .EMPTY_N(int_sqrt_fNext_20$EMPTY_N)); - - // submodule int_sqrt_fNext_21 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_21(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_21$D_IN), - .ENQ(int_sqrt_fNext_21$ENQ), - .DEQ(int_sqrt_fNext_21$DEQ), - .CLR(int_sqrt_fNext_21$CLR), - .D_OUT(int_sqrt_fNext_21$D_OUT), - .FULL_N(int_sqrt_fNext_21$FULL_N), - .EMPTY_N(int_sqrt_fNext_21$EMPTY_N)); - - // submodule int_sqrt_fNext_22 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_22(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_22$D_IN), - .ENQ(int_sqrt_fNext_22$ENQ), - .DEQ(int_sqrt_fNext_22$DEQ), - .CLR(int_sqrt_fNext_22$CLR), - .D_OUT(int_sqrt_fNext_22$D_OUT), - .FULL_N(int_sqrt_fNext_22$FULL_N), - .EMPTY_N(int_sqrt_fNext_22$EMPTY_N)); - - // submodule int_sqrt_fNext_23 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_23(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_23$D_IN), - .ENQ(int_sqrt_fNext_23$ENQ), - .DEQ(int_sqrt_fNext_23$DEQ), - .CLR(int_sqrt_fNext_23$CLR), - .D_OUT(int_sqrt_fNext_23$D_OUT), - .FULL_N(int_sqrt_fNext_23$FULL_N), - .EMPTY_N(int_sqrt_fNext_23$EMPTY_N)); - - // submodule int_sqrt_fNext_24 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_24(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_24$D_IN), - .ENQ(int_sqrt_fNext_24$ENQ), - .DEQ(int_sqrt_fNext_24$DEQ), - .CLR(int_sqrt_fNext_24$CLR), - .D_OUT(int_sqrt_fNext_24$D_OUT), - .FULL_N(int_sqrt_fNext_24$FULL_N), - .EMPTY_N(int_sqrt_fNext_24$EMPTY_N)); - - // submodule int_sqrt_fNext_25 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_25(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_25$D_IN), - .ENQ(int_sqrt_fNext_25$ENQ), - .DEQ(int_sqrt_fNext_25$DEQ), - .CLR(int_sqrt_fNext_25$CLR), - .D_OUT(int_sqrt_fNext_25$D_OUT), - .FULL_N(int_sqrt_fNext_25$FULL_N), - .EMPTY_N(int_sqrt_fNext_25$EMPTY_N)); - - // submodule int_sqrt_fNext_26 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_26(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_26$D_IN), - .ENQ(int_sqrt_fNext_26$ENQ), - .DEQ(int_sqrt_fNext_26$DEQ), - .CLR(int_sqrt_fNext_26$CLR), - .D_OUT(int_sqrt_fNext_26$D_OUT), - .FULL_N(int_sqrt_fNext_26$FULL_N), - .EMPTY_N(int_sqrt_fNext_26$EMPTY_N)); - - // submodule int_sqrt_fNext_27 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_27(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_27$D_IN), - .ENQ(int_sqrt_fNext_27$ENQ), - .DEQ(int_sqrt_fNext_27$DEQ), - .CLR(int_sqrt_fNext_27$CLR), - .D_OUT(int_sqrt_fNext_27$D_OUT), - .FULL_N(int_sqrt_fNext_27$FULL_N), - .EMPTY_N(int_sqrt_fNext_27$EMPTY_N)); - - // submodule int_sqrt_fNext_28 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_28(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_28$D_IN), - .ENQ(int_sqrt_fNext_28$ENQ), - .DEQ(int_sqrt_fNext_28$DEQ), - .CLR(int_sqrt_fNext_28$CLR), - .D_OUT(int_sqrt_fNext_28$D_OUT), - .FULL_N(int_sqrt_fNext_28$FULL_N), - .EMPTY_N(int_sqrt_fNext_28$EMPTY_N)); - - // submodule int_sqrt_fNext_29 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_29(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_29$D_IN), - .ENQ(int_sqrt_fNext_29$ENQ), - .DEQ(int_sqrt_fNext_29$DEQ), - .CLR(int_sqrt_fNext_29$CLR), - .D_OUT(int_sqrt_fNext_29$D_OUT), - .FULL_N(int_sqrt_fNext_29$FULL_N), - .EMPTY_N(int_sqrt_fNext_29$EMPTY_N)); - - // submodule int_sqrt_fNext_3 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_3(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_3$D_IN), - .ENQ(int_sqrt_fNext_3$ENQ), - .DEQ(int_sqrt_fNext_3$DEQ), - .CLR(int_sqrt_fNext_3$CLR), - .D_OUT(int_sqrt_fNext_3$D_OUT), - .FULL_N(int_sqrt_fNext_3$FULL_N), - .EMPTY_N(int_sqrt_fNext_3$EMPTY_N)); - - // submodule int_sqrt_fNext_30 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_30(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_30$D_IN), - .ENQ(int_sqrt_fNext_30$ENQ), - .DEQ(int_sqrt_fNext_30$DEQ), - .CLR(int_sqrt_fNext_30$CLR), - .D_OUT(int_sqrt_fNext_30$D_OUT), - .FULL_N(int_sqrt_fNext_30$FULL_N), - .EMPTY_N(int_sqrt_fNext_30$EMPTY_N)); - - // submodule int_sqrt_fNext_31 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_31(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_31$D_IN), - .ENQ(int_sqrt_fNext_31$ENQ), - .DEQ(int_sqrt_fNext_31$DEQ), - .CLR(int_sqrt_fNext_31$CLR), - .D_OUT(int_sqrt_fNext_31$D_OUT), - .FULL_N(int_sqrt_fNext_31$FULL_N), - .EMPTY_N(int_sqrt_fNext_31$EMPTY_N)); - - // submodule int_sqrt_fNext_32 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_32(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_32$D_IN), - .ENQ(int_sqrt_fNext_32$ENQ), - .DEQ(int_sqrt_fNext_32$DEQ), - .CLR(int_sqrt_fNext_32$CLR), - .D_OUT(int_sqrt_fNext_32$D_OUT), - .FULL_N(int_sqrt_fNext_32$FULL_N), - .EMPTY_N(int_sqrt_fNext_32$EMPTY_N)); - - // submodule int_sqrt_fNext_33 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_33(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_33$D_IN), - .ENQ(int_sqrt_fNext_33$ENQ), - .DEQ(int_sqrt_fNext_33$DEQ), - .CLR(int_sqrt_fNext_33$CLR), - .D_OUT(int_sqrt_fNext_33$D_OUT), - .FULL_N(int_sqrt_fNext_33$FULL_N), - .EMPTY_N(int_sqrt_fNext_33$EMPTY_N)); - - // submodule int_sqrt_fNext_34 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_34(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_34$D_IN), - .ENQ(int_sqrt_fNext_34$ENQ), - .DEQ(int_sqrt_fNext_34$DEQ), - .CLR(int_sqrt_fNext_34$CLR), - .D_OUT(int_sqrt_fNext_34$D_OUT), - .FULL_N(int_sqrt_fNext_34$FULL_N), - .EMPTY_N(int_sqrt_fNext_34$EMPTY_N)); - - // submodule int_sqrt_fNext_35 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_35(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_35$D_IN), - .ENQ(int_sqrt_fNext_35$ENQ), - .DEQ(int_sqrt_fNext_35$DEQ), - .CLR(int_sqrt_fNext_35$CLR), - .D_OUT(int_sqrt_fNext_35$D_OUT), - .FULL_N(int_sqrt_fNext_35$FULL_N), - .EMPTY_N(int_sqrt_fNext_35$EMPTY_N)); - - // submodule int_sqrt_fNext_36 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_36(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_36$D_IN), - .ENQ(int_sqrt_fNext_36$ENQ), - .DEQ(int_sqrt_fNext_36$DEQ), - .CLR(int_sqrt_fNext_36$CLR), - .D_OUT(int_sqrt_fNext_36$D_OUT), - .FULL_N(int_sqrt_fNext_36$FULL_N), - .EMPTY_N(int_sqrt_fNext_36$EMPTY_N)); - - // submodule int_sqrt_fNext_37 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_37(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_37$D_IN), - .ENQ(int_sqrt_fNext_37$ENQ), - .DEQ(int_sqrt_fNext_37$DEQ), - .CLR(int_sqrt_fNext_37$CLR), - .D_OUT(int_sqrt_fNext_37$D_OUT), - .FULL_N(int_sqrt_fNext_37$FULL_N), - .EMPTY_N(int_sqrt_fNext_37$EMPTY_N)); - - // submodule int_sqrt_fNext_38 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_38(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_38$D_IN), - .ENQ(int_sqrt_fNext_38$ENQ), - .DEQ(int_sqrt_fNext_38$DEQ), - .CLR(int_sqrt_fNext_38$CLR), - .D_OUT(int_sqrt_fNext_38$D_OUT), - .FULL_N(int_sqrt_fNext_38$FULL_N), - .EMPTY_N(int_sqrt_fNext_38$EMPTY_N)); - - // submodule int_sqrt_fNext_39 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_39(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_39$D_IN), - .ENQ(int_sqrt_fNext_39$ENQ), - .DEQ(int_sqrt_fNext_39$DEQ), - .CLR(int_sqrt_fNext_39$CLR), - .D_OUT(int_sqrt_fNext_39$D_OUT), - .FULL_N(int_sqrt_fNext_39$FULL_N), - .EMPTY_N(int_sqrt_fNext_39$EMPTY_N)); - - // submodule int_sqrt_fNext_4 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_4(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_4$D_IN), - .ENQ(int_sqrt_fNext_4$ENQ), - .DEQ(int_sqrt_fNext_4$DEQ), - .CLR(int_sqrt_fNext_4$CLR), - .D_OUT(int_sqrt_fNext_4$D_OUT), - .FULL_N(int_sqrt_fNext_4$FULL_N), - .EMPTY_N(int_sqrt_fNext_4$EMPTY_N)); - - // submodule int_sqrt_fNext_40 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_40(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_40$D_IN), - .ENQ(int_sqrt_fNext_40$ENQ), - .DEQ(int_sqrt_fNext_40$DEQ), - .CLR(int_sqrt_fNext_40$CLR), - .D_OUT(int_sqrt_fNext_40$D_OUT), - .FULL_N(int_sqrt_fNext_40$FULL_N), - .EMPTY_N(int_sqrt_fNext_40$EMPTY_N)); - - // submodule int_sqrt_fNext_41 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_41(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_41$D_IN), - .ENQ(int_sqrt_fNext_41$ENQ), - .DEQ(int_sqrt_fNext_41$DEQ), - .CLR(int_sqrt_fNext_41$CLR), - .D_OUT(int_sqrt_fNext_41$D_OUT), - .FULL_N(int_sqrt_fNext_41$FULL_N), - .EMPTY_N(int_sqrt_fNext_41$EMPTY_N)); - - // submodule int_sqrt_fNext_42 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_42(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_42$D_IN), - .ENQ(int_sqrt_fNext_42$ENQ), - .DEQ(int_sqrt_fNext_42$DEQ), - .CLR(int_sqrt_fNext_42$CLR), - .D_OUT(int_sqrt_fNext_42$D_OUT), - .FULL_N(int_sqrt_fNext_42$FULL_N), - .EMPTY_N(int_sqrt_fNext_42$EMPTY_N)); - - // submodule int_sqrt_fNext_43 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_43(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_43$D_IN), - .ENQ(int_sqrt_fNext_43$ENQ), - .DEQ(int_sqrt_fNext_43$DEQ), - .CLR(int_sqrt_fNext_43$CLR), - .D_OUT(int_sqrt_fNext_43$D_OUT), - .FULL_N(int_sqrt_fNext_43$FULL_N), - .EMPTY_N(int_sqrt_fNext_43$EMPTY_N)); - - // submodule int_sqrt_fNext_44 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_44(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_44$D_IN), - .ENQ(int_sqrt_fNext_44$ENQ), - .DEQ(int_sqrt_fNext_44$DEQ), - .CLR(int_sqrt_fNext_44$CLR), - .D_OUT(int_sqrt_fNext_44$D_OUT), - .FULL_N(int_sqrt_fNext_44$FULL_N), - .EMPTY_N(int_sqrt_fNext_44$EMPTY_N)); - - // submodule int_sqrt_fNext_45 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_45(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_45$D_IN), - .ENQ(int_sqrt_fNext_45$ENQ), - .DEQ(int_sqrt_fNext_45$DEQ), - .CLR(int_sqrt_fNext_45$CLR), - .D_OUT(int_sqrt_fNext_45$D_OUT), - .FULL_N(int_sqrt_fNext_45$FULL_N), - .EMPTY_N(int_sqrt_fNext_45$EMPTY_N)); - - // submodule int_sqrt_fNext_46 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_46(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_46$D_IN), - .ENQ(int_sqrt_fNext_46$ENQ), - .DEQ(int_sqrt_fNext_46$DEQ), - .CLR(int_sqrt_fNext_46$CLR), - .D_OUT(int_sqrt_fNext_46$D_OUT), - .FULL_N(int_sqrt_fNext_46$FULL_N), - .EMPTY_N(int_sqrt_fNext_46$EMPTY_N)); - - // submodule int_sqrt_fNext_47 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_47(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_47$D_IN), - .ENQ(int_sqrt_fNext_47$ENQ), - .DEQ(int_sqrt_fNext_47$DEQ), - .CLR(int_sqrt_fNext_47$CLR), - .D_OUT(int_sqrt_fNext_47$D_OUT), - .FULL_N(int_sqrt_fNext_47$FULL_N), - .EMPTY_N(int_sqrt_fNext_47$EMPTY_N)); - - // submodule int_sqrt_fNext_48 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_48(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_48$D_IN), - .ENQ(int_sqrt_fNext_48$ENQ), - .DEQ(int_sqrt_fNext_48$DEQ), - .CLR(int_sqrt_fNext_48$CLR), - .D_OUT(int_sqrt_fNext_48$D_OUT), - .FULL_N(int_sqrt_fNext_48$FULL_N), - .EMPTY_N(int_sqrt_fNext_48$EMPTY_N)); - - // submodule int_sqrt_fNext_49 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_49(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_49$D_IN), - .ENQ(int_sqrt_fNext_49$ENQ), - .DEQ(int_sqrt_fNext_49$DEQ), - .CLR(int_sqrt_fNext_49$CLR), - .D_OUT(int_sqrt_fNext_49$D_OUT), - .FULL_N(int_sqrt_fNext_49$FULL_N), - .EMPTY_N(int_sqrt_fNext_49$EMPTY_N)); - - // submodule int_sqrt_fNext_5 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_5(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_5$D_IN), - .ENQ(int_sqrt_fNext_5$ENQ), - .DEQ(int_sqrt_fNext_5$DEQ), - .CLR(int_sqrt_fNext_5$CLR), - .D_OUT(int_sqrt_fNext_5$D_OUT), - .FULL_N(int_sqrt_fNext_5$FULL_N), - .EMPTY_N(int_sqrt_fNext_5$EMPTY_N)); - - // submodule int_sqrt_fNext_50 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_50(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_50$D_IN), - .ENQ(int_sqrt_fNext_50$ENQ), - .DEQ(int_sqrt_fNext_50$DEQ), - .CLR(int_sqrt_fNext_50$CLR), - .D_OUT(int_sqrt_fNext_50$D_OUT), - .FULL_N(int_sqrt_fNext_50$FULL_N), - .EMPTY_N(int_sqrt_fNext_50$EMPTY_N)); - - // submodule int_sqrt_fNext_51 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_51(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_51$D_IN), - .ENQ(int_sqrt_fNext_51$ENQ), - .DEQ(int_sqrt_fNext_51$DEQ), - .CLR(int_sqrt_fNext_51$CLR), - .D_OUT(int_sqrt_fNext_51$D_OUT), - .FULL_N(int_sqrt_fNext_51$FULL_N), - .EMPTY_N(int_sqrt_fNext_51$EMPTY_N)); - - // submodule int_sqrt_fNext_52 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_52(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_52$D_IN), - .ENQ(int_sqrt_fNext_52$ENQ), - .DEQ(int_sqrt_fNext_52$DEQ), - .CLR(int_sqrt_fNext_52$CLR), - .D_OUT(int_sqrt_fNext_52$D_OUT), - .FULL_N(int_sqrt_fNext_52$FULL_N), - .EMPTY_N(int_sqrt_fNext_52$EMPTY_N)); - - // submodule int_sqrt_fNext_53 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_53(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_53$D_IN), - .ENQ(int_sqrt_fNext_53$ENQ), - .DEQ(int_sqrt_fNext_53$DEQ), - .CLR(int_sqrt_fNext_53$CLR), - .D_OUT(int_sqrt_fNext_53$D_OUT), - .FULL_N(int_sqrt_fNext_53$FULL_N), - .EMPTY_N(int_sqrt_fNext_53$EMPTY_N)); - - // submodule int_sqrt_fNext_54 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_54(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_54$D_IN), - .ENQ(int_sqrt_fNext_54$ENQ), - .DEQ(int_sqrt_fNext_54$DEQ), - .CLR(int_sqrt_fNext_54$CLR), - .D_OUT(int_sqrt_fNext_54$D_OUT), - .FULL_N(int_sqrt_fNext_54$FULL_N), - .EMPTY_N(int_sqrt_fNext_54$EMPTY_N)); - - // submodule int_sqrt_fNext_55 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_55(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_55$D_IN), - .ENQ(int_sqrt_fNext_55$ENQ), - .DEQ(int_sqrt_fNext_55$DEQ), - .CLR(int_sqrt_fNext_55$CLR), - .D_OUT(int_sqrt_fNext_55$D_OUT), - .FULL_N(int_sqrt_fNext_55$FULL_N), - .EMPTY_N(int_sqrt_fNext_55$EMPTY_N)); - - // submodule int_sqrt_fNext_56 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_56(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_56$D_IN), - .ENQ(int_sqrt_fNext_56$ENQ), - .DEQ(int_sqrt_fNext_56$DEQ), - .CLR(int_sqrt_fNext_56$CLR), - .D_OUT(int_sqrt_fNext_56$D_OUT), - .FULL_N(int_sqrt_fNext_56$FULL_N), - .EMPTY_N(int_sqrt_fNext_56$EMPTY_N)); - - // submodule int_sqrt_fNext_57 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_57(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_57$D_IN), - .ENQ(int_sqrt_fNext_57$ENQ), - .DEQ(int_sqrt_fNext_57$DEQ), - .CLR(int_sqrt_fNext_57$CLR), - .D_OUT(int_sqrt_fNext_57$D_OUT), - .FULL_N(int_sqrt_fNext_57$FULL_N), - .EMPTY_N(int_sqrt_fNext_57$EMPTY_N)); - - // submodule int_sqrt_fNext_58 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_58(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_58$D_IN), - .ENQ(int_sqrt_fNext_58$ENQ), - .DEQ(int_sqrt_fNext_58$DEQ), - .CLR(int_sqrt_fNext_58$CLR), - .D_OUT(int_sqrt_fNext_58$D_OUT), - .FULL_N(int_sqrt_fNext_58$FULL_N), - .EMPTY_N(int_sqrt_fNext_58$EMPTY_N)); - - // submodule int_sqrt_fNext_6 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_6(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_6$D_IN), - .ENQ(int_sqrt_fNext_6$ENQ), - .DEQ(int_sqrt_fNext_6$DEQ), - .CLR(int_sqrt_fNext_6$CLR), - .D_OUT(int_sqrt_fNext_6$D_OUT), - .FULL_N(int_sqrt_fNext_6$FULL_N), - .EMPTY_N(int_sqrt_fNext_6$EMPTY_N)); - - // submodule int_sqrt_fNext_7 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_7(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_7$D_IN), - .ENQ(int_sqrt_fNext_7$ENQ), - .DEQ(int_sqrt_fNext_7$DEQ), - .CLR(int_sqrt_fNext_7$CLR), - .D_OUT(int_sqrt_fNext_7$D_OUT), - .FULL_N(int_sqrt_fNext_7$FULL_N), - .EMPTY_N(int_sqrt_fNext_7$EMPTY_N)); - - // submodule int_sqrt_fNext_8 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_8(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_8$D_IN), - .ENQ(int_sqrt_fNext_8$ENQ), - .DEQ(int_sqrt_fNext_8$DEQ), - .CLR(int_sqrt_fNext_8$CLR), - .D_OUT(int_sqrt_fNext_8$D_OUT), - .FULL_N(int_sqrt_fNext_8$FULL_N), - .EMPTY_N(int_sqrt_fNext_8$EMPTY_N)); - - // submodule int_sqrt_fNext_9 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_9(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_9$D_IN), - .ENQ(int_sqrt_fNext_9$ENQ), - .DEQ(int_sqrt_fNext_9$DEQ), - .CLR(int_sqrt_fNext_9$CLR), - .D_OUT(int_sqrt_fNext_9$D_OUT), - .FULL_N(int_sqrt_fNext_9$FULL_N), - .EMPTY_N(int_sqrt_fNext_9$EMPTY_N)); - - // submodule int_sqrt_fRequest - FIFOL1 #(.width(32'd116)) int_sqrt_fRequest(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fRequest$D_IN), - .ENQ(int_sqrt_fRequest$ENQ), - .DEQ(int_sqrt_fRequest$DEQ), - .CLR(int_sqrt_fRequest$CLR), - .D_OUT(int_sqrt_fRequest$D_OUT), - .FULL_N(int_sqrt_fRequest$FULL_N), - .EMPTY_N(int_sqrt_fRequest$EMPTY_N)); - - // submodule int_sqrt_fResponse - FIFOL1 #(.width(32'd117)) int_sqrt_fResponse(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fResponse$D_IN), - .ENQ(int_sqrt_fResponse$ENQ), - .DEQ(int_sqrt_fResponse$DEQ), - .CLR(int_sqrt_fResponse$CLR), - .D_OUT(int_sqrt_fResponse$D_OUT), - .FULL_N(int_sqrt_fResponse$FULL_N), - .EMPTY_N(int_sqrt_fResponse$EMPTY_N)); - - // rule RL_fpu_s5_stage - assign CAN_FIRE_RL_fpu_s5_stage = - fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; - - // rule RL_fpu_s4_stage - assign CAN_FIRE_RL_fpu_s4_stage = - fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; - - // rule RL_fpu_s3_stage - assign CAN_FIRE_RL_fpu_s3_stage = - fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && - (fpu_fState_S2$D_OUT[136] || int_sqrt_fResponse$EMPTY_N) ; - assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; - - // rule RL_int_sqrt_finish - assign CAN_FIRE_RL_int_sqrt_finish = - int_sqrt_fNext_58$EMPTY_N && int_sqrt_fResponse$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_finish = CAN_FIRE_RL_int_sqrt_finish ; - - // rule RL_int_sqrt_work_58 - assign CAN_FIRE_RL_int_sqrt_work_58 = - int_sqrt_fNext_57$EMPTY_N && int_sqrt_fNext_58$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_58 = CAN_FIRE_RL_int_sqrt_work_58 ; - - // rule RL_int_sqrt_work_57 - assign CAN_FIRE_RL_int_sqrt_work_57 = - int_sqrt_fNext_56$EMPTY_N && int_sqrt_fNext_57$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_57 = CAN_FIRE_RL_int_sqrt_work_57 ; - - // rule RL_int_sqrt_work_56 - assign CAN_FIRE_RL_int_sqrt_work_56 = - int_sqrt_fNext_55$EMPTY_N && int_sqrt_fNext_56$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_56 = CAN_FIRE_RL_int_sqrt_work_56 ; - - // rule RL_int_sqrt_work_55 - assign CAN_FIRE_RL_int_sqrt_work_55 = - int_sqrt_fNext_54$EMPTY_N && int_sqrt_fNext_55$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_55 = CAN_FIRE_RL_int_sqrt_work_55 ; - - // rule RL_int_sqrt_work_54 - assign CAN_FIRE_RL_int_sqrt_work_54 = - int_sqrt_fNext_53$EMPTY_N && int_sqrt_fNext_54$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_54 = CAN_FIRE_RL_int_sqrt_work_54 ; - - // rule RL_int_sqrt_work_53 - assign CAN_FIRE_RL_int_sqrt_work_53 = - int_sqrt_fNext_52$EMPTY_N && int_sqrt_fNext_53$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_53 = CAN_FIRE_RL_int_sqrt_work_53 ; - - // rule RL_int_sqrt_work_52 - assign CAN_FIRE_RL_int_sqrt_work_52 = - int_sqrt_fNext_51$EMPTY_N && int_sqrt_fNext_52$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_52 = CAN_FIRE_RL_int_sqrt_work_52 ; - - // rule RL_int_sqrt_work_51 - assign CAN_FIRE_RL_int_sqrt_work_51 = - int_sqrt_fNext_50$EMPTY_N && int_sqrt_fNext_51$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_51 = CAN_FIRE_RL_int_sqrt_work_51 ; - - // rule RL_int_sqrt_work_50 - assign CAN_FIRE_RL_int_sqrt_work_50 = - int_sqrt_fNext_49$EMPTY_N && int_sqrt_fNext_50$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_50 = CAN_FIRE_RL_int_sqrt_work_50 ; - - // rule RL_int_sqrt_work_49 - assign CAN_FIRE_RL_int_sqrt_work_49 = - int_sqrt_fNext_48$EMPTY_N && int_sqrt_fNext_49$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_49 = CAN_FIRE_RL_int_sqrt_work_49 ; - - // rule RL_int_sqrt_work_48 - assign CAN_FIRE_RL_int_sqrt_work_48 = - int_sqrt_fNext_47$EMPTY_N && int_sqrt_fNext_48$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_48 = CAN_FIRE_RL_int_sqrt_work_48 ; - - // rule RL_int_sqrt_work_47 - assign CAN_FIRE_RL_int_sqrt_work_47 = - int_sqrt_fNext_46$EMPTY_N && int_sqrt_fNext_47$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_47 = CAN_FIRE_RL_int_sqrt_work_47 ; - - // rule RL_int_sqrt_work_46 - assign CAN_FIRE_RL_int_sqrt_work_46 = - int_sqrt_fNext_45$EMPTY_N && int_sqrt_fNext_46$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_46 = CAN_FIRE_RL_int_sqrt_work_46 ; - - // rule RL_int_sqrt_work_45 - assign CAN_FIRE_RL_int_sqrt_work_45 = - int_sqrt_fNext_44$EMPTY_N && int_sqrt_fNext_45$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_45 = CAN_FIRE_RL_int_sqrt_work_45 ; - - // rule RL_int_sqrt_work_44 - assign CAN_FIRE_RL_int_sqrt_work_44 = - int_sqrt_fNext_43$EMPTY_N && int_sqrt_fNext_44$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_44 = CAN_FIRE_RL_int_sqrt_work_44 ; - - // rule RL_int_sqrt_work_43 - assign CAN_FIRE_RL_int_sqrt_work_43 = - int_sqrt_fNext_42$EMPTY_N && int_sqrt_fNext_43$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_43 = CAN_FIRE_RL_int_sqrt_work_43 ; - - // rule RL_int_sqrt_work_42 - assign CAN_FIRE_RL_int_sqrt_work_42 = - int_sqrt_fNext_41$EMPTY_N && int_sqrt_fNext_42$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_42 = CAN_FIRE_RL_int_sqrt_work_42 ; - - // rule RL_int_sqrt_work_41 - assign CAN_FIRE_RL_int_sqrt_work_41 = - int_sqrt_fNext_40$EMPTY_N && int_sqrt_fNext_41$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_41 = CAN_FIRE_RL_int_sqrt_work_41 ; - - // rule RL_int_sqrt_work_40 - assign CAN_FIRE_RL_int_sqrt_work_40 = - int_sqrt_fNext_39$EMPTY_N && int_sqrt_fNext_40$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_40 = CAN_FIRE_RL_int_sqrt_work_40 ; - - // rule RL_int_sqrt_work_39 - assign CAN_FIRE_RL_int_sqrt_work_39 = - int_sqrt_fNext_38$EMPTY_N && int_sqrt_fNext_39$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_39 = CAN_FIRE_RL_int_sqrt_work_39 ; - - // rule RL_int_sqrt_work_38 - assign CAN_FIRE_RL_int_sqrt_work_38 = - int_sqrt_fNext_37$EMPTY_N && int_sqrt_fNext_38$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_38 = CAN_FIRE_RL_int_sqrt_work_38 ; - - // rule RL_int_sqrt_work_37 - assign CAN_FIRE_RL_int_sqrt_work_37 = - int_sqrt_fNext_36$EMPTY_N && int_sqrt_fNext_37$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_37 = CAN_FIRE_RL_int_sqrt_work_37 ; - - // rule RL_int_sqrt_work_36 - assign CAN_FIRE_RL_int_sqrt_work_36 = - int_sqrt_fNext_35$EMPTY_N && int_sqrt_fNext_36$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_36 = CAN_FIRE_RL_int_sqrt_work_36 ; - - // rule RL_int_sqrt_work_35 - assign CAN_FIRE_RL_int_sqrt_work_35 = - int_sqrt_fNext_34$EMPTY_N && int_sqrt_fNext_35$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_35 = CAN_FIRE_RL_int_sqrt_work_35 ; - - // rule RL_int_sqrt_work_34 - assign CAN_FIRE_RL_int_sqrt_work_34 = - int_sqrt_fNext_33$EMPTY_N && int_sqrt_fNext_34$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_34 = CAN_FIRE_RL_int_sqrt_work_34 ; - - // rule RL_int_sqrt_work_33 - assign CAN_FIRE_RL_int_sqrt_work_33 = - int_sqrt_fNext_32$EMPTY_N && int_sqrt_fNext_33$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_33 = CAN_FIRE_RL_int_sqrt_work_33 ; - - // rule RL_int_sqrt_work_32 - assign CAN_FIRE_RL_int_sqrt_work_32 = - int_sqrt_fNext_31$EMPTY_N && int_sqrt_fNext_32$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_32 = CAN_FIRE_RL_int_sqrt_work_32 ; - - // rule RL_int_sqrt_work_31 - assign CAN_FIRE_RL_int_sqrt_work_31 = - int_sqrt_fNext_30$EMPTY_N && int_sqrt_fNext_31$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_31 = CAN_FIRE_RL_int_sqrt_work_31 ; - - // rule RL_int_sqrt_work_30 - assign CAN_FIRE_RL_int_sqrt_work_30 = - int_sqrt_fNext_29$EMPTY_N && int_sqrt_fNext_30$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_30 = CAN_FIRE_RL_int_sqrt_work_30 ; - - // rule RL_int_sqrt_work_29 - assign CAN_FIRE_RL_int_sqrt_work_29 = - int_sqrt_fNext_28$EMPTY_N && int_sqrt_fNext_29$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_29 = CAN_FIRE_RL_int_sqrt_work_29 ; - - // rule RL_int_sqrt_work_28 - assign CAN_FIRE_RL_int_sqrt_work_28 = - int_sqrt_fNext_27$EMPTY_N && int_sqrt_fNext_28$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_28 = CAN_FIRE_RL_int_sqrt_work_28 ; - - // rule RL_int_sqrt_work_27 - assign CAN_FIRE_RL_int_sqrt_work_27 = - int_sqrt_fNext_26$EMPTY_N && int_sqrt_fNext_27$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_27 = CAN_FIRE_RL_int_sqrt_work_27 ; - - // rule RL_int_sqrt_work_26 - assign CAN_FIRE_RL_int_sqrt_work_26 = - int_sqrt_fNext_25$EMPTY_N && int_sqrt_fNext_26$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_26 = CAN_FIRE_RL_int_sqrt_work_26 ; - - // rule RL_int_sqrt_work_25 - assign CAN_FIRE_RL_int_sqrt_work_25 = - int_sqrt_fNext_24$EMPTY_N && int_sqrt_fNext_25$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_25 = CAN_FIRE_RL_int_sqrt_work_25 ; - - // rule RL_int_sqrt_work_24 - assign CAN_FIRE_RL_int_sqrt_work_24 = - int_sqrt_fNext_23$EMPTY_N && int_sqrt_fNext_24$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_24 = CAN_FIRE_RL_int_sqrt_work_24 ; - - // rule RL_int_sqrt_work_23 - assign CAN_FIRE_RL_int_sqrt_work_23 = - int_sqrt_fNext_22$EMPTY_N && int_sqrt_fNext_23$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_23 = CAN_FIRE_RL_int_sqrt_work_23 ; - - // rule RL_int_sqrt_work_22 - assign CAN_FIRE_RL_int_sqrt_work_22 = - int_sqrt_fNext_21$EMPTY_N && int_sqrt_fNext_22$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_22 = CAN_FIRE_RL_int_sqrt_work_22 ; - - // rule RL_int_sqrt_work_21 - assign CAN_FIRE_RL_int_sqrt_work_21 = - int_sqrt_fNext_20$EMPTY_N && int_sqrt_fNext_21$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_21 = CAN_FIRE_RL_int_sqrt_work_21 ; - - // rule RL_int_sqrt_work_20 - assign CAN_FIRE_RL_int_sqrt_work_20 = - int_sqrt_fNext_19$EMPTY_N && int_sqrt_fNext_20$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_20 = CAN_FIRE_RL_int_sqrt_work_20 ; - - // rule RL_int_sqrt_work_19 - assign CAN_FIRE_RL_int_sqrt_work_19 = - int_sqrt_fNext_18$EMPTY_N && int_sqrt_fNext_19$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_19 = CAN_FIRE_RL_int_sqrt_work_19 ; - - // rule RL_int_sqrt_work_18 - assign CAN_FIRE_RL_int_sqrt_work_18 = - int_sqrt_fNext_17$EMPTY_N && int_sqrt_fNext_18$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_18 = CAN_FIRE_RL_int_sqrt_work_18 ; - - // rule RL_int_sqrt_work_17 - assign CAN_FIRE_RL_int_sqrt_work_17 = - int_sqrt_fNext_16$EMPTY_N && int_sqrt_fNext_17$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_17 = CAN_FIRE_RL_int_sqrt_work_17 ; - - // rule RL_int_sqrt_work_16 - assign CAN_FIRE_RL_int_sqrt_work_16 = - int_sqrt_fNext_15$EMPTY_N && int_sqrt_fNext_16$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_16 = CAN_FIRE_RL_int_sqrt_work_16 ; - - // rule RL_int_sqrt_work_15 - assign CAN_FIRE_RL_int_sqrt_work_15 = - int_sqrt_fNext_14$EMPTY_N && int_sqrt_fNext_15$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_15 = CAN_FIRE_RL_int_sqrt_work_15 ; - - // rule RL_int_sqrt_work_14 - assign CAN_FIRE_RL_int_sqrt_work_14 = - int_sqrt_fNext_13$EMPTY_N && int_sqrt_fNext_14$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_14 = CAN_FIRE_RL_int_sqrt_work_14 ; - - // rule RL_int_sqrt_work_13 - assign CAN_FIRE_RL_int_sqrt_work_13 = - int_sqrt_fNext_12$EMPTY_N && int_sqrt_fNext_13$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_13 = CAN_FIRE_RL_int_sqrt_work_13 ; - - // rule RL_int_sqrt_work_12 - assign CAN_FIRE_RL_int_sqrt_work_12 = - int_sqrt_fNext_11$EMPTY_N && int_sqrt_fNext_12$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_12 = CAN_FIRE_RL_int_sqrt_work_12 ; - - // rule RL_int_sqrt_work_11 - assign CAN_FIRE_RL_int_sqrt_work_11 = - int_sqrt_fNext_10$EMPTY_N && int_sqrt_fNext_11$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_11 = CAN_FIRE_RL_int_sqrt_work_11 ; - - // rule RL_int_sqrt_work_10 - assign CAN_FIRE_RL_int_sqrt_work_10 = - int_sqrt_fNext_9$EMPTY_N && int_sqrt_fNext_10$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_10 = CAN_FIRE_RL_int_sqrt_work_10 ; - - // rule RL_int_sqrt_work_9 - assign CAN_FIRE_RL_int_sqrt_work_9 = - int_sqrt_fNext_8$EMPTY_N && int_sqrt_fNext_9$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_9 = CAN_FIRE_RL_int_sqrt_work_9 ; - - // rule RL_int_sqrt_work_8 - assign CAN_FIRE_RL_int_sqrt_work_8 = - int_sqrt_fNext_7$EMPTY_N && int_sqrt_fNext_8$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_8 = CAN_FIRE_RL_int_sqrt_work_8 ; - - // rule RL_int_sqrt_work_7 - assign CAN_FIRE_RL_int_sqrt_work_7 = - int_sqrt_fNext_6$EMPTY_N && int_sqrt_fNext_7$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_7 = CAN_FIRE_RL_int_sqrt_work_7 ; - - // rule RL_int_sqrt_work_6 - assign CAN_FIRE_RL_int_sqrt_work_6 = - int_sqrt_fNext_5$EMPTY_N && int_sqrt_fNext_6$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_6 = CAN_FIRE_RL_int_sqrt_work_6 ; - - // rule RL_int_sqrt_work_5 - assign CAN_FIRE_RL_int_sqrt_work_5 = - int_sqrt_fNext_4$EMPTY_N && int_sqrt_fNext_5$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_5 = CAN_FIRE_RL_int_sqrt_work_5 ; - - // rule RL_int_sqrt_work_4 - assign CAN_FIRE_RL_int_sqrt_work_4 = - int_sqrt_fNext_3$EMPTY_N && int_sqrt_fNext_4$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_4 = CAN_FIRE_RL_int_sqrt_work_4 ; - - // rule RL_int_sqrt_work_3 - assign CAN_FIRE_RL_int_sqrt_work_3 = - int_sqrt_fNext_2$EMPTY_N && int_sqrt_fNext_3$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_3 = CAN_FIRE_RL_int_sqrt_work_3 ; - - // rule RL_int_sqrt_work_2 - assign CAN_FIRE_RL_int_sqrt_work_2 = - int_sqrt_fNext_1$EMPTY_N && int_sqrt_fNext_2$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_2 = CAN_FIRE_RL_int_sqrt_work_2 ; - - // rule RL_int_sqrt_work_1 - assign CAN_FIRE_RL_int_sqrt_work_1 = - int_sqrt_fNext_0$EMPTY_N && int_sqrt_fNext_1$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_1 = CAN_FIRE_RL_int_sqrt_work_1 ; - - // rule RL_int_sqrt_work - assign CAN_FIRE_RL_int_sqrt_work = - int_sqrt_fFirst$EMPTY_N && int_sqrt_fNext_0$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work = CAN_FIRE_RL_int_sqrt_work ; - - // rule RL_int_sqrt_start - assign CAN_FIRE_RL_int_sqrt_start = - int_sqrt_fRequest$EMPTY_N && int_sqrt_fFirst$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_start = CAN_FIRE_RL_int_sqrt_start ; - - // rule RL_fpu_s2_stage - assign CAN_FIRE_RL_fpu_s2_stage = - fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && - (fpu_fState_S1$D_OUT[194] || int_sqrt_fRequest$FULL_N) ; - assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; - - // rule RL_fpu_s1_stage - assign CAN_FIRE_RL_fpu_s1_stage = - fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; - - // submodule fpu_fOperand_S0 - assign fpu_fOperand_S0$D_IN = request_put ; - assign fpu_fOperand_S0$ENQ = EN_request_put ; - assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_fResult_S5 - assign fpu_fResult_S5$D_IN = - fpu_fState_S4$D_OUT[138] ? - fpu_fState_S4$D_OUT[137:69] : - { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[65:2] : - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15, - fpu_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h76509 == 11'd2047 && - _theResult___fst_sfd__h76510 == 52'd0, - 1'd0, - fpu_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fResult_S5$DEQ = EN_response_get ; - assign fpu_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_fState_S1 - assign fpu_fState_S1$D_IN = - (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54]) ? - { 1'd1, - fpu_fOperand_S0$D_OUT[66:55], - sfd__h49989, - 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 ; - assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S1$CLR = 1'b0 ; - - // submodule fpu_fState_S2 - assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[194:58] ; - assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S2$CLR = 1'b0 ; - - // submodule fpu_fState_S3 - assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT, x__h66665 } ; - assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S3$CLR = 1'b0 ; - - // submodule fpu_fState_S4 - assign fpu_fState_S4$D_IN = - { fpu_fState_S3$D_OUT[195:131], - fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[130], - fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[129], - IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813, - fpu_fState_S3$D_OUT[125:122], - fpu_fState_S3$D_OUT[195] ? - fpu_fState_S3$D_OUT[121:59] : - IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820, - x__h75654 } ; - assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S4$CLR = 1'b0 ; - - // submodule int_sqrt_fFirst - assign int_sqrt_fFirst$D_IN = - { 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - int_sqrt_fRequest$D_OUT, - 116'd0, - x__h402 } ; - assign int_sqrt_fFirst$ENQ = CAN_FIRE_RL_int_sqrt_start ; - assign int_sqrt_fFirst$DEQ = CAN_FIRE_RL_int_sqrt_work ; - assign int_sqrt_fFirst$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_0 - assign int_sqrt_fNext_0$D_IN = - { int_sqrt_fFirst$D_OUT[464] || - int_sqrt_fFirst$D_OUT[115:0] == 116'd0, - int_sqrt_fFirst$D_OUT[464] ? - int_sqrt_fFirst$D_OUT[463:348] : - ((int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? - int_sqrt_fFirst$D_OUT[231:116] : - int_sqrt_fFirst$D_OUT[463:348]), - int_sqrt_fFirst$D_OUT[464] ? - int_sqrt_fFirst$D_OUT[347:0] : - { _theResult___snd_fst__h25299, - (int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? - int_sqrt_fFirst$D_OUT[231:0] : - { _theResult___snd_snd__h25377, b__h25374 } } } ; - assign int_sqrt_fNext_0$ENQ = CAN_FIRE_RL_int_sqrt_work ; - assign int_sqrt_fNext_0$DEQ = CAN_FIRE_RL_int_sqrt_work_1 ; - assign int_sqrt_fNext_0$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_1 - assign int_sqrt_fNext_1$D_IN = - { int_sqrt_fNext_0$D_OUT[464] || - int_sqrt_fNext_0$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_0$D_OUT[464] ? - int_sqrt_fNext_0$D_OUT[463:348] : - ((int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_0$D_OUT[231:116] : - int_sqrt_fNext_0$D_OUT[463:348]), - int_sqrt_fNext_0$D_OUT[464] ? - int_sqrt_fNext_0$D_OUT[347:0] : - { _theResult___snd_fst__h25701, - (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_0$D_OUT[231:0] : - { _theResult___snd_snd__h25777, b__h25774 } } } ; - assign int_sqrt_fNext_1$ENQ = CAN_FIRE_RL_int_sqrt_work_1 ; - assign int_sqrt_fNext_1$DEQ = CAN_FIRE_RL_int_sqrt_work_2 ; - assign int_sqrt_fNext_1$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_10 - assign int_sqrt_fNext_10$D_IN = - { int_sqrt_fNext_9$D_OUT[464] || - int_sqrt_fNext_9$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_9$D_OUT[464] ? - int_sqrt_fNext_9$D_OUT[463:348] : - ((int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_9$D_OUT[231:116] : - int_sqrt_fNext_9$D_OUT[463:348]), - int_sqrt_fNext_9$D_OUT[464] ? - int_sqrt_fNext_9$D_OUT[347:0] : - { _theResult___snd_fst__h29301, - (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_9$D_OUT[231:0] : - { _theResult___snd_snd__h29377, b__h29374 } } } ; - assign int_sqrt_fNext_10$ENQ = CAN_FIRE_RL_int_sqrt_work_10 ; - assign int_sqrt_fNext_10$DEQ = CAN_FIRE_RL_int_sqrt_work_11 ; - assign int_sqrt_fNext_10$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_11 - assign int_sqrt_fNext_11$D_IN = - { int_sqrt_fNext_10$D_OUT[464] || - int_sqrt_fNext_10$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_10$D_OUT[464] ? - int_sqrt_fNext_10$D_OUT[463:348] : - ((int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_10$D_OUT[231:116] : - int_sqrt_fNext_10$D_OUT[463:348]), - int_sqrt_fNext_10$D_OUT[464] ? - int_sqrt_fNext_10$D_OUT[347:0] : - { _theResult___snd_fst__h29701, - (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_10$D_OUT[231:0] : - { _theResult___snd_snd__h29777, b__h29774 } } } ; - assign int_sqrt_fNext_11$ENQ = CAN_FIRE_RL_int_sqrt_work_11 ; - assign int_sqrt_fNext_11$DEQ = CAN_FIRE_RL_int_sqrt_work_12 ; - assign int_sqrt_fNext_11$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_12 - assign int_sqrt_fNext_12$D_IN = - { int_sqrt_fNext_11$D_OUT[464] || - int_sqrt_fNext_11$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_11$D_OUT[464] ? - int_sqrt_fNext_11$D_OUT[463:348] : - ((int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_11$D_OUT[231:116] : - int_sqrt_fNext_11$D_OUT[463:348]), - int_sqrt_fNext_11$D_OUT[464] ? - int_sqrt_fNext_11$D_OUT[347:0] : - { _theResult___snd_fst__h30101, - (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_11$D_OUT[231:0] : - { _theResult___snd_snd__h30177, b__h30174 } } } ; - assign int_sqrt_fNext_12$ENQ = CAN_FIRE_RL_int_sqrt_work_12 ; - assign int_sqrt_fNext_12$DEQ = CAN_FIRE_RL_int_sqrt_work_13 ; - assign int_sqrt_fNext_12$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_13 - assign int_sqrt_fNext_13$D_IN = - { int_sqrt_fNext_12$D_OUT[464] || - int_sqrt_fNext_12$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_12$D_OUT[464] ? - int_sqrt_fNext_12$D_OUT[463:348] : - ((int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_12$D_OUT[231:116] : - int_sqrt_fNext_12$D_OUT[463:348]), - int_sqrt_fNext_12$D_OUT[464] ? - int_sqrt_fNext_12$D_OUT[347:0] : - { _theResult___snd_fst__h30501, - (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_12$D_OUT[231:0] : - { _theResult___snd_snd__h30577, b__h30574 } } } ; - assign int_sqrt_fNext_13$ENQ = CAN_FIRE_RL_int_sqrt_work_13 ; - assign int_sqrt_fNext_13$DEQ = CAN_FIRE_RL_int_sqrt_work_14 ; - assign int_sqrt_fNext_13$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_14 - assign int_sqrt_fNext_14$D_IN = - { int_sqrt_fNext_13$D_OUT[464] || - int_sqrt_fNext_13$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_13$D_OUT[464] ? - int_sqrt_fNext_13$D_OUT[463:348] : - ((int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_13$D_OUT[231:116] : - int_sqrt_fNext_13$D_OUT[463:348]), - int_sqrt_fNext_13$D_OUT[464] ? - int_sqrt_fNext_13$D_OUT[347:0] : - { _theResult___snd_fst__h30901, - (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_13$D_OUT[231:0] : - { _theResult___snd_snd__h30977, b__h30974 } } } ; - assign int_sqrt_fNext_14$ENQ = CAN_FIRE_RL_int_sqrt_work_14 ; - assign int_sqrt_fNext_14$DEQ = CAN_FIRE_RL_int_sqrt_work_15 ; - assign int_sqrt_fNext_14$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_15 - assign int_sqrt_fNext_15$D_IN = - { int_sqrt_fNext_14$D_OUT[464] || - int_sqrt_fNext_14$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_14$D_OUT[464] ? - int_sqrt_fNext_14$D_OUT[463:348] : - ((int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_14$D_OUT[231:116] : - int_sqrt_fNext_14$D_OUT[463:348]), - int_sqrt_fNext_14$D_OUT[464] ? - int_sqrt_fNext_14$D_OUT[347:0] : - { _theResult___snd_fst__h31301, - (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_14$D_OUT[231:0] : - { _theResult___snd_snd__h31377, b__h31374 } } } ; - assign int_sqrt_fNext_15$ENQ = CAN_FIRE_RL_int_sqrt_work_15 ; - assign int_sqrt_fNext_15$DEQ = CAN_FIRE_RL_int_sqrt_work_16 ; - assign int_sqrt_fNext_15$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_16 - assign int_sqrt_fNext_16$D_IN = - { int_sqrt_fNext_15$D_OUT[464] || - int_sqrt_fNext_15$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_15$D_OUT[464] ? - int_sqrt_fNext_15$D_OUT[463:348] : - ((int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_15$D_OUT[231:116] : - int_sqrt_fNext_15$D_OUT[463:348]), - int_sqrt_fNext_15$D_OUT[464] ? - int_sqrt_fNext_15$D_OUT[347:0] : - { _theResult___snd_fst__h31701, - (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_15$D_OUT[231:0] : - { _theResult___snd_snd__h31777, b__h31774 } } } ; - assign int_sqrt_fNext_16$ENQ = CAN_FIRE_RL_int_sqrt_work_16 ; - assign int_sqrt_fNext_16$DEQ = CAN_FIRE_RL_int_sqrt_work_17 ; - assign int_sqrt_fNext_16$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_17 - assign int_sqrt_fNext_17$D_IN = - { int_sqrt_fNext_16$D_OUT[464] || - int_sqrt_fNext_16$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_16$D_OUT[464] ? - int_sqrt_fNext_16$D_OUT[463:348] : - ((int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_16$D_OUT[231:116] : - int_sqrt_fNext_16$D_OUT[463:348]), - int_sqrt_fNext_16$D_OUT[464] ? - int_sqrt_fNext_16$D_OUT[347:0] : - { _theResult___snd_fst__h32101, - (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_16$D_OUT[231:0] : - { _theResult___snd_snd__h32177, b__h32174 } } } ; - assign int_sqrt_fNext_17$ENQ = CAN_FIRE_RL_int_sqrt_work_17 ; - assign int_sqrt_fNext_17$DEQ = CAN_FIRE_RL_int_sqrt_work_18 ; - assign int_sqrt_fNext_17$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_18 - assign int_sqrt_fNext_18$D_IN = - { int_sqrt_fNext_17$D_OUT[464] || - int_sqrt_fNext_17$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_17$D_OUT[464] ? - int_sqrt_fNext_17$D_OUT[463:348] : - ((int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_17$D_OUT[231:116] : - int_sqrt_fNext_17$D_OUT[463:348]), - int_sqrt_fNext_17$D_OUT[464] ? - int_sqrt_fNext_17$D_OUT[347:0] : - { _theResult___snd_fst__h32501, - (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_17$D_OUT[231:0] : - { _theResult___snd_snd__h32577, b__h32574 } } } ; - assign int_sqrt_fNext_18$ENQ = CAN_FIRE_RL_int_sqrt_work_18 ; - assign int_sqrt_fNext_18$DEQ = CAN_FIRE_RL_int_sqrt_work_19 ; - assign int_sqrt_fNext_18$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_19 - assign int_sqrt_fNext_19$D_IN = - { int_sqrt_fNext_18$D_OUT[464] || - int_sqrt_fNext_18$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_18$D_OUT[464] ? - int_sqrt_fNext_18$D_OUT[463:348] : - ((int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_18$D_OUT[231:116] : - int_sqrt_fNext_18$D_OUT[463:348]), - int_sqrt_fNext_18$D_OUT[464] ? - int_sqrt_fNext_18$D_OUT[347:0] : - { _theResult___snd_fst__h32901, - (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_18$D_OUT[231:0] : - { _theResult___snd_snd__h32977, b__h32974 } } } ; - assign int_sqrt_fNext_19$ENQ = CAN_FIRE_RL_int_sqrt_work_19 ; - assign int_sqrt_fNext_19$DEQ = CAN_FIRE_RL_int_sqrt_work_20 ; - assign int_sqrt_fNext_19$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_2 - assign int_sqrt_fNext_2$D_IN = - { int_sqrt_fNext_1$D_OUT[464] || - int_sqrt_fNext_1$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_1$D_OUT[464] ? - int_sqrt_fNext_1$D_OUT[463:348] : - ((int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_1$D_OUT[231:116] : - int_sqrt_fNext_1$D_OUT[463:348]), - int_sqrt_fNext_1$D_OUT[464] ? - int_sqrt_fNext_1$D_OUT[347:0] : - { _theResult___snd_fst__h26101, - (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_1$D_OUT[231:0] : - { _theResult___snd_snd__h26177, b__h26174 } } } ; - assign int_sqrt_fNext_2$ENQ = CAN_FIRE_RL_int_sqrt_work_2 ; - assign int_sqrt_fNext_2$DEQ = CAN_FIRE_RL_int_sqrt_work_3 ; - assign int_sqrt_fNext_2$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_20 - assign int_sqrt_fNext_20$D_IN = - { int_sqrt_fNext_19$D_OUT[464] || - int_sqrt_fNext_19$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_19$D_OUT[464] ? - int_sqrt_fNext_19$D_OUT[463:348] : - ((int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_19$D_OUT[231:116] : - int_sqrt_fNext_19$D_OUT[463:348]), - int_sqrt_fNext_19$D_OUT[464] ? - int_sqrt_fNext_19$D_OUT[347:0] : - { _theResult___snd_fst__h33301, - (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_19$D_OUT[231:0] : - { _theResult___snd_snd__h33377, b__h33374 } } } ; - assign int_sqrt_fNext_20$ENQ = CAN_FIRE_RL_int_sqrt_work_20 ; - assign int_sqrt_fNext_20$DEQ = CAN_FIRE_RL_int_sqrt_work_21 ; - assign int_sqrt_fNext_20$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_21 - assign int_sqrt_fNext_21$D_IN = - { int_sqrt_fNext_20$D_OUT[464] || - int_sqrt_fNext_20$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_20$D_OUT[464] ? - int_sqrt_fNext_20$D_OUT[463:348] : - ((int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_20$D_OUT[231:116] : - int_sqrt_fNext_20$D_OUT[463:348]), - int_sqrt_fNext_20$D_OUT[464] ? - int_sqrt_fNext_20$D_OUT[347:0] : - { _theResult___snd_fst__h33701, - (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_20$D_OUT[231:0] : - { _theResult___snd_snd__h33777, b__h33774 } } } ; - assign int_sqrt_fNext_21$ENQ = CAN_FIRE_RL_int_sqrt_work_21 ; - assign int_sqrt_fNext_21$DEQ = CAN_FIRE_RL_int_sqrt_work_22 ; - assign int_sqrt_fNext_21$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_22 - assign int_sqrt_fNext_22$D_IN = - { int_sqrt_fNext_21$D_OUT[464] || - int_sqrt_fNext_21$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_21$D_OUT[464] ? - int_sqrt_fNext_21$D_OUT[463:348] : - ((int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_21$D_OUT[231:116] : - int_sqrt_fNext_21$D_OUT[463:348]), - int_sqrt_fNext_21$D_OUT[464] ? - int_sqrt_fNext_21$D_OUT[347:0] : - { _theResult___snd_fst__h34101, - (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_21$D_OUT[231:0] : - { _theResult___snd_snd__h34177, b__h34174 } } } ; - assign int_sqrt_fNext_22$ENQ = CAN_FIRE_RL_int_sqrt_work_22 ; - assign int_sqrt_fNext_22$DEQ = CAN_FIRE_RL_int_sqrt_work_23 ; - assign int_sqrt_fNext_22$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_23 - assign int_sqrt_fNext_23$D_IN = - { int_sqrt_fNext_22$D_OUT[464] || - int_sqrt_fNext_22$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_22$D_OUT[464] ? - int_sqrt_fNext_22$D_OUT[463:348] : - ((int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_22$D_OUT[231:116] : - int_sqrt_fNext_22$D_OUT[463:348]), - int_sqrt_fNext_22$D_OUT[464] ? - int_sqrt_fNext_22$D_OUT[347:0] : - { _theResult___snd_fst__h34501, - (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_22$D_OUT[231:0] : - { _theResult___snd_snd__h34577, b__h34574 } } } ; - assign int_sqrt_fNext_23$ENQ = CAN_FIRE_RL_int_sqrt_work_23 ; - assign int_sqrt_fNext_23$DEQ = CAN_FIRE_RL_int_sqrt_work_24 ; - assign int_sqrt_fNext_23$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_24 - assign int_sqrt_fNext_24$D_IN = - { int_sqrt_fNext_23$D_OUT[464] || - int_sqrt_fNext_23$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_23$D_OUT[464] ? - int_sqrt_fNext_23$D_OUT[463:348] : - ((int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_23$D_OUT[231:116] : - int_sqrt_fNext_23$D_OUT[463:348]), - int_sqrt_fNext_23$D_OUT[464] ? - int_sqrt_fNext_23$D_OUT[347:0] : - { _theResult___snd_fst__h34901, - (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_23$D_OUT[231:0] : - { _theResult___snd_snd__h34977, b__h34974 } } } ; - assign int_sqrt_fNext_24$ENQ = CAN_FIRE_RL_int_sqrt_work_24 ; - assign int_sqrt_fNext_24$DEQ = CAN_FIRE_RL_int_sqrt_work_25 ; - assign int_sqrt_fNext_24$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_25 - assign int_sqrt_fNext_25$D_IN = - { int_sqrt_fNext_24$D_OUT[464] || - int_sqrt_fNext_24$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_24$D_OUT[464] ? - int_sqrt_fNext_24$D_OUT[463:348] : - ((int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_24$D_OUT[231:116] : - int_sqrt_fNext_24$D_OUT[463:348]), - int_sqrt_fNext_24$D_OUT[464] ? - int_sqrt_fNext_24$D_OUT[347:0] : - { _theResult___snd_fst__h35301, - (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_24$D_OUT[231:0] : - { _theResult___snd_snd__h35377, b__h35374 } } } ; - assign int_sqrt_fNext_25$ENQ = CAN_FIRE_RL_int_sqrt_work_25 ; - assign int_sqrt_fNext_25$DEQ = CAN_FIRE_RL_int_sqrt_work_26 ; - assign int_sqrt_fNext_25$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_26 - assign int_sqrt_fNext_26$D_IN = - { int_sqrt_fNext_25$D_OUT[464] || - int_sqrt_fNext_25$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_25$D_OUT[464] ? - int_sqrt_fNext_25$D_OUT[463:348] : - ((int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_25$D_OUT[231:116] : - int_sqrt_fNext_25$D_OUT[463:348]), - int_sqrt_fNext_25$D_OUT[464] ? - int_sqrt_fNext_25$D_OUT[347:0] : - { _theResult___snd_fst__h35701, - (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_25$D_OUT[231:0] : - { _theResult___snd_snd__h35777, b__h35774 } } } ; - assign int_sqrt_fNext_26$ENQ = CAN_FIRE_RL_int_sqrt_work_26 ; - assign int_sqrt_fNext_26$DEQ = CAN_FIRE_RL_int_sqrt_work_27 ; - assign int_sqrt_fNext_26$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_27 - assign int_sqrt_fNext_27$D_IN = - { int_sqrt_fNext_26$D_OUT[464] || - int_sqrt_fNext_26$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_26$D_OUT[464] ? - int_sqrt_fNext_26$D_OUT[463:348] : - ((int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_26$D_OUT[231:116] : - int_sqrt_fNext_26$D_OUT[463:348]), - int_sqrt_fNext_26$D_OUT[464] ? - int_sqrt_fNext_26$D_OUT[347:0] : - { _theResult___snd_fst__h36101, - (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_26$D_OUT[231:0] : - { _theResult___snd_snd__h36177, b__h36174 } } } ; - assign int_sqrt_fNext_27$ENQ = CAN_FIRE_RL_int_sqrt_work_27 ; - assign int_sqrt_fNext_27$DEQ = CAN_FIRE_RL_int_sqrt_work_28 ; - assign int_sqrt_fNext_27$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_28 - assign int_sqrt_fNext_28$D_IN = - { int_sqrt_fNext_27$D_OUT[464] || - int_sqrt_fNext_27$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_27$D_OUT[464] ? - int_sqrt_fNext_27$D_OUT[463:348] : - ((int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_27$D_OUT[231:116] : - int_sqrt_fNext_27$D_OUT[463:348]), - int_sqrt_fNext_27$D_OUT[464] ? - int_sqrt_fNext_27$D_OUT[347:0] : - { _theResult___snd_fst__h36501, - (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_27$D_OUT[231:0] : - { _theResult___snd_snd__h36577, b__h36574 } } } ; - assign int_sqrt_fNext_28$ENQ = CAN_FIRE_RL_int_sqrt_work_28 ; - assign int_sqrt_fNext_28$DEQ = CAN_FIRE_RL_int_sqrt_work_29 ; - assign int_sqrt_fNext_28$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_29 - assign int_sqrt_fNext_29$D_IN = - { int_sqrt_fNext_28$D_OUT[464] || - int_sqrt_fNext_28$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_28$D_OUT[464] ? - int_sqrt_fNext_28$D_OUT[463:348] : - ((int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_28$D_OUT[231:116] : - int_sqrt_fNext_28$D_OUT[463:348]), - int_sqrt_fNext_28$D_OUT[464] ? - int_sqrt_fNext_28$D_OUT[347:0] : - { _theResult___snd_fst__h36901, - (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_28$D_OUT[231:0] : - { _theResult___snd_snd__h36977, b__h36974 } } } ; - assign int_sqrt_fNext_29$ENQ = CAN_FIRE_RL_int_sqrt_work_29 ; - assign int_sqrt_fNext_29$DEQ = CAN_FIRE_RL_int_sqrt_work_30 ; - assign int_sqrt_fNext_29$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_3 - assign int_sqrt_fNext_3$D_IN = - { int_sqrt_fNext_2$D_OUT[464] || - int_sqrt_fNext_2$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_2$D_OUT[464] ? - int_sqrt_fNext_2$D_OUT[463:348] : - ((int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_2$D_OUT[231:116] : - int_sqrt_fNext_2$D_OUT[463:348]), - int_sqrt_fNext_2$D_OUT[464] ? - int_sqrt_fNext_2$D_OUT[347:0] : - { _theResult___snd_fst__h26501, - (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_2$D_OUT[231:0] : - { _theResult___snd_snd__h26577, b__h26574 } } } ; - assign int_sqrt_fNext_3$ENQ = CAN_FIRE_RL_int_sqrt_work_3 ; - assign int_sqrt_fNext_3$DEQ = CAN_FIRE_RL_int_sqrt_work_4 ; - assign int_sqrt_fNext_3$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_30 - assign int_sqrt_fNext_30$D_IN = - { int_sqrt_fNext_29$D_OUT[464] || - int_sqrt_fNext_29$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_29$D_OUT[464] ? - int_sqrt_fNext_29$D_OUT[463:348] : - ((int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_29$D_OUT[231:116] : - int_sqrt_fNext_29$D_OUT[463:348]), - int_sqrt_fNext_29$D_OUT[464] ? - int_sqrt_fNext_29$D_OUT[347:0] : - { _theResult___snd_fst__h37301, - (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_29$D_OUT[231:0] : - { _theResult___snd_snd__h37377, b__h37374 } } } ; - assign int_sqrt_fNext_30$ENQ = CAN_FIRE_RL_int_sqrt_work_30 ; - assign int_sqrt_fNext_30$DEQ = CAN_FIRE_RL_int_sqrt_work_31 ; - assign int_sqrt_fNext_30$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_31 - assign int_sqrt_fNext_31$D_IN = - { int_sqrt_fNext_30$D_OUT[464] || - int_sqrt_fNext_30$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_30$D_OUT[464] ? - int_sqrt_fNext_30$D_OUT[463:348] : - ((int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_30$D_OUT[231:116] : - int_sqrt_fNext_30$D_OUT[463:348]), - int_sqrt_fNext_30$D_OUT[464] ? - int_sqrt_fNext_30$D_OUT[347:0] : - { _theResult___snd_fst__h37701, - (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_30$D_OUT[231:0] : - { _theResult___snd_snd__h37777, b__h37774 } } } ; - assign int_sqrt_fNext_31$ENQ = CAN_FIRE_RL_int_sqrt_work_31 ; - assign int_sqrt_fNext_31$DEQ = CAN_FIRE_RL_int_sqrt_work_32 ; - assign int_sqrt_fNext_31$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_32 - assign int_sqrt_fNext_32$D_IN = - { int_sqrt_fNext_31$D_OUT[464] || - int_sqrt_fNext_31$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_31$D_OUT[464] ? - int_sqrt_fNext_31$D_OUT[463:348] : - ((int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_31$D_OUT[231:116] : - int_sqrt_fNext_31$D_OUT[463:348]), - int_sqrt_fNext_31$D_OUT[464] ? - int_sqrt_fNext_31$D_OUT[347:0] : - { _theResult___snd_fst__h38101, - (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_31$D_OUT[231:0] : - { _theResult___snd_snd__h38177, b__h38174 } } } ; - assign int_sqrt_fNext_32$ENQ = CAN_FIRE_RL_int_sqrt_work_32 ; - assign int_sqrt_fNext_32$DEQ = CAN_FIRE_RL_int_sqrt_work_33 ; - assign int_sqrt_fNext_32$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_33 - assign int_sqrt_fNext_33$D_IN = - { int_sqrt_fNext_32$D_OUT[464] || - int_sqrt_fNext_32$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_32$D_OUT[464] ? - int_sqrt_fNext_32$D_OUT[463:348] : - ((int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_32$D_OUT[231:116] : - int_sqrt_fNext_32$D_OUT[463:348]), - int_sqrt_fNext_32$D_OUT[464] ? - int_sqrt_fNext_32$D_OUT[347:0] : - { _theResult___snd_fst__h38501, - (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_32$D_OUT[231:0] : - { _theResult___snd_snd__h38577, b__h38574 } } } ; - assign int_sqrt_fNext_33$ENQ = CAN_FIRE_RL_int_sqrt_work_33 ; - assign int_sqrt_fNext_33$DEQ = CAN_FIRE_RL_int_sqrt_work_34 ; - assign int_sqrt_fNext_33$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_34 - assign int_sqrt_fNext_34$D_IN = - { int_sqrt_fNext_33$D_OUT[464] || - int_sqrt_fNext_33$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_33$D_OUT[464] ? - int_sqrt_fNext_33$D_OUT[463:348] : - ((int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_33$D_OUT[231:116] : - int_sqrt_fNext_33$D_OUT[463:348]), - int_sqrt_fNext_33$D_OUT[464] ? - int_sqrt_fNext_33$D_OUT[347:0] : - { _theResult___snd_fst__h38901, - (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_33$D_OUT[231:0] : - { _theResult___snd_snd__h38977, b__h38974 } } } ; - assign int_sqrt_fNext_34$ENQ = CAN_FIRE_RL_int_sqrt_work_34 ; - assign int_sqrt_fNext_34$DEQ = CAN_FIRE_RL_int_sqrt_work_35 ; - assign int_sqrt_fNext_34$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_35 - assign int_sqrt_fNext_35$D_IN = - { int_sqrt_fNext_34$D_OUT[464] || - int_sqrt_fNext_34$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_34$D_OUT[464] ? - int_sqrt_fNext_34$D_OUT[463:348] : - ((int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_34$D_OUT[231:116] : - int_sqrt_fNext_34$D_OUT[463:348]), - int_sqrt_fNext_34$D_OUT[464] ? - int_sqrt_fNext_34$D_OUT[347:0] : - { _theResult___snd_fst__h39301, - (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_34$D_OUT[231:0] : - { _theResult___snd_snd__h39377, b__h39374 } } } ; - assign int_sqrt_fNext_35$ENQ = CAN_FIRE_RL_int_sqrt_work_35 ; - assign int_sqrt_fNext_35$DEQ = CAN_FIRE_RL_int_sqrt_work_36 ; - assign int_sqrt_fNext_35$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_36 - assign int_sqrt_fNext_36$D_IN = - { int_sqrt_fNext_35$D_OUT[464] || - int_sqrt_fNext_35$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_35$D_OUT[464] ? - int_sqrt_fNext_35$D_OUT[463:348] : - ((int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_35$D_OUT[231:116] : - int_sqrt_fNext_35$D_OUT[463:348]), - int_sqrt_fNext_35$D_OUT[464] ? - int_sqrt_fNext_35$D_OUT[347:0] : - { _theResult___snd_fst__h39701, - (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_35$D_OUT[231:0] : - { _theResult___snd_snd__h39777, b__h39774 } } } ; - assign int_sqrt_fNext_36$ENQ = CAN_FIRE_RL_int_sqrt_work_36 ; - assign int_sqrt_fNext_36$DEQ = CAN_FIRE_RL_int_sqrt_work_37 ; - assign int_sqrt_fNext_36$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_37 - assign int_sqrt_fNext_37$D_IN = - { int_sqrt_fNext_36$D_OUT[464] || - int_sqrt_fNext_36$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_36$D_OUT[464] ? - int_sqrt_fNext_36$D_OUT[463:348] : - ((int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_36$D_OUT[231:116] : - int_sqrt_fNext_36$D_OUT[463:348]), - int_sqrt_fNext_36$D_OUT[464] ? - int_sqrt_fNext_36$D_OUT[347:0] : - { _theResult___snd_fst__h40101, - (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_36$D_OUT[231:0] : - { _theResult___snd_snd__h40177, b__h40174 } } } ; - assign int_sqrt_fNext_37$ENQ = CAN_FIRE_RL_int_sqrt_work_37 ; - assign int_sqrt_fNext_37$DEQ = CAN_FIRE_RL_int_sqrt_work_38 ; - assign int_sqrt_fNext_37$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_38 - assign int_sqrt_fNext_38$D_IN = - { int_sqrt_fNext_37$D_OUT[464] || - int_sqrt_fNext_37$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_37$D_OUT[464] ? - int_sqrt_fNext_37$D_OUT[463:348] : - ((int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_37$D_OUT[231:116] : - int_sqrt_fNext_37$D_OUT[463:348]), - int_sqrt_fNext_37$D_OUT[464] ? - int_sqrt_fNext_37$D_OUT[347:0] : - { _theResult___snd_fst__h40501, - (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_37$D_OUT[231:0] : - { _theResult___snd_snd__h40577, b__h40574 } } } ; - assign int_sqrt_fNext_38$ENQ = CAN_FIRE_RL_int_sqrt_work_38 ; - assign int_sqrt_fNext_38$DEQ = CAN_FIRE_RL_int_sqrt_work_39 ; - assign int_sqrt_fNext_38$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_39 - assign int_sqrt_fNext_39$D_IN = - { int_sqrt_fNext_38$D_OUT[464] || - int_sqrt_fNext_38$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_38$D_OUT[464] ? - int_sqrt_fNext_38$D_OUT[463:348] : - ((int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_38$D_OUT[231:116] : - int_sqrt_fNext_38$D_OUT[463:348]), - int_sqrt_fNext_38$D_OUT[464] ? - int_sqrt_fNext_38$D_OUT[347:0] : - { _theResult___snd_fst__h40901, - (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_38$D_OUT[231:0] : - { _theResult___snd_snd__h40977, b__h40974 } } } ; - assign int_sqrt_fNext_39$ENQ = CAN_FIRE_RL_int_sqrt_work_39 ; - assign int_sqrt_fNext_39$DEQ = CAN_FIRE_RL_int_sqrt_work_40 ; - assign int_sqrt_fNext_39$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_4 - assign int_sqrt_fNext_4$D_IN = - { int_sqrt_fNext_3$D_OUT[464] || - int_sqrt_fNext_3$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_3$D_OUT[464] ? - int_sqrt_fNext_3$D_OUT[463:348] : - ((int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_3$D_OUT[231:116] : - int_sqrt_fNext_3$D_OUT[463:348]), - int_sqrt_fNext_3$D_OUT[464] ? - int_sqrt_fNext_3$D_OUT[347:0] : - { _theResult___snd_fst__h26901, - (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_3$D_OUT[231:0] : - { _theResult___snd_snd__h26977, b__h26974 } } } ; - assign int_sqrt_fNext_4$ENQ = CAN_FIRE_RL_int_sqrt_work_4 ; - assign int_sqrt_fNext_4$DEQ = CAN_FIRE_RL_int_sqrt_work_5 ; - assign int_sqrt_fNext_4$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_40 - assign int_sqrt_fNext_40$D_IN = - { int_sqrt_fNext_39$D_OUT[464] || - int_sqrt_fNext_39$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_39$D_OUT[464] ? - int_sqrt_fNext_39$D_OUT[463:348] : - ((int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_39$D_OUT[231:116] : - int_sqrt_fNext_39$D_OUT[463:348]), - int_sqrt_fNext_39$D_OUT[464] ? - int_sqrt_fNext_39$D_OUT[347:0] : - { _theResult___snd_fst__h41301, - (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_39$D_OUT[231:0] : - { _theResult___snd_snd__h41377, b__h41374 } } } ; - assign int_sqrt_fNext_40$ENQ = CAN_FIRE_RL_int_sqrt_work_40 ; - assign int_sqrt_fNext_40$DEQ = CAN_FIRE_RL_int_sqrt_work_41 ; - assign int_sqrt_fNext_40$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_41 - assign int_sqrt_fNext_41$D_IN = - { int_sqrt_fNext_40$D_OUT[464] || - int_sqrt_fNext_40$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_40$D_OUT[464] ? - int_sqrt_fNext_40$D_OUT[463:348] : - ((int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_40$D_OUT[231:116] : - int_sqrt_fNext_40$D_OUT[463:348]), - int_sqrt_fNext_40$D_OUT[464] ? - int_sqrt_fNext_40$D_OUT[347:0] : - { _theResult___snd_fst__h41701, - (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_40$D_OUT[231:0] : - { _theResult___snd_snd__h41777, b__h41774 } } } ; - assign int_sqrt_fNext_41$ENQ = CAN_FIRE_RL_int_sqrt_work_41 ; - assign int_sqrt_fNext_41$DEQ = CAN_FIRE_RL_int_sqrt_work_42 ; - assign int_sqrt_fNext_41$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_42 - assign int_sqrt_fNext_42$D_IN = - { int_sqrt_fNext_41$D_OUT[464] || - int_sqrt_fNext_41$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_41$D_OUT[464] ? - int_sqrt_fNext_41$D_OUT[463:348] : - ((int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_41$D_OUT[231:116] : - int_sqrt_fNext_41$D_OUT[463:348]), - int_sqrt_fNext_41$D_OUT[464] ? - int_sqrt_fNext_41$D_OUT[347:0] : - { _theResult___snd_fst__h42101, - (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_41$D_OUT[231:0] : - { _theResult___snd_snd__h42177, b__h42174 } } } ; - assign int_sqrt_fNext_42$ENQ = CAN_FIRE_RL_int_sqrt_work_42 ; - assign int_sqrt_fNext_42$DEQ = CAN_FIRE_RL_int_sqrt_work_43 ; - assign int_sqrt_fNext_42$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_43 - assign int_sqrt_fNext_43$D_IN = - { int_sqrt_fNext_42$D_OUT[464] || - int_sqrt_fNext_42$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_42$D_OUT[464] ? - int_sqrt_fNext_42$D_OUT[463:348] : - ((int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_42$D_OUT[231:116] : - int_sqrt_fNext_42$D_OUT[463:348]), - int_sqrt_fNext_42$D_OUT[464] ? - int_sqrt_fNext_42$D_OUT[347:0] : - { _theResult___snd_fst__h42501, - (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_42$D_OUT[231:0] : - { _theResult___snd_snd__h42577, b__h42574 } } } ; - assign int_sqrt_fNext_43$ENQ = CAN_FIRE_RL_int_sqrt_work_43 ; - assign int_sqrt_fNext_43$DEQ = CAN_FIRE_RL_int_sqrt_work_44 ; - assign int_sqrt_fNext_43$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_44 - assign int_sqrt_fNext_44$D_IN = - { int_sqrt_fNext_43$D_OUT[464] || - int_sqrt_fNext_43$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_43$D_OUT[464] ? - int_sqrt_fNext_43$D_OUT[463:348] : - ((int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_43$D_OUT[231:116] : - int_sqrt_fNext_43$D_OUT[463:348]), - int_sqrt_fNext_43$D_OUT[464] ? - int_sqrt_fNext_43$D_OUT[347:0] : - { _theResult___snd_fst__h42901, - (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_43$D_OUT[231:0] : - { _theResult___snd_snd__h42977, b__h42974 } } } ; - assign int_sqrt_fNext_44$ENQ = CAN_FIRE_RL_int_sqrt_work_44 ; - assign int_sqrt_fNext_44$DEQ = CAN_FIRE_RL_int_sqrt_work_45 ; - assign int_sqrt_fNext_44$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_45 - assign int_sqrt_fNext_45$D_IN = - { int_sqrt_fNext_44$D_OUT[464] || - int_sqrt_fNext_44$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_44$D_OUT[464] ? - int_sqrt_fNext_44$D_OUT[463:348] : - ((int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_44$D_OUT[231:116] : - int_sqrt_fNext_44$D_OUT[463:348]), - int_sqrt_fNext_44$D_OUT[464] ? - int_sqrt_fNext_44$D_OUT[347:0] : - { _theResult___snd_fst__h43301, - (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_44$D_OUT[231:0] : - { _theResult___snd_snd__h43377, b__h43374 } } } ; - assign int_sqrt_fNext_45$ENQ = CAN_FIRE_RL_int_sqrt_work_45 ; - assign int_sqrt_fNext_45$DEQ = CAN_FIRE_RL_int_sqrt_work_46 ; - assign int_sqrt_fNext_45$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_46 - assign int_sqrt_fNext_46$D_IN = - { int_sqrt_fNext_45$D_OUT[464] || - int_sqrt_fNext_45$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_45$D_OUT[464] ? - int_sqrt_fNext_45$D_OUT[463:348] : - ((int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_45$D_OUT[231:116] : - int_sqrt_fNext_45$D_OUT[463:348]), - int_sqrt_fNext_45$D_OUT[464] ? - int_sqrt_fNext_45$D_OUT[347:0] : - { _theResult___snd_fst__h43701, - (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_45$D_OUT[231:0] : - { _theResult___snd_snd__h43777, b__h43774 } } } ; - assign int_sqrt_fNext_46$ENQ = CAN_FIRE_RL_int_sqrt_work_46 ; - assign int_sqrt_fNext_46$DEQ = CAN_FIRE_RL_int_sqrt_work_47 ; - assign int_sqrt_fNext_46$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_47 - assign int_sqrt_fNext_47$D_IN = - { int_sqrt_fNext_46$D_OUT[464] || - int_sqrt_fNext_46$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_46$D_OUT[464] ? - int_sqrt_fNext_46$D_OUT[463:348] : - ((int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_46$D_OUT[231:116] : - int_sqrt_fNext_46$D_OUT[463:348]), - int_sqrt_fNext_46$D_OUT[464] ? - int_sqrt_fNext_46$D_OUT[347:0] : - { _theResult___snd_fst__h44101, - (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_46$D_OUT[231:0] : - { _theResult___snd_snd__h44177, b__h44174 } } } ; - assign int_sqrt_fNext_47$ENQ = CAN_FIRE_RL_int_sqrt_work_47 ; - assign int_sqrt_fNext_47$DEQ = CAN_FIRE_RL_int_sqrt_work_48 ; - assign int_sqrt_fNext_47$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_48 - assign int_sqrt_fNext_48$D_IN = - { int_sqrt_fNext_47$D_OUT[464] || - int_sqrt_fNext_47$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_47$D_OUT[464] ? - int_sqrt_fNext_47$D_OUT[463:348] : - ((int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_47$D_OUT[231:116] : - int_sqrt_fNext_47$D_OUT[463:348]), - int_sqrt_fNext_47$D_OUT[464] ? - int_sqrt_fNext_47$D_OUT[347:0] : - { _theResult___snd_fst__h44501, - (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_47$D_OUT[231:0] : - { _theResult___snd_snd__h44577, b__h44574 } } } ; - assign int_sqrt_fNext_48$ENQ = CAN_FIRE_RL_int_sqrt_work_48 ; - assign int_sqrt_fNext_48$DEQ = CAN_FIRE_RL_int_sqrt_work_49 ; - assign int_sqrt_fNext_48$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_49 - assign int_sqrt_fNext_49$D_IN = - { int_sqrt_fNext_48$D_OUT[464] || - int_sqrt_fNext_48$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_48$D_OUT[464] ? - int_sqrt_fNext_48$D_OUT[463:348] : - ((int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_48$D_OUT[231:116] : - int_sqrt_fNext_48$D_OUT[463:348]), - int_sqrt_fNext_48$D_OUT[464] ? - int_sqrt_fNext_48$D_OUT[347:0] : - { _theResult___snd_fst__h44901, - (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_48$D_OUT[231:0] : - { _theResult___snd_snd__h44977, b__h44974 } } } ; - assign int_sqrt_fNext_49$ENQ = CAN_FIRE_RL_int_sqrt_work_49 ; - assign int_sqrt_fNext_49$DEQ = CAN_FIRE_RL_int_sqrt_work_50 ; - assign int_sqrt_fNext_49$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_5 - assign int_sqrt_fNext_5$D_IN = - { int_sqrt_fNext_4$D_OUT[464] || - int_sqrt_fNext_4$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_4$D_OUT[464] ? - int_sqrt_fNext_4$D_OUT[463:348] : - ((int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_4$D_OUT[231:116] : - int_sqrt_fNext_4$D_OUT[463:348]), - int_sqrt_fNext_4$D_OUT[464] ? - int_sqrt_fNext_4$D_OUT[347:0] : - { _theResult___snd_fst__h27301, - (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_4$D_OUT[231:0] : - { _theResult___snd_snd__h27377, b__h27374 } } } ; - assign int_sqrt_fNext_5$ENQ = CAN_FIRE_RL_int_sqrt_work_5 ; - assign int_sqrt_fNext_5$DEQ = CAN_FIRE_RL_int_sqrt_work_6 ; - assign int_sqrt_fNext_5$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_50 - assign int_sqrt_fNext_50$D_IN = - { int_sqrt_fNext_49$D_OUT[464] || - int_sqrt_fNext_49$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_49$D_OUT[464] ? - int_sqrt_fNext_49$D_OUT[463:348] : - ((int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_49$D_OUT[231:116] : - int_sqrt_fNext_49$D_OUT[463:348]), - int_sqrt_fNext_49$D_OUT[464] ? - int_sqrt_fNext_49$D_OUT[347:0] : - { _theResult___snd_fst__h45301, - (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_49$D_OUT[231:0] : - { _theResult___snd_snd__h45377, b__h45374 } } } ; - assign int_sqrt_fNext_50$ENQ = CAN_FIRE_RL_int_sqrt_work_50 ; - assign int_sqrt_fNext_50$DEQ = CAN_FIRE_RL_int_sqrt_work_51 ; - assign int_sqrt_fNext_50$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_51 - assign int_sqrt_fNext_51$D_IN = - { int_sqrt_fNext_50$D_OUT[464] || - int_sqrt_fNext_50$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_50$D_OUT[464] ? - int_sqrt_fNext_50$D_OUT[463:348] : - ((int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_50$D_OUT[231:116] : - int_sqrt_fNext_50$D_OUT[463:348]), - int_sqrt_fNext_50$D_OUT[464] ? - int_sqrt_fNext_50$D_OUT[347:0] : - { _theResult___snd_fst__h45701, - (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_50$D_OUT[231:0] : - { _theResult___snd_snd__h45777, b__h45774 } } } ; - assign int_sqrt_fNext_51$ENQ = CAN_FIRE_RL_int_sqrt_work_51 ; - assign int_sqrt_fNext_51$DEQ = CAN_FIRE_RL_int_sqrt_work_52 ; - assign int_sqrt_fNext_51$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_52 - assign int_sqrt_fNext_52$D_IN = - { int_sqrt_fNext_51$D_OUT[464] || - int_sqrt_fNext_51$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_51$D_OUT[464] ? - int_sqrt_fNext_51$D_OUT[463:348] : - ((int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_51$D_OUT[231:116] : - int_sqrt_fNext_51$D_OUT[463:348]), - int_sqrt_fNext_51$D_OUT[464] ? - int_sqrt_fNext_51$D_OUT[347:0] : - { _theResult___snd_fst__h46101, - (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_51$D_OUT[231:0] : - { _theResult___snd_snd__h46177, b__h46174 } } } ; - assign int_sqrt_fNext_52$ENQ = CAN_FIRE_RL_int_sqrt_work_52 ; - assign int_sqrt_fNext_52$DEQ = CAN_FIRE_RL_int_sqrt_work_53 ; - assign int_sqrt_fNext_52$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_53 - assign int_sqrt_fNext_53$D_IN = - { int_sqrt_fNext_52$D_OUT[464] || - int_sqrt_fNext_52$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_52$D_OUT[464] ? - int_sqrt_fNext_52$D_OUT[463:348] : - ((int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_52$D_OUT[231:116] : - int_sqrt_fNext_52$D_OUT[463:348]), - int_sqrt_fNext_52$D_OUT[464] ? - int_sqrt_fNext_52$D_OUT[347:0] : - { _theResult___snd_fst__h46501, - (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_52$D_OUT[231:0] : - { _theResult___snd_snd__h46577, b__h46574 } } } ; - assign int_sqrt_fNext_53$ENQ = CAN_FIRE_RL_int_sqrt_work_53 ; - assign int_sqrt_fNext_53$DEQ = CAN_FIRE_RL_int_sqrt_work_54 ; - assign int_sqrt_fNext_53$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_54 - assign int_sqrt_fNext_54$D_IN = - { int_sqrt_fNext_53$D_OUT[464] || - int_sqrt_fNext_53$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_53$D_OUT[464] ? - int_sqrt_fNext_53$D_OUT[463:348] : - ((int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_53$D_OUT[231:116] : - int_sqrt_fNext_53$D_OUT[463:348]), - int_sqrt_fNext_53$D_OUT[464] ? - int_sqrt_fNext_53$D_OUT[347:0] : - { _theResult___snd_fst__h46901, - (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_53$D_OUT[231:0] : - { _theResult___snd_snd__h46977, b__h46974 } } } ; - assign int_sqrt_fNext_54$ENQ = CAN_FIRE_RL_int_sqrt_work_54 ; - assign int_sqrt_fNext_54$DEQ = CAN_FIRE_RL_int_sqrt_work_55 ; - assign int_sqrt_fNext_54$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_55 - assign int_sqrt_fNext_55$D_IN = - { int_sqrt_fNext_54$D_OUT[464] || - int_sqrt_fNext_54$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_54$D_OUT[464] ? - int_sqrt_fNext_54$D_OUT[463:348] : - ((int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_54$D_OUT[231:116] : - int_sqrt_fNext_54$D_OUT[463:348]), - int_sqrt_fNext_54$D_OUT[464] ? - int_sqrt_fNext_54$D_OUT[347:0] : - { _theResult___snd_fst__h47301, - (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_54$D_OUT[231:0] : - { _theResult___snd_snd__h47377, b__h47374 } } } ; - assign int_sqrt_fNext_55$ENQ = CAN_FIRE_RL_int_sqrt_work_55 ; - assign int_sqrt_fNext_55$DEQ = CAN_FIRE_RL_int_sqrt_work_56 ; - assign int_sqrt_fNext_55$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_56 - assign int_sqrt_fNext_56$D_IN = - { int_sqrt_fNext_55$D_OUT[464] || - int_sqrt_fNext_55$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_55$D_OUT[464] ? - int_sqrt_fNext_55$D_OUT[463:348] : - ((int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_55$D_OUT[231:116] : - int_sqrt_fNext_55$D_OUT[463:348]), - int_sqrt_fNext_55$D_OUT[464] ? - int_sqrt_fNext_55$D_OUT[347:0] : - { _theResult___snd_fst__h47701, - (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_55$D_OUT[231:0] : - { _theResult___snd_snd__h47777, b__h47774 } } } ; - assign int_sqrt_fNext_56$ENQ = CAN_FIRE_RL_int_sqrt_work_56 ; - assign int_sqrt_fNext_56$DEQ = CAN_FIRE_RL_int_sqrt_work_57 ; - assign int_sqrt_fNext_56$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_57 - assign int_sqrt_fNext_57$D_IN = - { int_sqrt_fNext_56$D_OUT[464] || - int_sqrt_fNext_56$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_56$D_OUT[464] ? - int_sqrt_fNext_56$D_OUT[463:348] : - ((int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_56$D_OUT[231:116] : - int_sqrt_fNext_56$D_OUT[463:348]), - int_sqrt_fNext_56$D_OUT[464] ? - int_sqrt_fNext_56$D_OUT[347:0] : - { _theResult___snd_fst__h48101, - (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_56$D_OUT[231:0] : - { _theResult___snd_snd__h48177, b__h48174 } } } ; - assign int_sqrt_fNext_57$ENQ = CAN_FIRE_RL_int_sqrt_work_57 ; - assign int_sqrt_fNext_57$DEQ = CAN_FIRE_RL_int_sqrt_work_58 ; - assign int_sqrt_fNext_57$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_58 - assign int_sqrt_fNext_58$D_IN = - { int_sqrt_fNext_57$D_OUT[464] || - int_sqrt_fNext_57$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_57$D_OUT[464] ? - int_sqrt_fNext_57$D_OUT[463:348] : - ((int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_57$D_OUT[231:116] : - int_sqrt_fNext_57$D_OUT[463:348]), - int_sqrt_fNext_57$D_OUT[464] ? - int_sqrt_fNext_57$D_OUT[347:0] : - { _theResult___snd_fst__h48501, - (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_57$D_OUT[231:0] : - { _theResult___snd_snd__h48577, b__h48574 } } } ; - assign int_sqrt_fNext_58$ENQ = CAN_FIRE_RL_int_sqrt_work_58 ; - assign int_sqrt_fNext_58$DEQ = CAN_FIRE_RL_int_sqrt_finish ; - assign int_sqrt_fNext_58$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_6 - assign int_sqrt_fNext_6$D_IN = - { int_sqrt_fNext_5$D_OUT[464] || - int_sqrt_fNext_5$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_5$D_OUT[464] ? - int_sqrt_fNext_5$D_OUT[463:348] : - ((int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_5$D_OUT[231:116] : - int_sqrt_fNext_5$D_OUT[463:348]), - int_sqrt_fNext_5$D_OUT[464] ? - int_sqrt_fNext_5$D_OUT[347:0] : - { _theResult___snd_fst__h27701, - (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_5$D_OUT[231:0] : - { _theResult___snd_snd__h27777, b__h27774 } } } ; - assign int_sqrt_fNext_6$ENQ = CAN_FIRE_RL_int_sqrt_work_6 ; - assign int_sqrt_fNext_6$DEQ = CAN_FIRE_RL_int_sqrt_work_7 ; - assign int_sqrt_fNext_6$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_7 - assign int_sqrt_fNext_7$D_IN = - { int_sqrt_fNext_6$D_OUT[464] || - int_sqrt_fNext_6$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_6$D_OUT[464] ? - int_sqrt_fNext_6$D_OUT[463:348] : - ((int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_6$D_OUT[231:116] : - int_sqrt_fNext_6$D_OUT[463:348]), - int_sqrt_fNext_6$D_OUT[464] ? - int_sqrt_fNext_6$D_OUT[347:0] : - { _theResult___snd_fst__h28101, - (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_6$D_OUT[231:0] : - { _theResult___snd_snd__h28177, b__h28174 } } } ; - assign int_sqrt_fNext_7$ENQ = CAN_FIRE_RL_int_sqrt_work_7 ; - assign int_sqrt_fNext_7$DEQ = CAN_FIRE_RL_int_sqrt_work_8 ; - assign int_sqrt_fNext_7$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_8 - assign int_sqrt_fNext_8$D_IN = - { int_sqrt_fNext_7$D_OUT[464] || - int_sqrt_fNext_7$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_7$D_OUT[464] ? - int_sqrt_fNext_7$D_OUT[463:348] : - ((int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_7$D_OUT[231:116] : - int_sqrt_fNext_7$D_OUT[463:348]), - int_sqrt_fNext_7$D_OUT[464] ? - int_sqrt_fNext_7$D_OUT[347:0] : - { _theResult___snd_fst__h28501, - (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_7$D_OUT[231:0] : - { _theResult___snd_snd__h28577, b__h28574 } } } ; - assign int_sqrt_fNext_8$ENQ = CAN_FIRE_RL_int_sqrt_work_8 ; - assign int_sqrt_fNext_8$DEQ = CAN_FIRE_RL_int_sqrt_work_9 ; - assign int_sqrt_fNext_8$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_9 - assign int_sqrt_fNext_9$D_IN = - { int_sqrt_fNext_8$D_OUT[464] || - int_sqrt_fNext_8$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_8$D_OUT[464] ? - int_sqrt_fNext_8$D_OUT[463:348] : - ((int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_8$D_OUT[231:116] : - int_sqrt_fNext_8$D_OUT[463:348]), - int_sqrt_fNext_8$D_OUT[464] ? - int_sqrt_fNext_8$D_OUT[347:0] : - { _theResult___snd_fst__h28901, - (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_8$D_OUT[231:0] : - { _theResult___snd_snd__h28977, b__h28974 } } } ; - assign int_sqrt_fNext_9$ENQ = CAN_FIRE_RL_int_sqrt_work_9 ; - assign int_sqrt_fNext_9$DEQ = CAN_FIRE_RL_int_sqrt_work_10 ; - assign int_sqrt_fNext_9$CLR = 1'b0 ; - - // submodule int_sqrt_fRequest - assign int_sqrt_fRequest$D_IN = { fpu_fState_S1$D_OUT[57:0], 58'd0 } ; - assign int_sqrt_fRequest$ENQ = - WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[194] ; - assign int_sqrt_fRequest$DEQ = CAN_FIRE_RL_int_sqrt_start ; - assign int_sqrt_fRequest$CLR = 1'b0 ; - - // submodule int_sqrt_fResponse - assign int_sqrt_fResponse$D_IN = - { b__h48712, int_sqrt_fNext_58$D_OUT[347:232] != 116'd0 } ; - assign int_sqrt_fResponse$ENQ = CAN_FIRE_RL_int_sqrt_finish ; - assign int_sqrt_fResponse$DEQ = - WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[136] ; - assign int_sqrt_fResponse$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6 = - _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 ? - _theResult___snd__h75342 : - _theResult___snd__h75337 ; - assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 = - sfd__h75932[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h76519, sfd__h75932[52:1] }) : - { IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, - sfd__h75932[51:0] } ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 = - (fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? - (fpu_fOperand_S0$D_OUT[54] ? - 6'd2 : - (fpu_fOperand_S0$D_OUT[53] ? - 6'd3 : - (fpu_fOperand_S0$D_OUT[52] ? - 6'd4 : - (fpu_fOperand_S0$D_OUT[51] ? - 6'd5 : - (fpu_fOperand_S0$D_OUT[50] ? - 6'd6 : - (fpu_fOperand_S0$D_OUT[49] ? - 6'd7 : - (fpu_fOperand_S0$D_OUT[48] ? - 6'd8 : - (fpu_fOperand_S0$D_OUT[47] ? - 6'd9 : - (fpu_fOperand_S0$D_OUT[46] ? - 6'd10 : - (fpu_fOperand_S0$D_OUT[45] ? - 6'd11 : - (fpu_fOperand_S0$D_OUT[44] ? - 6'd12 : - (fpu_fOperand_S0$D_OUT[43] ? - 6'd13 : - (fpu_fOperand_S0$D_OUT[42] ? - 6'd14 : - (fpu_fOperand_S0$D_OUT[41] ? - 6'd15 : - (fpu_fOperand_S0$D_OUT[40] ? - 6'd16 : - (fpu_fOperand_S0$D_OUT[39] ? - 6'd17 : - (fpu_fOperand_S0$D_OUT[38] ? - 6'd18 : - (fpu_fOperand_S0$D_OUT[37] ? - 6'd19 : - (fpu_fOperand_S0$D_OUT[36] ? - 6'd20 : - (fpu_fOperand_S0$D_OUT[35] ? - 6'd21 : - (fpu_fOperand_S0$D_OUT[34] ? - 6'd22 : - (fpu_fOperand_S0$D_OUT[33] ? - 6'd23 : - (fpu_fOperand_S0$D_OUT[32] ? - 6'd24 : - (fpu_fOperand_S0$D_OUT[31] ? - 6'd25 : - (fpu_fOperand_S0$D_OUT[30] ? - 6'd26 : - (fpu_fOperand_S0$D_OUT[29] ? - 6'd27 : - (fpu_fOperand_S0$D_OUT[28] ? - 6'd28 : - (fpu_fOperand_S0$D_OUT[27] ? - 6'd29 : - (fpu_fOperand_S0$D_OUT[26] ? - 6'd30 : - (fpu_fOperand_S0$D_OUT[25] ? - 6'd31 : - (fpu_fOperand_S0$D_OUT[24] ? - 6'd32 : - (fpu_fOperand_S0$D_OUT[23] ? - 6'd33 : - (fpu_fOperand_S0$D_OUT[22] ? - 6'd34 : - (fpu_fOperand_S0$D_OUT[21] ? - 6'd35 : - (fpu_fOperand_S0$D_OUT[20] ? - 6'd36 : - (fpu_fOperand_S0$D_OUT[19] ? - 6'd37 : - (fpu_fOperand_S0$D_OUT[18] ? - 6'd38 : - (fpu_fOperand_S0$D_OUT[17] ? - 6'd39 : - (fpu_fOperand_S0$D_OUT[16] ? - 6'd40 : - (fpu_fOperand_S0$D_OUT[15] ? - 6'd41 : - (fpu_fOperand_S0$D_OUT[14] ? - 6'd42 : - (fpu_fOperand_S0$D_OUT[13] ? - 6'd43 : - (fpu_fOperand_S0$D_OUT[12] ? - 6'd44 : - (fpu_fOperand_S0$D_OUT[11] ? - 6'd45 : - (fpu_fOperand_S0$D_OUT[10] ? - 6'd46 : - (fpu_fOperand_S0$D_OUT[9] ? - 6'd47 : - (fpu_fOperand_S0$D_OUT[8] ? - 6'd48 : - (fpu_fOperand_S0$D_OUT[7] ? - 6'd49 : - (fpu_fOperand_S0$D_OUT[6] ? - 6'd50 : - (fpu_fOperand_S0$D_OUT[5] ? - 6'd51 : - (fpu_fOperand_S0$D_OUT[4] ? - 6'd52 : - (fpu_fOperand_S0$D_OUT[3] ? - 6'd53 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1 ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460 = - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8[10]}}, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 }) - - { 7'd0, - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 } ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 = - (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 && - !fpu_fOperand_S0$D_OUT[66]) ? - { 1'd1, - fpu_fOperand_S0$D_OUT[66:3], - 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - (fpu_fOperand_S0$D_OUT[66] ? - 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - { 70'h155555555555555540, - fpu_fOperand_S0$D_OUT[2:0], - fpu_fOperand_S0$D_OUT[66], - x__h57541[10:0], - fpu_fOperand_S0$D_OUT[54:3], - x__h65683 }) ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 = - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[12:1] ; - assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 = - (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? - 12'd3074 : - { fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5[10], - fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 } ; - assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 = - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 - - 12'd3074 ; - assign IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813 = - fpu_fState_S3$D_OUT[195] ? - fpu_fState_S3$D_OUT[128:126] : - { fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023, - _theResult___fst_exp__h75269 == 11'd0 && - guard__h66951 != 2'd0, - fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023 } ; - assign IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820 = - (fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h75266, sfdin__h75260[58:7] } ; - assign IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 = - (fpu_fState_S3$D_OUT[58] ? - 6'd0 : - (fpu_fState_S3$D_OUT[57] ? - 6'd1 : - (fpu_fState_S3$D_OUT[56] ? - 6'd2 : - (fpu_fState_S3$D_OUT[55] ? - 6'd3 : - (fpu_fState_S3$D_OUT[54] ? - 6'd4 : - (fpu_fState_S3$D_OUT[53] ? - 6'd5 : - (fpu_fState_S3$D_OUT[52] ? - 6'd6 : - (fpu_fState_S3$D_OUT[51] ? - 6'd7 : - (fpu_fState_S3$D_OUT[50] ? - 6'd8 : - (fpu_fState_S3$D_OUT[49] ? - 6'd9 : - (fpu_fState_S3$D_OUT[48] ? - 6'd10 : - (fpu_fState_S3$D_OUT[47] ? - 6'd11 : - (fpu_fState_S3$D_OUT[46] ? - 6'd12 : - (fpu_fState_S3$D_OUT[45] ? - 6'd13 : - (fpu_fState_S3$D_OUT[44] ? - 6'd14 : - (fpu_fState_S3$D_OUT[43] ? - 6'd15 : - (fpu_fState_S3$D_OUT[42] ? - 6'd16 : - (fpu_fState_S3$D_OUT[41] ? - 6'd17 : - (fpu_fState_S3$D_OUT[40] ? - 6'd18 : - (fpu_fState_S3$D_OUT[39] ? - 6'd19 : - (fpu_fState_S3$D_OUT[38] ? - 6'd20 : - (fpu_fState_S3$D_OUT[37] ? - 6'd21 : - (fpu_fState_S3$D_OUT[36] ? - 6'd22 : - (fpu_fState_S3$D_OUT[35] ? - 6'd23 : - (fpu_fState_S3$D_OUT[34] ? - 6'd24 : - (fpu_fState_S3$D_OUT[33] ? - 6'd25 : - (fpu_fState_S3$D_OUT[32] ? - 6'd26 : - (fpu_fState_S3$D_OUT[31] ? - 6'd27 : - (fpu_fState_S3$D_OUT[30] ? - 6'd28 : - (fpu_fState_S3$D_OUT[29] ? - 6'd29 : - (fpu_fState_S3$D_OUT[28] ? - 6'd30 : - (fpu_fState_S3$D_OUT[27] ? - 6'd31 : - (fpu_fState_S3$D_OUT[26] ? - 6'd32 : - (fpu_fState_S3$D_OUT[25] ? - 6'd33 : - (fpu_fState_S3$D_OUT[24] ? - 6'd34 : - (fpu_fState_S3$D_OUT[23] ? - 6'd35 : - (fpu_fState_S3$D_OUT[22] ? - 6'd36 : - (fpu_fState_S3$D_OUT[21] ? - 6'd37 : - (fpu_fState_S3$D_OUT[20] ? - 6'd38 : - (fpu_fState_S3$D_OUT[19] ? - 6'd39 : - (fpu_fState_S3$D_OUT[18] ? - 6'd40 : - (fpu_fState_S3$D_OUT[17] ? - 6'd41 : - (fpu_fState_S3$D_OUT[16] ? - 6'd42 : - (fpu_fState_S3$D_OUT[15] ? - 6'd43 : - (fpu_fState_S3$D_OUT[14] ? - 6'd44 : - (fpu_fState_S3$D_OUT[13] ? - 6'd45 : - (fpu_fState_S3$D_OUT[12] ? - 6'd46 : - (fpu_fState_S3$D_OUT[11] ? - 6'd47 : - (fpu_fState_S3$D_OUT[10] ? - 6'd48 : - (fpu_fState_S3$D_OUT[9] ? - 6'd49 : - (fpu_fState_S3$D_OUT[8] ? - 6'd50 : - (fpu_fState_S3$D_OUT[7] ? - 6'd51 : - (fpu_fState_S3$D_OUT[6] ? - 6'd52 : - (fpu_fState_S3$D_OUT[5] ? - 6'd53 : - (fpu_fState_S3$D_OUT[4] ? - 6'd54 : - (fpu_fState_S3$D_OUT[3] ? - 6'd55 : - (fpu_fState_S3$D_OUT[2] ? - 6'd56 : - (fpu_fState_S3$D_OUT[1] ? - 6'd57 : - (fpu_fState_S3$D_OUT[0] ? - 6'd58 : - 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 = - (fpu_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h75932[53:52] == 2'b01) ? - 11'd1 : - fpu_fState_S4$D_OUT[64:54] ; - assign IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 = - (int_sqrt_fRequest$D_OUT[115] ? - 7'd0 : - (int_sqrt_fRequest$D_OUT[114] ? - 7'd1 : - (int_sqrt_fRequest$D_OUT[113] ? - 7'd2 : - (int_sqrt_fRequest$D_OUT[112] ? - 7'd3 : - (int_sqrt_fRequest$D_OUT[111] ? - 7'd4 : - (int_sqrt_fRequest$D_OUT[110] ? - 7'd5 : - (int_sqrt_fRequest$D_OUT[109] ? - 7'd6 : - (int_sqrt_fRequest$D_OUT[108] ? - 7'd7 : - (int_sqrt_fRequest$D_OUT[107] ? - 7'd8 : - (int_sqrt_fRequest$D_OUT[106] ? - 7'd9 : - (int_sqrt_fRequest$D_OUT[105] ? - 7'd10 : - (int_sqrt_fRequest$D_OUT[104] ? - 7'd11 : - (int_sqrt_fRequest$D_OUT[103] ? - 7'd12 : - (int_sqrt_fRequest$D_OUT[102] ? - 7'd13 : - (int_sqrt_fRequest$D_OUT[101] ? - 7'd14 : - (int_sqrt_fRequest$D_OUT[100] ? - 7'd15 : - (int_sqrt_fRequest$D_OUT[99] ? - 7'd16 : - (int_sqrt_fRequest$D_OUT[98] ? - 7'd17 : - (int_sqrt_fRequest$D_OUT[97] ? - 7'd18 : - (int_sqrt_fRequest$D_OUT[96] ? - 7'd19 : - (int_sqrt_fRequest$D_OUT[95] ? - 7'd20 : - (int_sqrt_fRequest$D_OUT[94] ? - 7'd21 : - (int_sqrt_fRequest$D_OUT[93] ? - 7'd22 : - (int_sqrt_fRequest$D_OUT[92] ? - 7'd23 : - (int_sqrt_fRequest$D_OUT[91] ? - 7'd24 : - (int_sqrt_fRequest$D_OUT[90] ? - 7'd25 : - (int_sqrt_fRequest$D_OUT[89] ? - 7'd26 : - (int_sqrt_fRequest$D_OUT[88] ? - 7'd27 : - (int_sqrt_fRequest$D_OUT[87] ? - 7'd28 : - (int_sqrt_fRequest$D_OUT[86] ? - 7'd29 : - (int_sqrt_fRequest$D_OUT[85] ? - 7'd30 : - (int_sqrt_fRequest$D_OUT[84] ? - 7'd31 : - (int_sqrt_fRequest$D_OUT[83] ? - 7'd32 : - (int_sqrt_fRequest$D_OUT[82] ? - 7'd33 : - (int_sqrt_fRequest$D_OUT[81] ? - 7'd34 : - (int_sqrt_fRequest$D_OUT[80] ? - 7'd35 : - (int_sqrt_fRequest$D_OUT[79] ? - 7'd36 : - (int_sqrt_fRequest$D_OUT[78] ? - 7'd37 : - (int_sqrt_fRequest$D_OUT[77] ? - 7'd38 : - (int_sqrt_fRequest$D_OUT[76] ? - 7'd39 : - (int_sqrt_fRequest$D_OUT[75] ? - 7'd40 : - (int_sqrt_fRequest$D_OUT[74] ? - 7'd41 : - (int_sqrt_fRequest$D_OUT[73] ? - 7'd42 : - (int_sqrt_fRequest$D_OUT[72] ? - 7'd43 : - (int_sqrt_fRequest$D_OUT[71] ? - 7'd44 : - (int_sqrt_fRequest$D_OUT[70] ? - 7'd45 : - (int_sqrt_fRequest$D_OUT[69] ? - 7'd46 : - (int_sqrt_fRequest$D_OUT[68] ? - 7'd47 : - (int_sqrt_fRequest$D_OUT[67] ? - 7'd48 : - (int_sqrt_fRequest$D_OUT[66] ? - 7'd49 : - (int_sqrt_fRequest$D_OUT[65] ? - 7'd50 : - (int_sqrt_fRequest$D_OUT[64] ? - 7'd51 : - (int_sqrt_fRequest$D_OUT[63] ? - 7'd52 : - (int_sqrt_fRequest$D_OUT[62] ? - 7'd53 : - (int_sqrt_fRequest$D_OUT[61] ? - 7'd54 : - (int_sqrt_fRequest$D_OUT[60] ? - 7'd55 : - (int_sqrt_fRequest$D_OUT[59] ? - 7'd56 : - (int_sqrt_fRequest$D_OUT[58] ? - 7'd57 : - (int_sqrt_fRequest$D_OUT[57] ? - 7'd58 : - (int_sqrt_fRequest$D_OUT[56] ? - 7'd59 : - (int_sqrt_fRequest$D_OUT[55] ? - 7'd60 : - (int_sqrt_fRequest$D_OUT[54] ? - 7'd61 : - (int_sqrt_fRequest$D_OUT[53] ? - 7'd62 : - (int_sqrt_fRequest$D_OUT[52] ? - 7'd63 : - (int_sqrt_fRequest$D_OUT[51] ? - 7'd64 : - (int_sqrt_fRequest$D_OUT[50] ? - 7'd65 : - (int_sqrt_fRequest$D_OUT[49] ? - 7'd66 : - (int_sqrt_fRequest$D_OUT[48] ? - 7'd67 : - (int_sqrt_fRequest$D_OUT[47] ? - 7'd68 : - (int_sqrt_fRequest$D_OUT[46] ? - 7'd69 : - (int_sqrt_fRequest$D_OUT[45] ? - 7'd70 : - (int_sqrt_fRequest$D_OUT[44] ? - 7'd71 : - (int_sqrt_fRequest$D_OUT[43] ? - 7'd72 : - (int_sqrt_fRequest$D_OUT[42] ? - 7'd73 : - (int_sqrt_fRequest$D_OUT[41] ? - 7'd74 : - (int_sqrt_fRequest$D_OUT[40] ? - 7'd75 : - (int_sqrt_fRequest$D_OUT[39] ? - 7'd76 : - (int_sqrt_fRequest$D_OUT[38] ? - 7'd77 : - (int_sqrt_fRequest$D_OUT[37] ? - 7'd78 : - (int_sqrt_fRequest$D_OUT[36] ? - 7'd79 : - (int_sqrt_fRequest$D_OUT[35] ? - 7'd80 : - (int_sqrt_fRequest$D_OUT[34] ? - 7'd81 : - (int_sqrt_fRequest$D_OUT[33] ? - 7'd82 : - (int_sqrt_fRequest$D_OUT[32] ? - 7'd83 : - (int_sqrt_fRequest$D_OUT[31] ? - 7'd84 : - (int_sqrt_fRequest$D_OUT[30] ? - 7'd85 : - (int_sqrt_fRequest$D_OUT[29] ? - 7'd86 : - (int_sqrt_fRequest$D_OUT[28] ? - 7'd87 : - (int_sqrt_fRequest$D_OUT[27] ? - 7'd88 : - (int_sqrt_fRequest$D_OUT[26] ? - 7'd89 : - (int_sqrt_fRequest$D_OUT[25] ? - 7'd90 : - (int_sqrt_fRequest$D_OUT[24] ? - 7'd91 : - (int_sqrt_fRequest$D_OUT[23] ? - 7'd92 : - (int_sqrt_fRequest$D_OUT[22] ? - 7'd93 : - (int_sqrt_fRequest$D_OUT[21] ? - 7'd94 : - (int_sqrt_fRequest$D_OUT[20] ? - 7'd95 : - (int_sqrt_fRequest$D_OUT[19] ? - 7'd96 : - (int_sqrt_fRequest$D_OUT[18] ? - 7'd97 : - (int_sqrt_fRequest$D_OUT[17] ? - 7'd98 : - (int_sqrt_fRequest$D_OUT[16] ? - 7'd99 : - (int_sqrt_fRequest$D_OUT[15] ? - 7'd100 : - (int_sqrt_fRequest$D_OUT[14] ? - 7'd101 : - (int_sqrt_fRequest$D_OUT[13] ? - 7'd102 : - (int_sqrt_fRequest$D_OUT[12] ? - 7'd103 : - (int_sqrt_fRequest$D_OUT[11] ? - 7'd104 : - (int_sqrt_fRequest$D_OUT[10] ? - 7'd105 : - (int_sqrt_fRequest$D_OUT[9] ? - 7'd106 : - (int_sqrt_fRequest$D_OUT[8] ? - 7'd107 : - (int_sqrt_fRequest$D_OUT[7] ? - 7'd108 : - (int_sqrt_fRequest$D_OUT[6] ? - 7'd109 : - (int_sqrt_fRequest$D_OUT[5] ? - 7'd110 : - (int_sqrt_fRequest$D_OUT[4] ? - 7'd111 : - (int_sqrt_fRequest$D_OUT[3] ? - 7'd112 : - (int_sqrt_fRequest$D_OUT[2] ? - 7'd113 : - (int_sqrt_fRequest$D_OUT[1] ? - 7'd114 : - (int_sqrt_fRequest$D_OUT[0] ? - 7'd115 : - 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7 = - sfdin__h75260[6] ? 2'd2 : 2'd0 ; - assign _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 = - ({ 6'd0, - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ^ - 12'h800) <= - (IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ^ - 12'h800) ; - assign _theResult___exp__h76428 = - sfd__h75932[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h76519) : - IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 ; - assign _theResult___fst_exp__h75266 = - fpu_fState_S3$D_OUT[58] ? - _theResult___fst_exp__h75289 : - _theResult___fst_exp__h75353 ; - assign _theResult___fst_exp__h75269 = - (fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h75266 ; - assign _theResult___fst_exp__h75289 = - (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd2 : - fpu_fState_S3$D_OUT[121:111] + 11'd1 ; - assign _theResult___fst_exp__h75305 = - (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd1 : - fpu_fState_S3$D_OUT[121:111] ; - assign _theResult___fst_exp__h75344 = - fpu_fState_S3$D_OUT[121:111] - - { 5'd0, - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ; - assign _theResult___fst_exp__h75350 = - (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && - !fpu_fState_S3$D_OUT[56] && - !fpu_fState_S3$D_OUT[55] && - !fpu_fState_S3$D_OUT[54] && - !fpu_fState_S3$D_OUT[53] && - !fpu_fState_S3$D_OUT[52] && - !fpu_fState_S3$D_OUT[51] && - !fpu_fState_S3$D_OUT[50] && - !fpu_fState_S3$D_OUT[49] && - !fpu_fState_S3$D_OUT[48] && - !fpu_fState_S3$D_OUT[47] && - !fpu_fState_S3$D_OUT[46] && - !fpu_fState_S3$D_OUT[45] && - !fpu_fState_S3$D_OUT[44] && - !fpu_fState_S3$D_OUT[43] && - !fpu_fState_S3$D_OUT[42] && - !fpu_fState_S3$D_OUT[41] && - !fpu_fState_S3$D_OUT[40] && - !fpu_fState_S3$D_OUT[39] && - !fpu_fState_S3$D_OUT[38] && - !fpu_fState_S3$D_OUT[37] && - !fpu_fState_S3$D_OUT[36] && - !fpu_fState_S3$D_OUT[35] && - !fpu_fState_S3$D_OUT[34] && - !fpu_fState_S3$D_OUT[33] && - !fpu_fState_S3$D_OUT[32] && - !fpu_fState_S3$D_OUT[31] && - !fpu_fState_S3$D_OUT[30] && - !fpu_fState_S3$D_OUT[29] && - !fpu_fState_S3$D_OUT[28] && - !fpu_fState_S3$D_OUT[27] && - !fpu_fState_S3$D_OUT[26] && - !fpu_fState_S3$D_OUT[25] && - !fpu_fState_S3$D_OUT[24] && - !fpu_fState_S3$D_OUT[23] && - !fpu_fState_S3$D_OUT[22] && - !fpu_fState_S3$D_OUT[21] && - !fpu_fState_S3$D_OUT[20] && - !fpu_fState_S3$D_OUT[19] && - !fpu_fState_S3$D_OUT[18] && - !fpu_fState_S3$D_OUT[17] && - !fpu_fState_S3$D_OUT[16] && - !fpu_fState_S3$D_OUT[15] && - !fpu_fState_S3$D_OUT[14] && - !fpu_fState_S3$D_OUT[13] && - !fpu_fState_S3$D_OUT[12] && - !fpu_fState_S3$D_OUT[11] && - !fpu_fState_S3$D_OUT[10] && - !fpu_fState_S3$D_OUT[9] && - !fpu_fState_S3$D_OUT[8] && - !fpu_fState_S3$D_OUT[7] && - !fpu_fState_S3$D_OUT[6] && - !fpu_fState_S3$D_OUT[5] && - !fpu_fState_S3$D_OUT[4] && - !fpu_fState_S3$D_OUT[3] && - !fpu_fState_S3$D_OUT[2] && - !fpu_fState_S3$D_OUT[1] && - !fpu_fState_S3$D_OUT[0] || - !_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775) ? - 11'd0 : - _theResult___fst_exp__h75344 ; - assign _theResult___fst_exp__h75353 = - (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? - _theResult___fst_exp__h75305 : - _theResult___fst_exp__h75350 ; - assign _theResult___fst_exp__h76509 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h76506 ; - assign _theResult___fst_sfd__h76510 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h76507 ; - assign _theResult___sfd__h76429 = - sfd__h75932[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h75932[52:1]) : - sfd__h75932[51:0] ; - assign _theResult___snd__h75283 = { fpu_fState_S3$D_OUT[57:0], 1'd0 } ; - assign _theResult___snd__h75298 = - (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? - _theResult___snd__h75300 : - _theResult___snd__h75313 ; - assign _theResult___snd__h75300 = { fpu_fState_S3$D_OUT[56:0], 2'd0 } ; - assign _theResult___snd__h75313 = - (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && - !fpu_fState_S3$D_OUT[56] && - !fpu_fState_S3$D_OUT[55] && - !fpu_fState_S3$D_OUT[54] && - !fpu_fState_S3$D_OUT[53] && - !fpu_fState_S3$D_OUT[52] && - !fpu_fState_S3$D_OUT[51] && - !fpu_fState_S3$D_OUT[50] && - !fpu_fState_S3$D_OUT[49] && - !fpu_fState_S3$D_OUT[48] && - !fpu_fState_S3$D_OUT[47] && - !fpu_fState_S3$D_OUT[46] && - !fpu_fState_S3$D_OUT[45] && - !fpu_fState_S3$D_OUT[44] && - !fpu_fState_S3$D_OUT[43] && - !fpu_fState_S3$D_OUT[42] && - !fpu_fState_S3$D_OUT[41] && - !fpu_fState_S3$D_OUT[40] && - !fpu_fState_S3$D_OUT[39] && - !fpu_fState_S3$D_OUT[38] && - !fpu_fState_S3$D_OUT[37] && - !fpu_fState_S3$D_OUT[36] && - !fpu_fState_S3$D_OUT[35] && - !fpu_fState_S3$D_OUT[34] && - !fpu_fState_S3$D_OUT[33] && - !fpu_fState_S3$D_OUT[32] && - !fpu_fState_S3$D_OUT[31] && - !fpu_fState_S3$D_OUT[30] && - !fpu_fState_S3$D_OUT[29] && - !fpu_fState_S3$D_OUT[28] && - !fpu_fState_S3$D_OUT[27] && - !fpu_fState_S3$D_OUT[26] && - !fpu_fState_S3$D_OUT[25] && - !fpu_fState_S3$D_OUT[24] && - !fpu_fState_S3$D_OUT[23] && - !fpu_fState_S3$D_OUT[22] && - !fpu_fState_S3$D_OUT[21] && - !fpu_fState_S3$D_OUT[20] && - !fpu_fState_S3$D_OUT[19] && - !fpu_fState_S3$D_OUT[18] && - !fpu_fState_S3$D_OUT[17] && - !fpu_fState_S3$D_OUT[16] && - !fpu_fState_S3$D_OUT[15] && - !fpu_fState_S3$D_OUT[14] && - !fpu_fState_S3$D_OUT[13] && - !fpu_fState_S3$D_OUT[12] && - !fpu_fState_S3$D_OUT[11] && - !fpu_fState_S3$D_OUT[10] && - !fpu_fState_S3$D_OUT[9] && - !fpu_fState_S3$D_OUT[8] && - !fpu_fState_S3$D_OUT[7] && - !fpu_fState_S3$D_OUT[6] && - !fpu_fState_S3$D_OUT[5] && - !fpu_fState_S3$D_OUT[4] && - !fpu_fState_S3$D_OUT[3] && - !fpu_fState_S3$D_OUT[2] && - !fpu_fState_S3$D_OUT[1] && - !fpu_fState_S3$D_OUT[0]) ? - fpu_fState_S3$D_OUT[58:0] : - _theResult___snd__h75319 ; - assign _theResult___snd__h75319 = - { IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6[56:0], - 2'd0 } ; - assign _theResult___snd__h75337 = - fpu_fState_S3$D_OUT[58:0] << - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ; - assign _theResult___snd__h75342 = - fpu_fState_S3$D_OUT[58:0] << - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 ; - assign _theResult___snd_fst__h25299 = - (int_sqrt_fFirst$D_OUT[115:0] == 116'd0 || - int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264) ? - int_sqrt_fFirst$D_OUT[347:232] : - s__h25385 ; - assign _theResult___snd_fst__h25701 = - (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299) ? - int_sqrt_fNext_0$D_OUT[347:232] : - s__h25785 ; - assign _theResult___snd_fst__h26101 = - (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334) ? - int_sqrt_fNext_1$D_OUT[347:232] : - s__h26185 ; - assign _theResult___snd_fst__h26501 = - (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369) ? - int_sqrt_fNext_2$D_OUT[347:232] : - s__h26585 ; - assign _theResult___snd_fst__h26901 = - (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404) ? - int_sqrt_fNext_3$D_OUT[347:232] : - s__h26985 ; - assign _theResult___snd_fst__h27301 = - (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439) ? - int_sqrt_fNext_4$D_OUT[347:232] : - s__h27385 ; - assign _theResult___snd_fst__h27701 = - (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474) ? - int_sqrt_fNext_5$D_OUT[347:232] : - s__h27785 ; - assign _theResult___snd_fst__h28101 = - (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509) ? - int_sqrt_fNext_6$D_OUT[347:232] : - s__h28185 ; - assign _theResult___snd_fst__h28501 = - (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544) ? - int_sqrt_fNext_7$D_OUT[347:232] : - s__h28585 ; - assign _theResult___snd_fst__h28901 = - (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579) ? - int_sqrt_fNext_8$D_OUT[347:232] : - s__h28985 ; - assign _theResult___snd_fst__h29301 = - (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614) ? - int_sqrt_fNext_9$D_OUT[347:232] : - s__h29385 ; - assign _theResult___snd_fst__h29701 = - (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649) ? - int_sqrt_fNext_10$D_OUT[347:232] : - s__h29785 ; - assign _theResult___snd_fst__h30101 = - (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684) ? - int_sqrt_fNext_11$D_OUT[347:232] : - s__h30185 ; - assign _theResult___snd_fst__h30501 = - (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719) ? - int_sqrt_fNext_12$D_OUT[347:232] : - s__h30585 ; - assign _theResult___snd_fst__h30901 = - (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754) ? - int_sqrt_fNext_13$D_OUT[347:232] : - s__h30985 ; - assign _theResult___snd_fst__h31301 = - (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789) ? - int_sqrt_fNext_14$D_OUT[347:232] : - s__h31385 ; - assign _theResult___snd_fst__h31701 = - (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824) ? - int_sqrt_fNext_15$D_OUT[347:232] : - s__h31785 ; - assign _theResult___snd_fst__h32101 = - (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859) ? - int_sqrt_fNext_16$D_OUT[347:232] : - s__h32185 ; - assign _theResult___snd_fst__h32501 = - (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894) ? - int_sqrt_fNext_17$D_OUT[347:232] : - s__h32585 ; - assign _theResult___snd_fst__h32901 = - (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929) ? - int_sqrt_fNext_18$D_OUT[347:232] : - s__h32985 ; - assign _theResult___snd_fst__h33301 = - (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964) ? - int_sqrt_fNext_19$D_OUT[347:232] : - s__h33385 ; - assign _theResult___snd_fst__h33701 = - (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999) ? - int_sqrt_fNext_20$D_OUT[347:232] : - s__h33785 ; - assign _theResult___snd_fst__h34101 = - (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034) ? - int_sqrt_fNext_21$D_OUT[347:232] : - s__h34185 ; - assign _theResult___snd_fst__h34501 = - (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069) ? - int_sqrt_fNext_22$D_OUT[347:232] : - s__h34585 ; - assign _theResult___snd_fst__h34901 = - (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104) ? - int_sqrt_fNext_23$D_OUT[347:232] : - s__h34985 ; - assign _theResult___snd_fst__h35301 = - (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139) ? - int_sqrt_fNext_24$D_OUT[347:232] : - s__h35385 ; - assign _theResult___snd_fst__h35701 = - (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174) ? - int_sqrt_fNext_25$D_OUT[347:232] : - s__h35785 ; - assign _theResult___snd_fst__h36101 = - (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209) ? - int_sqrt_fNext_26$D_OUT[347:232] : - s__h36185 ; - assign _theResult___snd_fst__h36501 = - (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244) ? - int_sqrt_fNext_27$D_OUT[347:232] : - s__h36585 ; - assign _theResult___snd_fst__h36901 = - (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279) ? - int_sqrt_fNext_28$D_OUT[347:232] : - s__h36985 ; - assign _theResult___snd_fst__h37301 = - (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314) ? - int_sqrt_fNext_29$D_OUT[347:232] : - s__h37385 ; - assign _theResult___snd_fst__h37701 = - (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349) ? - int_sqrt_fNext_30$D_OUT[347:232] : - s__h37785 ; - assign _theResult___snd_fst__h38101 = - (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384) ? - int_sqrt_fNext_31$D_OUT[347:232] : - s__h38185 ; - assign _theResult___snd_fst__h38501 = - (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419) ? - int_sqrt_fNext_32$D_OUT[347:232] : - s__h38585 ; - assign _theResult___snd_fst__h38901 = - (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454) ? - int_sqrt_fNext_33$D_OUT[347:232] : - s__h38985 ; - assign _theResult___snd_fst__h39301 = - (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489) ? - int_sqrt_fNext_34$D_OUT[347:232] : - s__h39385 ; - assign _theResult___snd_fst__h39701 = - (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524) ? - int_sqrt_fNext_35$D_OUT[347:232] : - s__h39785 ; - assign _theResult___snd_fst__h40101 = - (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559) ? - int_sqrt_fNext_36$D_OUT[347:232] : - s__h40185 ; - assign _theResult___snd_fst__h40501 = - (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594) ? - int_sqrt_fNext_37$D_OUT[347:232] : - s__h40585 ; - assign _theResult___snd_fst__h40901 = - (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629) ? - int_sqrt_fNext_38$D_OUT[347:232] : - s__h40985 ; - assign _theResult___snd_fst__h41301 = - (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664) ? - int_sqrt_fNext_39$D_OUT[347:232] : - s__h41385 ; - assign _theResult___snd_fst__h41701 = - (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699) ? - int_sqrt_fNext_40$D_OUT[347:232] : - s__h41785 ; - assign _theResult___snd_fst__h42101 = - (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734) ? - int_sqrt_fNext_41$D_OUT[347:232] : - s__h42185 ; - assign _theResult___snd_fst__h42501 = - (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769) ? - int_sqrt_fNext_42$D_OUT[347:232] : - s__h42585 ; - assign _theResult___snd_fst__h42901 = - (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804) ? - int_sqrt_fNext_43$D_OUT[347:232] : - s__h42985 ; - assign _theResult___snd_fst__h43301 = - (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839) ? - int_sqrt_fNext_44$D_OUT[347:232] : - s__h43385 ; - assign _theResult___snd_fst__h43701 = - (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874) ? - int_sqrt_fNext_45$D_OUT[347:232] : - s__h43785 ; - assign _theResult___snd_fst__h44101 = - (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909) ? - int_sqrt_fNext_46$D_OUT[347:232] : - s__h44185 ; - assign _theResult___snd_fst__h44501 = - (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944) ? - int_sqrt_fNext_47$D_OUT[347:232] : - s__h44585 ; - assign _theResult___snd_fst__h44901 = - (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979) ? - int_sqrt_fNext_48$D_OUT[347:232] : - s__h44985 ; - assign _theResult___snd_fst__h45301 = - (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014) ? - int_sqrt_fNext_49$D_OUT[347:232] : - s__h45385 ; - assign _theResult___snd_fst__h45701 = - (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049) ? - int_sqrt_fNext_50$D_OUT[347:232] : - s__h45785 ; - assign _theResult___snd_fst__h46101 = - (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084) ? - int_sqrt_fNext_51$D_OUT[347:232] : - s__h46185 ; - assign _theResult___snd_fst__h46501 = - (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119) ? - int_sqrt_fNext_52$D_OUT[347:232] : - s__h46585 ; - assign _theResult___snd_fst__h46901 = - (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154) ? - int_sqrt_fNext_53$D_OUT[347:232] : - s__h46985 ; - assign _theResult___snd_fst__h47301 = - (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189) ? - int_sqrt_fNext_54$D_OUT[347:232] : - s__h47385 ; - assign _theResult___snd_fst__h47701 = - (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224) ? - int_sqrt_fNext_55$D_OUT[347:232] : - s__h47785 ; - assign _theResult___snd_fst__h48101 = - (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259) ? - int_sqrt_fNext_56$D_OUT[347:232] : - s__h48185 ; - assign _theResult___snd_fst__h48501 = - (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294) ? - int_sqrt_fNext_57$D_OUT[347:232] : - s__h48585 ; - assign _theResult___snd_fst__h75372 = - { IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7[1], - { sfdin__h75260[5:0], 52'd0 } != 58'd0 } ; - assign _theResult___snd_snd__h25377 = - int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 ? - r__h25394 : - r__h25386 ; - assign _theResult___snd_snd__h25777 = - int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 ? - r__h25794 : - r__h25786 ; - assign _theResult___snd_snd__h26177 = - int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 ? - r__h26194 : - r__h26186 ; - assign _theResult___snd_snd__h26577 = - int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 ? - r__h26594 : - r__h26586 ; - assign _theResult___snd_snd__h26977 = - int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 ? - r__h26994 : - r__h26986 ; - assign _theResult___snd_snd__h27377 = - int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 ? - r__h27394 : - r__h27386 ; - assign _theResult___snd_snd__h27777 = - int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 ? - r__h27794 : - r__h27786 ; - assign _theResult___snd_snd__h28177 = - int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 ? - r__h28194 : - r__h28186 ; - assign _theResult___snd_snd__h28577 = - int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 ? - r__h28594 : - r__h28586 ; - assign _theResult___snd_snd__h28977 = - int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 ? - r__h28994 : - r__h28986 ; - assign _theResult___snd_snd__h29377 = - int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 ? - r__h29394 : - r__h29386 ; - assign _theResult___snd_snd__h29777 = - int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 ? - r__h29794 : - r__h29786 ; - assign _theResult___snd_snd__h30177 = - int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 ? - r__h30194 : - r__h30186 ; - assign _theResult___snd_snd__h30577 = - int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 ? - r__h30594 : - r__h30586 ; - assign _theResult___snd_snd__h30977 = - int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 ? - r__h30994 : - r__h30986 ; - assign _theResult___snd_snd__h31377 = - int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 ? - r__h31394 : - r__h31386 ; - assign _theResult___snd_snd__h31777 = - int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 ? - r__h31794 : - r__h31786 ; - assign _theResult___snd_snd__h32177 = - int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 ? - r__h32194 : - r__h32186 ; - assign _theResult___snd_snd__h32577 = - int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 ? - r__h32594 : - r__h32586 ; - assign _theResult___snd_snd__h32977 = - int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 ? - r__h32994 : - r__h32986 ; - assign _theResult___snd_snd__h33377 = - int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 ? - r__h33394 : - r__h33386 ; - assign _theResult___snd_snd__h33777 = - int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 ? - r__h33794 : - r__h33786 ; - assign _theResult___snd_snd__h34177 = - int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 ? - r__h34194 : - r__h34186 ; - assign _theResult___snd_snd__h34577 = - int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 ? - r__h34594 : - r__h34586 ; - assign _theResult___snd_snd__h34977 = - int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 ? - r__h34994 : - r__h34986 ; - assign _theResult___snd_snd__h35377 = - int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 ? - r__h35394 : - r__h35386 ; - assign _theResult___snd_snd__h35777 = - int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 ? - r__h35794 : - r__h35786 ; - assign _theResult___snd_snd__h36177 = - int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 ? - r__h36194 : - r__h36186 ; - assign _theResult___snd_snd__h36577 = - int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 ? - r__h36594 : - r__h36586 ; - assign _theResult___snd_snd__h36977 = - int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 ? - r__h36994 : - r__h36986 ; - assign _theResult___snd_snd__h37377 = - int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 ? - r__h37394 : - r__h37386 ; - assign _theResult___snd_snd__h37777 = - int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 ? - r__h37794 : - r__h37786 ; - assign _theResult___snd_snd__h38177 = - int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 ? - r__h38194 : - r__h38186 ; - assign _theResult___snd_snd__h38577 = - int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 ? - r__h38594 : - r__h38586 ; - assign _theResult___snd_snd__h38977 = - int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 ? - r__h38994 : - r__h38986 ; - assign _theResult___snd_snd__h39377 = - int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 ? - r__h39394 : - r__h39386 ; - assign _theResult___snd_snd__h39777 = - int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 ? - r__h39794 : - r__h39786 ; - assign _theResult___snd_snd__h40177 = - int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 ? - r__h40194 : - r__h40186 ; - assign _theResult___snd_snd__h40577 = - int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 ? - r__h40594 : - r__h40586 ; - assign _theResult___snd_snd__h40977 = - int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 ? - r__h40994 : - r__h40986 ; - assign _theResult___snd_snd__h41377 = - int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 ? - r__h41394 : - r__h41386 ; - assign _theResult___snd_snd__h41777 = - int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 ? - r__h41794 : - r__h41786 ; - assign _theResult___snd_snd__h42177 = - int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 ? - r__h42194 : - r__h42186 ; - assign _theResult___snd_snd__h42577 = - int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 ? - r__h42594 : - r__h42586 ; - assign _theResult___snd_snd__h42977 = - int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 ? - r__h42994 : - r__h42986 ; - assign _theResult___snd_snd__h43377 = - int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 ? - r__h43394 : - r__h43386 ; - assign _theResult___snd_snd__h43777 = - int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 ? - r__h43794 : - r__h43786 ; - assign _theResult___snd_snd__h44177 = - int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 ? - r__h44194 : - r__h44186 ; - assign _theResult___snd_snd__h44577 = - int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 ? - r__h44594 : - r__h44586 ; - assign _theResult___snd_snd__h44977 = - int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 ? - r__h44994 : - r__h44986 ; - assign _theResult___snd_snd__h45377 = - int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 ? - r__h45394 : - r__h45386 ; - assign _theResult___snd_snd__h45777 = - int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 ? - r__h45794 : - r__h45786 ; - assign _theResult___snd_snd__h46177 = - int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 ? - r__h46194 : - r__h46186 ; - assign _theResult___snd_snd__h46577 = - int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 ? - r__h46594 : - r__h46586 ; - assign _theResult___snd_snd__h46977 = - int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 ? - r__h46994 : - r__h46986 ; - assign _theResult___snd_snd__h47377 = - int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 ? - r__h47394 : - r__h47386 ; - assign _theResult___snd_snd__h47777 = - int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 ? - r__h47794 : - r__h47786 ; - assign _theResult___snd_snd__h48177 = - int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 ? - r__h48194 : - r__h48186 ; - assign _theResult___snd_snd__h48577 = - int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 ? - r__h48594 : - r__h48586 ; - assign b___1__h16687 = 116'h40000000000000000000000000000 >> x__h24992 ; - assign b__h25374 = { 2'd0, int_sqrt_fFirst$D_OUT[115:2] } ; - assign b__h25774 = { 2'd0, int_sqrt_fNext_0$D_OUT[115:2] } ; - assign b__h26174 = { 2'd0, int_sqrt_fNext_1$D_OUT[115:2] } ; - assign b__h26574 = { 2'd0, int_sqrt_fNext_2$D_OUT[115:2] } ; - assign b__h26974 = { 2'd0, int_sqrt_fNext_3$D_OUT[115:2] } ; - assign b__h27374 = { 2'd0, int_sqrt_fNext_4$D_OUT[115:2] } ; - assign b__h27774 = { 2'd0, int_sqrt_fNext_5$D_OUT[115:2] } ; - assign b__h28174 = { 2'd0, int_sqrt_fNext_6$D_OUT[115:2] } ; - assign b__h28574 = { 2'd0, int_sqrt_fNext_7$D_OUT[115:2] } ; - assign b__h28974 = { 2'd0, int_sqrt_fNext_8$D_OUT[115:2] } ; - assign b__h29374 = { 2'd0, int_sqrt_fNext_9$D_OUT[115:2] } ; - assign b__h29774 = { 2'd0, int_sqrt_fNext_10$D_OUT[115:2] } ; - assign b__h30174 = { 2'd0, int_sqrt_fNext_11$D_OUT[115:2] } ; - assign b__h30574 = { 2'd0, int_sqrt_fNext_12$D_OUT[115:2] } ; - assign b__h30974 = { 2'd0, int_sqrt_fNext_13$D_OUT[115:2] } ; - assign b__h31374 = { 2'd0, int_sqrt_fNext_14$D_OUT[115:2] } ; - assign b__h31774 = { 2'd0, int_sqrt_fNext_15$D_OUT[115:2] } ; - assign b__h32174 = { 2'd0, int_sqrt_fNext_16$D_OUT[115:2] } ; - assign b__h32574 = { 2'd0, int_sqrt_fNext_17$D_OUT[115:2] } ; - assign b__h32974 = { 2'd0, int_sqrt_fNext_18$D_OUT[115:2] } ; - assign b__h33374 = { 2'd0, int_sqrt_fNext_19$D_OUT[115:2] } ; - assign b__h33774 = { 2'd0, int_sqrt_fNext_20$D_OUT[115:2] } ; - assign b__h34174 = { 2'd0, int_sqrt_fNext_21$D_OUT[115:2] } ; - assign b__h34574 = { 2'd0, int_sqrt_fNext_22$D_OUT[115:2] } ; - assign b__h34974 = { 2'd0, int_sqrt_fNext_23$D_OUT[115:2] } ; - assign b__h35374 = { 2'd0, int_sqrt_fNext_24$D_OUT[115:2] } ; - assign b__h35774 = { 2'd0, int_sqrt_fNext_25$D_OUT[115:2] } ; - assign b__h36174 = { 2'd0, int_sqrt_fNext_26$D_OUT[115:2] } ; - assign b__h36574 = { 2'd0, int_sqrt_fNext_27$D_OUT[115:2] } ; - assign b__h36974 = { 2'd0, int_sqrt_fNext_28$D_OUT[115:2] } ; - assign b__h37374 = { 2'd0, int_sqrt_fNext_29$D_OUT[115:2] } ; - assign b__h37774 = { 2'd0, int_sqrt_fNext_30$D_OUT[115:2] } ; - assign b__h38174 = { 2'd0, int_sqrt_fNext_31$D_OUT[115:2] } ; - assign b__h38574 = { 2'd0, int_sqrt_fNext_32$D_OUT[115:2] } ; - assign b__h38974 = { 2'd0, int_sqrt_fNext_33$D_OUT[115:2] } ; - assign b__h39374 = { 2'd0, int_sqrt_fNext_34$D_OUT[115:2] } ; - assign b__h39774 = { 2'd0, int_sqrt_fNext_35$D_OUT[115:2] } ; - assign b__h40174 = { 2'd0, int_sqrt_fNext_36$D_OUT[115:2] } ; - assign b__h40574 = { 2'd0, int_sqrt_fNext_37$D_OUT[115:2] } ; - assign b__h40974 = { 2'd0, int_sqrt_fNext_38$D_OUT[115:2] } ; - assign b__h41374 = { 2'd0, int_sqrt_fNext_39$D_OUT[115:2] } ; - assign b__h41774 = { 2'd0, int_sqrt_fNext_40$D_OUT[115:2] } ; - assign b__h42174 = { 2'd0, int_sqrt_fNext_41$D_OUT[115:2] } ; - assign b__h42574 = { 2'd0, int_sqrt_fNext_42$D_OUT[115:2] } ; - assign b__h42974 = { 2'd0, int_sqrt_fNext_43$D_OUT[115:2] } ; - assign b__h43374 = { 2'd0, int_sqrt_fNext_44$D_OUT[115:2] } ; - assign b__h43774 = { 2'd0, int_sqrt_fNext_45$D_OUT[115:2] } ; - assign b__h44174 = { 2'd0, int_sqrt_fNext_46$D_OUT[115:2] } ; - assign b__h44574 = { 2'd0, int_sqrt_fNext_47$D_OUT[115:2] } ; - assign b__h44974 = { 2'd0, int_sqrt_fNext_48$D_OUT[115:2] } ; - assign b__h45374 = { 2'd0, int_sqrt_fNext_49$D_OUT[115:2] } ; - assign b__h45774 = { 2'd0, int_sqrt_fNext_50$D_OUT[115:2] } ; - assign b__h46174 = { 2'd0, int_sqrt_fNext_51$D_OUT[115:2] } ; - assign b__h46574 = { 2'd0, int_sqrt_fNext_52$D_OUT[115:2] } ; - assign b__h46974 = { 2'd0, int_sqrt_fNext_53$D_OUT[115:2] } ; - assign b__h47374 = { 2'd0, int_sqrt_fNext_54$D_OUT[115:2] } ; - assign b__h47774 = { 2'd0, int_sqrt_fNext_55$D_OUT[115:2] } ; - assign b__h48174 = { 2'd0, int_sqrt_fNext_56$D_OUT[115:2] } ; - assign b__h48574 = { 2'd0, int_sqrt_fNext_57$D_OUT[115:2] } ; - assign b__h48712 = - int_sqrt_fNext_58$D_OUT[464] ? - int_sqrt_fNext_58$D_OUT[463:348] : - 116'd0 ; - assign din_inc___2_exp__h76519 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; - assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 = - fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 = - fpu_fState_S3$D_OUT[121:111] - 11'd1023 ; - assign guard__h66951 = x__h75654 ; - assign int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 = - int_sqrt_fFirst$D_OUT[347:232] < sum__h25372 ; - assign int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 = - int_sqrt_fNext_0$D_OUT[347:232] < sum__h25772 ; - assign int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 = - int_sqrt_fNext_10$D_OUT[347:232] < sum__h29772 ; - assign int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 = - int_sqrt_fNext_11$D_OUT[347:232] < sum__h30172 ; - assign int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 = - int_sqrt_fNext_12$D_OUT[347:232] < sum__h30572 ; - assign int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 = - int_sqrt_fNext_13$D_OUT[347:232] < sum__h30972 ; - assign int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 = - int_sqrt_fNext_14$D_OUT[347:232] < sum__h31372 ; - assign int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 = - int_sqrt_fNext_15$D_OUT[347:232] < sum__h31772 ; - assign int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 = - int_sqrt_fNext_16$D_OUT[347:232] < sum__h32172 ; - assign int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 = - int_sqrt_fNext_17$D_OUT[347:232] < sum__h32572 ; - assign int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 = - int_sqrt_fNext_18$D_OUT[347:232] < sum__h32972 ; - assign int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 = - int_sqrt_fNext_19$D_OUT[347:232] < sum__h33372 ; - assign int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 = - int_sqrt_fNext_1$D_OUT[347:232] < sum__h26172 ; - assign int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 = - int_sqrt_fNext_20$D_OUT[347:232] < sum__h33772 ; - assign int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 = - int_sqrt_fNext_21$D_OUT[347:232] < sum__h34172 ; - assign int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 = - int_sqrt_fNext_22$D_OUT[347:232] < sum__h34572 ; - assign int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 = - int_sqrt_fNext_23$D_OUT[347:232] < sum__h34972 ; - assign int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 = - int_sqrt_fNext_24$D_OUT[347:232] < sum__h35372 ; - assign int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 = - int_sqrt_fNext_25$D_OUT[347:232] < sum__h35772 ; - assign int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 = - int_sqrt_fNext_26$D_OUT[347:232] < sum__h36172 ; - assign int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 = - int_sqrt_fNext_27$D_OUT[347:232] < sum__h36572 ; - assign int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 = - int_sqrt_fNext_28$D_OUT[347:232] < sum__h36972 ; - assign int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 = - int_sqrt_fNext_29$D_OUT[347:232] < sum__h37372 ; - assign int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 = - int_sqrt_fNext_2$D_OUT[347:232] < sum__h26572 ; - assign int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 = - int_sqrt_fNext_30$D_OUT[347:232] < sum__h37772 ; - assign int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 = - int_sqrt_fNext_31$D_OUT[347:232] < sum__h38172 ; - assign int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 = - int_sqrt_fNext_32$D_OUT[347:232] < sum__h38572 ; - assign int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 = - int_sqrt_fNext_33$D_OUT[347:232] < sum__h38972 ; - assign int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 = - int_sqrt_fNext_34$D_OUT[347:232] < sum__h39372 ; - assign int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 = - int_sqrt_fNext_35$D_OUT[347:232] < sum__h39772 ; - assign int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 = - int_sqrt_fNext_36$D_OUT[347:232] < sum__h40172 ; - assign int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 = - int_sqrt_fNext_37$D_OUT[347:232] < sum__h40572 ; - assign int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 = - int_sqrt_fNext_38$D_OUT[347:232] < sum__h40972 ; - assign int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 = - int_sqrt_fNext_39$D_OUT[347:232] < sum__h41372 ; - assign int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 = - int_sqrt_fNext_3$D_OUT[347:232] < sum__h26972 ; - assign int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 = - int_sqrt_fNext_40$D_OUT[347:232] < sum__h41772 ; - assign int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 = - int_sqrt_fNext_41$D_OUT[347:232] < sum__h42172 ; - assign int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 = - int_sqrt_fNext_42$D_OUT[347:232] < sum__h42572 ; - assign int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 = - int_sqrt_fNext_43$D_OUT[347:232] < sum__h42972 ; - assign int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 = - int_sqrt_fNext_44$D_OUT[347:232] < sum__h43372 ; - assign int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 = - int_sqrt_fNext_45$D_OUT[347:232] < sum__h43772 ; - assign int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 = - int_sqrt_fNext_46$D_OUT[347:232] < sum__h44172 ; - assign int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 = - int_sqrt_fNext_47$D_OUT[347:232] < sum__h44572 ; - assign int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 = - int_sqrt_fNext_48$D_OUT[347:232] < sum__h44972 ; - assign int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 = - int_sqrt_fNext_49$D_OUT[347:232] < sum__h45372 ; - assign int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 = - int_sqrt_fNext_4$D_OUT[347:232] < sum__h27372 ; - assign int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 = - int_sqrt_fNext_50$D_OUT[347:232] < sum__h45772 ; - assign int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 = - int_sqrt_fNext_51$D_OUT[347:232] < sum__h46172 ; - assign int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 = - int_sqrt_fNext_52$D_OUT[347:232] < sum__h46572 ; - assign int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 = - int_sqrt_fNext_53$D_OUT[347:232] < sum__h46972 ; - assign int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 = - int_sqrt_fNext_54$D_OUT[347:232] < sum__h47372 ; - assign int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 = - int_sqrt_fNext_55$D_OUT[347:232] < sum__h47772 ; - assign int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 = - int_sqrt_fNext_56$D_OUT[347:232] < sum__h48172 ; - assign int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 = - int_sqrt_fNext_57$D_OUT[347:232] < sum__h48572 ; - assign int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 = - int_sqrt_fNext_5$D_OUT[347:232] < sum__h27772 ; - assign int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 = - int_sqrt_fNext_6$D_OUT[347:232] < sum__h28172 ; - assign int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 = - int_sqrt_fNext_7$D_OUT[347:232] < sum__h28572 ; - assign int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 = - int_sqrt_fNext_8$D_OUT[347:232] < sum__h28972 ; - assign int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 = - int_sqrt_fNext_9$D_OUT[347:232] < sum__h29372 ; - assign out_exp__h76431 = - fpu_fState_S4$D_OUT[2] ? - _theResult___exp__h76428 : - fpu_fState_S4$D_OUT[64:54] ; - assign out_sfd__h76432 = - fpu_fState_S4$D_OUT[2] ? - _theResult___sfd__h76429 : - fpu_fState_S4$D_OUT[53:2] ; - assign r__h25386 = r__h25394 + int_sqrt_fFirst$D_OUT[115:0] ; - assign r__h25394 = { 1'd0, int_sqrt_fFirst$D_OUT[231:117] } ; - assign r__h25786 = r__h25794 + int_sqrt_fNext_0$D_OUT[115:0] ; - assign r__h25794 = { 1'd0, int_sqrt_fNext_0$D_OUT[231:117] } ; - assign r__h26186 = r__h26194 + int_sqrt_fNext_1$D_OUT[115:0] ; - assign r__h26194 = { 1'd0, int_sqrt_fNext_1$D_OUT[231:117] } ; - assign r__h26586 = r__h26594 + int_sqrt_fNext_2$D_OUT[115:0] ; - assign r__h26594 = { 1'd0, int_sqrt_fNext_2$D_OUT[231:117] } ; - assign r__h26986 = r__h26994 + int_sqrt_fNext_3$D_OUT[115:0] ; - assign r__h26994 = { 1'd0, int_sqrt_fNext_3$D_OUT[231:117] } ; - assign r__h27386 = r__h27394 + int_sqrt_fNext_4$D_OUT[115:0] ; - assign r__h27394 = { 1'd0, int_sqrt_fNext_4$D_OUT[231:117] } ; - assign r__h27786 = r__h27794 + int_sqrt_fNext_5$D_OUT[115:0] ; - assign r__h27794 = { 1'd0, int_sqrt_fNext_5$D_OUT[231:117] } ; - assign r__h28186 = r__h28194 + int_sqrt_fNext_6$D_OUT[115:0] ; - assign r__h28194 = { 1'd0, int_sqrt_fNext_6$D_OUT[231:117] } ; - assign r__h28586 = r__h28594 + int_sqrt_fNext_7$D_OUT[115:0] ; - assign r__h28594 = { 1'd0, int_sqrt_fNext_7$D_OUT[231:117] } ; - assign r__h28986 = r__h28994 + int_sqrt_fNext_8$D_OUT[115:0] ; - assign r__h28994 = { 1'd0, int_sqrt_fNext_8$D_OUT[231:117] } ; - assign r__h29386 = r__h29394 + int_sqrt_fNext_9$D_OUT[115:0] ; - assign r__h29394 = { 1'd0, int_sqrt_fNext_9$D_OUT[231:117] } ; - assign r__h29786 = r__h29794 + int_sqrt_fNext_10$D_OUT[115:0] ; - assign r__h29794 = { 1'd0, int_sqrt_fNext_10$D_OUT[231:117] } ; - assign r__h30186 = r__h30194 + int_sqrt_fNext_11$D_OUT[115:0] ; - assign r__h30194 = { 1'd0, int_sqrt_fNext_11$D_OUT[231:117] } ; - assign r__h30586 = r__h30594 + int_sqrt_fNext_12$D_OUT[115:0] ; - assign r__h30594 = { 1'd0, int_sqrt_fNext_12$D_OUT[231:117] } ; - assign r__h30986 = r__h30994 + int_sqrt_fNext_13$D_OUT[115:0] ; - assign r__h30994 = { 1'd0, int_sqrt_fNext_13$D_OUT[231:117] } ; - assign r__h31386 = r__h31394 + int_sqrt_fNext_14$D_OUT[115:0] ; - assign r__h31394 = { 1'd0, int_sqrt_fNext_14$D_OUT[231:117] } ; - assign r__h31786 = r__h31794 + int_sqrt_fNext_15$D_OUT[115:0] ; - assign r__h31794 = { 1'd0, int_sqrt_fNext_15$D_OUT[231:117] } ; - assign r__h32186 = r__h32194 + int_sqrt_fNext_16$D_OUT[115:0] ; - assign r__h32194 = { 1'd0, int_sqrt_fNext_16$D_OUT[231:117] } ; - assign r__h32586 = r__h32594 + int_sqrt_fNext_17$D_OUT[115:0] ; - assign r__h32594 = { 1'd0, int_sqrt_fNext_17$D_OUT[231:117] } ; - assign r__h32986 = r__h32994 + int_sqrt_fNext_18$D_OUT[115:0] ; - assign r__h32994 = { 1'd0, int_sqrt_fNext_18$D_OUT[231:117] } ; - assign r__h33386 = r__h33394 + int_sqrt_fNext_19$D_OUT[115:0] ; - assign r__h33394 = { 1'd0, int_sqrt_fNext_19$D_OUT[231:117] } ; - assign r__h33786 = r__h33794 + int_sqrt_fNext_20$D_OUT[115:0] ; - assign r__h33794 = { 1'd0, int_sqrt_fNext_20$D_OUT[231:117] } ; - assign r__h34186 = r__h34194 + int_sqrt_fNext_21$D_OUT[115:0] ; - assign r__h34194 = { 1'd0, int_sqrt_fNext_21$D_OUT[231:117] } ; - assign r__h34586 = r__h34594 + int_sqrt_fNext_22$D_OUT[115:0] ; - assign r__h34594 = { 1'd0, int_sqrt_fNext_22$D_OUT[231:117] } ; - assign r__h34986 = r__h34994 + int_sqrt_fNext_23$D_OUT[115:0] ; - assign r__h34994 = { 1'd0, int_sqrt_fNext_23$D_OUT[231:117] } ; - assign r__h35386 = r__h35394 + int_sqrt_fNext_24$D_OUT[115:0] ; - assign r__h35394 = { 1'd0, int_sqrt_fNext_24$D_OUT[231:117] } ; - assign r__h35786 = r__h35794 + int_sqrt_fNext_25$D_OUT[115:0] ; - assign r__h35794 = { 1'd0, int_sqrt_fNext_25$D_OUT[231:117] } ; - assign r__h36186 = r__h36194 + int_sqrt_fNext_26$D_OUT[115:0] ; - assign r__h36194 = { 1'd0, int_sqrt_fNext_26$D_OUT[231:117] } ; - assign r__h36586 = r__h36594 + int_sqrt_fNext_27$D_OUT[115:0] ; - assign r__h36594 = { 1'd0, int_sqrt_fNext_27$D_OUT[231:117] } ; - assign r__h36986 = r__h36994 + int_sqrt_fNext_28$D_OUT[115:0] ; - assign r__h36994 = { 1'd0, int_sqrt_fNext_28$D_OUT[231:117] } ; - assign r__h37386 = r__h37394 + int_sqrt_fNext_29$D_OUT[115:0] ; - assign r__h37394 = { 1'd0, int_sqrt_fNext_29$D_OUT[231:117] } ; - assign r__h37786 = r__h37794 + int_sqrt_fNext_30$D_OUT[115:0] ; - assign r__h37794 = { 1'd0, int_sqrt_fNext_30$D_OUT[231:117] } ; - assign r__h38186 = r__h38194 + int_sqrt_fNext_31$D_OUT[115:0] ; - assign r__h38194 = { 1'd0, int_sqrt_fNext_31$D_OUT[231:117] } ; - assign r__h38586 = r__h38594 + int_sqrt_fNext_32$D_OUT[115:0] ; - assign r__h38594 = { 1'd0, int_sqrt_fNext_32$D_OUT[231:117] } ; - assign r__h38986 = r__h38994 + int_sqrt_fNext_33$D_OUT[115:0] ; - assign r__h38994 = { 1'd0, int_sqrt_fNext_33$D_OUT[231:117] } ; - assign r__h39386 = r__h39394 + int_sqrt_fNext_34$D_OUT[115:0] ; - assign r__h39394 = { 1'd0, int_sqrt_fNext_34$D_OUT[231:117] } ; - assign r__h39786 = r__h39794 + int_sqrt_fNext_35$D_OUT[115:0] ; - assign r__h39794 = { 1'd0, int_sqrt_fNext_35$D_OUT[231:117] } ; - assign r__h40186 = r__h40194 + int_sqrt_fNext_36$D_OUT[115:0] ; - assign r__h40194 = { 1'd0, int_sqrt_fNext_36$D_OUT[231:117] } ; - assign r__h40586 = r__h40594 + int_sqrt_fNext_37$D_OUT[115:0] ; - assign r__h40594 = { 1'd0, int_sqrt_fNext_37$D_OUT[231:117] } ; - assign r__h40986 = r__h40994 + int_sqrt_fNext_38$D_OUT[115:0] ; - assign r__h40994 = { 1'd0, int_sqrt_fNext_38$D_OUT[231:117] } ; - assign r__h41386 = r__h41394 + int_sqrt_fNext_39$D_OUT[115:0] ; - assign r__h41394 = { 1'd0, int_sqrt_fNext_39$D_OUT[231:117] } ; - assign r__h41786 = r__h41794 + int_sqrt_fNext_40$D_OUT[115:0] ; - assign r__h41794 = { 1'd0, int_sqrt_fNext_40$D_OUT[231:117] } ; - assign r__h42186 = r__h42194 + int_sqrt_fNext_41$D_OUT[115:0] ; - assign r__h42194 = { 1'd0, int_sqrt_fNext_41$D_OUT[231:117] } ; - assign r__h42586 = r__h42594 + int_sqrt_fNext_42$D_OUT[115:0] ; - assign r__h42594 = { 1'd0, int_sqrt_fNext_42$D_OUT[231:117] } ; - assign r__h42986 = r__h42994 + int_sqrt_fNext_43$D_OUT[115:0] ; - assign r__h42994 = { 1'd0, int_sqrt_fNext_43$D_OUT[231:117] } ; - assign r__h43386 = r__h43394 + int_sqrt_fNext_44$D_OUT[115:0] ; - assign r__h43394 = { 1'd0, int_sqrt_fNext_44$D_OUT[231:117] } ; - assign r__h43786 = r__h43794 + int_sqrt_fNext_45$D_OUT[115:0] ; - assign r__h43794 = { 1'd0, int_sqrt_fNext_45$D_OUT[231:117] } ; - assign r__h44186 = r__h44194 + int_sqrt_fNext_46$D_OUT[115:0] ; - assign r__h44194 = { 1'd0, int_sqrt_fNext_46$D_OUT[231:117] } ; - assign r__h44586 = r__h44594 + int_sqrt_fNext_47$D_OUT[115:0] ; - assign r__h44594 = { 1'd0, int_sqrt_fNext_47$D_OUT[231:117] } ; - assign r__h44986 = r__h44994 + int_sqrt_fNext_48$D_OUT[115:0] ; - assign r__h44994 = { 1'd0, int_sqrt_fNext_48$D_OUT[231:117] } ; - assign r__h45386 = r__h45394 + int_sqrt_fNext_49$D_OUT[115:0] ; - assign r__h45394 = { 1'd0, int_sqrt_fNext_49$D_OUT[231:117] } ; - assign r__h45786 = r__h45794 + int_sqrt_fNext_50$D_OUT[115:0] ; - assign r__h45794 = { 1'd0, int_sqrt_fNext_50$D_OUT[231:117] } ; - assign r__h46186 = r__h46194 + int_sqrt_fNext_51$D_OUT[115:0] ; - assign r__h46194 = { 1'd0, int_sqrt_fNext_51$D_OUT[231:117] } ; - assign r__h46586 = r__h46594 + int_sqrt_fNext_52$D_OUT[115:0] ; - assign r__h46594 = { 1'd0, int_sqrt_fNext_52$D_OUT[231:117] } ; - assign r__h46986 = r__h46994 + int_sqrt_fNext_53$D_OUT[115:0] ; - assign r__h46994 = { 1'd0, int_sqrt_fNext_53$D_OUT[231:117] } ; - assign r__h47386 = r__h47394 + int_sqrt_fNext_54$D_OUT[115:0] ; - assign r__h47394 = { 1'd0, int_sqrt_fNext_54$D_OUT[231:117] } ; - assign r__h47786 = r__h47794 + int_sqrt_fNext_55$D_OUT[115:0] ; - assign r__h47794 = { 1'd0, int_sqrt_fNext_55$D_OUT[231:117] } ; - assign r__h48186 = r__h48194 + int_sqrt_fNext_56$D_OUT[115:0] ; - assign r__h48194 = { 1'd0, int_sqrt_fNext_56$D_OUT[231:117] } ; - assign r__h48586 = r__h48594 + int_sqrt_fNext_57$D_OUT[115:0] ; - assign r__h48594 = { 1'd0, int_sqrt_fNext_57$D_OUT[231:117] } ; - assign result__h66451 = { int_sqrt_fResponse$D_OUT[59:2], 1'd1 } ; - assign s__h25385 = int_sqrt_fFirst$D_OUT[347:232] - sum__h25372 ; - assign s__h25785 = int_sqrt_fNext_0$D_OUT[347:232] - sum__h25772 ; - assign s__h26185 = int_sqrt_fNext_1$D_OUT[347:232] - sum__h26172 ; - assign s__h26585 = int_sqrt_fNext_2$D_OUT[347:232] - sum__h26572 ; - assign s__h26985 = int_sqrt_fNext_3$D_OUT[347:232] - sum__h26972 ; - assign s__h27385 = int_sqrt_fNext_4$D_OUT[347:232] - sum__h27372 ; - assign s__h27785 = int_sqrt_fNext_5$D_OUT[347:232] - sum__h27772 ; - assign s__h28185 = int_sqrt_fNext_6$D_OUT[347:232] - sum__h28172 ; - assign s__h28585 = int_sqrt_fNext_7$D_OUT[347:232] - sum__h28572 ; - assign s__h28985 = int_sqrt_fNext_8$D_OUT[347:232] - sum__h28972 ; - assign s__h29385 = int_sqrt_fNext_9$D_OUT[347:232] - sum__h29372 ; - assign s__h29785 = int_sqrt_fNext_10$D_OUT[347:232] - sum__h29772 ; - assign s__h30185 = int_sqrt_fNext_11$D_OUT[347:232] - sum__h30172 ; - assign s__h30585 = int_sqrt_fNext_12$D_OUT[347:232] - sum__h30572 ; - assign s__h30985 = int_sqrt_fNext_13$D_OUT[347:232] - sum__h30972 ; - assign s__h31385 = int_sqrt_fNext_14$D_OUT[347:232] - sum__h31372 ; - assign s__h31785 = int_sqrt_fNext_15$D_OUT[347:232] - sum__h31772 ; - assign s__h32185 = int_sqrt_fNext_16$D_OUT[347:232] - sum__h32172 ; - assign s__h32585 = int_sqrt_fNext_17$D_OUT[347:232] - sum__h32572 ; - assign s__h32985 = int_sqrt_fNext_18$D_OUT[347:232] - sum__h32972 ; - assign s__h33385 = int_sqrt_fNext_19$D_OUT[347:232] - sum__h33372 ; - assign s__h33785 = int_sqrt_fNext_20$D_OUT[347:232] - sum__h33772 ; - assign s__h34185 = int_sqrt_fNext_21$D_OUT[347:232] - sum__h34172 ; - assign s__h34585 = int_sqrt_fNext_22$D_OUT[347:232] - sum__h34572 ; - assign s__h34985 = int_sqrt_fNext_23$D_OUT[347:232] - sum__h34972 ; - assign s__h35385 = int_sqrt_fNext_24$D_OUT[347:232] - sum__h35372 ; - assign s__h35785 = int_sqrt_fNext_25$D_OUT[347:232] - sum__h35772 ; - assign s__h36185 = int_sqrt_fNext_26$D_OUT[347:232] - sum__h36172 ; - assign s__h36585 = int_sqrt_fNext_27$D_OUT[347:232] - sum__h36572 ; - assign s__h36985 = int_sqrt_fNext_28$D_OUT[347:232] - sum__h36972 ; - assign s__h37385 = int_sqrt_fNext_29$D_OUT[347:232] - sum__h37372 ; - assign s__h37785 = int_sqrt_fNext_30$D_OUT[347:232] - sum__h37772 ; - assign s__h38185 = int_sqrt_fNext_31$D_OUT[347:232] - sum__h38172 ; - assign s__h38585 = int_sqrt_fNext_32$D_OUT[347:232] - sum__h38572 ; - assign s__h38985 = int_sqrt_fNext_33$D_OUT[347:232] - sum__h38972 ; - assign s__h39385 = int_sqrt_fNext_34$D_OUT[347:232] - sum__h39372 ; - assign s__h39785 = int_sqrt_fNext_35$D_OUT[347:232] - sum__h39772 ; - assign s__h40185 = int_sqrt_fNext_36$D_OUT[347:232] - sum__h40172 ; - assign s__h40585 = int_sqrt_fNext_37$D_OUT[347:232] - sum__h40572 ; - assign s__h40985 = int_sqrt_fNext_38$D_OUT[347:232] - sum__h40972 ; - assign s__h41385 = int_sqrt_fNext_39$D_OUT[347:232] - sum__h41372 ; - assign s__h41785 = int_sqrt_fNext_40$D_OUT[347:232] - sum__h41772 ; - assign s__h42185 = int_sqrt_fNext_41$D_OUT[347:232] - sum__h42172 ; - assign s__h42585 = int_sqrt_fNext_42$D_OUT[347:232] - sum__h42572 ; - assign s__h42985 = int_sqrt_fNext_43$D_OUT[347:232] - sum__h42972 ; - assign s__h43385 = int_sqrt_fNext_44$D_OUT[347:232] - sum__h43372 ; - assign s__h43785 = int_sqrt_fNext_45$D_OUT[347:232] - sum__h43772 ; - assign s__h44185 = int_sqrt_fNext_46$D_OUT[347:232] - sum__h44172 ; - assign s__h44585 = int_sqrt_fNext_47$D_OUT[347:232] - sum__h44572 ; - assign s__h44985 = int_sqrt_fNext_48$D_OUT[347:232] - sum__h44972 ; - assign s__h45385 = int_sqrt_fNext_49$D_OUT[347:232] - sum__h45372 ; - assign s__h45785 = int_sqrt_fNext_50$D_OUT[347:232] - sum__h45772 ; - assign s__h46185 = int_sqrt_fNext_51$D_OUT[347:232] - sum__h46172 ; - assign s__h46585 = int_sqrt_fNext_52$D_OUT[347:232] - sum__h46572 ; - assign s__h46985 = int_sqrt_fNext_53$D_OUT[347:232] - sum__h46972 ; - assign s__h47385 = int_sqrt_fNext_54$D_OUT[347:232] - sum__h47372 ; - assign s__h47785 = int_sqrt_fNext_55$D_OUT[347:232] - sum__h47772 ; - assign s__h48185 = int_sqrt_fNext_56$D_OUT[347:232] - sum__h48172 ; - assign s__h48585 = int_sqrt_fNext_57$D_OUT[347:232] - sum__h48572 ; - assign sfd___1__h65692 = { 1'd0, sfd__h49938[57:1] } ; - assign sfd__h49936 = { value__h58164, 4'd0 } ; - assign sfd__h49938 = sfd__h49936 << x__h65722 ; - assign sfd__h49989 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h75932 = - { 1'b0, - fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfdin__h75260 = - fpu_fState_S3$D_OUT[58] ? - _theResult___snd__h75283 : - _theResult___snd__h75298 ; - assign sum__h25372 = - int_sqrt_fFirst$D_OUT[231:116] + int_sqrt_fFirst$D_OUT[115:0] ; - assign sum__h25772 = - int_sqrt_fNext_0$D_OUT[231:116] + int_sqrt_fNext_0$D_OUT[115:0] ; - assign sum__h26172 = - int_sqrt_fNext_1$D_OUT[231:116] + int_sqrt_fNext_1$D_OUT[115:0] ; - assign sum__h26572 = - int_sqrt_fNext_2$D_OUT[231:116] + int_sqrt_fNext_2$D_OUT[115:0] ; - assign sum__h26972 = - int_sqrt_fNext_3$D_OUT[231:116] + int_sqrt_fNext_3$D_OUT[115:0] ; - assign sum__h27372 = - int_sqrt_fNext_4$D_OUT[231:116] + int_sqrt_fNext_4$D_OUT[115:0] ; - assign sum__h27772 = - int_sqrt_fNext_5$D_OUT[231:116] + int_sqrt_fNext_5$D_OUT[115:0] ; - assign sum__h28172 = - int_sqrt_fNext_6$D_OUT[231:116] + int_sqrt_fNext_6$D_OUT[115:0] ; - assign sum__h28572 = - int_sqrt_fNext_7$D_OUT[231:116] + int_sqrt_fNext_7$D_OUT[115:0] ; - assign sum__h28972 = - int_sqrt_fNext_8$D_OUT[231:116] + int_sqrt_fNext_8$D_OUT[115:0] ; - assign sum__h29372 = - int_sqrt_fNext_9$D_OUT[231:116] + int_sqrt_fNext_9$D_OUT[115:0] ; - assign sum__h29772 = - int_sqrt_fNext_10$D_OUT[231:116] + - int_sqrt_fNext_10$D_OUT[115:0] ; - assign sum__h30172 = - int_sqrt_fNext_11$D_OUT[231:116] + - int_sqrt_fNext_11$D_OUT[115:0] ; - assign sum__h30572 = - int_sqrt_fNext_12$D_OUT[231:116] + - int_sqrt_fNext_12$D_OUT[115:0] ; - assign sum__h30972 = - int_sqrt_fNext_13$D_OUT[231:116] + - int_sqrt_fNext_13$D_OUT[115:0] ; - assign sum__h31372 = - int_sqrt_fNext_14$D_OUT[231:116] + - int_sqrt_fNext_14$D_OUT[115:0] ; - assign sum__h31772 = - int_sqrt_fNext_15$D_OUT[231:116] + - int_sqrt_fNext_15$D_OUT[115:0] ; - assign sum__h32172 = - int_sqrt_fNext_16$D_OUT[231:116] + - int_sqrt_fNext_16$D_OUT[115:0] ; - assign sum__h32572 = - int_sqrt_fNext_17$D_OUT[231:116] + - int_sqrt_fNext_17$D_OUT[115:0] ; - assign sum__h32972 = - int_sqrt_fNext_18$D_OUT[231:116] + - int_sqrt_fNext_18$D_OUT[115:0] ; - assign sum__h33372 = - int_sqrt_fNext_19$D_OUT[231:116] + - int_sqrt_fNext_19$D_OUT[115:0] ; - assign sum__h33772 = - int_sqrt_fNext_20$D_OUT[231:116] + - int_sqrt_fNext_20$D_OUT[115:0] ; - assign sum__h34172 = - int_sqrt_fNext_21$D_OUT[231:116] + - int_sqrt_fNext_21$D_OUT[115:0] ; - assign sum__h34572 = - int_sqrt_fNext_22$D_OUT[231:116] + - int_sqrt_fNext_22$D_OUT[115:0] ; - assign sum__h34972 = - int_sqrt_fNext_23$D_OUT[231:116] + - int_sqrt_fNext_23$D_OUT[115:0] ; - assign sum__h35372 = - int_sqrt_fNext_24$D_OUT[231:116] + - int_sqrt_fNext_24$D_OUT[115:0] ; - assign sum__h35772 = - int_sqrt_fNext_25$D_OUT[231:116] + - int_sqrt_fNext_25$D_OUT[115:0] ; - assign sum__h36172 = - int_sqrt_fNext_26$D_OUT[231:116] + - int_sqrt_fNext_26$D_OUT[115:0] ; - assign sum__h36572 = - int_sqrt_fNext_27$D_OUT[231:116] + - int_sqrt_fNext_27$D_OUT[115:0] ; - assign sum__h36972 = - int_sqrt_fNext_28$D_OUT[231:116] + - int_sqrt_fNext_28$D_OUT[115:0] ; - assign sum__h37372 = - int_sqrt_fNext_29$D_OUT[231:116] + - int_sqrt_fNext_29$D_OUT[115:0] ; - assign sum__h37772 = - int_sqrt_fNext_30$D_OUT[231:116] + - int_sqrt_fNext_30$D_OUT[115:0] ; - assign sum__h38172 = - int_sqrt_fNext_31$D_OUT[231:116] + - int_sqrt_fNext_31$D_OUT[115:0] ; - assign sum__h38572 = - int_sqrt_fNext_32$D_OUT[231:116] + - int_sqrt_fNext_32$D_OUT[115:0] ; - assign sum__h38972 = - int_sqrt_fNext_33$D_OUT[231:116] + - int_sqrt_fNext_33$D_OUT[115:0] ; - assign sum__h39372 = - int_sqrt_fNext_34$D_OUT[231:116] + - int_sqrt_fNext_34$D_OUT[115:0] ; - assign sum__h39772 = - int_sqrt_fNext_35$D_OUT[231:116] + - int_sqrt_fNext_35$D_OUT[115:0] ; - assign sum__h40172 = - int_sqrt_fNext_36$D_OUT[231:116] + - int_sqrt_fNext_36$D_OUT[115:0] ; - assign sum__h40572 = - int_sqrt_fNext_37$D_OUT[231:116] + - int_sqrt_fNext_37$D_OUT[115:0] ; - assign sum__h40972 = - int_sqrt_fNext_38$D_OUT[231:116] + - int_sqrt_fNext_38$D_OUT[115:0] ; - assign sum__h41372 = - int_sqrt_fNext_39$D_OUT[231:116] + - int_sqrt_fNext_39$D_OUT[115:0] ; - assign sum__h41772 = - int_sqrt_fNext_40$D_OUT[231:116] + - int_sqrt_fNext_40$D_OUT[115:0] ; - assign sum__h42172 = - int_sqrt_fNext_41$D_OUT[231:116] + - int_sqrt_fNext_41$D_OUT[115:0] ; - assign sum__h42572 = - int_sqrt_fNext_42$D_OUT[231:116] + - int_sqrt_fNext_42$D_OUT[115:0] ; - assign sum__h42972 = - int_sqrt_fNext_43$D_OUT[231:116] + - int_sqrt_fNext_43$D_OUT[115:0] ; - assign sum__h43372 = - int_sqrt_fNext_44$D_OUT[231:116] + - int_sqrt_fNext_44$D_OUT[115:0] ; - assign sum__h43772 = - int_sqrt_fNext_45$D_OUT[231:116] + - int_sqrt_fNext_45$D_OUT[115:0] ; - assign sum__h44172 = - int_sqrt_fNext_46$D_OUT[231:116] + - int_sqrt_fNext_46$D_OUT[115:0] ; - assign sum__h44572 = - int_sqrt_fNext_47$D_OUT[231:116] + - int_sqrt_fNext_47$D_OUT[115:0] ; - assign sum__h44972 = - int_sqrt_fNext_48$D_OUT[231:116] + - int_sqrt_fNext_48$D_OUT[115:0] ; - assign sum__h45372 = - int_sqrt_fNext_49$D_OUT[231:116] + - int_sqrt_fNext_49$D_OUT[115:0] ; - assign sum__h45772 = - int_sqrt_fNext_50$D_OUT[231:116] + - int_sqrt_fNext_50$D_OUT[115:0] ; - assign sum__h46172 = - int_sqrt_fNext_51$D_OUT[231:116] + - int_sqrt_fNext_51$D_OUT[115:0] ; - assign sum__h46572 = - int_sqrt_fNext_52$D_OUT[231:116] + - int_sqrt_fNext_52$D_OUT[115:0] ; - assign sum__h46972 = - int_sqrt_fNext_53$D_OUT[231:116] + - int_sqrt_fNext_53$D_OUT[115:0] ; - assign sum__h47372 = - int_sqrt_fNext_54$D_OUT[231:116] + - int_sqrt_fNext_54$D_OUT[115:0] ; - assign sum__h47772 = - int_sqrt_fNext_55$D_OUT[231:116] + - int_sqrt_fNext_55$D_OUT[115:0] ; - assign sum__h48172 = - int_sqrt_fNext_56$D_OUT[231:116] + - int_sqrt_fNext_56$D_OUT[115:0] ; - assign sum__h48572 = - int_sqrt_fNext_57$D_OUT[231:116] + - int_sqrt_fNext_57$D_OUT[115:0] ; - assign value_BIT_52___h58260 = fpu_fOperand_S0$D_OUT[65:55] != 11'd0 ; - assign value__h58164 = - { 1'b0, value_BIT_52___h58260, fpu_fOperand_S0$D_OUT[54:3] } ; - assign x__h24992 = - IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237[0] ? - IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 + - 7'd1 : - IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 ; - assign x__h402 = - int_sqrt_fRequest$D_OUT[115] ? - 116'h40000000000000000000000000000 : - b___1__h16687 ; - assign x__h57541 = x__h57559 + 13'd1024 ; - assign x__h57559 = - { IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9[11], - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 } ; - assign x__h65683 = - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[0] ? - sfd__h49938 : - sfd___1__h65692 ; - assign x__h65722 = - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 - - 6'd1 ; - assign x__h66665 = - int_sqrt_fResponse$D_OUT[0] ? - result__h66451 : - int_sqrt_fResponse$D_OUT[59:1] ; - assign x__h75654 = - (fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h75372 ; - always@(fpu_fState_S4$D_OUT or out_sfd__h76432 or _theResult___sfd__h76429) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - fpu_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - out_sfd__h76432; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - _theResult___sfd__h76429; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___sfd__h76429) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - fpu_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - _theResult___sfd__h76429; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or - _theResult___sfd__h76429) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h76507 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; - 3'd1: - _theResult___fst_sfd__h76507 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; - 3'd2: - _theResult___fst_sfd__h76507 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___sfd__h76429; - 3'd3: - _theResult___fst_sfd__h76507 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[53:2] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___sfd__h76429 : - fpu_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h76507 = fpu_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h76507 = 52'd0; - endcase - end - always@(fpu_fState_S4$D_OUT or out_exp__h76431 or _theResult___exp__h76428) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = - fpu_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = - out_exp__h76431; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = - _theResult___exp__h76428; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___exp__h76428) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = - fpu_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = - _theResult___exp__h76428; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 or - _theResult___exp__h76428) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h76506 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3; - 3'd1: - _theResult___fst_exp__h76506 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4; - 3'd2: - _theResult___fst_exp__h76506 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___exp__h76428; - 3'd3: - _theResult___fst_exp__h76506 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:54] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___exp__h76428 : - fpu_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h76506 = fpu_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h76506 = 11'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = - fpu_fState_S4$D_OUT[65]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = - fpu_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; - 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:2] : - (fpu_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : - fpu_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = - fpu_fState_S4$D_OUT[64:2]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = 63'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = - fpu_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = - fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : - fpu_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = - { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 }; - 3'd1: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[65:2] : - { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_fState_S4$D_OUT[65], - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 }; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = - { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 }; - endcase - end + // submodule fpu + mkXilinxFpSqrt fpu(.CLK(CLK), + .RST_N(RST_N), + .request_put(fpu$request_put), + .EN_request_put(fpu$EN_request_put), + .EN_response_get(fpu$EN_response_get), + .RDY_request_put(fpu$RDY_request_put), + .response_get(fpu$response_get), + .RDY_response_get(fpu$RDY_response_get)); + + // submodule fpu + assign fpu$request_put = request_put ; + assign fpu$EN_request_put = EN_request_put ; + assign fpu$EN_response_get = EN_response_get ; endmodule // mkDoubleSqrt diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 1e25443..d10f5a0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1828,52 +1828,52 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h4212; - reg [31 : 0] v__h4385; - reg [31 : 0] v__h4649; - reg [31 : 0] v__h6688; - reg [31 : 0] v__h2488; - reg [31 : 0] v__h6989; - reg [31 : 0] v__h7482; - reg [31 : 0] v__h7645; - reg [31 : 0] v__h111446; - reg [31 : 0] v__h111613; - reg [31 : 0] v__h113716; - reg [31 : 0] v__h131062; - reg [31 : 0] v__h110827; - reg [31 : 0] v__h137757; - reg [31 : 0] v__h138265; - reg [31 : 0] v__h2482; - reg [31 : 0] v__h4206; - reg [31 : 0] v__h4379; - reg [31 : 0] v__h4643; - reg [31 : 0] v__h6682; - reg [31 : 0] v__h6983; - reg [31 : 0] v__h7476; - reg [31 : 0] v__h7639; - reg [31 : 0] v__h110821; - reg [31 : 0] v__h111440; - reg [31 : 0] v__h111607; - reg [31 : 0] v__h113710; - reg [31 : 0] v__h131056; - reg [31 : 0] v__h137751; - reg [31 : 0] v__h138259; + reg [31 : 0] v__h4198; + reg [31 : 0] v__h4371; + reg [31 : 0] v__h4635; + reg [31 : 0] v__h6674; + reg [31 : 0] v__h2474; + reg [31 : 0] v__h6975; + reg [31 : 0] v__h7468; + reg [31 : 0] v__h7631; + reg [31 : 0] v__h111433; + reg [31 : 0] v__h111600; + reg [31 : 0] v__h113703; + reg [31 : 0] v__h131049; + reg [31 : 0] v__h110814; + reg [31 : 0] v__h137744; + reg [31 : 0] v__h138252; + reg [31 : 0] v__h2468; + reg [31 : 0] v__h4192; + reg [31 : 0] v__h4365; + reg [31 : 0] v__h4629; + reg [31 : 0] v__h6668; + reg [31 : 0] v__h6969; + reg [31 : 0] v__h7462; + reg [31 : 0] v__h7625; + reg [31 : 0] v__h110808; + reg [31 : 0] v__h111427; + reg [31 : 0] v__h111594; + reg [31 : 0] v__h113697; + reg [31 : 0] v__h131043; + reg [31 : 0] v__h137738; + reg [31 : 0] v__h138246; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26, - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26, + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818, @@ -1883,34 +1883,34 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876, IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844, IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846, - data64__h124886, - ld_data__h108620, - w1__h45369, - w1__h45374, - w2__h45370, - w2__h45376, - x__h45365; + data64__h124873, + ld_data__h108607, + w1__h45356, + w1__h45361, + w2__h45357, + w2__h45363, + x__h45352; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944; - reg [7 : 0] strb8__h124887; + reg [7 : 0] strb8__h124874; reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [2 : 0] x__h59083; - reg [1 : 0] CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; + reg [2 : 0] x__h59070; + reg [1 : 0] CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12, + CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050, SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319, - x__h59090, - x__h79808; + x__h59077, + x__h79795; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - new_cline__h111749; + new_cline__h111736; wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394; wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360; @@ -1929,82 +1929,82 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - data__h29459, - failed_testnum__h139655, - mem_req_rd_addr_araddr__h111047, - mem_req_wr_addr_awaddr__h124971, - mmioPlatform_fromHostQ_data_0__h40159, - mmioPlatform_mtime__h34773, - mmioPlatform_reqData__h45961, - n__read_addr__h58951, - n__read_addr__h59036, - n__read_addr__h77570, - n__read_addr__h77649, - n__read_snd_addr__h91741, - newData__h29540, - newData__h32470, - op_result__h45977, - op_result__h46507, - op_result__h46512, - op_result__h46517, + data__h29445, + failed_testnum__h139642, + mem_req_rd_addr_araddr__h111034, + mem_req_wr_addr_awaddr__h124958, + mmioPlatform_fromHostQ_data_0__h40146, + mmioPlatform_mtime__h34759, + mmioPlatform_reqData__h45948, + n__read_addr__h58938, + n__read_addr__h59023, + n__read_addr__h77557, + n__read_addr__h77636, + n__read_snd_addr__h91728, + newData__h29526, + newData__h32456, + op_result__h45964, + op_result__h46494, + op_result__h46499, + op_result__h46504, + op_result__h46509, + op_result__h46515, op_result__h46522, op_result__h46528, - op_result__h46535, - op_result__h46541, - result__h45420, - result__h45544, - result__h45572, - result__h45600, - result__h45628, - result__h45656, - result__h45684, - result__h45712, - result__h45740, - result__h45785, - result__h45813, - result__h45841, - result__h45869, - result__h45910, - result__h45938, - result__h46064, - result__h46091, - result__h46118, - result__h46145, - result__h46172, - result__h46199, - result__h46226, - result__h46253, - result__h46297, - result__h46324, - result__h46351, - result__h46378, - result__h46418, - result__h46445, - result__h46562, - result__h46628, - result__h46694, - result__h46760, - result__h46826, - result__h46892, - result__h46958, - result__h47020, - result__h47065, - result__h47131, - result__h47197, - result__h47255, - result__h47300, - w1___1__h45479, - w2___1__h45480, - x1_avValue_data__h37831, - x1_avValue_data__h42298, - x__h29651, - x__h32561, - x__h34921, - x__h38349, - x__h38360, - x__h40369, - x__h40380, - x__h47477; + result__h45407, + result__h45531, + result__h45559, + result__h45587, + result__h45615, + result__h45643, + result__h45671, + result__h45699, + result__h45727, + result__h45772, + result__h45800, + result__h45828, + result__h45856, + result__h45897, + result__h45925, + result__h46051, + result__h46078, + result__h46105, + result__h46132, + result__h46159, + result__h46186, + result__h46213, + result__h46240, + result__h46284, + result__h46311, + result__h46338, + result__h46365, + result__h46405, + result__h46432, + result__h46549, + result__h46615, + result__h46681, + result__h46747, + result__h46813, + result__h46879, + result__h46945, + result__h47007, + result__h47052, + result__h47118, + result__h47184, + result__h47242, + result__h47287, + w1___1__h45466, + w2___1__h45467, + x1_avValue_data__h37818, + x1_avValue_data__h42285, + x__h29637, + x__h32547, + x__h34907, + x__h38336, + x__h38347, + x__h40356, + x__h40367, + x__h47464; wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671; @@ -2016,16 +2016,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h29252, - v__h29289, - w15369_BITS_31_TO_0__q7, - w25370_BITS_31_TO_0__q8, - x_data__h28042; + v__h29238, + v__h29275, + w15356_BITS_31_TO_0__q7, + w25357_BITS_31_TO_0__q8, + x_data__h28028; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121; - wire [5 : 0] x__h111082, x__h124996; + wire [5 : 0] x__h111069, x__h124983; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120; - wire [3 : 0] b__h110754, b__h2382; - wire [2 : 0] n__read_id__h58955, n__read_id__h59040; + wire [3 : 0] b__h110741, b__h2368; + wire [2 : 0] n__read_id__h58942, n__read_id__h59027; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073, IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083, @@ -2084,22 +2084,22 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27667, - mmioPlatform_reqBE_BIT_4___h27627, + mmioPlatform_reqBE_BIT_0___h27653, + mmioPlatform_reqBE_BIT_4___h27613, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h58956, - n__read_child__h59041, - n__read_child__h77573, - n__read_child__h77652, - n__read_snd_id__h91742, + n__read_child__h58943, + n__read_child__h59028, + n__read_child__h77560, + n__read_child__h77639, + n__read_snd_id__h91729, propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093, propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097, - x__h58769, - x__h72321, - x__h77392; + x__h58756, + x__h72308, + x__h77379; // action method hart0_server_reset_request_put assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -3183,13 +3183,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2382 == 4'd0 ; + b__h2368 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2382 != 4'd0 && + b__h2368 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3301,7 +3301,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40369 == 64'd0 || + x__h40356 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3478,13 +3478,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h110754 == 4'd0 ; + b__h110741 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h110754 != 4'd0 && + b__h110741 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3576,7 +3576,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h28042 } ; + x_data__h28028 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && @@ -3616,7 +3616,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29459 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29445 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3730,7 +3730,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45365 } ; + x__h45352 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, @@ -3739,53 +3739,53 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47477, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47464, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40369 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40356 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40369 != 64'd0 ; + x__h40356 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38349 == 64'd0 ; + x__h38336 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - x__h58769 ; + x__h58756 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15, + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - x__h77392 ; + x__h77379 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26, + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 } ; assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h91741, n__read_snd_id__h91742 } ; + { 1'd1, n__read_snd_addr__h91728, n__read_snd_id__h91729 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -3834,11 +3834,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2382 - 4'd1 ; + b__h2368 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2382 ; + b__h2368 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = CAN_FIRE_RL_rl_reset ? 4'd0 : @@ -3891,11 +3891,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h110754 - 4'd1 ; + b__h110741 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h110754 ; + b__h110741 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = CAN_FIRE_RL_rl_reset ? 4'd0 : @@ -3970,7 +3970,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h111047, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h111034, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3981,13 +3981,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h124971, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h124958, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h124886, strb8__h124887, 1'd1 } ; + { 4'd0, data64__h124873, strb8__h124874, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3999,7 +3999,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h111749 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h111736 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4136,7 +4136,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32470 : + newData__h32456 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4145,7 +4145,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29540 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29526 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4567,7 +4567,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h108620, llc$dma_respLd_first[3] } ; + { ld_data__h108607, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4710,7 +4710,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h111749, + { new_cline__h111736, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -4971,47 +4971,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), - .amoExec_current_data(x__h34921), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h29651)); + .amoExec_current_data(x__h34907), + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h29637)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34773), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h32561)); + .amoExec_current_data(mmioPlatform_mtime__h34759), + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h32547)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40159), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h38360)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40146), + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h38347)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h40380)); + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h40367)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37831 } } ; + x1_avValue_data__h37818 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && !mmioPlatform_mtip_0 || @@ -5027,7 +5027,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29540 <= mmioPlatform_mtime ; + newData__h29526 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054 = NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5096,7 +5096,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - x__h72321 } ; + x__h72308 } ; assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5241,11 +5241,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40369 == 64'd0 : - x__h38349 == 64'd0, + x__h40356 == 64'd0 : + x__h38336 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42298 } ; + x1_avValue_data__h42285 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -5475,55 +5475,55 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 = - { CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, + { CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 = - { CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - x__h79808 } ; + x__h79795 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360 = - { CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 = - { CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12, - x__h59083, - x__h59090 } ; - assign b__h110754 = + { CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12, + x__h59070, + x__h59077 } ; + assign b__h110741 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2382 = + assign b__h2368 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29459 = + assign data__h29445 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29252, 32'd0 } ; - assign failed_testnum__h139655 = + { v__h29238, 32'd0 } ; + assign failed_testnum__h139642 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign mem_req_rd_addr_araddr__h111047 = - { llc$to_mem_toM_first[68:11], x__h111082 } ; - assign mem_req_wr_addr_awaddr__h124971 = - { llc$to_mem_toM_first[639:582], x__h124996 } ; + assign mem_req_rd_addr_araddr__h111034 = + { llc$to_mem_toM_first[68:11], x__h111069 } ; + assign mem_req_wr_addr_awaddr__h124958 = + { llc$to_mem_toM_first[639:582], x__h124983 } ; assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40159 = + assign mmioPlatform_fromHostQ_data_0__h40146 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -5534,18 +5534,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34773 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h34759 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32470 ; + mmioPlatform_mtimecmp_0 <= newData__h32456 ; assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27667 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27627 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h45961 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h27653 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27613 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h45948 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -5572,104 +5572,104 @@ module mkProc(CLK, !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h58951 = + assign n__read_addr__h58938 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h59036 = + assign n__read_addr__h59023 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h77570 = + assign n__read_addr__h77557 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 : 64'd0 ; - assign n__read_addr__h77649 = + assign n__read_addr__h77636 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 : 64'd0 ; - assign n__read_child__h58956 = + assign n__read_child__h58943 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h59041 = + assign n__read_child__h59028 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h77573 = + assign n__read_child__h77560 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 ; - assign n__read_child__h77652 = + assign n__read_child__h77639 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 ; - assign n__read_id__h58955 = + assign n__read_id__h58942 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h59040 = + assign n__read_id__h59027 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h91741 = + assign n__read_snd_addr__h91728 = propDstData_0_dummy2_1_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[64:1] : propDstData_0_rl_1[64:1]) : 64'd0 ; - assign n__read_snd_id__h91742 = + assign n__read_snd_id__h91729 = propDstData_0_dummy2_1_1$Q_OUT && (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[0] : propDstData_0_rl_1[0]) ; - assign newData__h29540 = + assign newData__h29526 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29651 : + x__h29637 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32470 = + assign newData__h32456 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32561 : + x__h32547 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h111749 = + assign new_cline__h111736 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h45977 = + assign op_result__h45964 = IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 + IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ; - assign op_result__h46507 = w1__h45374 ^ w2__h45376 ; - assign op_result__h46512 = w1__h45374 & w2__h45376 ; - assign op_result__h46517 = w1__h45374 | w2__h45376 ; + assign op_result__h46494 = w1__h45361 ^ w2__h45363 ; + assign op_result__h46499 = w1__h45361 & w2__h45363 ; + assign op_result__h46504 = w1__h45361 | w2__h45363 ; + assign op_result__h46509 = + (w1__h45361 < w2__h45363) ? w1__h45361 : w2__h45363 ; + assign op_result__h46515 = + (w1__h45361 <= w2__h45363) ? w2__h45363 : w1__h45361 ; assign op_result__h46522 = - (w1__h45374 < w2__h45376) ? w1__h45374 : w2__h45376 ; - assign op_result__h46528 = - (w1__h45374 <= w2__h45376) ? w2__h45376 : w1__h45374 ; - assign op_result__h46535 = ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ 64'h8000000000000000)) ? - w1__h45374 : - w2__h45376 ; - assign op_result__h46541 = + w1__h45361 : + w2__h45363 ; + assign op_result__h46528 = ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ 64'h8000000000000000)) ? - w2__h45376 : - w1__h45374 ; + w2__h45363 : + w1__h45361 ; assign propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -5680,126 +5680,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h45420 = + assign result__h45407 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0] } ; - assign result__h45544 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45572 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45600 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45628 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45656 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45684 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45712 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45740 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h45785 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h45813 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h45841 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h45869 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h45910 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h45938 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46064 = + assign result__h45531 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45559 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45587 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45615 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45643 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45671 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45699 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h45727 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h45772 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h45800 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h45828 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h45856 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h45897 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h45925 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h46051 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46091 = + assign result__h46078 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46118 = + assign result__h46105 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46145 = + assign result__h46132 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46172 = + assign result__h46159 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46199 = + assign result__h46186 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46226 = + assign result__h46213 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46253 = + assign result__h46240 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46297 = + assign result__h46284 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46324 = + assign result__h46311 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46351 = + assign result__h46338 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46378 = + assign result__h46365 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46418 = + assign result__h46405 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46445 = + assign result__h46432 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46562 = + assign result__h46549 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46628 = + assign result__h46615 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46694 = + assign result__h46681 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h46760 = + assign result__h46747 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h46826 = + assign result__h46813 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h46892 = + assign result__h46879 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h46958 = + assign result__h46945 = { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h47020 = + assign result__h47007 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0] } ; - assign result__h47065 = + assign result__h47052 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47131 = + assign result__h47118 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47197 = + assign result__h47184 = { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47255 = + assign result__h47242 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0] } ; - assign result__h47300 = + assign result__h47287 = { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29252 = mmioPlatform_waitUpperMSIPCRs ? v__h29289 : 32'd0 ; - assign v__h29289 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15369_BITS_31_TO_0__q7 = w1__h45369[31:0] ; - assign w1___1__h45479 = { 32'd0, w1__h45369[31:0] } ; - assign w25370_BITS_31_TO_0__q8 = w2__h45370[31:0] ; - assign w2___1__h45480 = { 32'd0, w2__h45370[31:0] } ; - assign x1_avValue_data__h37831 = + assign v__h29238 = mmioPlatform_waitUpperMSIPCRs ? v__h29275 : 32'd0 ; + assign v__h29275 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15356_BITS_31_TO_0__q7 = w1__h45356[31:0] ; + assign w1___1__h45466 = { 32'd0, w1__h45356[31:0] } ; + assign w25357_BITS_31_TO_0__q8 = w2__h45357[31:0] ; + assign w2___1__h45467 = { 32'd0, w2__h45357[31:0] } ; + assign x1_avValue_data__h37818 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42298 = + assign x1_avValue_data__h42285 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h111082 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h124996 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34921 = mmioPlatform_mtimecmp_0 ; - assign x__h38349 = + assign x__h111069 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h124983 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34907 = mmioPlatform_mtimecmp_0 ; + assign x__h38336 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38360 : + x__h38347 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 ; - assign x__h40369 = + assign x__h40356 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40380 : + x__h40367 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -5808,123 +5808,123 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47477 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58769 = + assign x__h47464 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58756 = SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ; - assign x__h72321 = + assign x__h72308 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 ; - assign x__h77392 = + assign x__h77379 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ; - assign x_data__h28042 = { 31'd0, mmioPlatform_reqData[0] } ; + assign x_data__h28028 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h108620 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h108620 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h108620 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h108620 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h108620 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h108620 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h108620 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h108620 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h108607 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h108607 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h108607 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h108607 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h108607 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h108607 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h108607 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h108607 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h124886 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h124886 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h124886 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h124886 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h124886 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h124886 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h124886 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h124886 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h124873 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h124873 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h124873 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h124873 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h124873 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h124873 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h124873 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h124873 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h124887 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h124887 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h124887 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h124887 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h124887 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h124887 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h124887 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h124887 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h124874 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h124874 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h124874 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h124874 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h124874 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h124874 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h124874 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h124874 = llc$to_mem_toM_first[575:568]; endcase end always@(mmioPlatform_curReq or - result__h45544 or - result__h45572 or - result__h45600 or - result__h45628 or - result__h45656 or - result__h45684 or result__h45712 or result__h45740) + result__h45531 or + result__h45559 or + result__h45587 or + result__h45615 or + result__h45643 or + result__h45671 or result__h45699 or result__h45727) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45544; + result__h45531; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45572; + result__h45559; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45600; + result__h45587; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45628; + result__h45615; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45656; + result__h45643; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45684; + result__h45671; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45712; + result__h45699; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45740; + result__h45727; endcase end always@(mmioPlatform_curReq or - result__h45785 or - result__h45813 or result__h45841 or result__h45869) + result__h45772 or + result__h45800 or result__h45828 or result__h45856) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45785; + result__h45772; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45813; + result__h45800; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45841; + result__h45828; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45869; + result__h45856; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h45910 or result__h45938) + always@(mmioPlatform_curReq or result__h45897 or result__h45925) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h45910; + result__h45897; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h45938; + result__h45925; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -5936,102 +5936,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h45370 = + w2__h45357 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; 2'b01: - w2__h45370 = + w2__h45357 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; 2'b10: - w2__h45370 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h45357 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h45370 = + w2__h45357 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w2___1__h45480 or + w2___1__h45467 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45376 = + w2__h45363 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; 2'b01: - w2__h45376 = + w2__h45363 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: w2__h45376 = w2___1__h45480; + 2'b10: w2__h45363 = w2___1__h45467; 2'b11: - w2__h45376 = + w2__h45363 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end always@(mmioPlatform_curReq or - result__h46297 or - result__h46324 or result__h46351 or result__h46378) + result__h46284 or + result__h46311 or result__h46338 or result__h46365) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46297; + result__h46284; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46324; + result__h46311; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46351; + result__h46338; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46378; + result__h46365; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h46064 or - result__h46091 or - result__h46118 or - result__h46145 or - result__h46172 or - result__h46199 or result__h46226 or result__h46253) + result__h46051 or + result__h46078 or + result__h46105 or + result__h46132 or + result__h46159 or + result__h46186 or result__h46213 or result__h46240) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46064; + result__h46051; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46091; + result__h46078; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46118; + result__h46105; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46145; + result__h46132; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46172; + result__h46159; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46199; + result__h46186; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46226; + result__h46213; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46253; + result__h46240; endcase end - always@(mmioPlatform_curReq or result__h46418 or result__h46445) + always@(mmioPlatform_curReq or result__h46405 or result__h46432) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46418; + result__h46405; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46445; + result__h46432; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6043,41 +6043,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h45369 = + w1__h45356 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; 2'b01: - w1__h45369 = + w1__h45356 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; 2'b10: - w1__h45369 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h45356 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h45369 = + w1__h45356 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w1___1__h45479 or + w1___1__h45466 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45374 = + w1__h45361 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; 2'b01: - w1__h45374 = + w1__h45361 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: w1__h45374 = w1___1__h45479; + 2'b10: w1__h45361 = w1___1__h45466; 2'b11: - w1__h45374 = + w1__h45361 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w15369_BITS_31_TO_0__q7 or + w15356_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) begin case (mmioPlatform_reqSz) @@ -6089,7 +6089,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; 2'b10: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - { {32{w15369_BITS_31_TO_0__q7[31]}}, w15369_BITS_31_TO_0__q7 }; + { {32{w15356_BITS_31_TO_0__q7[31]}}, w15356_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; @@ -6098,7 +6098,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w25370_BITS_31_TO_0__q8 or + w25357_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) begin case (mmioPlatform_reqSz) @@ -6110,115 +6110,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; 2'b10: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - { {32{w25370_BITS_31_TO_0__q8[31]}}, w25370_BITS_31_TO_0__q8 }; + { {32{w25357_BITS_31_TO_0__q8[31]}}, w25357_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46541 or - w2__h45376 or - op_result__h45977 or - op_result__h46507 or - op_result__h46512 or - op_result__h46517 or - op_result__h46535 or op_result__h46522 or op_result__h46528) + op_result__h46528 or + w2__h45363 or + op_result__h45964 or + op_result__h46494 or + op_result__h46499 or + op_result__h46504 or + op_result__h46522 or op_result__h46509 or op_result__h46515) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - w2__h45376; + w2__h45363; 4'd1: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h45977; + op_result__h45964; 4'd2: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46507; + op_result__h46494; 4'd3: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46512; + op_result__h46499; 4'd4: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46517; + op_result__h46504; 4'd5: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46535; + op_result__h46522; 4'd7: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46522; + op_result__h46509; 4'd8: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46528; + op_result__h46515; default: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46541; + op_result__h46528; endcase end always@(mmioPlatform_curReq or - result__h47020 or - result__h47065 or result__h47131 or result__h47197) + result__h47007 or + result__h47052 or result__h47118 or result__h47184) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47020; + result__h47007; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47065; + result__h47052; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47131; + result__h47118; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47197; + result__h47184; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45420 or - result__h46562 or - result__h46628 or - result__h46694 or - result__h46760 or - result__h46826 or result__h46892 or result__h46958) + result__h45407 or + result__h46549 or + result__h46615 or + result__h46681 or + result__h46747 or + result__h46813 or result__h46879 or result__h46945) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h45420; + result__h45407; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46562; + result__h46549; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46628; + result__h46615; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46694; + result__h46681; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46760; + result__h46747; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46826; + result__h46813; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46892; + result__h46879; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46958; + result__h46945; endcase end - always@(mmioPlatform_curReq or result__h47255 or result__h47300) + always@(mmioPlatform_curReq or result__h47242 or result__h47287) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47255; + result__h47242; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47300; + result__h47287; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6230,15 +6230,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h45365 = + x__h45352 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900; 2'b01: - x__h45365 = + x__h45352 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909; 2'b10: - x__h45365 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h45352 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h45365 = + x__h45352 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end @@ -6322,278 +6322,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145; endcase end - always@(x__h58769 or n__read_id__h58955 or n__read_id__h59040) + always@(x__h58756 or n__read_id__h58942 or n__read_id__h59027) begin - case (x__h58769) - 1'd0: x__h59083 = n__read_id__h58955; - 1'd1: x__h59083 = n__read_id__h59040; + case (x__h58756) + 1'd0: x__h59070 = n__read_id__h58942; + 1'd1: x__h59070 = n__read_id__h59027; endcase end - always@(x__h58769 or n__read_child__h58956 or n__read_child__h59041) + always@(x__h58756 or n__read_child__h58943 or n__read_child__h59028) begin - case (x__h58769) - 1'd0: x__h59090 = n__read_child__h58956; - 1'd1: x__h59090 = n__read_child__h59041; + case (x__h58756) + 1'd0: x__h59077 = n__read_child__h58943; + 1'd1: x__h59077 = n__read_child__h59028; endcase end - always@(x__h58769 or + always@(x__h58756 or propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 or propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12 = + CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12 = propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093; 1'd1: - CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12 = + CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12 = propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097; endcase end - always@(x__h58769 or + always@(x__h58756 or IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 or IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073; 1'd1: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077; endcase end - always@(x__h58769 or + always@(x__h58756 or IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 or IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083; 1'd1: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; endcase end - always@(x__h58769 or n__read_addr__h58951 or n__read_addr__h59036) + always@(x__h58756 or n__read_addr__h58938 or n__read_addr__h59023) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15 = - n__read_addr__h58951; + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15 = + n__read_addr__h58938; 1'd1: - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15 = - n__read_addr__h59036; + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15 = + n__read_addr__h59023; endcase end - always@(x__h77392 or n__read_child__h77573 or n__read_child__h77652) + always@(x__h77379 or n__read_child__h77560 or n__read_child__h77639) begin - case (x__h77392) - 1'd0: x__h79808 = n__read_child__h77573; - 1'd1: x__h79808 = n__read_child__h77652; + case (x__h77379) + 1'd0: x__h79795 = n__read_child__h77560; + 1'd1: x__h79795 = n__read_child__h77639; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77392 or + always@(x__h77379 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 : 2'd0; 1'd1: - CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 : 2'd0; endcase end - always@(x__h77392 or + always@(x__h77379 or NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 or NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338; 1'd1: - CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340; endcase end - always@(x__h77392 or n__read_addr__h77570 or n__read_addr__h77649) + always@(x__h77379 or n__read_addr__h77557 or n__read_addr__h77636) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26 = - n__read_addr__h77570; + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26 = + n__read_addr__h77557; 1'd1: - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26 = - n__read_addr__h77649; + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26 = + n__read_addr__h77636; endcase end @@ -7001,7 +7001,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h139655); + $display("FAIL %0d", failed_testnum__h139642); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -7009,14 +7009,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4212 = $stime; + v__h4198 = $stime; #0; end - v__h4206 = v__h4212 / 32'd10; + v__h4192 = v__h4198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4206); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4192); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7076,16 +7076,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4385 = $stime; + v__h4371 = $stime; #0; end - v__h4379 = v__h4385 / 32'd10; + v__h4365 = v__h4371 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4379); + v__h4365); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -7189,15 +7189,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4649 = $stime; + v__h4635 = $stime; #0; end - v__h4643 = v__h4649 / 32'd10; + v__h4629 = v__h4635 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4643); + v__h4629); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7366,14 +7366,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6688 = $stime; + v__h6674 = $stime; #0; end - v__h6682 = v__h6688 / 32'd10; + v__h6668 = v__h6674 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6682); + $display("%0d: ERROR: CreditCounter: overflow", v__h6668); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -7526,15 +7526,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2488 = $stime; + v__h2474 = $stime; #0; end - v__h2482 = v__h2488 / 32'd10; + v__h2468 = v__h2474 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2482); + v__h2468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7799,14 +7799,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6989 = $stime; + v__h6975 = $stime; #0; end - v__h6983 = v__h6989 / 32'd10; + v__h6969 = v__h6975 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6983); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6969); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7843,15 +7843,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7482 = $stime; + v__h7468 = $stime; #0; end - v__h7476 = v__h7482 / 32'd10; + v__h7462 = v__h7468 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7476); + v__h7462); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -7891,14 +7891,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7645 = $stime; + v__h7631 = $stime; #0; end - v__h7639 = v__h7645 / 32'd10; + v__h7625 = v__h7631 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7639); + v__h7625); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -8085,15 +8085,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) begin - v__h111446 = $stime; + v__h111433 = $stime; #0; end - v__h111440 = v__h111446 / 32'd10; + v__h111427 = v__h111433 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h111440, + v__h111427, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -8153,15 +8153,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h111613 = $stime; + v__h111600 = $stime; #0; end - v__h111607 = v__h111613 / 32'd10; + v__h111594 = v__h111600 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h111607); + v__h111594); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -8342,16 +8342,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h113716 = $stime; + v__h113703 = $stime; #0; end - v__h113710 = v__h113716 / 32'd10; + v__h113697 = v__h113703 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h113710); + v__h113697); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -9549,14 +9549,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h131062 = $stime; + v__h131049 = $stime; #0; end - v__h131056 = v__h131062 / 32'd10; + v__h131043 = v__h131049 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h131056); + $display("%0d: ERROR: CreditCounter: overflow", v__h131043); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -9580,7 +9580,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", mem_req_wr_addr_awaddr__h124971); + $write("'h%h", mem_req_wr_addr_awaddr__h124958); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9676,7 +9676,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", data64__h124886); + $write("'h%h", data64__h124873); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9684,7 +9684,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", strb8__h124887); + $write("'h%h", strb8__h124874); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9710,16 +9710,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h110827 = $stime; + v__h110814 = $stime; #0; end - v__h110821 = v__h110827 / 32'd10; + v__h110808 = v__h110814 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h110821, + v__h110808, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -9807,7 +9807,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", mem_req_rd_addr_araddr__h111047); + $write("'h%h", mem_req_rd_addr_araddr__h111034); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9888,15 +9888,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) begin - v__h137757 = $stime; + v__h137744 = $stime; #0; end - v__h137751 = v__h137757 / 32'd10; + v__h137738 = v__h137744 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h137751, + v__h137738, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -9934,15 +9934,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h138265 = $stime; + v__h138252 = $stime; #0; end - v__h138259 = v__h138265 / 32'd10; + v__h138246 = v__h138252 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h138259); + v__h138246); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 0165684..c6c37b4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -9449,6 +9449,7 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9498,6 +9499,7 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9595,6 +9597,7 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -9625,6 +9628,7 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && @@ -10419,11 +10423,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$RDY_first && IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = - CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && - !WILL_FIRE_RL_commitStage_doCommitTrap_flush && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = @@ -14456,7 +14456,7 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq = - WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; + CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ; assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v index e885e7d..5e92dd3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v @@ -7,16 +7,15 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 reg -// RDY_response_get O 1 reg +// response_get O 69 +// RDY_response_get O 1 // CLK I 1 clock // RST_N I 1 reset -// request_put I 131 reg +// request_put I 131 // EN_request_put I 1 // EN_response_get I 1 // -// Combinational paths from inputs to outputs: -// EN_response_get -> RDY_request_put +// No combinational paths from inputs to outputs // // @@ -60,4031 +59,44 @@ module mkDoubleDiv(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu_fOperands_S0 - wire [130 : 0] fpu_fOperands_S0$D_IN, fpu_fOperands_S0$D_OUT; - wire fpu_fOperands_S0$CLR, - fpu_fOperands_S0$DEQ, - fpu_fOperands_S0$EMPTY_N, - fpu_fOperands_S0$ENQ, - fpu_fOperands_S0$FULL_N; - - // ports of submodule fpu_fResult_S5 - wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; - wire fpu_fResult_S5$CLR, - fpu_fResult_S5$DEQ, - fpu_fResult_S5$EMPTY_N, - fpu_fResult_S5$ENQ, - fpu_fResult_S5$FULL_N; - - // ports of submodule fpu_fState_S1 - wire [318 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; - wire fpu_fState_S1$CLR, - fpu_fState_S1$DEQ, - fpu_fState_S1$EMPTY_N, - fpu_fState_S1$ENQ, - fpu_fState_S1$FULL_N; - - // ports of submodule fpu_fState_S2 - wire [147 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; - wire fpu_fState_S2$CLR, - fpu_fState_S2$DEQ, - fpu_fState_S2$EMPTY_N, - fpu_fState_S2$ENQ, - fpu_fState_S2$FULL_N; - - // ports of submodule fpu_fState_S3 - wire [194 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; - wire fpu_fState_S3$CLR, - fpu_fState_S3$DEQ, - fpu_fState_S3$EMPTY_N, - fpu_fState_S3$ENQ, - fpu_fState_S3$FULL_N; - - // ports of submodule fpu_fState_S4 - wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; - wire fpu_fState_S4$CLR, - fpu_fState_S4$DEQ, - fpu_fState_S4$EMPTY_N, - fpu_fState_S4$ENQ, - fpu_fState_S4$FULL_N; - - // ports of submodule int_div_fFirst - wire [231 : 0] int_div_fFirst$D_IN, int_div_fFirst$D_OUT; - wire int_div_fFirst$CLR, - int_div_fFirst$DEQ, - int_div_fFirst$EMPTY_N, - int_div_fFirst$ENQ, - int_div_fFirst$FULL_N; - - // ports of submodule int_div_fNext_0 - wire [231 : 0] int_div_fNext_0$D_IN, int_div_fNext_0$D_OUT; - wire int_div_fNext_0$CLR, - int_div_fNext_0$DEQ, - int_div_fNext_0$EMPTY_N, - int_div_fNext_0$ENQ, - int_div_fNext_0$FULL_N; - - // ports of submodule int_div_fNext_1 - wire [231 : 0] int_div_fNext_1$D_IN, int_div_fNext_1$D_OUT; - wire int_div_fNext_1$CLR, - int_div_fNext_1$DEQ, - int_div_fNext_1$EMPTY_N, - int_div_fNext_1$ENQ, - int_div_fNext_1$FULL_N; - - // ports of submodule int_div_fNext_10 - wire [231 : 0] int_div_fNext_10$D_IN, int_div_fNext_10$D_OUT; - wire int_div_fNext_10$CLR, - int_div_fNext_10$DEQ, - int_div_fNext_10$EMPTY_N, - int_div_fNext_10$ENQ, - int_div_fNext_10$FULL_N; - - // ports of submodule int_div_fNext_11 - wire [231 : 0] int_div_fNext_11$D_IN, int_div_fNext_11$D_OUT; - wire int_div_fNext_11$CLR, - int_div_fNext_11$DEQ, - int_div_fNext_11$EMPTY_N, - int_div_fNext_11$ENQ, - int_div_fNext_11$FULL_N; - - // ports of submodule int_div_fNext_12 - wire [231 : 0] int_div_fNext_12$D_IN, int_div_fNext_12$D_OUT; - wire int_div_fNext_12$CLR, - int_div_fNext_12$DEQ, - int_div_fNext_12$EMPTY_N, - int_div_fNext_12$ENQ, - int_div_fNext_12$FULL_N; - - // ports of submodule int_div_fNext_13 - wire [231 : 0] int_div_fNext_13$D_IN, int_div_fNext_13$D_OUT; - wire int_div_fNext_13$CLR, - int_div_fNext_13$DEQ, - int_div_fNext_13$EMPTY_N, - int_div_fNext_13$ENQ, - int_div_fNext_13$FULL_N; - - // ports of submodule int_div_fNext_14 - wire [231 : 0] int_div_fNext_14$D_IN, int_div_fNext_14$D_OUT; - wire int_div_fNext_14$CLR, - int_div_fNext_14$DEQ, - int_div_fNext_14$EMPTY_N, - int_div_fNext_14$ENQ, - int_div_fNext_14$FULL_N; - - // ports of submodule int_div_fNext_15 - wire [231 : 0] int_div_fNext_15$D_IN, int_div_fNext_15$D_OUT; - wire int_div_fNext_15$CLR, - int_div_fNext_15$DEQ, - int_div_fNext_15$EMPTY_N, - int_div_fNext_15$ENQ, - int_div_fNext_15$FULL_N; - - // ports of submodule int_div_fNext_16 - wire [231 : 0] int_div_fNext_16$D_IN, int_div_fNext_16$D_OUT; - wire int_div_fNext_16$CLR, - int_div_fNext_16$DEQ, - int_div_fNext_16$EMPTY_N, - int_div_fNext_16$ENQ, - int_div_fNext_16$FULL_N; - - // ports of submodule int_div_fNext_17 - wire [231 : 0] int_div_fNext_17$D_IN, int_div_fNext_17$D_OUT; - wire int_div_fNext_17$CLR, - int_div_fNext_17$DEQ, - int_div_fNext_17$EMPTY_N, - int_div_fNext_17$ENQ, - int_div_fNext_17$FULL_N; - - // ports of submodule int_div_fNext_18 - wire [231 : 0] int_div_fNext_18$D_IN, int_div_fNext_18$D_OUT; - wire int_div_fNext_18$CLR, - int_div_fNext_18$DEQ, - int_div_fNext_18$EMPTY_N, - int_div_fNext_18$ENQ, - int_div_fNext_18$FULL_N; - - // ports of submodule int_div_fNext_19 - wire [231 : 0] int_div_fNext_19$D_IN, int_div_fNext_19$D_OUT; - wire int_div_fNext_19$CLR, - int_div_fNext_19$DEQ, - int_div_fNext_19$EMPTY_N, - int_div_fNext_19$ENQ, - int_div_fNext_19$FULL_N; - - // ports of submodule int_div_fNext_2 - wire [231 : 0] int_div_fNext_2$D_IN, int_div_fNext_2$D_OUT; - wire int_div_fNext_2$CLR, - int_div_fNext_2$DEQ, - int_div_fNext_2$EMPTY_N, - int_div_fNext_2$ENQ, - int_div_fNext_2$FULL_N; - - // ports of submodule int_div_fNext_20 - wire [231 : 0] int_div_fNext_20$D_IN, int_div_fNext_20$D_OUT; - wire int_div_fNext_20$CLR, - int_div_fNext_20$DEQ, - int_div_fNext_20$EMPTY_N, - int_div_fNext_20$ENQ, - int_div_fNext_20$FULL_N; - - // ports of submodule int_div_fNext_21 - wire [231 : 0] int_div_fNext_21$D_IN, int_div_fNext_21$D_OUT; - wire int_div_fNext_21$CLR, - int_div_fNext_21$DEQ, - int_div_fNext_21$EMPTY_N, - int_div_fNext_21$ENQ, - int_div_fNext_21$FULL_N; - - // ports of submodule int_div_fNext_22 - wire [231 : 0] int_div_fNext_22$D_IN, int_div_fNext_22$D_OUT; - wire int_div_fNext_22$CLR, - int_div_fNext_22$DEQ, - int_div_fNext_22$EMPTY_N, - int_div_fNext_22$ENQ, - int_div_fNext_22$FULL_N; - - // ports of submodule int_div_fNext_23 - wire [231 : 0] int_div_fNext_23$D_IN, int_div_fNext_23$D_OUT; - wire int_div_fNext_23$CLR, - int_div_fNext_23$DEQ, - int_div_fNext_23$EMPTY_N, - int_div_fNext_23$ENQ, - int_div_fNext_23$FULL_N; - - // ports of submodule int_div_fNext_24 - wire [231 : 0] int_div_fNext_24$D_IN, int_div_fNext_24$D_OUT; - wire int_div_fNext_24$CLR, - int_div_fNext_24$DEQ, - int_div_fNext_24$EMPTY_N, - int_div_fNext_24$ENQ, - int_div_fNext_24$FULL_N; - - // ports of submodule int_div_fNext_25 - wire [231 : 0] int_div_fNext_25$D_IN, int_div_fNext_25$D_OUT; - wire int_div_fNext_25$CLR, - int_div_fNext_25$DEQ, - int_div_fNext_25$EMPTY_N, - int_div_fNext_25$ENQ, - int_div_fNext_25$FULL_N; - - // ports of submodule int_div_fNext_26 - wire [231 : 0] int_div_fNext_26$D_IN, int_div_fNext_26$D_OUT; - wire int_div_fNext_26$CLR, - int_div_fNext_26$DEQ, - int_div_fNext_26$EMPTY_N, - int_div_fNext_26$ENQ, - int_div_fNext_26$FULL_N; - - // ports of submodule int_div_fNext_27 - wire [231 : 0] int_div_fNext_27$D_IN, int_div_fNext_27$D_OUT; - wire int_div_fNext_27$CLR, - int_div_fNext_27$DEQ, - int_div_fNext_27$EMPTY_N, - int_div_fNext_27$ENQ, - int_div_fNext_27$FULL_N; - - // ports of submodule int_div_fNext_28 - wire [231 : 0] int_div_fNext_28$D_IN, int_div_fNext_28$D_OUT; - wire int_div_fNext_28$CLR, - int_div_fNext_28$DEQ, - int_div_fNext_28$EMPTY_N, - int_div_fNext_28$ENQ, - int_div_fNext_28$FULL_N; - - // ports of submodule int_div_fNext_29 - wire [231 : 0] int_div_fNext_29$D_IN, int_div_fNext_29$D_OUT; - wire int_div_fNext_29$CLR, - int_div_fNext_29$DEQ, - int_div_fNext_29$EMPTY_N, - int_div_fNext_29$ENQ, - int_div_fNext_29$FULL_N; - - // ports of submodule int_div_fNext_3 - wire [231 : 0] int_div_fNext_3$D_IN, int_div_fNext_3$D_OUT; - wire int_div_fNext_3$CLR, - int_div_fNext_3$DEQ, - int_div_fNext_3$EMPTY_N, - int_div_fNext_3$ENQ, - int_div_fNext_3$FULL_N; - - // ports of submodule int_div_fNext_30 - wire [231 : 0] int_div_fNext_30$D_IN, int_div_fNext_30$D_OUT; - wire int_div_fNext_30$CLR, - int_div_fNext_30$DEQ, - int_div_fNext_30$EMPTY_N, - int_div_fNext_30$ENQ, - int_div_fNext_30$FULL_N; - - // ports of submodule int_div_fNext_31 - wire [231 : 0] int_div_fNext_31$D_IN, int_div_fNext_31$D_OUT; - wire int_div_fNext_31$CLR, - int_div_fNext_31$DEQ, - int_div_fNext_31$EMPTY_N, - int_div_fNext_31$ENQ, - int_div_fNext_31$FULL_N; - - // ports of submodule int_div_fNext_32 - wire [231 : 0] int_div_fNext_32$D_IN, int_div_fNext_32$D_OUT; - wire int_div_fNext_32$CLR, - int_div_fNext_32$DEQ, - int_div_fNext_32$EMPTY_N, - int_div_fNext_32$ENQ, - int_div_fNext_32$FULL_N; - - // ports of submodule int_div_fNext_33 - wire [231 : 0] int_div_fNext_33$D_IN, int_div_fNext_33$D_OUT; - wire int_div_fNext_33$CLR, - int_div_fNext_33$DEQ, - int_div_fNext_33$EMPTY_N, - int_div_fNext_33$ENQ, - int_div_fNext_33$FULL_N; - - // ports of submodule int_div_fNext_34 - wire [231 : 0] int_div_fNext_34$D_IN, int_div_fNext_34$D_OUT; - wire int_div_fNext_34$CLR, - int_div_fNext_34$DEQ, - int_div_fNext_34$EMPTY_N, - int_div_fNext_34$ENQ, - int_div_fNext_34$FULL_N; - - // ports of submodule int_div_fNext_35 - wire [231 : 0] int_div_fNext_35$D_IN, int_div_fNext_35$D_OUT; - wire int_div_fNext_35$CLR, - int_div_fNext_35$DEQ, - int_div_fNext_35$EMPTY_N, - int_div_fNext_35$ENQ, - int_div_fNext_35$FULL_N; - - // ports of submodule int_div_fNext_36 - wire [231 : 0] int_div_fNext_36$D_IN, int_div_fNext_36$D_OUT; - wire int_div_fNext_36$CLR, - int_div_fNext_36$DEQ, - int_div_fNext_36$EMPTY_N, - int_div_fNext_36$ENQ, - int_div_fNext_36$FULL_N; - - // ports of submodule int_div_fNext_37 - wire [231 : 0] int_div_fNext_37$D_IN, int_div_fNext_37$D_OUT; - wire int_div_fNext_37$CLR, - int_div_fNext_37$DEQ, - int_div_fNext_37$EMPTY_N, - int_div_fNext_37$ENQ, - int_div_fNext_37$FULL_N; - - // ports of submodule int_div_fNext_38 - wire [231 : 0] int_div_fNext_38$D_IN, int_div_fNext_38$D_OUT; - wire int_div_fNext_38$CLR, - int_div_fNext_38$DEQ, - int_div_fNext_38$EMPTY_N, - int_div_fNext_38$ENQ, - int_div_fNext_38$FULL_N; - - // ports of submodule int_div_fNext_39 - wire [231 : 0] int_div_fNext_39$D_IN, int_div_fNext_39$D_OUT; - wire int_div_fNext_39$CLR, - int_div_fNext_39$DEQ, - int_div_fNext_39$EMPTY_N, - int_div_fNext_39$ENQ, - int_div_fNext_39$FULL_N; - - // ports of submodule int_div_fNext_4 - wire [231 : 0] int_div_fNext_4$D_IN, int_div_fNext_4$D_OUT; - wire int_div_fNext_4$CLR, - int_div_fNext_4$DEQ, - int_div_fNext_4$EMPTY_N, - int_div_fNext_4$ENQ, - int_div_fNext_4$FULL_N; - - // ports of submodule int_div_fNext_40 - wire [231 : 0] int_div_fNext_40$D_IN, int_div_fNext_40$D_OUT; - wire int_div_fNext_40$CLR, - int_div_fNext_40$DEQ, - int_div_fNext_40$EMPTY_N, - int_div_fNext_40$ENQ, - int_div_fNext_40$FULL_N; - - // ports of submodule int_div_fNext_41 - wire [231 : 0] int_div_fNext_41$D_IN, int_div_fNext_41$D_OUT; - wire int_div_fNext_41$CLR, - int_div_fNext_41$DEQ, - int_div_fNext_41$EMPTY_N, - int_div_fNext_41$ENQ, - int_div_fNext_41$FULL_N; - - // ports of submodule int_div_fNext_42 - wire [231 : 0] int_div_fNext_42$D_IN, int_div_fNext_42$D_OUT; - wire int_div_fNext_42$CLR, - int_div_fNext_42$DEQ, - int_div_fNext_42$EMPTY_N, - int_div_fNext_42$ENQ, - int_div_fNext_42$FULL_N; - - // ports of submodule int_div_fNext_43 - wire [231 : 0] int_div_fNext_43$D_IN, int_div_fNext_43$D_OUT; - wire int_div_fNext_43$CLR, - int_div_fNext_43$DEQ, - int_div_fNext_43$EMPTY_N, - int_div_fNext_43$ENQ, - int_div_fNext_43$FULL_N; - - // ports of submodule int_div_fNext_44 - wire [231 : 0] int_div_fNext_44$D_IN, int_div_fNext_44$D_OUT; - wire int_div_fNext_44$CLR, - int_div_fNext_44$DEQ, - int_div_fNext_44$EMPTY_N, - int_div_fNext_44$ENQ, - int_div_fNext_44$FULL_N; - - // ports of submodule int_div_fNext_45 - wire [231 : 0] int_div_fNext_45$D_IN, int_div_fNext_45$D_OUT; - wire int_div_fNext_45$CLR, - int_div_fNext_45$DEQ, - int_div_fNext_45$EMPTY_N, - int_div_fNext_45$ENQ, - int_div_fNext_45$FULL_N; - - // ports of submodule int_div_fNext_46 - wire [231 : 0] int_div_fNext_46$D_IN, int_div_fNext_46$D_OUT; - wire int_div_fNext_46$CLR, - int_div_fNext_46$DEQ, - int_div_fNext_46$EMPTY_N, - int_div_fNext_46$ENQ, - int_div_fNext_46$FULL_N; - - // ports of submodule int_div_fNext_47 - wire [231 : 0] int_div_fNext_47$D_IN, int_div_fNext_47$D_OUT; - wire int_div_fNext_47$CLR, - int_div_fNext_47$DEQ, - int_div_fNext_47$EMPTY_N, - int_div_fNext_47$ENQ, - int_div_fNext_47$FULL_N; - - // ports of submodule int_div_fNext_48 - wire [231 : 0] int_div_fNext_48$D_IN, int_div_fNext_48$D_OUT; - wire int_div_fNext_48$CLR, - int_div_fNext_48$DEQ, - int_div_fNext_48$EMPTY_N, - int_div_fNext_48$ENQ, - int_div_fNext_48$FULL_N; - - // ports of submodule int_div_fNext_49 - wire [231 : 0] int_div_fNext_49$D_IN, int_div_fNext_49$D_OUT; - wire int_div_fNext_49$CLR, - int_div_fNext_49$DEQ, - int_div_fNext_49$EMPTY_N, - int_div_fNext_49$ENQ, - int_div_fNext_49$FULL_N; - - // ports of submodule int_div_fNext_5 - wire [231 : 0] int_div_fNext_5$D_IN, int_div_fNext_5$D_OUT; - wire int_div_fNext_5$CLR, - int_div_fNext_5$DEQ, - int_div_fNext_5$EMPTY_N, - int_div_fNext_5$ENQ, - int_div_fNext_5$FULL_N; - - // ports of submodule int_div_fNext_50 - wire [231 : 0] int_div_fNext_50$D_IN, int_div_fNext_50$D_OUT; - wire int_div_fNext_50$CLR, - int_div_fNext_50$DEQ, - int_div_fNext_50$EMPTY_N, - int_div_fNext_50$ENQ, - int_div_fNext_50$FULL_N; - - // ports of submodule int_div_fNext_51 - wire [231 : 0] int_div_fNext_51$D_IN, int_div_fNext_51$D_OUT; - wire int_div_fNext_51$CLR, - int_div_fNext_51$DEQ, - int_div_fNext_51$EMPTY_N, - int_div_fNext_51$ENQ, - int_div_fNext_51$FULL_N; - - // ports of submodule int_div_fNext_52 - wire [231 : 0] int_div_fNext_52$D_IN, int_div_fNext_52$D_OUT; - wire int_div_fNext_52$CLR, - int_div_fNext_52$DEQ, - int_div_fNext_52$EMPTY_N, - int_div_fNext_52$ENQ, - int_div_fNext_52$FULL_N; - - // ports of submodule int_div_fNext_53 - wire [231 : 0] int_div_fNext_53$D_IN, int_div_fNext_53$D_OUT; - wire int_div_fNext_53$CLR, - int_div_fNext_53$DEQ, - int_div_fNext_53$EMPTY_N, - int_div_fNext_53$ENQ, - int_div_fNext_53$FULL_N; - - // ports of submodule int_div_fNext_54 - wire [231 : 0] int_div_fNext_54$D_IN, int_div_fNext_54$D_OUT; - wire int_div_fNext_54$CLR, - int_div_fNext_54$DEQ, - int_div_fNext_54$EMPTY_N, - int_div_fNext_54$ENQ, - int_div_fNext_54$FULL_N; - - // ports of submodule int_div_fNext_55 - wire [231 : 0] int_div_fNext_55$D_IN, int_div_fNext_55$D_OUT; - wire int_div_fNext_55$CLR, - int_div_fNext_55$DEQ, - int_div_fNext_55$EMPTY_N, - int_div_fNext_55$ENQ, - int_div_fNext_55$FULL_N; - - // ports of submodule int_div_fNext_56 - wire [231 : 0] int_div_fNext_56$D_IN, int_div_fNext_56$D_OUT; - wire int_div_fNext_56$CLR, - int_div_fNext_56$DEQ, - int_div_fNext_56$EMPTY_N, - int_div_fNext_56$ENQ, - int_div_fNext_56$FULL_N; - - // ports of submodule int_div_fNext_57 - wire [231 : 0] int_div_fNext_57$D_IN, int_div_fNext_57$D_OUT; - wire int_div_fNext_57$CLR, - int_div_fNext_57$DEQ, - int_div_fNext_57$EMPTY_N, - int_div_fNext_57$ENQ, - int_div_fNext_57$FULL_N; - - // ports of submodule int_div_fNext_6 - wire [231 : 0] int_div_fNext_6$D_IN, int_div_fNext_6$D_OUT; - wire int_div_fNext_6$CLR, - int_div_fNext_6$DEQ, - int_div_fNext_6$EMPTY_N, - int_div_fNext_6$ENQ, - int_div_fNext_6$FULL_N; - - // ports of submodule int_div_fNext_7 - wire [231 : 0] int_div_fNext_7$D_IN, int_div_fNext_7$D_OUT; - wire int_div_fNext_7$CLR, - int_div_fNext_7$DEQ, - int_div_fNext_7$EMPTY_N, - int_div_fNext_7$ENQ, - int_div_fNext_7$FULL_N; - - // ports of submodule int_div_fNext_8 - wire [231 : 0] int_div_fNext_8$D_IN, int_div_fNext_8$D_OUT; - wire int_div_fNext_8$CLR, - int_div_fNext_8$DEQ, - int_div_fNext_8$EMPTY_N, - int_div_fNext_8$ENQ, - int_div_fNext_8$FULL_N; - - // ports of submodule int_div_fNext_9 - wire [231 : 0] int_div_fNext_9$D_IN, int_div_fNext_9$D_OUT; - wire int_div_fNext_9$CLR, - int_div_fNext_9$DEQ, - int_div_fNext_9$EMPTY_N, - int_div_fNext_9$ENQ, - int_div_fNext_9$FULL_N; - - // ports of submodule int_div_fRequest - wire [170 : 0] int_div_fRequest$D_IN, int_div_fRequest$D_OUT; - wire int_div_fRequest$CLR, - int_div_fRequest$DEQ, - int_div_fRequest$EMPTY_N, - int_div_fRequest$ENQ, - int_div_fRequest$FULL_N; - - // ports of submodule int_div_fResponse - wire [113 : 0] int_div_fResponse$D_IN, int_div_fResponse$D_OUT; - wire int_div_fResponse$CLR, - int_div_fResponse$DEQ, - int_div_fResponse$EMPTY_N, - int_div_fResponse$ENQ, - int_div_fResponse$FULL_N; + // ports of submodule fpu + wire [130 : 0] fpu$request_put; + wire [68 : 0] fpu$response_get; + wire fpu$EN_request_put, + fpu$EN_response_get, + fpu$RDY_request_put, + fpu$RDY_response_get; // rule scheduling signals - wire CAN_FIRE_RL_fpu_s1_stage, - CAN_FIRE_RL_fpu_s2_stage, - CAN_FIRE_RL_fpu_s3_stage, - CAN_FIRE_RL_fpu_s4_stage, - CAN_FIRE_RL_fpu_s5_stage, - CAN_FIRE_RL_int_div_finish, - CAN_FIRE_RL_int_div_start, - CAN_FIRE_RL_int_div_work, - CAN_FIRE_RL_int_div_work_1, - CAN_FIRE_RL_int_div_work_10, - CAN_FIRE_RL_int_div_work_11, - CAN_FIRE_RL_int_div_work_12, - CAN_FIRE_RL_int_div_work_13, - CAN_FIRE_RL_int_div_work_14, - CAN_FIRE_RL_int_div_work_15, - CAN_FIRE_RL_int_div_work_16, - CAN_FIRE_RL_int_div_work_17, - CAN_FIRE_RL_int_div_work_18, - CAN_FIRE_RL_int_div_work_19, - CAN_FIRE_RL_int_div_work_2, - CAN_FIRE_RL_int_div_work_20, - CAN_FIRE_RL_int_div_work_21, - CAN_FIRE_RL_int_div_work_22, - CAN_FIRE_RL_int_div_work_23, - CAN_FIRE_RL_int_div_work_24, - CAN_FIRE_RL_int_div_work_25, - CAN_FIRE_RL_int_div_work_26, - CAN_FIRE_RL_int_div_work_27, - CAN_FIRE_RL_int_div_work_28, - CAN_FIRE_RL_int_div_work_29, - CAN_FIRE_RL_int_div_work_3, - CAN_FIRE_RL_int_div_work_30, - CAN_FIRE_RL_int_div_work_31, - CAN_FIRE_RL_int_div_work_32, - CAN_FIRE_RL_int_div_work_33, - CAN_FIRE_RL_int_div_work_34, - CAN_FIRE_RL_int_div_work_35, - CAN_FIRE_RL_int_div_work_36, - CAN_FIRE_RL_int_div_work_37, - CAN_FIRE_RL_int_div_work_38, - CAN_FIRE_RL_int_div_work_39, - CAN_FIRE_RL_int_div_work_4, - CAN_FIRE_RL_int_div_work_40, - CAN_FIRE_RL_int_div_work_41, - CAN_FIRE_RL_int_div_work_42, - CAN_FIRE_RL_int_div_work_43, - CAN_FIRE_RL_int_div_work_44, - CAN_FIRE_RL_int_div_work_45, - CAN_FIRE_RL_int_div_work_46, - CAN_FIRE_RL_int_div_work_47, - CAN_FIRE_RL_int_div_work_48, - CAN_FIRE_RL_int_div_work_49, - CAN_FIRE_RL_int_div_work_5, - CAN_FIRE_RL_int_div_work_50, - CAN_FIRE_RL_int_div_work_51, - CAN_FIRE_RL_int_div_work_52, - CAN_FIRE_RL_int_div_work_53, - CAN_FIRE_RL_int_div_work_54, - CAN_FIRE_RL_int_div_work_55, - CAN_FIRE_RL_int_div_work_56, - CAN_FIRE_RL_int_div_work_57, - CAN_FIRE_RL_int_div_work_6, - CAN_FIRE_RL_int_div_work_7, - CAN_FIRE_RL_int_div_work_8, - CAN_FIRE_RL_int_div_work_9, - CAN_FIRE_request_put, + wire CAN_FIRE_request_put, CAN_FIRE_response_get, - WILL_FIRE_RL_fpu_s1_stage, - WILL_FIRE_RL_fpu_s2_stage, - WILL_FIRE_RL_fpu_s3_stage, - WILL_FIRE_RL_fpu_s4_stage, - WILL_FIRE_RL_fpu_s5_stage, - WILL_FIRE_RL_int_div_finish, - WILL_FIRE_RL_int_div_start, - WILL_FIRE_RL_int_div_work, - WILL_FIRE_RL_int_div_work_1, - WILL_FIRE_RL_int_div_work_10, - WILL_FIRE_RL_int_div_work_11, - WILL_FIRE_RL_int_div_work_12, - WILL_FIRE_RL_int_div_work_13, - WILL_FIRE_RL_int_div_work_14, - WILL_FIRE_RL_int_div_work_15, - WILL_FIRE_RL_int_div_work_16, - WILL_FIRE_RL_int_div_work_17, - WILL_FIRE_RL_int_div_work_18, - WILL_FIRE_RL_int_div_work_19, - WILL_FIRE_RL_int_div_work_2, - WILL_FIRE_RL_int_div_work_20, - WILL_FIRE_RL_int_div_work_21, - WILL_FIRE_RL_int_div_work_22, - WILL_FIRE_RL_int_div_work_23, - WILL_FIRE_RL_int_div_work_24, - WILL_FIRE_RL_int_div_work_25, - WILL_FIRE_RL_int_div_work_26, - WILL_FIRE_RL_int_div_work_27, - WILL_FIRE_RL_int_div_work_28, - WILL_FIRE_RL_int_div_work_29, - WILL_FIRE_RL_int_div_work_3, - WILL_FIRE_RL_int_div_work_30, - WILL_FIRE_RL_int_div_work_31, - WILL_FIRE_RL_int_div_work_32, - WILL_FIRE_RL_int_div_work_33, - WILL_FIRE_RL_int_div_work_34, - WILL_FIRE_RL_int_div_work_35, - WILL_FIRE_RL_int_div_work_36, - WILL_FIRE_RL_int_div_work_37, - WILL_FIRE_RL_int_div_work_38, - WILL_FIRE_RL_int_div_work_39, - WILL_FIRE_RL_int_div_work_4, - WILL_FIRE_RL_int_div_work_40, - WILL_FIRE_RL_int_div_work_41, - WILL_FIRE_RL_int_div_work_42, - WILL_FIRE_RL_int_div_work_43, - WILL_FIRE_RL_int_div_work_44, - WILL_FIRE_RL_int_div_work_45, - WILL_FIRE_RL_int_div_work_46, - WILL_FIRE_RL_int_div_work_47, - WILL_FIRE_RL_int_div_work_48, - WILL_FIRE_RL_int_div_work_49, - WILL_FIRE_RL_int_div_work_5, - WILL_FIRE_RL_int_div_work_50, - WILL_FIRE_RL_int_div_work_51, - WILL_FIRE_RL_int_div_work_52, - WILL_FIRE_RL_int_div_work_53, - WILL_FIRE_RL_int_div_work_54, - WILL_FIRE_RL_int_div_work_55, - WILL_FIRE_RL_int_div_work_56, - WILL_FIRE_RL_int_div_work_57, - WILL_FIRE_RL_int_div_work_6, - WILL_FIRE_RL_int_div_work_7, - WILL_FIRE_RL_int_div_work_8, - WILL_FIRE_RL_int_div_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; - // remaining internal signals - reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16; - reg [62 : 0] CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12; - reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, - _theResult___fst_sfd__h37218, - _theResult___fst_sfd__h37707, - _theResult___fst_sfd__h60989; - reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9, - _theResult___fst_exp__h37217, - _theResult___fst_exp__h60988; - reg CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5, - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11; - wire [115 : 0] b__h10163, - b__h10487, - b__h10811, - b__h1091, - b__h11135, - b__h11459, - b__h11783, - b__h12107, - b__h12431, - b__h12755, - b__h13079, - b__h13403, - b__h13727, - b__h14051, - b__h1415, - b__h14375, - b__h14699, - b__h15023, - b__h15347, - b__h15671, - b__h15995, - b__h16319, - b__h16643, - b__h16967, - b__h17291, - b__h1739, - b__h17615, - b__h17939, - b__h18263, - b__h18587, - b__h18911, - b__h19235, - b__h19482, - b__h2063, - b__h2387, - b__h2711, - b__h3035, - b__h3359, - b__h3683, - b__h4007, - b__h4331, - b__h4655, - b__h4979, - b__h5303, - b__h5627, - b__h5951, - b__h6275, - b__h6599, - b__h6923, - b__h7247, - b__h7571, - b__h767, - b__h7895, - b__h8219, - b__h8543, - b__h8867, - b__h9191, - b__h9515, - b__h9839, - value__h19447; - wire [113 : 0] x__h49176; - wire [63 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305, - fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773; - wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7, - IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19, - _theResult____h50063, - _theResult___snd__h52150, - _theResult___snd__h59785, - _theResult___snd__h59800, - _theResult___snd__h59802, - _theResult___snd__h59815, - _theResult___snd__h59821, - _theResult___snd__h59839, - _theResult___snd__h59844, - _theResult___snd_snd_snd__h51398, - b__h378, - int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945, - result__h50077, - result__h50108, - result__h50258, - sfdin__h51553, - sfdin__h59762, - x__h50197, - x__h50487; - wire [56 : 0] value__h50121, x__h49237; - wire [53 : 0] sfd__h60417, value__h49179; - wire [52 : 0] sfdA__h19785, sfdA__h19789, sfdB__h19786, sfdB__h19791; - wire [51 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303, - _theResult___fst_sfd__h60992, - _theResult___sfd__h60911, - _theResult___snd_fst_sfd__h49112, - out_sfd__h60914, - sfd__h36684, - sfd__h36687; - wire [12 : 0] IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205, - value__h49124, - value__h49300; - wire [11 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726; - wire [10 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, - IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, - _theResult___exp__h60910, - _theResult___fst__h49072, - _theResult___fst_exp__h59719, - _theResult___fst_exp__h59722, - _theResult___fst_exp__h59725, - _theResult___fst_exp__h59768, - _theResult___fst_exp__h59771, - _theResult___fst_exp__h59791, - _theResult___fst_exp__h59807, - _theResult___fst_exp__h59846, - _theResult___fst_exp__h59852, - _theResult___fst_exp__h59855, - _theResult___fst_exp__h60991, - _theResult___snd_fst_exp__h49084, - _theResult___snd_fst_exp__h49087, - _theResult___snd_fst_exp__h49111, - din_inc___2_exp__h61001, - fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3, - fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4, - out_exp__h60913, - theResult___fst_exp9725_MINUS_1023__q6, - x__h49291, - x__h50204; - wire [5 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724, - b__h21789, - b__h29207; - wire [4 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765; - wire [1 : 0] IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8, - _theResult___snd_fst__h59874, - guard__h51381, - x__h60140; - wire IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208, - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352, - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441, - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253, - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, - _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351, - fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212, - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, - sfdlsb__h50103; - // action method request_put - assign RDY_request_put = fpu_fOperands_S0$FULL_N ; - assign CAN_FIRE_request_put = fpu_fOperands_S0$FULL_N ; + assign RDY_request_put = fpu$RDY_request_put ; + assign CAN_FIRE_request_put = fpu$RDY_request_put ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu_fResult_S5$D_OUT ; - assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; - assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; + assign response_get = fpu$response_get ; + assign RDY_response_get = fpu$RDY_response_get ; + assign CAN_FIRE_response_get = fpu$RDY_response_get ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu_fOperands_S0 - FIFOL1 #(.width(32'd131)) fpu_fOperands_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fOperands_S0$D_IN), - .ENQ(fpu_fOperands_S0$ENQ), - .DEQ(fpu_fOperands_S0$DEQ), - .CLR(fpu_fOperands_S0$CLR), - .D_OUT(fpu_fOperands_S0$D_OUT), - .FULL_N(fpu_fOperands_S0$FULL_N), - .EMPTY_N(fpu_fOperands_S0$EMPTY_N)); - - // submodule fpu_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fResult_S5$D_IN), - .ENQ(fpu_fResult_S5$ENQ), - .DEQ(fpu_fResult_S5$DEQ), - .CLR(fpu_fResult_S5$CLR), - .D_OUT(fpu_fResult_S5$D_OUT), - .FULL_N(fpu_fResult_S5$FULL_N), - .EMPTY_N(fpu_fResult_S5$EMPTY_N)); - - // submodule fpu_fState_S1 - FIFOL1 #(.width(32'd319)) fpu_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S1$D_IN), - .ENQ(fpu_fState_S1$ENQ), - .DEQ(fpu_fState_S1$DEQ), - .CLR(fpu_fState_S1$CLR), - .D_OUT(fpu_fState_S1$D_OUT), - .FULL_N(fpu_fState_S1$FULL_N), - .EMPTY_N(fpu_fState_S1$EMPTY_N)); - - // submodule fpu_fState_S2 - FIFOL1 #(.width(32'd148)) fpu_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S2$D_IN), - .ENQ(fpu_fState_S2$ENQ), - .DEQ(fpu_fState_S2$DEQ), - .CLR(fpu_fState_S2$CLR), - .D_OUT(fpu_fState_S2$D_OUT), - .FULL_N(fpu_fState_S2$FULL_N), - .EMPTY_N(fpu_fState_S2$EMPTY_N)); - - // submodule fpu_fState_S3 - FIFOL1 #(.width(32'd195)) fpu_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S3$D_IN), - .ENQ(fpu_fState_S3$ENQ), - .DEQ(fpu_fState_S3$DEQ), - .CLR(fpu_fState_S3$CLR), - .D_OUT(fpu_fState_S3$D_OUT), - .FULL_N(fpu_fState_S3$FULL_N), - .EMPTY_N(fpu_fState_S3$EMPTY_N)); - - // submodule fpu_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S4$D_IN), - .ENQ(fpu_fState_S4$ENQ), - .DEQ(fpu_fState_S4$DEQ), - .CLR(fpu_fState_S4$CLR), - .D_OUT(fpu_fState_S4$D_OUT), - .FULL_N(fpu_fState_S4$FULL_N), - .EMPTY_N(fpu_fState_S4$EMPTY_N)); - - // submodule int_div_fFirst - FIFOL1 #(.width(32'd232)) int_div_fFirst(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fFirst$D_IN), - .ENQ(int_div_fFirst$ENQ), - .DEQ(int_div_fFirst$DEQ), - .CLR(int_div_fFirst$CLR), - .D_OUT(int_div_fFirst$D_OUT), - .FULL_N(int_div_fFirst$FULL_N), - .EMPTY_N(int_div_fFirst$EMPTY_N)); - - // submodule int_div_fNext_0 - FIFOL1 #(.width(32'd232)) int_div_fNext_0(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_0$D_IN), - .ENQ(int_div_fNext_0$ENQ), - .DEQ(int_div_fNext_0$DEQ), - .CLR(int_div_fNext_0$CLR), - .D_OUT(int_div_fNext_0$D_OUT), - .FULL_N(int_div_fNext_0$FULL_N), - .EMPTY_N(int_div_fNext_0$EMPTY_N)); - - // submodule int_div_fNext_1 - FIFOL1 #(.width(32'd232)) int_div_fNext_1(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_1$D_IN), - .ENQ(int_div_fNext_1$ENQ), - .DEQ(int_div_fNext_1$DEQ), - .CLR(int_div_fNext_1$CLR), - .D_OUT(int_div_fNext_1$D_OUT), - .FULL_N(int_div_fNext_1$FULL_N), - .EMPTY_N(int_div_fNext_1$EMPTY_N)); - - // submodule int_div_fNext_10 - FIFOL1 #(.width(32'd232)) int_div_fNext_10(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_10$D_IN), - .ENQ(int_div_fNext_10$ENQ), - .DEQ(int_div_fNext_10$DEQ), - .CLR(int_div_fNext_10$CLR), - .D_OUT(int_div_fNext_10$D_OUT), - .FULL_N(int_div_fNext_10$FULL_N), - .EMPTY_N(int_div_fNext_10$EMPTY_N)); - - // submodule int_div_fNext_11 - FIFOL1 #(.width(32'd232)) int_div_fNext_11(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_11$D_IN), - .ENQ(int_div_fNext_11$ENQ), - .DEQ(int_div_fNext_11$DEQ), - .CLR(int_div_fNext_11$CLR), - .D_OUT(int_div_fNext_11$D_OUT), - .FULL_N(int_div_fNext_11$FULL_N), - .EMPTY_N(int_div_fNext_11$EMPTY_N)); - - // submodule int_div_fNext_12 - FIFOL1 #(.width(32'd232)) int_div_fNext_12(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_12$D_IN), - .ENQ(int_div_fNext_12$ENQ), - .DEQ(int_div_fNext_12$DEQ), - .CLR(int_div_fNext_12$CLR), - .D_OUT(int_div_fNext_12$D_OUT), - .FULL_N(int_div_fNext_12$FULL_N), - .EMPTY_N(int_div_fNext_12$EMPTY_N)); - - // submodule int_div_fNext_13 - FIFOL1 #(.width(32'd232)) int_div_fNext_13(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_13$D_IN), - .ENQ(int_div_fNext_13$ENQ), - .DEQ(int_div_fNext_13$DEQ), - .CLR(int_div_fNext_13$CLR), - .D_OUT(int_div_fNext_13$D_OUT), - .FULL_N(int_div_fNext_13$FULL_N), - .EMPTY_N(int_div_fNext_13$EMPTY_N)); - - // submodule int_div_fNext_14 - FIFOL1 #(.width(32'd232)) int_div_fNext_14(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_14$D_IN), - .ENQ(int_div_fNext_14$ENQ), - .DEQ(int_div_fNext_14$DEQ), - .CLR(int_div_fNext_14$CLR), - .D_OUT(int_div_fNext_14$D_OUT), - .FULL_N(int_div_fNext_14$FULL_N), - .EMPTY_N(int_div_fNext_14$EMPTY_N)); - - // submodule int_div_fNext_15 - FIFOL1 #(.width(32'd232)) int_div_fNext_15(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_15$D_IN), - .ENQ(int_div_fNext_15$ENQ), - .DEQ(int_div_fNext_15$DEQ), - .CLR(int_div_fNext_15$CLR), - .D_OUT(int_div_fNext_15$D_OUT), - .FULL_N(int_div_fNext_15$FULL_N), - .EMPTY_N(int_div_fNext_15$EMPTY_N)); - - // submodule int_div_fNext_16 - FIFOL1 #(.width(32'd232)) int_div_fNext_16(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_16$D_IN), - .ENQ(int_div_fNext_16$ENQ), - .DEQ(int_div_fNext_16$DEQ), - .CLR(int_div_fNext_16$CLR), - .D_OUT(int_div_fNext_16$D_OUT), - .FULL_N(int_div_fNext_16$FULL_N), - .EMPTY_N(int_div_fNext_16$EMPTY_N)); - - // submodule int_div_fNext_17 - FIFOL1 #(.width(32'd232)) int_div_fNext_17(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_17$D_IN), - .ENQ(int_div_fNext_17$ENQ), - .DEQ(int_div_fNext_17$DEQ), - .CLR(int_div_fNext_17$CLR), - .D_OUT(int_div_fNext_17$D_OUT), - .FULL_N(int_div_fNext_17$FULL_N), - .EMPTY_N(int_div_fNext_17$EMPTY_N)); - - // submodule int_div_fNext_18 - FIFOL1 #(.width(32'd232)) int_div_fNext_18(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_18$D_IN), - .ENQ(int_div_fNext_18$ENQ), - .DEQ(int_div_fNext_18$DEQ), - .CLR(int_div_fNext_18$CLR), - .D_OUT(int_div_fNext_18$D_OUT), - .FULL_N(int_div_fNext_18$FULL_N), - .EMPTY_N(int_div_fNext_18$EMPTY_N)); - - // submodule int_div_fNext_19 - FIFOL1 #(.width(32'd232)) int_div_fNext_19(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_19$D_IN), - .ENQ(int_div_fNext_19$ENQ), - .DEQ(int_div_fNext_19$DEQ), - .CLR(int_div_fNext_19$CLR), - .D_OUT(int_div_fNext_19$D_OUT), - .FULL_N(int_div_fNext_19$FULL_N), - .EMPTY_N(int_div_fNext_19$EMPTY_N)); - - // submodule int_div_fNext_2 - FIFOL1 #(.width(32'd232)) int_div_fNext_2(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_2$D_IN), - .ENQ(int_div_fNext_2$ENQ), - .DEQ(int_div_fNext_2$DEQ), - .CLR(int_div_fNext_2$CLR), - .D_OUT(int_div_fNext_2$D_OUT), - .FULL_N(int_div_fNext_2$FULL_N), - .EMPTY_N(int_div_fNext_2$EMPTY_N)); - - // submodule int_div_fNext_20 - FIFOL1 #(.width(32'd232)) int_div_fNext_20(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_20$D_IN), - .ENQ(int_div_fNext_20$ENQ), - .DEQ(int_div_fNext_20$DEQ), - .CLR(int_div_fNext_20$CLR), - .D_OUT(int_div_fNext_20$D_OUT), - .FULL_N(int_div_fNext_20$FULL_N), - .EMPTY_N(int_div_fNext_20$EMPTY_N)); - - // submodule int_div_fNext_21 - FIFOL1 #(.width(32'd232)) int_div_fNext_21(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_21$D_IN), - .ENQ(int_div_fNext_21$ENQ), - .DEQ(int_div_fNext_21$DEQ), - .CLR(int_div_fNext_21$CLR), - .D_OUT(int_div_fNext_21$D_OUT), - .FULL_N(int_div_fNext_21$FULL_N), - .EMPTY_N(int_div_fNext_21$EMPTY_N)); - - // submodule int_div_fNext_22 - FIFOL1 #(.width(32'd232)) int_div_fNext_22(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_22$D_IN), - .ENQ(int_div_fNext_22$ENQ), - .DEQ(int_div_fNext_22$DEQ), - .CLR(int_div_fNext_22$CLR), - .D_OUT(int_div_fNext_22$D_OUT), - .FULL_N(int_div_fNext_22$FULL_N), - .EMPTY_N(int_div_fNext_22$EMPTY_N)); - - // submodule int_div_fNext_23 - FIFOL1 #(.width(32'd232)) int_div_fNext_23(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_23$D_IN), - .ENQ(int_div_fNext_23$ENQ), - .DEQ(int_div_fNext_23$DEQ), - .CLR(int_div_fNext_23$CLR), - .D_OUT(int_div_fNext_23$D_OUT), - .FULL_N(int_div_fNext_23$FULL_N), - .EMPTY_N(int_div_fNext_23$EMPTY_N)); - - // submodule int_div_fNext_24 - FIFOL1 #(.width(32'd232)) int_div_fNext_24(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_24$D_IN), - .ENQ(int_div_fNext_24$ENQ), - .DEQ(int_div_fNext_24$DEQ), - .CLR(int_div_fNext_24$CLR), - .D_OUT(int_div_fNext_24$D_OUT), - .FULL_N(int_div_fNext_24$FULL_N), - .EMPTY_N(int_div_fNext_24$EMPTY_N)); - - // submodule int_div_fNext_25 - FIFOL1 #(.width(32'd232)) int_div_fNext_25(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_25$D_IN), - .ENQ(int_div_fNext_25$ENQ), - .DEQ(int_div_fNext_25$DEQ), - .CLR(int_div_fNext_25$CLR), - .D_OUT(int_div_fNext_25$D_OUT), - .FULL_N(int_div_fNext_25$FULL_N), - .EMPTY_N(int_div_fNext_25$EMPTY_N)); - - // submodule int_div_fNext_26 - FIFOL1 #(.width(32'd232)) int_div_fNext_26(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_26$D_IN), - .ENQ(int_div_fNext_26$ENQ), - .DEQ(int_div_fNext_26$DEQ), - .CLR(int_div_fNext_26$CLR), - .D_OUT(int_div_fNext_26$D_OUT), - .FULL_N(int_div_fNext_26$FULL_N), - .EMPTY_N(int_div_fNext_26$EMPTY_N)); - - // submodule int_div_fNext_27 - FIFOL1 #(.width(32'd232)) int_div_fNext_27(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_27$D_IN), - .ENQ(int_div_fNext_27$ENQ), - .DEQ(int_div_fNext_27$DEQ), - .CLR(int_div_fNext_27$CLR), - .D_OUT(int_div_fNext_27$D_OUT), - .FULL_N(int_div_fNext_27$FULL_N), - .EMPTY_N(int_div_fNext_27$EMPTY_N)); - - // submodule int_div_fNext_28 - FIFOL1 #(.width(32'd232)) int_div_fNext_28(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_28$D_IN), - .ENQ(int_div_fNext_28$ENQ), - .DEQ(int_div_fNext_28$DEQ), - .CLR(int_div_fNext_28$CLR), - .D_OUT(int_div_fNext_28$D_OUT), - .FULL_N(int_div_fNext_28$FULL_N), - .EMPTY_N(int_div_fNext_28$EMPTY_N)); - - // submodule int_div_fNext_29 - FIFOL1 #(.width(32'd232)) int_div_fNext_29(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_29$D_IN), - .ENQ(int_div_fNext_29$ENQ), - .DEQ(int_div_fNext_29$DEQ), - .CLR(int_div_fNext_29$CLR), - .D_OUT(int_div_fNext_29$D_OUT), - .FULL_N(int_div_fNext_29$FULL_N), - .EMPTY_N(int_div_fNext_29$EMPTY_N)); - - // submodule int_div_fNext_3 - FIFOL1 #(.width(32'd232)) int_div_fNext_3(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_3$D_IN), - .ENQ(int_div_fNext_3$ENQ), - .DEQ(int_div_fNext_3$DEQ), - .CLR(int_div_fNext_3$CLR), - .D_OUT(int_div_fNext_3$D_OUT), - .FULL_N(int_div_fNext_3$FULL_N), - .EMPTY_N(int_div_fNext_3$EMPTY_N)); - - // submodule int_div_fNext_30 - FIFOL1 #(.width(32'd232)) int_div_fNext_30(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_30$D_IN), - .ENQ(int_div_fNext_30$ENQ), - .DEQ(int_div_fNext_30$DEQ), - .CLR(int_div_fNext_30$CLR), - .D_OUT(int_div_fNext_30$D_OUT), - .FULL_N(int_div_fNext_30$FULL_N), - .EMPTY_N(int_div_fNext_30$EMPTY_N)); - - // submodule int_div_fNext_31 - FIFOL1 #(.width(32'd232)) int_div_fNext_31(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_31$D_IN), - .ENQ(int_div_fNext_31$ENQ), - .DEQ(int_div_fNext_31$DEQ), - .CLR(int_div_fNext_31$CLR), - .D_OUT(int_div_fNext_31$D_OUT), - .FULL_N(int_div_fNext_31$FULL_N), - .EMPTY_N(int_div_fNext_31$EMPTY_N)); - - // submodule int_div_fNext_32 - FIFOL1 #(.width(32'd232)) int_div_fNext_32(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_32$D_IN), - .ENQ(int_div_fNext_32$ENQ), - .DEQ(int_div_fNext_32$DEQ), - .CLR(int_div_fNext_32$CLR), - .D_OUT(int_div_fNext_32$D_OUT), - .FULL_N(int_div_fNext_32$FULL_N), - .EMPTY_N(int_div_fNext_32$EMPTY_N)); - - // submodule int_div_fNext_33 - FIFOL1 #(.width(32'd232)) int_div_fNext_33(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_33$D_IN), - .ENQ(int_div_fNext_33$ENQ), - .DEQ(int_div_fNext_33$DEQ), - .CLR(int_div_fNext_33$CLR), - .D_OUT(int_div_fNext_33$D_OUT), - .FULL_N(int_div_fNext_33$FULL_N), - .EMPTY_N(int_div_fNext_33$EMPTY_N)); - - // submodule int_div_fNext_34 - FIFOL1 #(.width(32'd232)) int_div_fNext_34(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_34$D_IN), - .ENQ(int_div_fNext_34$ENQ), - .DEQ(int_div_fNext_34$DEQ), - .CLR(int_div_fNext_34$CLR), - .D_OUT(int_div_fNext_34$D_OUT), - .FULL_N(int_div_fNext_34$FULL_N), - .EMPTY_N(int_div_fNext_34$EMPTY_N)); - - // submodule int_div_fNext_35 - FIFOL1 #(.width(32'd232)) int_div_fNext_35(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_35$D_IN), - .ENQ(int_div_fNext_35$ENQ), - .DEQ(int_div_fNext_35$DEQ), - .CLR(int_div_fNext_35$CLR), - .D_OUT(int_div_fNext_35$D_OUT), - .FULL_N(int_div_fNext_35$FULL_N), - .EMPTY_N(int_div_fNext_35$EMPTY_N)); - - // submodule int_div_fNext_36 - FIFOL1 #(.width(32'd232)) int_div_fNext_36(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_36$D_IN), - .ENQ(int_div_fNext_36$ENQ), - .DEQ(int_div_fNext_36$DEQ), - .CLR(int_div_fNext_36$CLR), - .D_OUT(int_div_fNext_36$D_OUT), - .FULL_N(int_div_fNext_36$FULL_N), - .EMPTY_N(int_div_fNext_36$EMPTY_N)); - - // submodule int_div_fNext_37 - FIFOL1 #(.width(32'd232)) int_div_fNext_37(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_37$D_IN), - .ENQ(int_div_fNext_37$ENQ), - .DEQ(int_div_fNext_37$DEQ), - .CLR(int_div_fNext_37$CLR), - .D_OUT(int_div_fNext_37$D_OUT), - .FULL_N(int_div_fNext_37$FULL_N), - .EMPTY_N(int_div_fNext_37$EMPTY_N)); - - // submodule int_div_fNext_38 - FIFOL1 #(.width(32'd232)) int_div_fNext_38(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_38$D_IN), - .ENQ(int_div_fNext_38$ENQ), - .DEQ(int_div_fNext_38$DEQ), - .CLR(int_div_fNext_38$CLR), - .D_OUT(int_div_fNext_38$D_OUT), - .FULL_N(int_div_fNext_38$FULL_N), - .EMPTY_N(int_div_fNext_38$EMPTY_N)); - - // submodule int_div_fNext_39 - FIFOL1 #(.width(32'd232)) int_div_fNext_39(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_39$D_IN), - .ENQ(int_div_fNext_39$ENQ), - .DEQ(int_div_fNext_39$DEQ), - .CLR(int_div_fNext_39$CLR), - .D_OUT(int_div_fNext_39$D_OUT), - .FULL_N(int_div_fNext_39$FULL_N), - .EMPTY_N(int_div_fNext_39$EMPTY_N)); - - // submodule int_div_fNext_4 - FIFOL1 #(.width(32'd232)) int_div_fNext_4(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_4$D_IN), - .ENQ(int_div_fNext_4$ENQ), - .DEQ(int_div_fNext_4$DEQ), - .CLR(int_div_fNext_4$CLR), - .D_OUT(int_div_fNext_4$D_OUT), - .FULL_N(int_div_fNext_4$FULL_N), - .EMPTY_N(int_div_fNext_4$EMPTY_N)); - - // submodule int_div_fNext_40 - FIFOL1 #(.width(32'd232)) int_div_fNext_40(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_40$D_IN), - .ENQ(int_div_fNext_40$ENQ), - .DEQ(int_div_fNext_40$DEQ), - .CLR(int_div_fNext_40$CLR), - .D_OUT(int_div_fNext_40$D_OUT), - .FULL_N(int_div_fNext_40$FULL_N), - .EMPTY_N(int_div_fNext_40$EMPTY_N)); - - // submodule int_div_fNext_41 - FIFOL1 #(.width(32'd232)) int_div_fNext_41(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_41$D_IN), - .ENQ(int_div_fNext_41$ENQ), - .DEQ(int_div_fNext_41$DEQ), - .CLR(int_div_fNext_41$CLR), - .D_OUT(int_div_fNext_41$D_OUT), - .FULL_N(int_div_fNext_41$FULL_N), - .EMPTY_N(int_div_fNext_41$EMPTY_N)); - - // submodule int_div_fNext_42 - FIFOL1 #(.width(32'd232)) int_div_fNext_42(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_42$D_IN), - .ENQ(int_div_fNext_42$ENQ), - .DEQ(int_div_fNext_42$DEQ), - .CLR(int_div_fNext_42$CLR), - .D_OUT(int_div_fNext_42$D_OUT), - .FULL_N(int_div_fNext_42$FULL_N), - .EMPTY_N(int_div_fNext_42$EMPTY_N)); - - // submodule int_div_fNext_43 - FIFOL1 #(.width(32'd232)) int_div_fNext_43(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_43$D_IN), - .ENQ(int_div_fNext_43$ENQ), - .DEQ(int_div_fNext_43$DEQ), - .CLR(int_div_fNext_43$CLR), - .D_OUT(int_div_fNext_43$D_OUT), - .FULL_N(int_div_fNext_43$FULL_N), - .EMPTY_N(int_div_fNext_43$EMPTY_N)); - - // submodule int_div_fNext_44 - FIFOL1 #(.width(32'd232)) int_div_fNext_44(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_44$D_IN), - .ENQ(int_div_fNext_44$ENQ), - .DEQ(int_div_fNext_44$DEQ), - .CLR(int_div_fNext_44$CLR), - .D_OUT(int_div_fNext_44$D_OUT), - .FULL_N(int_div_fNext_44$FULL_N), - .EMPTY_N(int_div_fNext_44$EMPTY_N)); - - // submodule int_div_fNext_45 - FIFOL1 #(.width(32'd232)) int_div_fNext_45(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_45$D_IN), - .ENQ(int_div_fNext_45$ENQ), - .DEQ(int_div_fNext_45$DEQ), - .CLR(int_div_fNext_45$CLR), - .D_OUT(int_div_fNext_45$D_OUT), - .FULL_N(int_div_fNext_45$FULL_N), - .EMPTY_N(int_div_fNext_45$EMPTY_N)); - - // submodule int_div_fNext_46 - FIFOL1 #(.width(32'd232)) int_div_fNext_46(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_46$D_IN), - .ENQ(int_div_fNext_46$ENQ), - .DEQ(int_div_fNext_46$DEQ), - .CLR(int_div_fNext_46$CLR), - .D_OUT(int_div_fNext_46$D_OUT), - .FULL_N(int_div_fNext_46$FULL_N), - .EMPTY_N(int_div_fNext_46$EMPTY_N)); - - // submodule int_div_fNext_47 - FIFOL1 #(.width(32'd232)) int_div_fNext_47(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_47$D_IN), - .ENQ(int_div_fNext_47$ENQ), - .DEQ(int_div_fNext_47$DEQ), - .CLR(int_div_fNext_47$CLR), - .D_OUT(int_div_fNext_47$D_OUT), - .FULL_N(int_div_fNext_47$FULL_N), - .EMPTY_N(int_div_fNext_47$EMPTY_N)); - - // submodule int_div_fNext_48 - FIFOL1 #(.width(32'd232)) int_div_fNext_48(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_48$D_IN), - .ENQ(int_div_fNext_48$ENQ), - .DEQ(int_div_fNext_48$DEQ), - .CLR(int_div_fNext_48$CLR), - .D_OUT(int_div_fNext_48$D_OUT), - .FULL_N(int_div_fNext_48$FULL_N), - .EMPTY_N(int_div_fNext_48$EMPTY_N)); - - // submodule int_div_fNext_49 - FIFOL1 #(.width(32'd232)) int_div_fNext_49(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_49$D_IN), - .ENQ(int_div_fNext_49$ENQ), - .DEQ(int_div_fNext_49$DEQ), - .CLR(int_div_fNext_49$CLR), - .D_OUT(int_div_fNext_49$D_OUT), - .FULL_N(int_div_fNext_49$FULL_N), - .EMPTY_N(int_div_fNext_49$EMPTY_N)); - - // submodule int_div_fNext_5 - FIFOL1 #(.width(32'd232)) int_div_fNext_5(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_5$D_IN), - .ENQ(int_div_fNext_5$ENQ), - .DEQ(int_div_fNext_5$DEQ), - .CLR(int_div_fNext_5$CLR), - .D_OUT(int_div_fNext_5$D_OUT), - .FULL_N(int_div_fNext_5$FULL_N), - .EMPTY_N(int_div_fNext_5$EMPTY_N)); - - // submodule int_div_fNext_50 - FIFOL1 #(.width(32'd232)) int_div_fNext_50(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_50$D_IN), - .ENQ(int_div_fNext_50$ENQ), - .DEQ(int_div_fNext_50$DEQ), - .CLR(int_div_fNext_50$CLR), - .D_OUT(int_div_fNext_50$D_OUT), - .FULL_N(int_div_fNext_50$FULL_N), - .EMPTY_N(int_div_fNext_50$EMPTY_N)); - - // submodule int_div_fNext_51 - FIFOL1 #(.width(32'd232)) int_div_fNext_51(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_51$D_IN), - .ENQ(int_div_fNext_51$ENQ), - .DEQ(int_div_fNext_51$DEQ), - .CLR(int_div_fNext_51$CLR), - .D_OUT(int_div_fNext_51$D_OUT), - .FULL_N(int_div_fNext_51$FULL_N), - .EMPTY_N(int_div_fNext_51$EMPTY_N)); - - // submodule int_div_fNext_52 - FIFOL1 #(.width(32'd232)) int_div_fNext_52(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_52$D_IN), - .ENQ(int_div_fNext_52$ENQ), - .DEQ(int_div_fNext_52$DEQ), - .CLR(int_div_fNext_52$CLR), - .D_OUT(int_div_fNext_52$D_OUT), - .FULL_N(int_div_fNext_52$FULL_N), - .EMPTY_N(int_div_fNext_52$EMPTY_N)); - - // submodule int_div_fNext_53 - FIFOL1 #(.width(32'd232)) int_div_fNext_53(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_53$D_IN), - .ENQ(int_div_fNext_53$ENQ), - .DEQ(int_div_fNext_53$DEQ), - .CLR(int_div_fNext_53$CLR), - .D_OUT(int_div_fNext_53$D_OUT), - .FULL_N(int_div_fNext_53$FULL_N), - .EMPTY_N(int_div_fNext_53$EMPTY_N)); - - // submodule int_div_fNext_54 - FIFOL1 #(.width(32'd232)) int_div_fNext_54(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_54$D_IN), - .ENQ(int_div_fNext_54$ENQ), - .DEQ(int_div_fNext_54$DEQ), - .CLR(int_div_fNext_54$CLR), - .D_OUT(int_div_fNext_54$D_OUT), - .FULL_N(int_div_fNext_54$FULL_N), - .EMPTY_N(int_div_fNext_54$EMPTY_N)); - - // submodule int_div_fNext_55 - FIFOL1 #(.width(32'd232)) int_div_fNext_55(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_55$D_IN), - .ENQ(int_div_fNext_55$ENQ), - .DEQ(int_div_fNext_55$DEQ), - .CLR(int_div_fNext_55$CLR), - .D_OUT(int_div_fNext_55$D_OUT), - .FULL_N(int_div_fNext_55$FULL_N), - .EMPTY_N(int_div_fNext_55$EMPTY_N)); - - // submodule int_div_fNext_56 - FIFOL1 #(.width(32'd232)) int_div_fNext_56(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_56$D_IN), - .ENQ(int_div_fNext_56$ENQ), - .DEQ(int_div_fNext_56$DEQ), - .CLR(int_div_fNext_56$CLR), - .D_OUT(int_div_fNext_56$D_OUT), - .FULL_N(int_div_fNext_56$FULL_N), - .EMPTY_N(int_div_fNext_56$EMPTY_N)); - - // submodule int_div_fNext_57 - FIFOL1 #(.width(32'd232)) int_div_fNext_57(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_57$D_IN), - .ENQ(int_div_fNext_57$ENQ), - .DEQ(int_div_fNext_57$DEQ), - .CLR(int_div_fNext_57$CLR), - .D_OUT(int_div_fNext_57$D_OUT), - .FULL_N(int_div_fNext_57$FULL_N), - .EMPTY_N(int_div_fNext_57$EMPTY_N)); - - // submodule int_div_fNext_6 - FIFOL1 #(.width(32'd232)) int_div_fNext_6(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_6$D_IN), - .ENQ(int_div_fNext_6$ENQ), - .DEQ(int_div_fNext_6$DEQ), - .CLR(int_div_fNext_6$CLR), - .D_OUT(int_div_fNext_6$D_OUT), - .FULL_N(int_div_fNext_6$FULL_N), - .EMPTY_N(int_div_fNext_6$EMPTY_N)); - - // submodule int_div_fNext_7 - FIFOL1 #(.width(32'd232)) int_div_fNext_7(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_7$D_IN), - .ENQ(int_div_fNext_7$ENQ), - .DEQ(int_div_fNext_7$DEQ), - .CLR(int_div_fNext_7$CLR), - .D_OUT(int_div_fNext_7$D_OUT), - .FULL_N(int_div_fNext_7$FULL_N), - .EMPTY_N(int_div_fNext_7$EMPTY_N)); - - // submodule int_div_fNext_8 - FIFOL1 #(.width(32'd232)) int_div_fNext_8(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_8$D_IN), - .ENQ(int_div_fNext_8$ENQ), - .DEQ(int_div_fNext_8$DEQ), - .CLR(int_div_fNext_8$CLR), - .D_OUT(int_div_fNext_8$D_OUT), - .FULL_N(int_div_fNext_8$FULL_N), - .EMPTY_N(int_div_fNext_8$EMPTY_N)); - - // submodule int_div_fNext_9 - FIFOL1 #(.width(32'd232)) int_div_fNext_9(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fNext_9$D_IN), - .ENQ(int_div_fNext_9$ENQ), - .DEQ(int_div_fNext_9$DEQ), - .CLR(int_div_fNext_9$CLR), - .D_OUT(int_div_fNext_9$D_OUT), - .FULL_N(int_div_fNext_9$FULL_N), - .EMPTY_N(int_div_fNext_9$EMPTY_N)); - - // submodule int_div_fRequest - FIFOL1 #(.width(32'd171)) int_div_fRequest(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fRequest$D_IN), - .ENQ(int_div_fRequest$ENQ), - .DEQ(int_div_fRequest$DEQ), - .CLR(int_div_fRequest$CLR), - .D_OUT(int_div_fRequest$D_OUT), - .FULL_N(int_div_fRequest$FULL_N), - .EMPTY_N(int_div_fRequest$EMPTY_N)); - - // submodule int_div_fResponse - FIFOL1 #(.width(32'd114)) int_div_fResponse(.RST(RST_N), - .CLK(CLK), - .D_IN(int_div_fResponse$D_IN), - .ENQ(int_div_fResponse$ENQ), - .DEQ(int_div_fResponse$DEQ), - .CLR(int_div_fResponse$CLR), - .D_OUT(int_div_fResponse$D_OUT), - .FULL_N(int_div_fResponse$FULL_N), - .EMPTY_N(int_div_fResponse$EMPTY_N)); - - // rule RL_fpu_s5_stage - assign CAN_FIRE_RL_fpu_s5_stage = - fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; - - // rule RL_fpu_s4_stage - assign CAN_FIRE_RL_fpu_s4_stage = - fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; - - // rule RL_fpu_s3_stage - assign CAN_FIRE_RL_fpu_s3_stage = - fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && - (fpu_fState_S2$D_OUT[147] || int_div_fResponse$EMPTY_N) ; - assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; - - // rule RL_int_div_finish - assign CAN_FIRE_RL_int_div_finish = - int_div_fNext_57$EMPTY_N && int_div_fResponse$FULL_N ; - assign WILL_FIRE_RL_int_div_finish = CAN_FIRE_RL_int_div_finish ; - - // rule RL_int_div_work_57 - assign CAN_FIRE_RL_int_div_work_57 = - int_div_fNext_56$EMPTY_N && int_div_fNext_57$FULL_N ; - assign WILL_FIRE_RL_int_div_work_57 = CAN_FIRE_RL_int_div_work_57 ; - - // rule RL_int_div_work_56 - assign CAN_FIRE_RL_int_div_work_56 = - int_div_fNext_55$EMPTY_N && int_div_fNext_56$FULL_N ; - assign WILL_FIRE_RL_int_div_work_56 = CAN_FIRE_RL_int_div_work_56 ; - - // rule RL_int_div_work_55 - assign CAN_FIRE_RL_int_div_work_55 = - int_div_fNext_54$EMPTY_N && int_div_fNext_55$FULL_N ; - assign WILL_FIRE_RL_int_div_work_55 = CAN_FIRE_RL_int_div_work_55 ; - - // rule RL_int_div_work_54 - assign CAN_FIRE_RL_int_div_work_54 = - int_div_fNext_53$EMPTY_N && int_div_fNext_54$FULL_N ; - assign WILL_FIRE_RL_int_div_work_54 = CAN_FIRE_RL_int_div_work_54 ; - - // rule RL_int_div_work_53 - assign CAN_FIRE_RL_int_div_work_53 = - int_div_fNext_52$EMPTY_N && int_div_fNext_53$FULL_N ; - assign WILL_FIRE_RL_int_div_work_53 = CAN_FIRE_RL_int_div_work_53 ; - - // rule RL_int_div_work_52 - assign CAN_FIRE_RL_int_div_work_52 = - int_div_fNext_51$EMPTY_N && int_div_fNext_52$FULL_N ; - assign WILL_FIRE_RL_int_div_work_52 = CAN_FIRE_RL_int_div_work_52 ; - - // rule RL_int_div_work_51 - assign CAN_FIRE_RL_int_div_work_51 = - int_div_fNext_50$EMPTY_N && int_div_fNext_51$FULL_N ; - assign WILL_FIRE_RL_int_div_work_51 = CAN_FIRE_RL_int_div_work_51 ; - - // rule RL_int_div_work_50 - assign CAN_FIRE_RL_int_div_work_50 = - int_div_fNext_49$EMPTY_N && int_div_fNext_50$FULL_N ; - assign WILL_FIRE_RL_int_div_work_50 = CAN_FIRE_RL_int_div_work_50 ; - - // rule RL_int_div_work_49 - assign CAN_FIRE_RL_int_div_work_49 = - int_div_fNext_48$EMPTY_N && int_div_fNext_49$FULL_N ; - assign WILL_FIRE_RL_int_div_work_49 = CAN_FIRE_RL_int_div_work_49 ; - - // rule RL_int_div_work_48 - assign CAN_FIRE_RL_int_div_work_48 = - int_div_fNext_47$EMPTY_N && int_div_fNext_48$FULL_N ; - assign WILL_FIRE_RL_int_div_work_48 = CAN_FIRE_RL_int_div_work_48 ; - - // rule RL_int_div_work_47 - assign CAN_FIRE_RL_int_div_work_47 = - int_div_fNext_46$EMPTY_N && int_div_fNext_47$FULL_N ; - assign WILL_FIRE_RL_int_div_work_47 = CAN_FIRE_RL_int_div_work_47 ; - - // rule RL_int_div_work_46 - assign CAN_FIRE_RL_int_div_work_46 = - int_div_fNext_45$EMPTY_N && int_div_fNext_46$FULL_N ; - assign WILL_FIRE_RL_int_div_work_46 = CAN_FIRE_RL_int_div_work_46 ; - - // rule RL_int_div_work_45 - assign CAN_FIRE_RL_int_div_work_45 = - int_div_fNext_44$EMPTY_N && int_div_fNext_45$FULL_N ; - assign WILL_FIRE_RL_int_div_work_45 = CAN_FIRE_RL_int_div_work_45 ; - - // rule RL_int_div_work_44 - assign CAN_FIRE_RL_int_div_work_44 = - int_div_fNext_43$EMPTY_N && int_div_fNext_44$FULL_N ; - assign WILL_FIRE_RL_int_div_work_44 = CAN_FIRE_RL_int_div_work_44 ; - - // rule RL_int_div_work_43 - assign CAN_FIRE_RL_int_div_work_43 = - int_div_fNext_42$EMPTY_N && int_div_fNext_43$FULL_N ; - assign WILL_FIRE_RL_int_div_work_43 = CAN_FIRE_RL_int_div_work_43 ; - - // rule RL_int_div_work_42 - assign CAN_FIRE_RL_int_div_work_42 = - int_div_fNext_41$EMPTY_N && int_div_fNext_42$FULL_N ; - assign WILL_FIRE_RL_int_div_work_42 = CAN_FIRE_RL_int_div_work_42 ; - - // rule RL_int_div_work_41 - assign CAN_FIRE_RL_int_div_work_41 = - int_div_fNext_40$EMPTY_N && int_div_fNext_41$FULL_N ; - assign WILL_FIRE_RL_int_div_work_41 = CAN_FIRE_RL_int_div_work_41 ; - - // rule RL_int_div_work_40 - assign CAN_FIRE_RL_int_div_work_40 = - int_div_fNext_39$EMPTY_N && int_div_fNext_40$FULL_N ; - assign WILL_FIRE_RL_int_div_work_40 = CAN_FIRE_RL_int_div_work_40 ; - - // rule RL_int_div_work_39 - assign CAN_FIRE_RL_int_div_work_39 = - int_div_fNext_38$EMPTY_N && int_div_fNext_39$FULL_N ; - assign WILL_FIRE_RL_int_div_work_39 = CAN_FIRE_RL_int_div_work_39 ; - - // rule RL_int_div_work_38 - assign CAN_FIRE_RL_int_div_work_38 = - int_div_fNext_37$EMPTY_N && int_div_fNext_38$FULL_N ; - assign WILL_FIRE_RL_int_div_work_38 = CAN_FIRE_RL_int_div_work_38 ; - - // rule RL_int_div_work_37 - assign CAN_FIRE_RL_int_div_work_37 = - int_div_fNext_36$EMPTY_N && int_div_fNext_37$FULL_N ; - assign WILL_FIRE_RL_int_div_work_37 = CAN_FIRE_RL_int_div_work_37 ; - - // rule RL_int_div_work_36 - assign CAN_FIRE_RL_int_div_work_36 = - int_div_fNext_35$EMPTY_N && int_div_fNext_36$FULL_N ; - assign WILL_FIRE_RL_int_div_work_36 = CAN_FIRE_RL_int_div_work_36 ; - - // rule RL_int_div_work_35 - assign CAN_FIRE_RL_int_div_work_35 = - int_div_fNext_34$EMPTY_N && int_div_fNext_35$FULL_N ; - assign WILL_FIRE_RL_int_div_work_35 = CAN_FIRE_RL_int_div_work_35 ; - - // rule RL_int_div_work_34 - assign CAN_FIRE_RL_int_div_work_34 = - int_div_fNext_33$EMPTY_N && int_div_fNext_34$FULL_N ; - assign WILL_FIRE_RL_int_div_work_34 = CAN_FIRE_RL_int_div_work_34 ; - - // rule RL_int_div_work_33 - assign CAN_FIRE_RL_int_div_work_33 = - int_div_fNext_32$EMPTY_N && int_div_fNext_33$FULL_N ; - assign WILL_FIRE_RL_int_div_work_33 = CAN_FIRE_RL_int_div_work_33 ; - - // rule RL_int_div_work_32 - assign CAN_FIRE_RL_int_div_work_32 = - int_div_fNext_31$EMPTY_N && int_div_fNext_32$FULL_N ; - assign WILL_FIRE_RL_int_div_work_32 = CAN_FIRE_RL_int_div_work_32 ; - - // rule RL_int_div_work_31 - assign CAN_FIRE_RL_int_div_work_31 = - int_div_fNext_30$EMPTY_N && int_div_fNext_31$FULL_N ; - assign WILL_FIRE_RL_int_div_work_31 = CAN_FIRE_RL_int_div_work_31 ; - - // rule RL_int_div_work_30 - assign CAN_FIRE_RL_int_div_work_30 = - int_div_fNext_29$EMPTY_N && int_div_fNext_30$FULL_N ; - assign WILL_FIRE_RL_int_div_work_30 = CAN_FIRE_RL_int_div_work_30 ; - - // rule RL_int_div_work_29 - assign CAN_FIRE_RL_int_div_work_29 = - int_div_fNext_28$EMPTY_N && int_div_fNext_29$FULL_N ; - assign WILL_FIRE_RL_int_div_work_29 = CAN_FIRE_RL_int_div_work_29 ; - - // rule RL_int_div_work_28 - assign CAN_FIRE_RL_int_div_work_28 = - int_div_fNext_27$EMPTY_N && int_div_fNext_28$FULL_N ; - assign WILL_FIRE_RL_int_div_work_28 = CAN_FIRE_RL_int_div_work_28 ; - - // rule RL_int_div_work_27 - assign CAN_FIRE_RL_int_div_work_27 = - int_div_fNext_26$EMPTY_N && int_div_fNext_27$FULL_N ; - assign WILL_FIRE_RL_int_div_work_27 = CAN_FIRE_RL_int_div_work_27 ; - - // rule RL_int_div_work_26 - assign CAN_FIRE_RL_int_div_work_26 = - int_div_fNext_25$EMPTY_N && int_div_fNext_26$FULL_N ; - assign WILL_FIRE_RL_int_div_work_26 = CAN_FIRE_RL_int_div_work_26 ; - - // rule RL_int_div_work_25 - assign CAN_FIRE_RL_int_div_work_25 = - int_div_fNext_24$EMPTY_N && int_div_fNext_25$FULL_N ; - assign WILL_FIRE_RL_int_div_work_25 = CAN_FIRE_RL_int_div_work_25 ; - - // rule RL_int_div_work_24 - assign CAN_FIRE_RL_int_div_work_24 = - int_div_fNext_23$EMPTY_N && int_div_fNext_24$FULL_N ; - assign WILL_FIRE_RL_int_div_work_24 = CAN_FIRE_RL_int_div_work_24 ; - - // rule RL_int_div_work_23 - assign CAN_FIRE_RL_int_div_work_23 = - int_div_fNext_22$EMPTY_N && int_div_fNext_23$FULL_N ; - assign WILL_FIRE_RL_int_div_work_23 = CAN_FIRE_RL_int_div_work_23 ; - - // rule RL_int_div_work_22 - assign CAN_FIRE_RL_int_div_work_22 = - int_div_fNext_21$EMPTY_N && int_div_fNext_22$FULL_N ; - assign WILL_FIRE_RL_int_div_work_22 = CAN_FIRE_RL_int_div_work_22 ; - - // rule RL_int_div_work_21 - assign CAN_FIRE_RL_int_div_work_21 = - int_div_fNext_20$EMPTY_N && int_div_fNext_21$FULL_N ; - assign WILL_FIRE_RL_int_div_work_21 = CAN_FIRE_RL_int_div_work_21 ; - - // rule RL_int_div_work_20 - assign CAN_FIRE_RL_int_div_work_20 = - int_div_fNext_19$EMPTY_N && int_div_fNext_20$FULL_N ; - assign WILL_FIRE_RL_int_div_work_20 = CAN_FIRE_RL_int_div_work_20 ; - - // rule RL_int_div_work_19 - assign CAN_FIRE_RL_int_div_work_19 = - int_div_fNext_18$EMPTY_N && int_div_fNext_19$FULL_N ; - assign WILL_FIRE_RL_int_div_work_19 = CAN_FIRE_RL_int_div_work_19 ; - - // rule RL_int_div_work_18 - assign CAN_FIRE_RL_int_div_work_18 = - int_div_fNext_17$EMPTY_N && int_div_fNext_18$FULL_N ; - assign WILL_FIRE_RL_int_div_work_18 = CAN_FIRE_RL_int_div_work_18 ; - - // rule RL_int_div_work_17 - assign CAN_FIRE_RL_int_div_work_17 = - int_div_fNext_16$EMPTY_N && int_div_fNext_17$FULL_N ; - assign WILL_FIRE_RL_int_div_work_17 = CAN_FIRE_RL_int_div_work_17 ; - - // rule RL_int_div_work_16 - assign CAN_FIRE_RL_int_div_work_16 = - int_div_fNext_15$EMPTY_N && int_div_fNext_16$FULL_N ; - assign WILL_FIRE_RL_int_div_work_16 = CAN_FIRE_RL_int_div_work_16 ; - - // rule RL_int_div_work_15 - assign CAN_FIRE_RL_int_div_work_15 = - int_div_fNext_14$EMPTY_N && int_div_fNext_15$FULL_N ; - assign WILL_FIRE_RL_int_div_work_15 = CAN_FIRE_RL_int_div_work_15 ; - - // rule RL_int_div_work_14 - assign CAN_FIRE_RL_int_div_work_14 = - int_div_fNext_13$EMPTY_N && int_div_fNext_14$FULL_N ; - assign WILL_FIRE_RL_int_div_work_14 = CAN_FIRE_RL_int_div_work_14 ; - - // rule RL_int_div_work_13 - assign CAN_FIRE_RL_int_div_work_13 = - int_div_fNext_12$EMPTY_N && int_div_fNext_13$FULL_N ; - assign WILL_FIRE_RL_int_div_work_13 = CAN_FIRE_RL_int_div_work_13 ; - - // rule RL_int_div_work_12 - assign CAN_FIRE_RL_int_div_work_12 = - int_div_fNext_11$EMPTY_N && int_div_fNext_12$FULL_N ; - assign WILL_FIRE_RL_int_div_work_12 = CAN_FIRE_RL_int_div_work_12 ; - - // rule RL_int_div_work_11 - assign CAN_FIRE_RL_int_div_work_11 = - int_div_fNext_10$EMPTY_N && int_div_fNext_11$FULL_N ; - assign WILL_FIRE_RL_int_div_work_11 = CAN_FIRE_RL_int_div_work_11 ; - - // rule RL_int_div_work_10 - assign CAN_FIRE_RL_int_div_work_10 = - int_div_fNext_9$EMPTY_N && int_div_fNext_10$FULL_N ; - assign WILL_FIRE_RL_int_div_work_10 = CAN_FIRE_RL_int_div_work_10 ; - - // rule RL_int_div_work_9 - assign CAN_FIRE_RL_int_div_work_9 = - int_div_fNext_8$EMPTY_N && int_div_fNext_9$FULL_N ; - assign WILL_FIRE_RL_int_div_work_9 = CAN_FIRE_RL_int_div_work_9 ; - - // rule RL_int_div_work_8 - assign CAN_FIRE_RL_int_div_work_8 = - int_div_fNext_7$EMPTY_N && int_div_fNext_8$FULL_N ; - assign WILL_FIRE_RL_int_div_work_8 = CAN_FIRE_RL_int_div_work_8 ; - - // rule RL_int_div_work_7 - assign CAN_FIRE_RL_int_div_work_7 = - int_div_fNext_6$EMPTY_N && int_div_fNext_7$FULL_N ; - assign WILL_FIRE_RL_int_div_work_7 = CAN_FIRE_RL_int_div_work_7 ; - - // rule RL_int_div_work_6 - assign CAN_FIRE_RL_int_div_work_6 = - int_div_fNext_5$EMPTY_N && int_div_fNext_6$FULL_N ; - assign WILL_FIRE_RL_int_div_work_6 = CAN_FIRE_RL_int_div_work_6 ; - - // rule RL_int_div_work_5 - assign CAN_FIRE_RL_int_div_work_5 = - int_div_fNext_4$EMPTY_N && int_div_fNext_5$FULL_N ; - assign WILL_FIRE_RL_int_div_work_5 = CAN_FIRE_RL_int_div_work_5 ; - - // rule RL_int_div_work_4 - assign CAN_FIRE_RL_int_div_work_4 = - int_div_fNext_3$EMPTY_N && int_div_fNext_4$FULL_N ; - assign WILL_FIRE_RL_int_div_work_4 = CAN_FIRE_RL_int_div_work_4 ; - - // rule RL_int_div_work_3 - assign CAN_FIRE_RL_int_div_work_3 = - int_div_fNext_2$EMPTY_N && int_div_fNext_3$FULL_N ; - assign WILL_FIRE_RL_int_div_work_3 = CAN_FIRE_RL_int_div_work_3 ; - - // rule RL_int_div_work_2 - assign CAN_FIRE_RL_int_div_work_2 = - int_div_fNext_1$EMPTY_N && int_div_fNext_2$FULL_N ; - assign WILL_FIRE_RL_int_div_work_2 = CAN_FIRE_RL_int_div_work_2 ; - - // rule RL_int_div_work_1 - assign CAN_FIRE_RL_int_div_work_1 = - int_div_fNext_0$EMPTY_N && int_div_fNext_1$FULL_N ; - assign WILL_FIRE_RL_int_div_work_1 = CAN_FIRE_RL_int_div_work_1 ; - - // rule RL_int_div_work - assign CAN_FIRE_RL_int_div_work = - int_div_fFirst$EMPTY_N && int_div_fNext_0$FULL_N ; - assign WILL_FIRE_RL_int_div_work = CAN_FIRE_RL_int_div_work ; - - // rule RL_int_div_start - assign CAN_FIRE_RL_int_div_start = - int_div_fRequest$EMPTY_N && int_div_fFirst$FULL_N ; - assign WILL_FIRE_RL_int_div_start = CAN_FIRE_RL_int_div_start ; - - // rule RL_fpu_s2_stage - assign CAN_FIRE_RL_fpu_s2_stage = - fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && - (fpu_fState_S1$D_OUT[318] || int_div_fRequest$FULL_N) ; - assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; - - // rule RL_fpu_s1_stage - assign CAN_FIRE_RL_fpu_s1_stage = - fpu_fOperands_S0$EMPTY_N && fpu_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; - - // submodule fpu_fOperands_S0 - assign fpu_fOperands_S0$D_IN = request_put ; - assign fpu_fOperands_S0$ENQ = EN_request_put ; - assign fpu_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fOperands_S0$CLR = 1'b0 ; - - // submodule fpu_fResult_S5 - assign fpu_fResult_S5$D_IN = - fpu_fState_S4$D_OUT[138] ? - fpu_fState_S4$D_OUT[137:69] : - { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[65:2] : - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16, - fpu_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h60991 == 11'd2047 && - _theResult___fst_sfd__h60992 == 52'd0, - 1'd0, - fpu_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fResult_S5$DEQ = EN_response_get ; - assign fpu_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_fState_S1 - assign fpu_fState_S1$D_IN = - { fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216, - (fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118]) ? - { fpu_fOperands_S0$D_OUT[130:119], sfd__h36684 } : - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308, - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54] || - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289, - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0), - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206, - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334, - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[54]) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[118]) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperands_S0$D_OUT[54]) && - NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341, - fpu_fOperands_S0$D_OUT[2:0], - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258, - _theResult___snd_fst_exp__h49111, - _theResult___snd_fst_sfd__h49112, - x__h49176, - x__h49237, - x__h49291 } ; - assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S1$CLR = 1'b0 ; - - // submodule fpu_fState_S2 - assign fpu_fState_S2$D_IN = - { fpu_fState_S1$D_OUT[318:182], fpu_fState_S1$D_OUT[10:0] } ; - assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S2$CLR = 1'b0 ; - - // submodule fpu_fState_S3 - assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT[147:11], x__h50487 } ; - assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S3$CLR = 1'b0 ; - - // submodule fpu_fState_S4 - assign fpu_fState_S4$D_IN = - { (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[194] : - fpu_fState_S3$D_OUT[194], - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - fpu_fState_S3$D_OUT[193:130] : - { CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17, - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 }) : - fpu_fState_S3$D_OUT[193:130], - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770, - fpu_fState_S3$D_OUT[124:122], - fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780, - x__h60140 } ; - assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S4$CLR = 1'b0 ; - - // submodule int_div_fFirst - assign int_div_fFirst$D_IN = - { b__h378, 60'd0, int_div_fRequest$D_OUT[170:57] } ; - assign int_div_fFirst$ENQ = CAN_FIRE_RL_int_div_start ; - assign int_div_fFirst$DEQ = CAN_FIRE_RL_int_div_work ; - assign int_div_fFirst$CLR = 1'b0 ; - - // submodule int_div_fNext_0 - assign int_div_fNext_0$D_IN = - { int_div_fFirst$D_OUT[231:174], - int_div_fFirst$D_OUT[172:116], - !int_div_fFirst$D_OUT[115], - int_div_fFirst$D_OUT[115] ? - { int_div_fFirst$D_OUT[114:0], 1'd0 } + b__h767 : - { int_div_fFirst$D_OUT[114:0], 1'd0 } - b__h767 } ; - assign int_div_fNext_0$ENQ = CAN_FIRE_RL_int_div_work ; - assign int_div_fNext_0$DEQ = CAN_FIRE_RL_int_div_work_1 ; - assign int_div_fNext_0$CLR = 1'b0 ; - - // submodule int_div_fNext_1 - assign int_div_fNext_1$D_IN = - { int_div_fNext_0$D_OUT[231:174], - int_div_fNext_0$D_OUT[172:116], - !int_div_fNext_0$D_OUT[115], - int_div_fNext_0$D_OUT[115] ? - { int_div_fNext_0$D_OUT[114:0], 1'd0 } + b__h1091 : - { int_div_fNext_0$D_OUT[114:0], 1'd0 } - b__h1091 } ; - assign int_div_fNext_1$ENQ = CAN_FIRE_RL_int_div_work_1 ; - assign int_div_fNext_1$DEQ = CAN_FIRE_RL_int_div_work_2 ; - assign int_div_fNext_1$CLR = 1'b0 ; - - // submodule int_div_fNext_10 - assign int_div_fNext_10$D_IN = - { int_div_fNext_9$D_OUT[231:174], - int_div_fNext_9$D_OUT[172:116], - !int_div_fNext_9$D_OUT[115], - int_div_fNext_9$D_OUT[115] ? - { int_div_fNext_9$D_OUT[114:0], 1'd0 } + b__h4007 : - { int_div_fNext_9$D_OUT[114:0], 1'd0 } - b__h4007 } ; - assign int_div_fNext_10$ENQ = CAN_FIRE_RL_int_div_work_10 ; - assign int_div_fNext_10$DEQ = CAN_FIRE_RL_int_div_work_11 ; - assign int_div_fNext_10$CLR = 1'b0 ; - - // submodule int_div_fNext_11 - assign int_div_fNext_11$D_IN = - { int_div_fNext_10$D_OUT[231:174], - int_div_fNext_10$D_OUT[172:116], - !int_div_fNext_10$D_OUT[115], - int_div_fNext_10$D_OUT[115] ? - { int_div_fNext_10$D_OUT[114:0], 1'd0 } + b__h4331 : - { int_div_fNext_10$D_OUT[114:0], 1'd0 } - b__h4331 } ; - assign int_div_fNext_11$ENQ = CAN_FIRE_RL_int_div_work_11 ; - assign int_div_fNext_11$DEQ = CAN_FIRE_RL_int_div_work_12 ; - assign int_div_fNext_11$CLR = 1'b0 ; - - // submodule int_div_fNext_12 - assign int_div_fNext_12$D_IN = - { int_div_fNext_11$D_OUT[231:174], - int_div_fNext_11$D_OUT[172:116], - !int_div_fNext_11$D_OUT[115], - int_div_fNext_11$D_OUT[115] ? - { int_div_fNext_11$D_OUT[114:0], 1'd0 } + b__h4655 : - { int_div_fNext_11$D_OUT[114:0], 1'd0 } - b__h4655 } ; - assign int_div_fNext_12$ENQ = CAN_FIRE_RL_int_div_work_12 ; - assign int_div_fNext_12$DEQ = CAN_FIRE_RL_int_div_work_13 ; - assign int_div_fNext_12$CLR = 1'b0 ; - - // submodule int_div_fNext_13 - assign int_div_fNext_13$D_IN = - { int_div_fNext_12$D_OUT[231:174], - int_div_fNext_12$D_OUT[172:116], - !int_div_fNext_12$D_OUT[115], - int_div_fNext_12$D_OUT[115] ? - { int_div_fNext_12$D_OUT[114:0], 1'd0 } + b__h4979 : - { int_div_fNext_12$D_OUT[114:0], 1'd0 } - b__h4979 } ; - assign int_div_fNext_13$ENQ = CAN_FIRE_RL_int_div_work_13 ; - assign int_div_fNext_13$DEQ = CAN_FIRE_RL_int_div_work_14 ; - assign int_div_fNext_13$CLR = 1'b0 ; - - // submodule int_div_fNext_14 - assign int_div_fNext_14$D_IN = - { int_div_fNext_13$D_OUT[231:174], - int_div_fNext_13$D_OUT[172:116], - !int_div_fNext_13$D_OUT[115], - int_div_fNext_13$D_OUT[115] ? - { int_div_fNext_13$D_OUT[114:0], 1'd0 } + b__h5303 : - { int_div_fNext_13$D_OUT[114:0], 1'd0 } - b__h5303 } ; - assign int_div_fNext_14$ENQ = CAN_FIRE_RL_int_div_work_14 ; - assign int_div_fNext_14$DEQ = CAN_FIRE_RL_int_div_work_15 ; - assign int_div_fNext_14$CLR = 1'b0 ; - - // submodule int_div_fNext_15 - assign int_div_fNext_15$D_IN = - { int_div_fNext_14$D_OUT[231:174], - int_div_fNext_14$D_OUT[172:116], - !int_div_fNext_14$D_OUT[115], - int_div_fNext_14$D_OUT[115] ? - { int_div_fNext_14$D_OUT[114:0], 1'd0 } + b__h5627 : - { int_div_fNext_14$D_OUT[114:0], 1'd0 } - b__h5627 } ; - assign int_div_fNext_15$ENQ = CAN_FIRE_RL_int_div_work_15 ; - assign int_div_fNext_15$DEQ = CAN_FIRE_RL_int_div_work_16 ; - assign int_div_fNext_15$CLR = 1'b0 ; - - // submodule int_div_fNext_16 - assign int_div_fNext_16$D_IN = - { int_div_fNext_15$D_OUT[231:174], - int_div_fNext_15$D_OUT[172:116], - !int_div_fNext_15$D_OUT[115], - int_div_fNext_15$D_OUT[115] ? - { int_div_fNext_15$D_OUT[114:0], 1'd0 } + b__h5951 : - { int_div_fNext_15$D_OUT[114:0], 1'd0 } - b__h5951 } ; - assign int_div_fNext_16$ENQ = CAN_FIRE_RL_int_div_work_16 ; - assign int_div_fNext_16$DEQ = CAN_FIRE_RL_int_div_work_17 ; - assign int_div_fNext_16$CLR = 1'b0 ; - - // submodule int_div_fNext_17 - assign int_div_fNext_17$D_IN = - { int_div_fNext_16$D_OUT[231:174], - int_div_fNext_16$D_OUT[172:116], - !int_div_fNext_16$D_OUT[115], - int_div_fNext_16$D_OUT[115] ? - { int_div_fNext_16$D_OUT[114:0], 1'd0 } + b__h6275 : - { int_div_fNext_16$D_OUT[114:0], 1'd0 } - b__h6275 } ; - assign int_div_fNext_17$ENQ = CAN_FIRE_RL_int_div_work_17 ; - assign int_div_fNext_17$DEQ = CAN_FIRE_RL_int_div_work_18 ; - assign int_div_fNext_17$CLR = 1'b0 ; - - // submodule int_div_fNext_18 - assign int_div_fNext_18$D_IN = - { int_div_fNext_17$D_OUT[231:174], - int_div_fNext_17$D_OUT[172:116], - !int_div_fNext_17$D_OUT[115], - int_div_fNext_17$D_OUT[115] ? - { int_div_fNext_17$D_OUT[114:0], 1'd0 } + b__h6599 : - { int_div_fNext_17$D_OUT[114:0], 1'd0 } - b__h6599 } ; - assign int_div_fNext_18$ENQ = CAN_FIRE_RL_int_div_work_18 ; - assign int_div_fNext_18$DEQ = CAN_FIRE_RL_int_div_work_19 ; - assign int_div_fNext_18$CLR = 1'b0 ; - - // submodule int_div_fNext_19 - assign int_div_fNext_19$D_IN = - { int_div_fNext_18$D_OUT[231:174], - int_div_fNext_18$D_OUT[172:116], - !int_div_fNext_18$D_OUT[115], - int_div_fNext_18$D_OUT[115] ? - { int_div_fNext_18$D_OUT[114:0], 1'd0 } + b__h6923 : - { int_div_fNext_18$D_OUT[114:0], 1'd0 } - b__h6923 } ; - assign int_div_fNext_19$ENQ = CAN_FIRE_RL_int_div_work_19 ; - assign int_div_fNext_19$DEQ = CAN_FIRE_RL_int_div_work_20 ; - assign int_div_fNext_19$CLR = 1'b0 ; - - // submodule int_div_fNext_2 - assign int_div_fNext_2$D_IN = - { int_div_fNext_1$D_OUT[231:174], - int_div_fNext_1$D_OUT[172:116], - !int_div_fNext_1$D_OUT[115], - int_div_fNext_1$D_OUT[115] ? - { int_div_fNext_1$D_OUT[114:0], 1'd0 } + b__h1415 : - { int_div_fNext_1$D_OUT[114:0], 1'd0 } - b__h1415 } ; - assign int_div_fNext_2$ENQ = CAN_FIRE_RL_int_div_work_2 ; - assign int_div_fNext_2$DEQ = CAN_FIRE_RL_int_div_work_3 ; - assign int_div_fNext_2$CLR = 1'b0 ; - - // submodule int_div_fNext_20 - assign int_div_fNext_20$D_IN = - { int_div_fNext_19$D_OUT[231:174], - int_div_fNext_19$D_OUT[172:116], - !int_div_fNext_19$D_OUT[115], - int_div_fNext_19$D_OUT[115] ? - { int_div_fNext_19$D_OUT[114:0], 1'd0 } + b__h7247 : - { int_div_fNext_19$D_OUT[114:0], 1'd0 } - b__h7247 } ; - assign int_div_fNext_20$ENQ = CAN_FIRE_RL_int_div_work_20 ; - assign int_div_fNext_20$DEQ = CAN_FIRE_RL_int_div_work_21 ; - assign int_div_fNext_20$CLR = 1'b0 ; - - // submodule int_div_fNext_21 - assign int_div_fNext_21$D_IN = - { int_div_fNext_20$D_OUT[231:174], - int_div_fNext_20$D_OUT[172:116], - !int_div_fNext_20$D_OUT[115], - int_div_fNext_20$D_OUT[115] ? - { int_div_fNext_20$D_OUT[114:0], 1'd0 } + b__h7571 : - { int_div_fNext_20$D_OUT[114:0], 1'd0 } - b__h7571 } ; - assign int_div_fNext_21$ENQ = CAN_FIRE_RL_int_div_work_21 ; - assign int_div_fNext_21$DEQ = CAN_FIRE_RL_int_div_work_22 ; - assign int_div_fNext_21$CLR = 1'b0 ; - - // submodule int_div_fNext_22 - assign int_div_fNext_22$D_IN = - { int_div_fNext_21$D_OUT[231:174], - int_div_fNext_21$D_OUT[172:116], - !int_div_fNext_21$D_OUT[115], - int_div_fNext_21$D_OUT[115] ? - { int_div_fNext_21$D_OUT[114:0], 1'd0 } + b__h7895 : - { int_div_fNext_21$D_OUT[114:0], 1'd0 } - b__h7895 } ; - assign int_div_fNext_22$ENQ = CAN_FIRE_RL_int_div_work_22 ; - assign int_div_fNext_22$DEQ = CAN_FIRE_RL_int_div_work_23 ; - assign int_div_fNext_22$CLR = 1'b0 ; - - // submodule int_div_fNext_23 - assign int_div_fNext_23$D_IN = - { int_div_fNext_22$D_OUT[231:174], - int_div_fNext_22$D_OUT[172:116], - !int_div_fNext_22$D_OUT[115], - int_div_fNext_22$D_OUT[115] ? - { int_div_fNext_22$D_OUT[114:0], 1'd0 } + b__h8219 : - { int_div_fNext_22$D_OUT[114:0], 1'd0 } - b__h8219 } ; - assign int_div_fNext_23$ENQ = CAN_FIRE_RL_int_div_work_23 ; - assign int_div_fNext_23$DEQ = CAN_FIRE_RL_int_div_work_24 ; - assign int_div_fNext_23$CLR = 1'b0 ; - - // submodule int_div_fNext_24 - assign int_div_fNext_24$D_IN = - { int_div_fNext_23$D_OUT[231:174], - int_div_fNext_23$D_OUT[172:116], - !int_div_fNext_23$D_OUT[115], - int_div_fNext_23$D_OUT[115] ? - { int_div_fNext_23$D_OUT[114:0], 1'd0 } + b__h8543 : - { int_div_fNext_23$D_OUT[114:0], 1'd0 } - b__h8543 } ; - assign int_div_fNext_24$ENQ = CAN_FIRE_RL_int_div_work_24 ; - assign int_div_fNext_24$DEQ = CAN_FIRE_RL_int_div_work_25 ; - assign int_div_fNext_24$CLR = 1'b0 ; - - // submodule int_div_fNext_25 - assign int_div_fNext_25$D_IN = - { int_div_fNext_24$D_OUT[231:174], - int_div_fNext_24$D_OUT[172:116], - !int_div_fNext_24$D_OUT[115], - int_div_fNext_24$D_OUT[115] ? - { int_div_fNext_24$D_OUT[114:0], 1'd0 } + b__h8867 : - { int_div_fNext_24$D_OUT[114:0], 1'd0 } - b__h8867 } ; - assign int_div_fNext_25$ENQ = CAN_FIRE_RL_int_div_work_25 ; - assign int_div_fNext_25$DEQ = CAN_FIRE_RL_int_div_work_26 ; - assign int_div_fNext_25$CLR = 1'b0 ; - - // submodule int_div_fNext_26 - assign int_div_fNext_26$D_IN = - { int_div_fNext_25$D_OUT[231:174], - int_div_fNext_25$D_OUT[172:116], - !int_div_fNext_25$D_OUT[115], - int_div_fNext_25$D_OUT[115] ? - { int_div_fNext_25$D_OUT[114:0], 1'd0 } + b__h9191 : - { int_div_fNext_25$D_OUT[114:0], 1'd0 } - b__h9191 } ; - assign int_div_fNext_26$ENQ = CAN_FIRE_RL_int_div_work_26 ; - assign int_div_fNext_26$DEQ = CAN_FIRE_RL_int_div_work_27 ; - assign int_div_fNext_26$CLR = 1'b0 ; - - // submodule int_div_fNext_27 - assign int_div_fNext_27$D_IN = - { int_div_fNext_26$D_OUT[231:174], - int_div_fNext_26$D_OUT[172:116], - !int_div_fNext_26$D_OUT[115], - int_div_fNext_26$D_OUT[115] ? - { int_div_fNext_26$D_OUT[114:0], 1'd0 } + b__h9515 : - { int_div_fNext_26$D_OUT[114:0], 1'd0 } - b__h9515 } ; - assign int_div_fNext_27$ENQ = CAN_FIRE_RL_int_div_work_27 ; - assign int_div_fNext_27$DEQ = CAN_FIRE_RL_int_div_work_28 ; - assign int_div_fNext_27$CLR = 1'b0 ; - - // submodule int_div_fNext_28 - assign int_div_fNext_28$D_IN = - { int_div_fNext_27$D_OUT[231:174], - int_div_fNext_27$D_OUT[172:116], - !int_div_fNext_27$D_OUT[115], - int_div_fNext_27$D_OUT[115] ? - { int_div_fNext_27$D_OUT[114:0], 1'd0 } + b__h9839 : - { int_div_fNext_27$D_OUT[114:0], 1'd0 } - b__h9839 } ; - assign int_div_fNext_28$ENQ = CAN_FIRE_RL_int_div_work_28 ; - assign int_div_fNext_28$DEQ = CAN_FIRE_RL_int_div_work_29 ; - assign int_div_fNext_28$CLR = 1'b0 ; - - // submodule int_div_fNext_29 - assign int_div_fNext_29$D_IN = - { int_div_fNext_28$D_OUT[231:174], - int_div_fNext_28$D_OUT[172:116], - !int_div_fNext_28$D_OUT[115], - int_div_fNext_28$D_OUT[115] ? - { int_div_fNext_28$D_OUT[114:0], 1'd0 } + b__h10163 : - { int_div_fNext_28$D_OUT[114:0], 1'd0 } - b__h10163 } ; - assign int_div_fNext_29$ENQ = CAN_FIRE_RL_int_div_work_29 ; - assign int_div_fNext_29$DEQ = CAN_FIRE_RL_int_div_work_30 ; - assign int_div_fNext_29$CLR = 1'b0 ; - - // submodule int_div_fNext_3 - assign int_div_fNext_3$D_IN = - { int_div_fNext_2$D_OUT[231:174], - int_div_fNext_2$D_OUT[172:116], - !int_div_fNext_2$D_OUT[115], - int_div_fNext_2$D_OUT[115] ? - { int_div_fNext_2$D_OUT[114:0], 1'd0 } + b__h1739 : - { int_div_fNext_2$D_OUT[114:0], 1'd0 } - b__h1739 } ; - assign int_div_fNext_3$ENQ = CAN_FIRE_RL_int_div_work_3 ; - assign int_div_fNext_3$DEQ = CAN_FIRE_RL_int_div_work_4 ; - assign int_div_fNext_3$CLR = 1'b0 ; - - // submodule int_div_fNext_30 - assign int_div_fNext_30$D_IN = - { int_div_fNext_29$D_OUT[231:174], - int_div_fNext_29$D_OUT[172:116], - !int_div_fNext_29$D_OUT[115], - int_div_fNext_29$D_OUT[115] ? - { int_div_fNext_29$D_OUT[114:0], 1'd0 } + b__h10487 : - { int_div_fNext_29$D_OUT[114:0], 1'd0 } - b__h10487 } ; - assign int_div_fNext_30$ENQ = CAN_FIRE_RL_int_div_work_30 ; - assign int_div_fNext_30$DEQ = CAN_FIRE_RL_int_div_work_31 ; - assign int_div_fNext_30$CLR = 1'b0 ; - - // submodule int_div_fNext_31 - assign int_div_fNext_31$D_IN = - { int_div_fNext_30$D_OUT[231:174], - int_div_fNext_30$D_OUT[172:116], - !int_div_fNext_30$D_OUT[115], - int_div_fNext_30$D_OUT[115] ? - { int_div_fNext_30$D_OUT[114:0], 1'd0 } + b__h10811 : - { int_div_fNext_30$D_OUT[114:0], 1'd0 } - b__h10811 } ; - assign int_div_fNext_31$ENQ = CAN_FIRE_RL_int_div_work_31 ; - assign int_div_fNext_31$DEQ = CAN_FIRE_RL_int_div_work_32 ; - assign int_div_fNext_31$CLR = 1'b0 ; - - // submodule int_div_fNext_32 - assign int_div_fNext_32$D_IN = - { int_div_fNext_31$D_OUT[231:174], - int_div_fNext_31$D_OUT[172:116], - !int_div_fNext_31$D_OUT[115], - int_div_fNext_31$D_OUT[115] ? - { int_div_fNext_31$D_OUT[114:0], 1'd0 } + b__h11135 : - { int_div_fNext_31$D_OUT[114:0], 1'd0 } - b__h11135 } ; - assign int_div_fNext_32$ENQ = CAN_FIRE_RL_int_div_work_32 ; - assign int_div_fNext_32$DEQ = CAN_FIRE_RL_int_div_work_33 ; - assign int_div_fNext_32$CLR = 1'b0 ; - - // submodule int_div_fNext_33 - assign int_div_fNext_33$D_IN = - { int_div_fNext_32$D_OUT[231:174], - int_div_fNext_32$D_OUT[172:116], - !int_div_fNext_32$D_OUT[115], - int_div_fNext_32$D_OUT[115] ? - { int_div_fNext_32$D_OUT[114:0], 1'd0 } + b__h11459 : - { int_div_fNext_32$D_OUT[114:0], 1'd0 } - b__h11459 } ; - assign int_div_fNext_33$ENQ = CAN_FIRE_RL_int_div_work_33 ; - assign int_div_fNext_33$DEQ = CAN_FIRE_RL_int_div_work_34 ; - assign int_div_fNext_33$CLR = 1'b0 ; - - // submodule int_div_fNext_34 - assign int_div_fNext_34$D_IN = - { int_div_fNext_33$D_OUT[231:174], - int_div_fNext_33$D_OUT[172:116], - !int_div_fNext_33$D_OUT[115], - int_div_fNext_33$D_OUT[115] ? - { int_div_fNext_33$D_OUT[114:0], 1'd0 } + b__h11783 : - { int_div_fNext_33$D_OUT[114:0], 1'd0 } - b__h11783 } ; - assign int_div_fNext_34$ENQ = CAN_FIRE_RL_int_div_work_34 ; - assign int_div_fNext_34$DEQ = CAN_FIRE_RL_int_div_work_35 ; - assign int_div_fNext_34$CLR = 1'b0 ; - - // submodule int_div_fNext_35 - assign int_div_fNext_35$D_IN = - { int_div_fNext_34$D_OUT[231:174], - int_div_fNext_34$D_OUT[172:116], - !int_div_fNext_34$D_OUT[115], - int_div_fNext_34$D_OUT[115] ? - { int_div_fNext_34$D_OUT[114:0], 1'd0 } + b__h12107 : - { int_div_fNext_34$D_OUT[114:0], 1'd0 } - b__h12107 } ; - assign int_div_fNext_35$ENQ = CAN_FIRE_RL_int_div_work_35 ; - assign int_div_fNext_35$DEQ = CAN_FIRE_RL_int_div_work_36 ; - assign int_div_fNext_35$CLR = 1'b0 ; - - // submodule int_div_fNext_36 - assign int_div_fNext_36$D_IN = - { int_div_fNext_35$D_OUT[231:174], - int_div_fNext_35$D_OUT[172:116], - !int_div_fNext_35$D_OUT[115], - int_div_fNext_35$D_OUT[115] ? - { int_div_fNext_35$D_OUT[114:0], 1'd0 } + b__h12431 : - { int_div_fNext_35$D_OUT[114:0], 1'd0 } - b__h12431 } ; - assign int_div_fNext_36$ENQ = CAN_FIRE_RL_int_div_work_36 ; - assign int_div_fNext_36$DEQ = CAN_FIRE_RL_int_div_work_37 ; - assign int_div_fNext_36$CLR = 1'b0 ; - - // submodule int_div_fNext_37 - assign int_div_fNext_37$D_IN = - { int_div_fNext_36$D_OUT[231:174], - int_div_fNext_36$D_OUT[172:116], - !int_div_fNext_36$D_OUT[115], - int_div_fNext_36$D_OUT[115] ? - { int_div_fNext_36$D_OUT[114:0], 1'd0 } + b__h12755 : - { int_div_fNext_36$D_OUT[114:0], 1'd0 } - b__h12755 } ; - assign int_div_fNext_37$ENQ = CAN_FIRE_RL_int_div_work_37 ; - assign int_div_fNext_37$DEQ = CAN_FIRE_RL_int_div_work_38 ; - assign int_div_fNext_37$CLR = 1'b0 ; - - // submodule int_div_fNext_38 - assign int_div_fNext_38$D_IN = - { int_div_fNext_37$D_OUT[231:174], - int_div_fNext_37$D_OUT[172:116], - !int_div_fNext_37$D_OUT[115], - int_div_fNext_37$D_OUT[115] ? - { int_div_fNext_37$D_OUT[114:0], 1'd0 } + b__h13079 : - { int_div_fNext_37$D_OUT[114:0], 1'd0 } - b__h13079 } ; - assign int_div_fNext_38$ENQ = CAN_FIRE_RL_int_div_work_38 ; - assign int_div_fNext_38$DEQ = CAN_FIRE_RL_int_div_work_39 ; - assign int_div_fNext_38$CLR = 1'b0 ; - - // submodule int_div_fNext_39 - assign int_div_fNext_39$D_IN = - { int_div_fNext_38$D_OUT[231:174], - int_div_fNext_38$D_OUT[172:116], - !int_div_fNext_38$D_OUT[115], - int_div_fNext_38$D_OUT[115] ? - { int_div_fNext_38$D_OUT[114:0], 1'd0 } + b__h13403 : - { int_div_fNext_38$D_OUT[114:0], 1'd0 } - b__h13403 } ; - assign int_div_fNext_39$ENQ = CAN_FIRE_RL_int_div_work_39 ; - assign int_div_fNext_39$DEQ = CAN_FIRE_RL_int_div_work_40 ; - assign int_div_fNext_39$CLR = 1'b0 ; - - // submodule int_div_fNext_4 - assign int_div_fNext_4$D_IN = - { int_div_fNext_3$D_OUT[231:174], - int_div_fNext_3$D_OUT[172:116], - !int_div_fNext_3$D_OUT[115], - int_div_fNext_3$D_OUT[115] ? - { int_div_fNext_3$D_OUT[114:0], 1'd0 } + b__h2063 : - { int_div_fNext_3$D_OUT[114:0], 1'd0 } - b__h2063 } ; - assign int_div_fNext_4$ENQ = CAN_FIRE_RL_int_div_work_4 ; - assign int_div_fNext_4$DEQ = CAN_FIRE_RL_int_div_work_5 ; - assign int_div_fNext_4$CLR = 1'b0 ; - - // submodule int_div_fNext_40 - assign int_div_fNext_40$D_IN = - { int_div_fNext_39$D_OUT[231:174], - int_div_fNext_39$D_OUT[172:116], - !int_div_fNext_39$D_OUT[115], - int_div_fNext_39$D_OUT[115] ? - { int_div_fNext_39$D_OUT[114:0], 1'd0 } + b__h13727 : - { int_div_fNext_39$D_OUT[114:0], 1'd0 } - b__h13727 } ; - assign int_div_fNext_40$ENQ = CAN_FIRE_RL_int_div_work_40 ; - assign int_div_fNext_40$DEQ = CAN_FIRE_RL_int_div_work_41 ; - assign int_div_fNext_40$CLR = 1'b0 ; - - // submodule int_div_fNext_41 - assign int_div_fNext_41$D_IN = - { int_div_fNext_40$D_OUT[231:174], - int_div_fNext_40$D_OUT[172:116], - !int_div_fNext_40$D_OUT[115], - int_div_fNext_40$D_OUT[115] ? - { int_div_fNext_40$D_OUT[114:0], 1'd0 } + b__h14051 : - { int_div_fNext_40$D_OUT[114:0], 1'd0 } - b__h14051 } ; - assign int_div_fNext_41$ENQ = CAN_FIRE_RL_int_div_work_41 ; - assign int_div_fNext_41$DEQ = CAN_FIRE_RL_int_div_work_42 ; - assign int_div_fNext_41$CLR = 1'b0 ; - - // submodule int_div_fNext_42 - assign int_div_fNext_42$D_IN = - { int_div_fNext_41$D_OUT[231:174], - int_div_fNext_41$D_OUT[172:116], - !int_div_fNext_41$D_OUT[115], - int_div_fNext_41$D_OUT[115] ? - { int_div_fNext_41$D_OUT[114:0], 1'd0 } + b__h14375 : - { int_div_fNext_41$D_OUT[114:0], 1'd0 } - b__h14375 } ; - assign int_div_fNext_42$ENQ = CAN_FIRE_RL_int_div_work_42 ; - assign int_div_fNext_42$DEQ = CAN_FIRE_RL_int_div_work_43 ; - assign int_div_fNext_42$CLR = 1'b0 ; - - // submodule int_div_fNext_43 - assign int_div_fNext_43$D_IN = - { int_div_fNext_42$D_OUT[231:174], - int_div_fNext_42$D_OUT[172:116], - !int_div_fNext_42$D_OUT[115], - int_div_fNext_42$D_OUT[115] ? - { int_div_fNext_42$D_OUT[114:0], 1'd0 } + b__h14699 : - { int_div_fNext_42$D_OUT[114:0], 1'd0 } - b__h14699 } ; - assign int_div_fNext_43$ENQ = CAN_FIRE_RL_int_div_work_43 ; - assign int_div_fNext_43$DEQ = CAN_FIRE_RL_int_div_work_44 ; - assign int_div_fNext_43$CLR = 1'b0 ; - - // submodule int_div_fNext_44 - assign int_div_fNext_44$D_IN = - { int_div_fNext_43$D_OUT[231:174], - int_div_fNext_43$D_OUT[172:116], - !int_div_fNext_43$D_OUT[115], - int_div_fNext_43$D_OUT[115] ? - { int_div_fNext_43$D_OUT[114:0], 1'd0 } + b__h15023 : - { int_div_fNext_43$D_OUT[114:0], 1'd0 } - b__h15023 } ; - assign int_div_fNext_44$ENQ = CAN_FIRE_RL_int_div_work_44 ; - assign int_div_fNext_44$DEQ = CAN_FIRE_RL_int_div_work_45 ; - assign int_div_fNext_44$CLR = 1'b0 ; - - // submodule int_div_fNext_45 - assign int_div_fNext_45$D_IN = - { int_div_fNext_44$D_OUT[231:174], - int_div_fNext_44$D_OUT[172:116], - !int_div_fNext_44$D_OUT[115], - int_div_fNext_44$D_OUT[115] ? - { int_div_fNext_44$D_OUT[114:0], 1'd0 } + b__h15347 : - { int_div_fNext_44$D_OUT[114:0], 1'd0 } - b__h15347 } ; - assign int_div_fNext_45$ENQ = CAN_FIRE_RL_int_div_work_45 ; - assign int_div_fNext_45$DEQ = CAN_FIRE_RL_int_div_work_46 ; - assign int_div_fNext_45$CLR = 1'b0 ; - - // submodule int_div_fNext_46 - assign int_div_fNext_46$D_IN = - { int_div_fNext_45$D_OUT[231:174], - int_div_fNext_45$D_OUT[172:116], - !int_div_fNext_45$D_OUT[115], - int_div_fNext_45$D_OUT[115] ? - { int_div_fNext_45$D_OUT[114:0], 1'd0 } + b__h15671 : - { int_div_fNext_45$D_OUT[114:0], 1'd0 } - b__h15671 } ; - assign int_div_fNext_46$ENQ = CAN_FIRE_RL_int_div_work_46 ; - assign int_div_fNext_46$DEQ = CAN_FIRE_RL_int_div_work_47 ; - assign int_div_fNext_46$CLR = 1'b0 ; - - // submodule int_div_fNext_47 - assign int_div_fNext_47$D_IN = - { int_div_fNext_46$D_OUT[231:174], - int_div_fNext_46$D_OUT[172:116], - !int_div_fNext_46$D_OUT[115], - int_div_fNext_46$D_OUT[115] ? - { int_div_fNext_46$D_OUT[114:0], 1'd0 } + b__h15995 : - { int_div_fNext_46$D_OUT[114:0], 1'd0 } - b__h15995 } ; - assign int_div_fNext_47$ENQ = CAN_FIRE_RL_int_div_work_47 ; - assign int_div_fNext_47$DEQ = CAN_FIRE_RL_int_div_work_48 ; - assign int_div_fNext_47$CLR = 1'b0 ; - - // submodule int_div_fNext_48 - assign int_div_fNext_48$D_IN = - { int_div_fNext_47$D_OUT[231:174], - int_div_fNext_47$D_OUT[172:116], - !int_div_fNext_47$D_OUT[115], - int_div_fNext_47$D_OUT[115] ? - { int_div_fNext_47$D_OUT[114:0], 1'd0 } + b__h16319 : - { int_div_fNext_47$D_OUT[114:0], 1'd0 } - b__h16319 } ; - assign int_div_fNext_48$ENQ = CAN_FIRE_RL_int_div_work_48 ; - assign int_div_fNext_48$DEQ = CAN_FIRE_RL_int_div_work_49 ; - assign int_div_fNext_48$CLR = 1'b0 ; - - // submodule int_div_fNext_49 - assign int_div_fNext_49$D_IN = - { int_div_fNext_48$D_OUT[231:174], - int_div_fNext_48$D_OUT[172:116], - !int_div_fNext_48$D_OUT[115], - int_div_fNext_48$D_OUT[115] ? - { int_div_fNext_48$D_OUT[114:0], 1'd0 } + b__h16643 : - { int_div_fNext_48$D_OUT[114:0], 1'd0 } - b__h16643 } ; - assign int_div_fNext_49$ENQ = CAN_FIRE_RL_int_div_work_49 ; - assign int_div_fNext_49$DEQ = CAN_FIRE_RL_int_div_work_50 ; - assign int_div_fNext_49$CLR = 1'b0 ; - - // submodule int_div_fNext_5 - assign int_div_fNext_5$D_IN = - { int_div_fNext_4$D_OUT[231:174], - int_div_fNext_4$D_OUT[172:116], - !int_div_fNext_4$D_OUT[115], - int_div_fNext_4$D_OUT[115] ? - { int_div_fNext_4$D_OUT[114:0], 1'd0 } + b__h2387 : - { int_div_fNext_4$D_OUT[114:0], 1'd0 } - b__h2387 } ; - assign int_div_fNext_5$ENQ = CAN_FIRE_RL_int_div_work_5 ; - assign int_div_fNext_5$DEQ = CAN_FIRE_RL_int_div_work_6 ; - assign int_div_fNext_5$CLR = 1'b0 ; - - // submodule int_div_fNext_50 - assign int_div_fNext_50$D_IN = - { int_div_fNext_49$D_OUT[231:174], - int_div_fNext_49$D_OUT[172:116], - !int_div_fNext_49$D_OUT[115], - int_div_fNext_49$D_OUT[115] ? - { int_div_fNext_49$D_OUT[114:0], 1'd0 } + b__h16967 : - { int_div_fNext_49$D_OUT[114:0], 1'd0 } - b__h16967 } ; - assign int_div_fNext_50$ENQ = CAN_FIRE_RL_int_div_work_50 ; - assign int_div_fNext_50$DEQ = CAN_FIRE_RL_int_div_work_51 ; - assign int_div_fNext_50$CLR = 1'b0 ; - - // submodule int_div_fNext_51 - assign int_div_fNext_51$D_IN = - { int_div_fNext_50$D_OUT[231:174], - int_div_fNext_50$D_OUT[172:116], - !int_div_fNext_50$D_OUT[115], - int_div_fNext_50$D_OUT[115] ? - { int_div_fNext_50$D_OUT[114:0], 1'd0 } + b__h17291 : - { int_div_fNext_50$D_OUT[114:0], 1'd0 } - b__h17291 } ; - assign int_div_fNext_51$ENQ = CAN_FIRE_RL_int_div_work_51 ; - assign int_div_fNext_51$DEQ = CAN_FIRE_RL_int_div_work_52 ; - assign int_div_fNext_51$CLR = 1'b0 ; - - // submodule int_div_fNext_52 - assign int_div_fNext_52$D_IN = - { int_div_fNext_51$D_OUT[231:174], - int_div_fNext_51$D_OUT[172:116], - !int_div_fNext_51$D_OUT[115], - int_div_fNext_51$D_OUT[115] ? - { int_div_fNext_51$D_OUT[114:0], 1'd0 } + b__h17615 : - { int_div_fNext_51$D_OUT[114:0], 1'd0 } - b__h17615 } ; - assign int_div_fNext_52$ENQ = CAN_FIRE_RL_int_div_work_52 ; - assign int_div_fNext_52$DEQ = CAN_FIRE_RL_int_div_work_53 ; - assign int_div_fNext_52$CLR = 1'b0 ; - - // submodule int_div_fNext_53 - assign int_div_fNext_53$D_IN = - { int_div_fNext_52$D_OUT[231:174], - int_div_fNext_52$D_OUT[172:116], - !int_div_fNext_52$D_OUT[115], - int_div_fNext_52$D_OUT[115] ? - { int_div_fNext_52$D_OUT[114:0], 1'd0 } + b__h17939 : - { int_div_fNext_52$D_OUT[114:0], 1'd0 } - b__h17939 } ; - assign int_div_fNext_53$ENQ = CAN_FIRE_RL_int_div_work_53 ; - assign int_div_fNext_53$DEQ = CAN_FIRE_RL_int_div_work_54 ; - assign int_div_fNext_53$CLR = 1'b0 ; - - // submodule int_div_fNext_54 - assign int_div_fNext_54$D_IN = - { int_div_fNext_53$D_OUT[231:174], - int_div_fNext_53$D_OUT[172:116], - !int_div_fNext_53$D_OUT[115], - int_div_fNext_53$D_OUT[115] ? - { int_div_fNext_53$D_OUT[114:0], 1'd0 } + b__h18263 : - { int_div_fNext_53$D_OUT[114:0], 1'd0 } - b__h18263 } ; - assign int_div_fNext_54$ENQ = CAN_FIRE_RL_int_div_work_54 ; - assign int_div_fNext_54$DEQ = CAN_FIRE_RL_int_div_work_55 ; - assign int_div_fNext_54$CLR = 1'b0 ; - - // submodule int_div_fNext_55 - assign int_div_fNext_55$D_IN = - { int_div_fNext_54$D_OUT[231:174], - int_div_fNext_54$D_OUT[172:116], - !int_div_fNext_54$D_OUT[115], - int_div_fNext_54$D_OUT[115] ? - { int_div_fNext_54$D_OUT[114:0], 1'd0 } + b__h18587 : - { int_div_fNext_54$D_OUT[114:0], 1'd0 } - b__h18587 } ; - assign int_div_fNext_55$ENQ = CAN_FIRE_RL_int_div_work_55 ; - assign int_div_fNext_55$DEQ = CAN_FIRE_RL_int_div_work_56 ; - assign int_div_fNext_55$CLR = 1'b0 ; - - // submodule int_div_fNext_56 - assign int_div_fNext_56$D_IN = - { int_div_fNext_55$D_OUT[231:174], - int_div_fNext_55$D_OUT[172:116], - !int_div_fNext_55$D_OUT[115], - int_div_fNext_55$D_OUT[115] ? - { int_div_fNext_55$D_OUT[114:0], 1'd0 } + b__h18911 : - { int_div_fNext_55$D_OUT[114:0], 1'd0 } - b__h18911 } ; - assign int_div_fNext_56$ENQ = CAN_FIRE_RL_int_div_work_56 ; - assign int_div_fNext_56$DEQ = CAN_FIRE_RL_int_div_work_57 ; - assign int_div_fNext_56$CLR = 1'b0 ; - - // submodule int_div_fNext_57 - assign int_div_fNext_57$D_IN = - { int_div_fNext_56$D_OUT[231:174], - int_div_fNext_56$D_OUT[172:116], - !int_div_fNext_56$D_OUT[115], - int_div_fNext_56$D_OUT[115] ? - { int_div_fNext_56$D_OUT[114:0], 1'd0 } + b__h19235 : - { int_div_fNext_56$D_OUT[114:0], 1'd0 } - b__h19235 } ; - assign int_div_fNext_57$ENQ = CAN_FIRE_RL_int_div_work_57 ; - assign int_div_fNext_57$DEQ = CAN_FIRE_RL_int_div_finish ; - assign int_div_fNext_57$CLR = 1'b0 ; - - // submodule int_div_fNext_6 - assign int_div_fNext_6$D_IN = - { int_div_fNext_5$D_OUT[231:174], - int_div_fNext_5$D_OUT[172:116], - !int_div_fNext_5$D_OUT[115], - int_div_fNext_5$D_OUT[115] ? - { int_div_fNext_5$D_OUT[114:0], 1'd0 } + b__h2711 : - { int_div_fNext_5$D_OUT[114:0], 1'd0 } - b__h2711 } ; - assign int_div_fNext_6$ENQ = CAN_FIRE_RL_int_div_work_6 ; - assign int_div_fNext_6$DEQ = CAN_FIRE_RL_int_div_work_7 ; - assign int_div_fNext_6$CLR = 1'b0 ; - - // submodule int_div_fNext_7 - assign int_div_fNext_7$D_IN = - { int_div_fNext_6$D_OUT[231:174], - int_div_fNext_6$D_OUT[172:116], - !int_div_fNext_6$D_OUT[115], - int_div_fNext_6$D_OUT[115] ? - { int_div_fNext_6$D_OUT[114:0], 1'd0 } + b__h3035 : - { int_div_fNext_6$D_OUT[114:0], 1'd0 } - b__h3035 } ; - assign int_div_fNext_7$ENQ = CAN_FIRE_RL_int_div_work_7 ; - assign int_div_fNext_7$DEQ = CAN_FIRE_RL_int_div_work_8 ; - assign int_div_fNext_7$CLR = 1'b0 ; - - // submodule int_div_fNext_8 - assign int_div_fNext_8$D_IN = - { int_div_fNext_7$D_OUT[231:174], - int_div_fNext_7$D_OUT[172:116], - !int_div_fNext_7$D_OUT[115], - int_div_fNext_7$D_OUT[115] ? - { int_div_fNext_7$D_OUT[114:0], 1'd0 } + b__h3359 : - { int_div_fNext_7$D_OUT[114:0], 1'd0 } - b__h3359 } ; - assign int_div_fNext_8$ENQ = CAN_FIRE_RL_int_div_work_8 ; - assign int_div_fNext_8$DEQ = CAN_FIRE_RL_int_div_work_9 ; - assign int_div_fNext_8$CLR = 1'b0 ; - - // submodule int_div_fNext_9 - assign int_div_fNext_9$D_IN = - { int_div_fNext_8$D_OUT[231:174], - int_div_fNext_8$D_OUT[172:116], - !int_div_fNext_8$D_OUT[115], - int_div_fNext_8$D_OUT[115] ? - { int_div_fNext_8$D_OUT[114:0], 1'd0 } + b__h3683 : - { int_div_fNext_8$D_OUT[114:0], 1'd0 } - b__h3683 } ; - assign int_div_fNext_9$ENQ = CAN_FIRE_RL_int_div_work_9 ; - assign int_div_fNext_9$DEQ = CAN_FIRE_RL_int_div_work_10 ; - assign int_div_fNext_9$CLR = 1'b0 ; - - // submodule int_div_fRequest - assign int_div_fRequest$D_IN = fpu_fState_S1$D_OUT[181:11] ; - assign int_div_fRequest$ENQ = - WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[318] ; - assign int_div_fRequest$DEQ = CAN_FIRE_RL_int_div_start ; - assign int_div_fRequest$CLR = 1'b0 ; - - // submodule int_div_fResponse - assign int_div_fResponse$D_IN = - { IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19[56:0], - value__h19447[114:58] } ; - assign int_div_fResponse$ENQ = CAN_FIRE_RL_int_div_finish ; - assign int_div_fResponse$DEQ = - WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[147] ; - assign int_div_fResponse$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7 = - _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 ? - _theResult___snd__h59844 : - _theResult___snd__h59839 ; - assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 = - sfd__h60417[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h61001, sfd__h60417[52:1] }) : - { IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821, - sfd__h60417[51:0] } ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 = - (_theResult___fst_exp__h59725 == 11'd0) ? - 12'd3074 : - { theResult___fst_exp9725_MINUS_1023__q6[10], - theResult___fst_exp9725_MINUS_1023__q6 } ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 = - (sfdin__h51553[57] ? - 6'd0 : - (sfdin__h51553[56] ? - 6'd1 : - (sfdin__h51553[55] ? - 6'd2 : - (sfdin__h51553[54] ? - 6'd3 : - (sfdin__h51553[53] ? - 6'd4 : - (sfdin__h51553[52] ? - 6'd5 : - (sfdin__h51553[51] ? - 6'd6 : - (sfdin__h51553[50] ? - 6'd7 : - (sfdin__h51553[49] ? - 6'd8 : - (sfdin__h51553[48] ? - 6'd9 : - (sfdin__h51553[47] ? - 6'd10 : - (sfdin__h51553[46] ? - 6'd11 : - (sfdin__h51553[45] ? - 6'd12 : - (sfdin__h51553[44] ? - 6'd13 : - (sfdin__h51553[43] ? - 6'd14 : - (sfdin__h51553[42] ? - 6'd15 : - (sfdin__h51553[41] ? - 6'd16 : - (sfdin__h51553[40] ? - 6'd17 : - (sfdin__h51553[39] ? - 6'd18 : - (sfdin__h51553[38] ? - 6'd19 : - (sfdin__h51553[37] ? - 6'd20 : - (sfdin__h51553[36] ? - 6'd21 : - (sfdin__h51553[35] ? - 6'd22 : - (sfdin__h51553[34] ? - 6'd23 : - (sfdin__h51553[33] ? - 6'd24 : - (sfdin__h51553[32] ? - 6'd25 : - (sfdin__h51553[31] ? - 6'd26 : - (sfdin__h51553[30] ? - 6'd27 : - (sfdin__h51553[29] ? - 6'd28 : - (sfdin__h51553[28] ? - 6'd29 : - (sfdin__h51553[27] ? - 6'd30 : - (sfdin__h51553[26] ? - 6'd31 : - (sfdin__h51553[25] ? - 6'd32 : - (sfdin__h51553[24] ? - 6'd33 : - (sfdin__h51553[23] ? - 6'd34 : - (sfdin__h51553[22] ? - 6'd35 : - (sfdin__h51553[21] ? - 6'd36 : - (sfdin__h51553[20] ? - 6'd37 : - (sfdin__h51553[19] ? - 6'd38 : - (sfdin__h51553[18] ? - 6'd39 : - (sfdin__h51553[17] ? - 6'd40 : - (sfdin__h51553[16] ? - 6'd41 : - (sfdin__h51553[15] ? - 6'd42 : - (sfdin__h51553[14] ? - 6'd43 : - (sfdin__h51553[13] ? - 6'd44 : - (sfdin__h51553[12] ? - 6'd45 : - (sfdin__h51553[11] ? - 6'd46 : - (sfdin__h51553[10] ? - 6'd47 : - (sfdin__h51553[9] ? - 6'd48 : - (sfdin__h51553[8] ? - 6'd49 : - (sfdin__h51553[7] ? - 6'd50 : - (sfdin__h51553[6] ? - 6'd51 : - (sfdin__h51553[5] ? - 6'd52 : - (sfdin__h51553[4] ? - 6'd53 : - (sfdin__h51553[3] ? - 6'd54 : - (sfdin__h51553[2] ? - 6'd55 : - (sfdin__h51553[1] ? - 6'd56 : - (sfdin__h51553[0] ? - 6'd57 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 = - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 - - 12'd3074 ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770 = - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 : - { fpu_fState_S3$D_OUT[129:128], - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[127] : - fpu_fState_S3$D_OUT[127], - fpu_fState_S3$D_OUT[126], - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[125] : - fpu_fState_S3$D_OUT[125] } ; - assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 = - (sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h59768, sfdin__h59762[57:6] } ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 = - (((fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3[10]}}, - fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 }) - - { 7'd0, b__h21789 }) - - (((fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4[10]}}, - fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 }) - - { 7'd0, b__h29207 }) ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ - 13'h1000) <= - 13'd5120 ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ - 13'h1000) < - 13'd3020 ; - assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^ - 13'h1000) < - 13'd3074 ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 : - CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0) ? - 11'd2047 : - ((fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? - 11'd0 : - _theResult___fst_exp__h37217) ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ? - 52'd0 : - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? - _theResult___fst_sfd__h37707 : - _theResult___fst_sfd__h37218) ; - assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54]) ? - { fpu_fOperands_S0$D_OUT[66:55], sfd__h36687 } : - ((fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118]) ? - fpu_fOperands_S0$D_OUT[130:67] : - ((fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54]) ? - fpu_fOperands_S0$D_OUT[66:3] : - NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305)) ; - assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 = - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_fState_S3$D_OUT[57:56] == 2'b0 && - !fpu_fState_S3$D_OUT[194] : - !fpu_fState_S3$D_OUT[194] ; - assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 = - ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - { fpu_fState_S3$D_OUT[129:128], - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[127], - fpu_fState_S3$D_OUT[126], - fpu_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_fState_S3$D_OUT[125] } : - fpu_fState_S3$D_OUT[129:125]) | - { 2'd0, - sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023, - _theResult___fst_exp__h59771 == 11'd0 && guard__h51381 != 2'd0, - sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023 } ; - assign IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 = - (fpu_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h60417[53:52] == 2'b01) ? - 11'd1 : - fpu_fState_S4$D_OUT[64:54] ; - assign IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19 = - int_div_fNext_57$D_OUT[115] ? - int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 - - 58'd1 : - int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 ; - assign IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8 = - sfdin__h59762[5] ? 2'd2 : 2'd0 ; - assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 = - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) ; - assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305 = - { NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 && - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275, - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286, - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 ? - 52'h8000000000000 : - IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 } ; - assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334 = - (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 && - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; - assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341 = - (fpu_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperands_S0$D_OUT[54:3] != 52'd0) && - (!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208) ; - assign _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 = - ({ 6'd0, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ^ - 12'h800) <= - (IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ^ - 12'h800) ; - assign _theResult____h50063 = - (fpu_fState_S2$D_OUT[10:0] < 11'd58) ? - result__h50108 : - result__h50258 ; - assign _theResult___exp__h60910 = - sfd__h60417[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h61001) : - IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 ; - assign _theResult___fst__h49072 = - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 ? - value__h49300[10:0] : - 11'd0 ; - assign _theResult___fst_exp__h59719 = fpu_fState_S3$D_OUT[120:110] - 11'd1 ; - assign _theResult___fst_exp__h59722 = - (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___fst_exp__h59719 : - 11'd2046 ; - assign _theResult___fst_exp__h59725 = - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___fst_exp__h59722 : - fpu_fState_S3$D_OUT[120:110] ; - assign _theResult___fst_exp__h59768 = - sfdin__h51553[57] ? - _theResult___fst_exp__h59791 : - _theResult___fst_exp__h59855 ; - assign _theResult___fst_exp__h59771 = - (sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h59768 ; - assign _theResult___fst_exp__h59791 = - (_theResult___fst_exp__h59725 == 11'd0) ? - 11'd2 : - _theResult___fst_exp__h59725 + 11'd1 ; - assign _theResult___fst_exp__h59807 = - (_theResult___fst_exp__h59725 == 11'd0) ? - 11'd1 : - _theResult___fst_exp__h59725 ; - assign _theResult___fst_exp__h59846 = - _theResult___fst_exp__h59725 - - { 5'd0, - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ; - assign _theResult___fst_exp__h59852 = - (!sfdin__h51553[57] && !sfdin__h51553[56] && - !sfdin__h51553[55] && - !sfdin__h51553[54] && - !sfdin__h51553[53] && - !sfdin__h51553[52] && - !sfdin__h51553[51] && - !sfdin__h51553[50] && - !sfdin__h51553[49] && - !sfdin__h51553[48] && - !sfdin__h51553[47] && - !sfdin__h51553[46] && - !sfdin__h51553[45] && - !sfdin__h51553[44] && - !sfdin__h51553[43] && - !sfdin__h51553[42] && - !sfdin__h51553[41] && - !sfdin__h51553[40] && - !sfdin__h51553[39] && - !sfdin__h51553[38] && - !sfdin__h51553[37] && - !sfdin__h51553[36] && - !sfdin__h51553[35] && - !sfdin__h51553[34] && - !sfdin__h51553[33] && - !sfdin__h51553[32] && - !sfdin__h51553[31] && - !sfdin__h51553[30] && - !sfdin__h51553[29] && - !sfdin__h51553[28] && - !sfdin__h51553[27] && - !sfdin__h51553[26] && - !sfdin__h51553[25] && - !sfdin__h51553[24] && - !sfdin__h51553[23] && - !sfdin__h51553[22] && - !sfdin__h51553[21] && - !sfdin__h51553[20] && - !sfdin__h51553[19] && - !sfdin__h51553[18] && - !sfdin__h51553[17] && - !sfdin__h51553[16] && - !sfdin__h51553[15] && - !sfdin__h51553[14] && - !sfdin__h51553[13] && - !sfdin__h51553[12] && - !sfdin__h51553[11] && - !sfdin__h51553[10] && - !sfdin__h51553[9] && - !sfdin__h51553[8] && - !sfdin__h51553[7] && - !sfdin__h51553[6] && - !sfdin__h51553[5] && - !sfdin__h51553[4] && - !sfdin__h51553[3] && - !sfdin__h51553[2] && - !sfdin__h51553[1] && - !sfdin__h51553[0] || - !_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727) ? - 11'd0 : - _theResult___fst_exp__h59846 ; - assign _theResult___fst_exp__h59855 = - (!sfdin__h51553[57] && sfdin__h51553[56]) ? - _theResult___fst_exp__h59807 : - _theResult___fst_exp__h59852 ; - assign _theResult___fst_exp__h60991 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h60988 ; - assign _theResult___fst_sfd__h60992 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h60989 ; - assign _theResult___sfd__h60911 = - sfd__h60417[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h60417[52:1]) : - sfd__h60417[51:0] ; - assign _theResult___snd__h52150 = { fpu_fState_S3$D_OUT[56:0], 1'd0 } ; - assign _theResult___snd__h59785 = { sfdin__h51553[56:0], 1'd0 } ; - assign _theResult___snd__h59800 = - (!sfdin__h51553[57] && sfdin__h51553[56]) ? - _theResult___snd__h59802 : - _theResult___snd__h59815 ; - assign _theResult___snd__h59802 = { sfdin__h51553[55:0], 2'd0 } ; - assign _theResult___snd__h59815 = - (!sfdin__h51553[57] && !sfdin__h51553[56] && - !sfdin__h51553[55] && - !sfdin__h51553[54] && - !sfdin__h51553[53] && - !sfdin__h51553[52] && - !sfdin__h51553[51] && - !sfdin__h51553[50] && - !sfdin__h51553[49] && - !sfdin__h51553[48] && - !sfdin__h51553[47] && - !sfdin__h51553[46] && - !sfdin__h51553[45] && - !sfdin__h51553[44] && - !sfdin__h51553[43] && - !sfdin__h51553[42] && - !sfdin__h51553[41] && - !sfdin__h51553[40] && - !sfdin__h51553[39] && - !sfdin__h51553[38] && - !sfdin__h51553[37] && - !sfdin__h51553[36] && - !sfdin__h51553[35] && - !sfdin__h51553[34] && - !sfdin__h51553[33] && - !sfdin__h51553[32] && - !sfdin__h51553[31] && - !sfdin__h51553[30] && - !sfdin__h51553[29] && - !sfdin__h51553[28] && - !sfdin__h51553[27] && - !sfdin__h51553[26] && - !sfdin__h51553[25] && - !sfdin__h51553[24] && - !sfdin__h51553[23] && - !sfdin__h51553[22] && - !sfdin__h51553[21] && - !sfdin__h51553[20] && - !sfdin__h51553[19] && - !sfdin__h51553[18] && - !sfdin__h51553[17] && - !sfdin__h51553[16] && - !sfdin__h51553[15] && - !sfdin__h51553[14] && - !sfdin__h51553[13] && - !sfdin__h51553[12] && - !sfdin__h51553[11] && - !sfdin__h51553[10] && - !sfdin__h51553[9] && - !sfdin__h51553[8] && - !sfdin__h51553[7] && - !sfdin__h51553[6] && - !sfdin__h51553[5] && - !sfdin__h51553[4] && - !sfdin__h51553[3] && - !sfdin__h51553[2] && - !sfdin__h51553[1] && - !sfdin__h51553[0]) ? - sfdin__h51553 : - _theResult___snd__h59821 ; - assign _theResult___snd__h59821 = - { IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7[55:0], - 2'd0 } ; - assign _theResult___snd__h59839 = - sfdin__h51553 << - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ; - assign _theResult___snd__h59844 = - sfdin__h51553 << - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 ; - assign _theResult___snd_fst__h59874 = - { IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8[1], - { sfdin__h59762[4:0], 52'd0 } != 57'd0 } ; - assign _theResult___snd_fst_exp__h49084 = - (IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352) ? - 11'd0 : - value__h49124[10:0] ; - assign _theResult___snd_fst_exp__h49087 = - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ? - _theResult___snd_fst_exp__h49084 : - 11'd2046 ; - assign _theResult___snd_fst_exp__h49111 = - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 ? - 11'd0 : - _theResult___snd_fst_exp__h49087 ; - assign _theResult___snd_fst_sfd__h49112 = - (fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ? - 52'd0 : - 52'hFFFFFFFFFFFFF ; - assign _theResult___snd_snd_snd__h51398 = - (fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___snd__h52150 : - fpu_fState_S3$D_OUT[57:0] ; - assign b__h10163 = { int_div_fNext_28$D_OUT[231:174], 58'd0 } ; - assign b__h10487 = { int_div_fNext_29$D_OUT[231:174], 58'd0 } ; - assign b__h10811 = { int_div_fNext_30$D_OUT[231:174], 58'd0 } ; - assign b__h1091 = { int_div_fNext_0$D_OUT[231:174], 58'd0 } ; - assign b__h11135 = { int_div_fNext_31$D_OUT[231:174], 58'd0 } ; - assign b__h11459 = { int_div_fNext_32$D_OUT[231:174], 58'd0 } ; - assign b__h11783 = { int_div_fNext_33$D_OUT[231:174], 58'd0 } ; - assign b__h12107 = { int_div_fNext_34$D_OUT[231:174], 58'd0 } ; - assign b__h12431 = { int_div_fNext_35$D_OUT[231:174], 58'd0 } ; - assign b__h12755 = { int_div_fNext_36$D_OUT[231:174], 58'd0 } ; - assign b__h13079 = { int_div_fNext_37$D_OUT[231:174], 58'd0 } ; - assign b__h13403 = { int_div_fNext_38$D_OUT[231:174], 58'd0 } ; - assign b__h13727 = { int_div_fNext_39$D_OUT[231:174], 58'd0 } ; - assign b__h14051 = { int_div_fNext_40$D_OUT[231:174], 58'd0 } ; - assign b__h1415 = { int_div_fNext_1$D_OUT[231:174], 58'd0 } ; - assign b__h14375 = { int_div_fNext_41$D_OUT[231:174], 58'd0 } ; - assign b__h14699 = { int_div_fNext_42$D_OUT[231:174], 58'd0 } ; - assign b__h15023 = { int_div_fNext_43$D_OUT[231:174], 58'd0 } ; - assign b__h15347 = { int_div_fNext_44$D_OUT[231:174], 58'd0 } ; - assign b__h15671 = { int_div_fNext_45$D_OUT[231:174], 58'd0 } ; - assign b__h15995 = { int_div_fNext_46$D_OUT[231:174], 58'd0 } ; - assign b__h16319 = { int_div_fNext_47$D_OUT[231:174], 58'd0 } ; - assign b__h16643 = { int_div_fNext_48$D_OUT[231:174], 58'd0 } ; - assign b__h16967 = { int_div_fNext_49$D_OUT[231:174], 58'd0 } ; - assign b__h17291 = { int_div_fNext_50$D_OUT[231:174], 58'd0 } ; - assign b__h1739 = { int_div_fNext_2$D_OUT[231:174], 58'd0 } ; - assign b__h17615 = { int_div_fNext_51$D_OUT[231:174], 58'd0 } ; - assign b__h17939 = { int_div_fNext_52$D_OUT[231:174], 58'd0 } ; - assign b__h18263 = { int_div_fNext_53$D_OUT[231:174], 58'd0 } ; - assign b__h18587 = { int_div_fNext_54$D_OUT[231:174], 58'd0 } ; - assign b__h18911 = { int_div_fNext_55$D_OUT[231:174], 58'd0 } ; - assign b__h19235 = { int_div_fNext_56$D_OUT[231:174], 58'd0 } ; - assign b__h19482 = { int_div_fNext_57$D_OUT[231:174], 58'd0 } ; - assign b__h2063 = { int_div_fNext_3$D_OUT[231:174], 58'd0 } ; - assign b__h21789 = - (fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ? - (fpu_fOperands_S0$D_OUT[118] ? - 6'd1 : - (fpu_fOperands_S0$D_OUT[117] ? - 6'd2 : - (fpu_fOperands_S0$D_OUT[116] ? - 6'd3 : - (fpu_fOperands_S0$D_OUT[115] ? - 6'd4 : - (fpu_fOperands_S0$D_OUT[114] ? - 6'd5 : - (fpu_fOperands_S0$D_OUT[113] ? - 6'd6 : - (fpu_fOperands_S0$D_OUT[112] ? - 6'd7 : - (fpu_fOperands_S0$D_OUT[111] ? - 6'd8 : - (fpu_fOperands_S0$D_OUT[110] ? - 6'd9 : - (fpu_fOperands_S0$D_OUT[109] ? - 6'd10 : - (fpu_fOperands_S0$D_OUT[108] ? - 6'd11 : - (fpu_fOperands_S0$D_OUT[107] ? - 6'd12 : - (fpu_fOperands_S0$D_OUT[106] ? - 6'd13 : - (fpu_fOperands_S0$D_OUT[105] ? - 6'd14 : - (fpu_fOperands_S0$D_OUT[104] ? - 6'd15 : - (fpu_fOperands_S0$D_OUT[103] ? - 6'd16 : - (fpu_fOperands_S0$D_OUT[102] ? - 6'd17 : - (fpu_fOperands_S0$D_OUT[101] ? - 6'd18 : - (fpu_fOperands_S0$D_OUT[100] ? - 6'd19 : - (fpu_fOperands_S0$D_OUT[99] ? - 6'd20 : - (fpu_fOperands_S0$D_OUT[98] ? - 6'd21 : - (fpu_fOperands_S0$D_OUT[97] ? - 6'd22 : - (fpu_fOperands_S0$D_OUT[96] ? - 6'd23 : - (fpu_fOperands_S0$D_OUT[95] ? - 6'd24 : - (fpu_fOperands_S0$D_OUT[94] ? - 6'd25 : - (fpu_fOperands_S0$D_OUT[93] ? - 6'd26 : - (fpu_fOperands_S0$D_OUT[92] ? - 6'd27 : - (fpu_fOperands_S0$D_OUT[91] ? - 6'd28 : - (fpu_fOperands_S0$D_OUT[90] ? - 6'd29 : - (fpu_fOperands_S0$D_OUT[89] ? - 6'd30 : - (fpu_fOperands_S0$D_OUT[88] ? - 6'd31 : - (fpu_fOperands_S0$D_OUT[87] ? - 6'd32 : - (fpu_fOperands_S0$D_OUT[86] ? - 6'd33 : - (fpu_fOperands_S0$D_OUT[85] ? - 6'd34 : - (fpu_fOperands_S0$D_OUT[84] ? - 6'd35 : - (fpu_fOperands_S0$D_OUT[83] ? - 6'd36 : - (fpu_fOperands_S0$D_OUT[82] ? - 6'd37 : - (fpu_fOperands_S0$D_OUT[81] ? - 6'd38 : - (fpu_fOperands_S0$D_OUT[80] ? - 6'd39 : - (fpu_fOperands_S0$D_OUT[79] ? - 6'd40 : - (fpu_fOperands_S0$D_OUT[78] ? - 6'd41 : - (fpu_fOperands_S0$D_OUT[77] ? - 6'd42 : - (fpu_fOperands_S0$D_OUT[76] ? - 6'd43 : - (fpu_fOperands_S0$D_OUT[75] ? - 6'd44 : - (fpu_fOperands_S0$D_OUT[74] ? - 6'd45 : - (fpu_fOperands_S0$D_OUT[73] ? - 6'd46 : - (fpu_fOperands_S0$D_OUT[72] ? - 6'd47 : - (fpu_fOperands_S0$D_OUT[71] ? - 6'd48 : - (fpu_fOperands_S0$D_OUT[70] ? - 6'd49 : - (fpu_fOperands_S0$D_OUT[69] ? - 6'd50 : - (fpu_fOperands_S0$D_OUT[68] ? - 6'd51 : - (fpu_fOperands_S0$D_OUT[67] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h2387 = { int_div_fNext_4$D_OUT[231:174], 58'd0 } ; - assign b__h2711 = { int_div_fNext_5$D_OUT[231:174], 58'd0 } ; - assign b__h29207 = - (fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ? - (fpu_fOperands_S0$D_OUT[54] ? - 6'd1 : - (fpu_fOperands_S0$D_OUT[53] ? - 6'd2 : - (fpu_fOperands_S0$D_OUT[52] ? - 6'd3 : - (fpu_fOperands_S0$D_OUT[51] ? - 6'd4 : - (fpu_fOperands_S0$D_OUT[50] ? - 6'd5 : - (fpu_fOperands_S0$D_OUT[49] ? - 6'd6 : - (fpu_fOperands_S0$D_OUT[48] ? - 6'd7 : - (fpu_fOperands_S0$D_OUT[47] ? - 6'd8 : - (fpu_fOperands_S0$D_OUT[46] ? - 6'd9 : - (fpu_fOperands_S0$D_OUT[45] ? - 6'd10 : - (fpu_fOperands_S0$D_OUT[44] ? - 6'd11 : - (fpu_fOperands_S0$D_OUT[43] ? - 6'd12 : - (fpu_fOperands_S0$D_OUT[42] ? - 6'd13 : - (fpu_fOperands_S0$D_OUT[41] ? - 6'd14 : - (fpu_fOperands_S0$D_OUT[40] ? - 6'd15 : - (fpu_fOperands_S0$D_OUT[39] ? - 6'd16 : - (fpu_fOperands_S0$D_OUT[38] ? - 6'd17 : - (fpu_fOperands_S0$D_OUT[37] ? - 6'd18 : - (fpu_fOperands_S0$D_OUT[36] ? - 6'd19 : - (fpu_fOperands_S0$D_OUT[35] ? - 6'd20 : - (fpu_fOperands_S0$D_OUT[34] ? - 6'd21 : - (fpu_fOperands_S0$D_OUT[33] ? - 6'd22 : - (fpu_fOperands_S0$D_OUT[32] ? - 6'd23 : - (fpu_fOperands_S0$D_OUT[31] ? - 6'd24 : - (fpu_fOperands_S0$D_OUT[30] ? - 6'd25 : - (fpu_fOperands_S0$D_OUT[29] ? - 6'd26 : - (fpu_fOperands_S0$D_OUT[28] ? - 6'd27 : - (fpu_fOperands_S0$D_OUT[27] ? - 6'd28 : - (fpu_fOperands_S0$D_OUT[26] ? - 6'd29 : - (fpu_fOperands_S0$D_OUT[25] ? - 6'd30 : - (fpu_fOperands_S0$D_OUT[24] ? - 6'd31 : - (fpu_fOperands_S0$D_OUT[23] ? - 6'd32 : - (fpu_fOperands_S0$D_OUT[22] ? - 6'd33 : - (fpu_fOperands_S0$D_OUT[21] ? - 6'd34 : - (fpu_fOperands_S0$D_OUT[20] ? - 6'd35 : - (fpu_fOperands_S0$D_OUT[19] ? - 6'd36 : - (fpu_fOperands_S0$D_OUT[18] ? - 6'd37 : - (fpu_fOperands_S0$D_OUT[17] ? - 6'd38 : - (fpu_fOperands_S0$D_OUT[16] ? - 6'd39 : - (fpu_fOperands_S0$D_OUT[15] ? - 6'd40 : - (fpu_fOperands_S0$D_OUT[14] ? - 6'd41 : - (fpu_fOperands_S0$D_OUT[13] ? - 6'd42 : - (fpu_fOperands_S0$D_OUT[12] ? - 6'd43 : - (fpu_fOperands_S0$D_OUT[11] ? - 6'd44 : - (fpu_fOperands_S0$D_OUT[10] ? - 6'd45 : - (fpu_fOperands_S0$D_OUT[9] ? - 6'd46 : - (fpu_fOperands_S0$D_OUT[8] ? - 6'd47 : - (fpu_fOperands_S0$D_OUT[7] ? - 6'd48 : - (fpu_fOperands_S0$D_OUT[6] ? - 6'd49 : - (fpu_fOperands_S0$D_OUT[5] ? - 6'd50 : - (fpu_fOperands_S0$D_OUT[4] ? - 6'd51 : - (fpu_fOperands_S0$D_OUT[3] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h3035 = { int_div_fNext_6$D_OUT[231:174], 58'd0 } ; - assign b__h3359 = { int_div_fNext_7$D_OUT[231:174], 58'd0 } ; - assign b__h3683 = { int_div_fNext_8$D_OUT[231:174], 58'd0 } ; - assign b__h378 = { 1'd0, int_div_fRequest$D_OUT[56:0] } ; - assign b__h4007 = { int_div_fNext_9$D_OUT[231:174], 58'd0 } ; - assign b__h4331 = { int_div_fNext_10$D_OUT[231:174], 58'd0 } ; - assign b__h4655 = { int_div_fNext_11$D_OUT[231:174], 58'd0 } ; - assign b__h4979 = { int_div_fNext_12$D_OUT[231:174], 58'd0 } ; - assign b__h5303 = { int_div_fNext_13$D_OUT[231:174], 58'd0 } ; - assign b__h5627 = { int_div_fNext_14$D_OUT[231:174], 58'd0 } ; - assign b__h5951 = { int_div_fNext_15$D_OUT[231:174], 58'd0 } ; - assign b__h6275 = { int_div_fNext_16$D_OUT[231:174], 58'd0 } ; - assign b__h6599 = { int_div_fNext_17$D_OUT[231:174], 58'd0 } ; - assign b__h6923 = { int_div_fNext_18$D_OUT[231:174], 58'd0 } ; - assign b__h7247 = { int_div_fNext_19$D_OUT[231:174], 58'd0 } ; - assign b__h7571 = { int_div_fNext_20$D_OUT[231:174], 58'd0 } ; - assign b__h767 = { int_div_fFirst$D_OUT[231:174], 58'd0 } ; - assign b__h7895 = { int_div_fNext_21$D_OUT[231:174], 58'd0 } ; - assign b__h8219 = { int_div_fNext_22$D_OUT[231:174], 58'd0 } ; - assign b__h8543 = { int_div_fNext_23$D_OUT[231:174], 58'd0 } ; - assign b__h8867 = { int_div_fNext_24$D_OUT[231:174], 58'd0 } ; - assign b__h9191 = { int_div_fNext_25$D_OUT[231:174], 58'd0 } ; - assign b__h9515 = { int_div_fNext_26$D_OUT[231:174], 58'd0 } ; - assign b__h9839 = { int_div_fNext_27$D_OUT[231:174], 58'd0 } ; - assign din_inc___2_exp__h61001 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; - assign fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 = - fpu_fOperands_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 = - fpu_fOperands_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 = - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54] || - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 ; - assign fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 = - fpu_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperands_S0$D_OUT[54:3] == 52'd0 || - !IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 || - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ; - assign fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 = - fpu_fOperands_S0$D_OUT[130] == fpu_fOperands_S0$D_OUT[66] ; - assign fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780 = - { fpu_fState_S3$D_OUT[121], - IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ? - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 : - ((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_fState_S3$D_OUT[57:56] == 2'b0) ? - { _theResult___fst_exp__h59719, - fpu_fState_S3$D_OUT[109:58] } : - 63'h7FEFFFFFFFFFFFFF) : - fpu_fState_S3$D_OUT[120:58]) } ; - assign guard__h51381 = x__h60140 ; - assign int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 = - int_div_fNext_57$D_OUT[173:116] + - -(~int_div_fNext_57$D_OUT[173:116]) ; - assign out_exp__h60913 = - fpu_fState_S4$D_OUT[2] ? - _theResult___exp__h60910 : - fpu_fState_S4$D_OUT[64:54] ; - assign out_sfd__h60914 = - fpu_fState_S4$D_OUT[2] ? - _theResult___sfd__h60911 : - fpu_fState_S4$D_OUT[53:2] ; - assign result__h50077 = { _theResult____h50063[57:1], 1'd1 } ; - assign result__h50108 = - { 1'd0, - value__h50121[56:1], - value__h50121[0] | sfdlsb__h50103 } ; - assign result__h50258 = - (int_div_fResponse$D_OUT[113:57] == 57'd0) ? 58'd0 : 58'd1 ; - assign sfdA__h19785 = - { fpu_fOperands_S0$D_OUT[129:119] != 11'd0, - fpu_fOperands_S0$D_OUT[118:67] } ; - assign sfdA__h19789 = sfdA__h19785 << b__h21789 ; - assign sfdB__h19786 = - { fpu_fOperands_S0$D_OUT[65:55] != 11'd0, - fpu_fOperands_S0$D_OUT[54:3] } ; - assign sfdB__h19791 = sfdB__h19786 << b__h29207 ; - assign sfd__h36684 = { 1'd1, fpu_fOperands_S0$D_OUT[117:67] } ; - assign sfd__h36687 = { 1'd1, fpu_fOperands_S0$D_OUT[53:3] } ; - assign sfd__h60417 = - { 1'b0, - fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfdin__h51553 = - (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___snd_snd_snd__h51398 : - fpu_fState_S3$D_OUT[57:0] ; - assign sfdin__h59762 = - sfdin__h51553[57] ? - _theResult___snd__h59785 : - _theResult___snd__h59800 ; - assign sfdlsb__h50103 = x__h50197 != 58'd0 ; - assign theResult___fst_exp9725_MINUS_1023__q6 = - _theResult___fst_exp__h59725 - 11'd1023 ; - assign value__h19447 = - int_div_fNext_57$D_OUT[115] ? - int_div_fNext_57$D_OUT[115:0] + b__h19482 : - int_div_fNext_57$D_OUT[115:0] ; - assign value__h49124 = - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 + - 13'd1023 ; - assign value__h49179 = { 1'b0, sfdA__h19789 } ; - assign value__h49300 = - 13'd7170 - - IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ; - assign value__h50121 = - int_div_fResponse$D_OUT[113:57] >> fpu_fState_S2$D_OUT[10:0] ; - assign x__h49176 = { value__h49179, 60'd0 } ; - assign x__h49237 = { sfdB__h19791, 4'b0 } ; - assign x__h49291 = - fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 ? - 11'd0 : - _theResult___fst__h49072 ; - assign x__h50197 = { 1'd0, int_div_fResponse$D_OUT[113:57] } << x__h50204 ; - assign x__h50204 = 11'd58 - fpu_fState_S2$D_OUT[10:0] ; - assign x__h50487 = - (int_div_fResponse$D_OUT[56:0] == 57'd0) ? - _theResult____h50063 : - result__h50077 ; - assign x__h60140 = - (sfdin__h51553[57] && - IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h59874 ; - always@(fpu_fState_S4$D_OUT or out_sfd__h60914 or _theResult___sfd__h60911) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - fpu_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - out_sfd__h60914; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - _theResult___sfd__h60911; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___sfd__h60911) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - fpu_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - _theResult___sfd__h60911; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or - _theResult___sfd__h60911) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h60989 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; - 3'd1: - _theResult___fst_sfd__h60989 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; - 3'd2: - _theResult___fst_sfd__h60989 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___sfd__h60911; - 3'd3: - _theResult___fst_sfd__h60989 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[53:2] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___sfd__h60911 : - fpu_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h60989 = fpu_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h60989 = 52'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_exp__h37217 = 11'd2047; - 3'd2: - _theResult___fst_exp__h37217 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 11'd2047 : - 11'd2046; - 3'd3: - _theResult___fst_exp__h37217 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 11'd2046 : - 11'd2047; - 3'd4: _theResult___fst_exp__h37217 = 11'd2046; - default: _theResult___fst_exp__h37217 = 11'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_sfd__h37218 = 52'd0; - 3'd2: - _theResult___fst_sfd__h37218 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - _theResult___fst_sfd__h37218 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'hFFFFFFFFFFFFF : - 52'd0; - 3'd4: _theResult___fst_sfd__h37218 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h37218 = 52'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0: _theResult___fst_sfd__h37707 = 52'd0; - 3'd1: _theResult___fst_sfd__h37707 = 52'd1; - 3'd2: - _theResult___fst_sfd__h37707 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'd1 : - 52'd0; - 3'd3: - _theResult___fst_sfd__h37707 = - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ? - 52'd0 : - 52'd1; - default: _theResult___fst_sfd__h37707 = 52'd0; - endcase - end - always@(fpu_fOperands_S0$D_OUT or - fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258) - begin - case (fpu_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; - default: CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 = - fpu_fOperands_S0$D_OUT[2:0] == 3'd4 && - !fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258; - endcase - end - always@(fpu_fState_S4$D_OUT or out_exp__h60913 or _theResult___exp__h60910) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = - fpu_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = - out_exp__h60913; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 = - _theResult___exp__h60910; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___exp__h60910) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = - fpu_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 = - _theResult___exp__h60910; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 or - _theResult___exp__h60910) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h60988 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9; - 3'd1: - _theResult___fst_exp__h60988 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10; - 3'd2: - _theResult___fst_exp__h60988 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___exp__h60910; - 3'd3: - _theResult___fst_exp__h60988 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:54] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___exp__h60910 : - fpu_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h60988 = fpu_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h60988 = 11'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = - fpu_fState_S4$D_OUT[65]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 = - fpu_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; - 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:2] : - (fpu_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : - fpu_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = - fpu_fState_S4$D_OUT[64:2]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = 63'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = - fpu_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = - fpu_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 : - fpu_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = - { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 }; - 3'd1: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[65:2] : - { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_fState_S4$D_OUT[65], - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 }; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 = - { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 }; - endcase - end - always@(fpu_fState_S3$D_OUT) - begin - case (fpu_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = - fpu_fState_S3$D_OUT[121]; - default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 = - fpu_fState_S3$D_OUT[124:122] == 3'd4 && - fpu_fState_S3$D_OUT[121]; - endcase - end - always@(fpu_fState_S3$D_OUT) - begin - case (fpu_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - 63'h7FF0000000000000; - 3'd2: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - fpu_fState_S3$D_OUT[121] ? - 63'h7FEFFFFFFFFFFFFF : - 63'h7FF0000000000000; - 3'd3: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - fpu_fState_S3$D_OUT[121] ? - 63'h7FF0000000000000 : - 63'h7FEFFFFFFFFFFFFF; - 3'd4: - CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = - 63'h7FEFFFFFFFFFFFFF; - default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = 63'd0; - endcase - end + // submodule fpu + mkXilinxFpDiv fpu(.CLK(CLK), + .RST_N(RST_N), + .request_put(fpu$request_put), + .EN_request_put(fpu$EN_request_put), + .EN_response_get(fpu$EN_response_get), + .RDY_request_put(fpu$RDY_request_put), + .response_get(fpu$response_get), + .RDY_response_get(fpu$RDY_response_get)); + + // submodule fpu + assign fpu$request_put = request_put ; + assign fpu$EN_request_put = EN_request_put ; + assign fpu$EN_response_get = EN_response_get ; endmodule // mkDoubleDiv diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v index de193e3..5d2e0d5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v @@ -7,16 +7,15 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 reg -// RDY_response_get O 1 reg +// response_get O 69 +// RDY_response_get O 1 // CLK I 1 clock // RST_N I 1 reset -// request_put I 196 reg +// request_put I 196 // EN_request_put I 1 // EN_response_get I 1 // -// Combinational paths from inputs to outputs: -// EN_response_get -> RDY_request_put +// No combinational paths from inputs to outputs // // @@ -60,2035 +59,44 @@ module mkDoubleFMA(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu_fOperand_S0 - wire [195 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; - wire fpu_fOperand_S0$CLR, - fpu_fOperand_S0$DEQ, - fpu_fOperand_S0$EMPTY_N, - fpu_fOperand_S0$ENQ, - fpu_fOperand_S0$FULL_N; - - // ports of submodule fpu_fProd_S2 - wire [105 : 0] fpu_fProd_S2$D_IN, fpu_fProd_S2$D_OUT; - wire fpu_fProd_S2$CLR, - fpu_fProd_S2$DEQ, - fpu_fProd_S2$EMPTY_N, - fpu_fProd_S2$ENQ, - fpu_fProd_S2$FULL_N; - - // ports of submodule fpu_fProd_S3 - wire [105 : 0] fpu_fProd_S3$D_IN, fpu_fProd_S3$D_OUT; - wire fpu_fProd_S3$CLR, - fpu_fProd_S3$DEQ, - fpu_fProd_S3$EMPTY_N, - fpu_fProd_S3$ENQ, - fpu_fProd_S3$FULL_N; - - // ports of submodule fpu_fResult_S9 - wire [68 : 0] fpu_fResult_S9$D_IN, fpu_fResult_S9$D_OUT; - wire fpu_fResult_S9$CLR, - fpu_fResult_S9$DEQ, - fpu_fResult_S9$EMPTY_N, - fpu_fResult_S9$ENQ, - fpu_fResult_S9$FULL_N; - - // ports of submodule fpu_fState_S1 - wire [257 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; - wire fpu_fState_S1$CLR, - fpu_fState_S1$DEQ, - fpu_fState_S1$EMPTY_N, - fpu_fState_S1$ENQ, - fpu_fState_S1$FULL_N; - - // ports of submodule fpu_fState_S2 - wire [151 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; - wire fpu_fState_S2$CLR, - fpu_fState_S2$DEQ, - fpu_fState_S2$EMPTY_N, - fpu_fState_S2$ENQ, - fpu_fState_S2$FULL_N; - - // ports of submodule fpu_fState_S3 - wire [151 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; - wire fpu_fState_S3$CLR, - fpu_fState_S3$DEQ, - fpu_fState_S3$EMPTY_N, - fpu_fState_S3$ENQ, - fpu_fState_S3$FULL_N; - - // ports of submodule fpu_fState_S4 - wire [203 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; - wire fpu_fState_S4$CLR, - fpu_fState_S4$DEQ, - fpu_fState_S4$EMPTY_N, - fpu_fState_S4$ENQ, - fpu_fState_S4$FULL_N; - - // ports of submodule fpu_fState_S5 - wire [215 : 0] fpu_fState_S5$D_IN, fpu_fState_S5$D_OUT; - wire fpu_fState_S5$CLR, - fpu_fState_S5$DEQ, - fpu_fState_S5$EMPTY_N, - fpu_fState_S5$ENQ, - fpu_fState_S5$FULL_N; - - // ports of submodule fpu_fState_S6 - wire [202 : 0] fpu_fState_S6$D_IN, fpu_fState_S6$D_OUT; - wire fpu_fState_S6$CLR, - fpu_fState_S6$DEQ, - fpu_fState_S6$EMPTY_N, - fpu_fState_S6$ENQ, - fpu_fState_S6$FULL_N; - - // ports of submodule fpu_fState_S7 - wire [202 : 0] fpu_fState_S7$D_IN, fpu_fState_S7$D_OUT; - wire fpu_fState_S7$CLR, - fpu_fState_S7$DEQ, - fpu_fState_S7$EMPTY_N, - fpu_fState_S7$ENQ, - fpu_fState_S7$FULL_N; - - // ports of submodule fpu_fState_S8 - wire [140 : 0] fpu_fState_S8$D_IN, fpu_fState_S8$D_OUT; - wire fpu_fState_S8$CLR, - fpu_fState_S8$DEQ, - fpu_fState_S8$EMPTY_N, - fpu_fState_S8$ENQ, - fpu_fState_S8$FULL_N; + // ports of submodule fpu + wire [195 : 0] fpu$request_put; + wire [68 : 0] fpu$response_get; + wire fpu$EN_request_put, + fpu$EN_response_get, + fpu$RDY_request_put, + fpu$RDY_response_get; // rule scheduling signals - wire CAN_FIRE_RL_fpu_s1_stage, - CAN_FIRE_RL_fpu_s2_stage, - CAN_FIRE_RL_fpu_s3_stage, - CAN_FIRE_RL_fpu_s4_stage, - CAN_FIRE_RL_fpu_s5_stage, - CAN_FIRE_RL_fpu_s6_stage, - CAN_FIRE_RL_fpu_s7_stage, - CAN_FIRE_RL_fpu_s8_stage, - CAN_FIRE_RL_fpu_s9_stage, - CAN_FIRE_request_put, + wire CAN_FIRE_request_put, CAN_FIRE_response_get, - WILL_FIRE_RL_fpu_s1_stage, - WILL_FIRE_RL_fpu_s2_stage, - WILL_FIRE_RL_fpu_s3_stage, - WILL_FIRE_RL_fpu_s4_stage, - WILL_FIRE_RL_fpu_s5_stage, - WILL_FIRE_RL_fpu_s6_stage, - WILL_FIRE_RL_fpu_s7_stage, - WILL_FIRE_RL_fpu_s8_stage, - WILL_FIRE_RL_fpu_s9_stage, WILL_FIRE_request_put, WILL_FIRE_response_get; - // remaining internal signals - reg [62 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17, - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18, - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19; - reg [51 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1, - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2, - _theResult___fst_sfd__h46438; - reg [10 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11, - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12, - _theResult___fst_exp__h46437; - reg CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14; - wire [139 : 0] IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796; - wire [118 : 0] IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160; - wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4, - _theResult___fst__h20642, - _theResult___snd__h34781, - _theResult___snd__h34795, - _theResult___snd__h34797, - _theResult___snd__h34809, - _theResult___snd__h34815, - _theResult___snd__h34833, - _theResult___snd__h34838, - fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213, - sfdBC__h19477, - sfdin__h34758, - x__h20711; - wire [68 : 0] IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282; - wire [63 : 0] IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137, - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735, - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132, - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737; - wire [56 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9, - _theResult___snd__h45207, - _theResult___snd__h45221, - _theResult___snd__h45223, - _theResult___snd__h45235, - _theResult___snd__h45241, - _theResult___snd__h45259, - _theResult___snd__h45264, - fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816, - guard__h36182, - result__h36187, - sfdA__h35392, - sfdBC__h35393, - sfd__h36934, - sfdin__h45184, - x__h35755, - x__h35759, - x__h36174, - x__h36686, - x__h36695; - wire [53 : 0] sfd__h45855; - wire [52 : 0] x__h18058, x__h18070; - wire [51 : 0] _theResult___fst_sfd__h396, - _theResult___sfd__h46360, - out_sfd__h46363, - sfd__h3208, - sfd__h3211, - sfd__h3214; - wire [12 : 0] IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208, - value__h34698, - value__h45122, - x__h20744, - x__h36286; - wire [11 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663, - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104, - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869; - wire [10 : 0] IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212, - _theResult___exp__h46359, - _theResult___fst_exp__h34764, - _theResult___fst_exp__h34767, - _theResult___fst_exp__h34786, - _theResult___fst_exp__h34801, - _theResult___fst_exp__h34840, - _theResult___fst_exp__h34846, - _theResult___fst_exp__h34849, - _theResult___fst_exp__h45190, - _theResult___fst_exp__h45193, - _theResult___fst_exp__h45212, - _theResult___fst_exp__h45227, - _theResult___fst_exp__h45266, - _theResult___fst_exp__h45272, - _theResult___fst_exp__h45275, - din_exp4681_MINUS_1023__q3, - din_exp__h34681, - din_inc___2_exp__h46444, - fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16, - fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7, - fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6, - out_exp__h46362, - value5122_BITS_10_TO_0_MINUS_1023__q8, - x__h327; - wire [6 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661; - wire [5 : 0] IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102; - wire [4 : 0] IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702, - fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, - fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244; - wire [2 : 0] NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724; - wire [1 : 0] IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5, - IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10, - _theResult___snd_fst__h34866, - _theResult___snd_fst__h45292, - _theResult___snd_snd__h35186, - _theResult___snd_snd_snd__h35184, - guardBC__h19481, - guard__h36938, - x__h35221, - x__h45575; - wire IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123, - IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, - IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717, - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722, - IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, - NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147, - NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, - NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785, - _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664, - _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105, - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209, - fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127, - fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58, - fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56, - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203, - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205, - sfdlsb__h20640; - // action method request_put - assign RDY_request_put = fpu_fOperand_S0$FULL_N ; - assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; + assign RDY_request_put = fpu$RDY_request_put ; + assign CAN_FIRE_request_put = fpu$RDY_request_put ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu_fResult_S9$D_OUT ; - assign RDY_response_get = fpu_fResult_S9$EMPTY_N ; - assign CAN_FIRE_response_get = fpu_fResult_S9$EMPTY_N ; + assign response_get = fpu$response_get ; + assign RDY_response_get = fpu$RDY_response_get ; + assign CAN_FIRE_response_get = fpu$RDY_response_get ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu_fOperand_S0 - FIFOL1 #(.width(32'd196)) fpu_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fOperand_S0$D_IN), - .ENQ(fpu_fOperand_S0$ENQ), - .DEQ(fpu_fOperand_S0$DEQ), - .CLR(fpu_fOperand_S0$CLR), - .D_OUT(fpu_fOperand_S0$D_OUT), - .FULL_N(fpu_fOperand_S0$FULL_N), - .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); + // submodule fpu + mkXilinxFpFma fpu(.CLK(CLK), + .RST_N(RST_N), + .request_put(fpu$request_put), + .EN_request_put(fpu$EN_request_put), + .EN_response_get(fpu$EN_response_get), + .RDY_request_put(fpu$RDY_request_put), + .response_get(fpu$response_get), + .RDY_response_get(fpu$RDY_response_get)); - // submodule fpu_fProd_S2 - FIFOL1 #(.width(32'd106)) fpu_fProd_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fProd_S2$D_IN), - .ENQ(fpu_fProd_S2$ENQ), - .DEQ(fpu_fProd_S2$DEQ), - .CLR(fpu_fProd_S2$CLR), - .D_OUT(fpu_fProd_S2$D_OUT), - .FULL_N(fpu_fProd_S2$FULL_N), - .EMPTY_N(fpu_fProd_S2$EMPTY_N)); - - // submodule fpu_fProd_S3 - FIFOL1 #(.width(32'd106)) fpu_fProd_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fProd_S3$D_IN), - .ENQ(fpu_fProd_S3$ENQ), - .DEQ(fpu_fProd_S3$DEQ), - .CLR(fpu_fProd_S3$CLR), - .D_OUT(fpu_fProd_S3$D_OUT), - .FULL_N(fpu_fProd_S3$FULL_N), - .EMPTY_N(fpu_fProd_S3$EMPTY_N)); - - // submodule fpu_fResult_S9 - FIFOL1 #(.width(32'd69)) fpu_fResult_S9(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fResult_S9$D_IN), - .ENQ(fpu_fResult_S9$ENQ), - .DEQ(fpu_fResult_S9$DEQ), - .CLR(fpu_fResult_S9$CLR), - .D_OUT(fpu_fResult_S9$D_OUT), - .FULL_N(fpu_fResult_S9$FULL_N), - .EMPTY_N(fpu_fResult_S9$EMPTY_N)); - - // submodule fpu_fState_S1 - FIFOL1 #(.width(32'd258)) fpu_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S1$D_IN), - .ENQ(fpu_fState_S1$ENQ), - .DEQ(fpu_fState_S1$DEQ), - .CLR(fpu_fState_S1$CLR), - .D_OUT(fpu_fState_S1$D_OUT), - .FULL_N(fpu_fState_S1$FULL_N), - .EMPTY_N(fpu_fState_S1$EMPTY_N)); - - // submodule fpu_fState_S2 - FIFOL1 #(.width(32'd152)) fpu_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S2$D_IN), - .ENQ(fpu_fState_S2$ENQ), - .DEQ(fpu_fState_S2$DEQ), - .CLR(fpu_fState_S2$CLR), - .D_OUT(fpu_fState_S2$D_OUT), - .FULL_N(fpu_fState_S2$FULL_N), - .EMPTY_N(fpu_fState_S2$EMPTY_N)); - - // submodule fpu_fState_S3 - FIFOL1 #(.width(32'd152)) fpu_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S3$D_IN), - .ENQ(fpu_fState_S3$ENQ), - .DEQ(fpu_fState_S3$DEQ), - .CLR(fpu_fState_S3$CLR), - .D_OUT(fpu_fState_S3$D_OUT), - .FULL_N(fpu_fState_S3$FULL_N), - .EMPTY_N(fpu_fState_S3$EMPTY_N)); - - // submodule fpu_fState_S4 - FIFOL1 #(.width(32'd204)) fpu_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S4$D_IN), - .ENQ(fpu_fState_S4$ENQ), - .DEQ(fpu_fState_S4$DEQ), - .CLR(fpu_fState_S4$CLR), - .D_OUT(fpu_fState_S4$D_OUT), - .FULL_N(fpu_fState_S4$FULL_N), - .EMPTY_N(fpu_fState_S4$EMPTY_N)); - - // submodule fpu_fState_S5 - FIFOL1 #(.width(32'd216)) fpu_fState_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S5$D_IN), - .ENQ(fpu_fState_S5$ENQ), - .DEQ(fpu_fState_S5$DEQ), - .CLR(fpu_fState_S5$CLR), - .D_OUT(fpu_fState_S5$D_OUT), - .FULL_N(fpu_fState_S5$FULL_N), - .EMPTY_N(fpu_fState_S5$EMPTY_N)); - - // submodule fpu_fState_S6 - FIFOL1 #(.width(32'd203)) fpu_fState_S6(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S6$D_IN), - .ENQ(fpu_fState_S6$ENQ), - .DEQ(fpu_fState_S6$DEQ), - .CLR(fpu_fState_S6$CLR), - .D_OUT(fpu_fState_S6$D_OUT), - .FULL_N(fpu_fState_S6$FULL_N), - .EMPTY_N(fpu_fState_S6$EMPTY_N)); - - // submodule fpu_fState_S7 - FIFOL1 #(.width(32'd203)) fpu_fState_S7(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S7$D_IN), - .ENQ(fpu_fState_S7$ENQ), - .DEQ(fpu_fState_S7$DEQ), - .CLR(fpu_fState_S7$CLR), - .D_OUT(fpu_fState_S7$D_OUT), - .FULL_N(fpu_fState_S7$FULL_N), - .EMPTY_N(fpu_fState_S7$EMPTY_N)); - - // submodule fpu_fState_S8 - FIFOL1 #(.width(32'd141)) fpu_fState_S8(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S8$D_IN), - .ENQ(fpu_fState_S8$ENQ), - .DEQ(fpu_fState_S8$DEQ), - .CLR(fpu_fState_S8$CLR), - .D_OUT(fpu_fState_S8$D_OUT), - .FULL_N(fpu_fState_S8$FULL_N), - .EMPTY_N(fpu_fState_S8$EMPTY_N)); - - // rule RL_fpu_s9_stage - assign CAN_FIRE_RL_fpu_s9_stage = - fpu_fState_S8$EMPTY_N && fpu_fResult_S9$FULL_N ; - assign WILL_FIRE_RL_fpu_s9_stage = CAN_FIRE_RL_fpu_s9_stage ; - - // rule RL_fpu_s8_stage - assign CAN_FIRE_RL_fpu_s8_stage = - fpu_fState_S7$EMPTY_N && fpu_fState_S8$FULL_N ; - assign WILL_FIRE_RL_fpu_s8_stage = CAN_FIRE_RL_fpu_s8_stage ; - - // rule RL_fpu_s7_stage - assign CAN_FIRE_RL_fpu_s7_stage = - fpu_fState_S6$EMPTY_N && fpu_fState_S7$FULL_N ; - assign WILL_FIRE_RL_fpu_s7_stage = CAN_FIRE_RL_fpu_s7_stage ; - - // rule RL_fpu_s6_stage - assign CAN_FIRE_RL_fpu_s6_stage = - fpu_fState_S5$EMPTY_N && fpu_fState_S6$FULL_N ; - assign WILL_FIRE_RL_fpu_s6_stage = CAN_FIRE_RL_fpu_s6_stage ; - - // rule RL_fpu_s5_stage - assign CAN_FIRE_RL_fpu_s5_stage = - fpu_fState_S4$EMPTY_N && fpu_fState_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; - - // rule RL_fpu_s4_stage - assign CAN_FIRE_RL_fpu_s4_stage = - fpu_fState_S3$EMPTY_N && fpu_fProd_S3$EMPTY_N && - fpu_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; - - // rule RL_fpu_s3_stage - assign CAN_FIRE_RL_fpu_s3_stage = - fpu_fState_S2$EMPTY_N && fpu_fProd_S2$EMPTY_N && - fpu_fProd_S3$FULL_N && - fpu_fState_S3$FULL_N ; - assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; - - // rule RL_fpu_s2_stage - assign CAN_FIRE_RL_fpu_s2_stage = - fpu_fState_S1$EMPTY_N && fpu_fProd_S2$FULL_N && - fpu_fState_S2$FULL_N ; - assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; - - // rule RL_fpu_s1_stage - assign CAN_FIRE_RL_fpu_s1_stage = - fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; - - // submodule fpu_fOperand_S0 - assign fpu_fOperand_S0$D_IN = request_put ; - assign fpu_fOperand_S0$ENQ = EN_request_put ; - assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_fProd_S2 - assign fpu_fProd_S2$D_IN = - fpu_fState_S1$D_OUT[105:53] * fpu_fState_S1$D_OUT[52:0] ; - assign fpu_fProd_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fProd_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fProd_S2$CLR = 1'b0 ; - - // submodule fpu_fProd_S3 - assign fpu_fProd_S3$D_IN = fpu_fProd_S2$D_OUT ; - assign fpu_fProd_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fProd_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fProd_S3$CLR = 1'b0 ; - - // submodule fpu_fResult_S9 - assign fpu_fResult_S9$D_IN = - fpu_fState_S8$D_OUT[140] ? - fpu_fState_S8$D_OUT[139:71] : - IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 ; - assign fpu_fResult_S9$ENQ = CAN_FIRE_RL_fpu_s9_stage ; - assign fpu_fResult_S9$DEQ = EN_response_get ; - assign fpu_fResult_S9$CLR = 1'b0 ; - - // submodule fpu_fState_S1 - assign fpu_fState_S1$D_IN = - { x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && - !_theResult___fst_sfd__h396[51] || - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperand_S0$D_OUT[118] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54] || - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62, - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140, - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148, - 4'd0, - fpu_fOperand_S0$D_OUT[2:0], - fpu_fOperand_S0$D_OUT[195], - fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112, - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 } ; - assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S1$CLR = 1'b0 ; - - // submodule fpu_fState_S2 - assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[257:106] ; - assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S2$CLR = 1'b0 ; - - // submodule fpu_fState_S3 - assign fpu_fState_S3$D_IN = fpu_fState_S2$D_OUT ; - assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S3$CLR = 1'b0 ; - - // submodule fpu_fState_S4 - assign fpu_fState_S4$D_IN = - { fpu_fState_S3$D_OUT[151:87], - IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726, - fpu_fState_S3$D_OUT[81:14], - !fpu_fState_S3$D_OUT[151] && fpu_fState_S3$D_OUT[13], - fpu_fState_S3$D_OUT[151] ? - 63'd0 : - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737, - x__h35221 } ; - assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S4$CLR = 1'b0 ; - - // submodule fpu_fState_S5 - assign fpu_fState_S5$D_IN = - { fpu_fState_S4$D_OUT[203:130], - fpu_fState_S4$D_OUT[129] != fpu_fState_S4$D_OUT[65], - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - fpu_fState_S4$D_OUT[65] : - fpu_fState_S4$D_OUT[129], - IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 } ; - assign fpu_fState_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S5$DEQ = CAN_FIRE_RL_fpu_s6_stage ; - assign fpu_fState_S5$CLR = 1'b0 ; - - // submodule fpu_fState_S6 - assign fpu_fState_S6$D_IN = - { fpu_fState_S5$D_OUT[215:127], - fpu_fState_S5$D_OUT[113:57], - x__h36174 } ; - assign fpu_fState_S6$ENQ = CAN_FIRE_RL_fpu_s6_stage ; - assign fpu_fState_S6$DEQ = CAN_FIRE_RL_fpu_s7_stage ; - assign fpu_fState_S6$CLR = 1'b0 ; - - // submodule fpu_fState_S7 - assign fpu_fState_S7$D_IN = - { fpu_fState_S6$D_OUT[202:114], x__h36686, x__h36695 } ; - assign fpu_fState_S7$ENQ = CAN_FIRE_RL_fpu_s7_stage ; - assign fpu_fState_S7$DEQ = CAN_FIRE_RL_fpu_s8_stage ; - assign fpu_fState_S7$CLR = 1'b0 ; - - // submodule fpu_fState_S8 - assign fpu_fState_S8$D_IN = - { fpu_fState_S7$D_OUT[202:138], - fpu_fState_S7$D_OUT[202] ? - fpu_fState_S7$D_OUT[137:133] : - fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143, - fpu_fState_S7$D_OUT[132:129], - !fpu_fState_S7$D_OUT[202] && fpu_fState_S7$D_OUT[127], - fpu_fState_S7$D_OUT[202] ? - 63'd0 : - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153, - x__h45575, - fpu_fState_S7$D_OUT[128] } ; - assign fpu_fState_S8$ENQ = CAN_FIRE_RL_fpu_s8_stage ; - assign fpu_fState_S8$DEQ = CAN_FIRE_RL_fpu_s9_stage ; - assign fpu_fState_S8$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4 = - _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 ? - _theResult___snd__h34838 : - _theResult___snd__h34833 ; - assign IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9 = - _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 ? - _theResult___snd__h45264 : - _theResult___snd__h45259 ; - assign IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 = - sfd__h45855[53] ? - ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h46444, sfd__h45855[52:1] }) : - { IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187, - sfd__h45855[51:0] } ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 = - (din_exp__h34681 == 11'd0) ? - 12'd3074 : - { din_exp4681_MINUS_1023__q3[10], - din_exp4681_MINUS_1023__q3 } ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 = - (sfdBC__h19477[105] ? - 7'd0 : - (sfdBC__h19477[104] ? - 7'd1 : - (sfdBC__h19477[103] ? - 7'd2 : - (sfdBC__h19477[102] ? - 7'd3 : - (sfdBC__h19477[101] ? - 7'd4 : - (sfdBC__h19477[100] ? - 7'd5 : - (sfdBC__h19477[99] ? - 7'd6 : - (sfdBC__h19477[98] ? - 7'd7 : - (sfdBC__h19477[97] ? - 7'd8 : - (sfdBC__h19477[96] ? - 7'd9 : - (sfdBC__h19477[95] ? - 7'd10 : - (sfdBC__h19477[94] ? - 7'd11 : - (sfdBC__h19477[93] ? - 7'd12 : - (sfdBC__h19477[92] ? - 7'd13 : - (sfdBC__h19477[91] ? - 7'd14 : - (sfdBC__h19477[90] ? - 7'd15 : - (sfdBC__h19477[89] ? - 7'd16 : - (sfdBC__h19477[88] ? - 7'd17 : - (sfdBC__h19477[87] ? - 7'd18 : - (sfdBC__h19477[86] ? - 7'd19 : - (sfdBC__h19477[85] ? - 7'd20 : - (sfdBC__h19477[84] ? - 7'd21 : - (sfdBC__h19477[83] ? - 7'd22 : - (sfdBC__h19477[82] ? - 7'd23 : - (sfdBC__h19477[81] ? - 7'd24 : - (sfdBC__h19477[80] ? - 7'd25 : - (sfdBC__h19477[79] ? - 7'd26 : - (sfdBC__h19477[78] ? - 7'd27 : - (sfdBC__h19477[77] ? - 7'd28 : - (sfdBC__h19477[76] ? - 7'd29 : - (sfdBC__h19477[75] ? - 7'd30 : - (sfdBC__h19477[74] ? - 7'd31 : - (sfdBC__h19477[73] ? - 7'd32 : - (sfdBC__h19477[72] ? - 7'd33 : - (sfdBC__h19477[71] ? - 7'd34 : - (sfdBC__h19477[70] ? - 7'd35 : - (sfdBC__h19477[69] ? - 7'd36 : - (sfdBC__h19477[68] ? - 7'd37 : - (sfdBC__h19477[67] ? - 7'd38 : - (sfdBC__h19477[66] ? - 7'd39 : - (sfdBC__h19477[65] ? - 7'd40 : - (sfdBC__h19477[64] ? - 7'd41 : - (sfdBC__h19477[63] ? - 7'd42 : - (sfdBC__h19477[62] ? - 7'd43 : - (sfdBC__h19477[61] ? - 7'd44 : - (sfdBC__h19477[60] ? - 7'd45 : - (sfdBC__h19477[59] ? - 7'd46 : - (sfdBC__h19477[58] ? - 7'd47 : - (sfdBC__h19477[57] ? - 7'd48 : - (sfdBC__h19477[56] ? - 7'd49 : - (sfdBC__h19477[55] ? - 7'd50 : - (sfdBC__h19477[54] ? - 7'd51 : - (sfdBC__h19477[53] ? - 7'd52 : - (sfdBC__h19477[52] ? - 7'd53 : - (sfdBC__h19477[51] ? - 7'd54 : - (sfdBC__h19477[50] ? - 7'd55 : - (sfdBC__h19477[49] ? - 7'd56 : - (sfdBC__h19477[48] ? - 7'd57 : - (sfdBC__h19477[47] ? - 7'd58 : - (sfdBC__h19477[46] ? - 7'd59 : - (sfdBC__h19477[45] ? - 7'd60 : - (sfdBC__h19477[44] ? - 7'd61 : - (sfdBC__h19477[43] ? - 7'd62 : - (sfdBC__h19477[42] ? - 7'd63 : - (sfdBC__h19477[41] ? - 7'd64 : - (sfdBC__h19477[40] ? - 7'd65 : - (sfdBC__h19477[39] ? - 7'd66 : - (sfdBC__h19477[38] ? - 7'd67 : - (sfdBC__h19477[37] ? - 7'd68 : - (sfdBC__h19477[36] ? - 7'd69 : - (sfdBC__h19477[35] ? - 7'd70 : - (sfdBC__h19477[34] ? - 7'd71 : - (sfdBC__h19477[33] ? - 7'd72 : - (sfdBC__h19477[32] ? - 7'd73 : - (sfdBC__h19477[31] ? - 7'd74 : - (sfdBC__h19477[30] ? - 7'd75 : - (sfdBC__h19477[29] ? - 7'd76 : - (sfdBC__h19477[28] ? - 7'd77 : - (sfdBC__h19477[27] ? - 7'd78 : - (sfdBC__h19477[26] ? - 7'd79 : - (sfdBC__h19477[25] ? - 7'd80 : - (sfdBC__h19477[24] ? - 7'd81 : - (sfdBC__h19477[23] ? - 7'd82 : - (sfdBC__h19477[22] ? - 7'd83 : - (sfdBC__h19477[21] ? - 7'd84 : - (sfdBC__h19477[20] ? - 7'd85 : - (sfdBC__h19477[19] ? - 7'd86 : - (sfdBC__h19477[18] ? - 7'd87 : - (sfdBC__h19477[17] ? - 7'd88 : - (sfdBC__h19477[16] ? - 7'd89 : - (sfdBC__h19477[15] ? - 7'd90 : - (sfdBC__h19477[14] ? - 7'd91 : - (sfdBC__h19477[13] ? - 7'd92 : - (sfdBC__h19477[12] ? - 7'd93 : - (sfdBC__h19477[11] ? - 7'd94 : - (sfdBC__h19477[10] ? - 7'd95 : - (sfdBC__h19477[9] ? - 7'd96 : - (sfdBC__h19477[8] ? - 7'd97 : - (sfdBC__h19477[7] ? - 7'd98 : - (sfdBC__h19477[6] ? - 7'd99 : - (sfdBC__h19477[5] ? - 7'd100 : - (sfdBC__h19477[4] ? - 7'd101 : - (sfdBC__h19477[3] ? - 7'd102 : - (sfdBC__h19477[2] ? - 7'd103 : - (sfdBC__h19477[1] ? - 7'd104 : - (sfdBC__h19477[0] ? - 7'd105 : - 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 = - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 - - 12'd3074 ; - assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735 = - (sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h34764, sfdin__h34758[105:54] } ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? - fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194] : - ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 : - fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ? - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 : - ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ? - 63'h7FF0000000000000 : - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112) ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51]) ? - { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 } : - ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118]) ? - fpu_fOperand_S0$D_OUT[130:67] : - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54]) ? - fpu_fOperand_S0$D_OUT[66:3] : - { NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124, - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 })) ; - assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140 = - (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && - !_theResult___fst_sfd__h396[51]) ? - { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194], - x__h327, - sfd__h3208 } : - IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 ; - assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 = - (sfd__h36934[56] ? - 6'd0 : - (sfd__h36934[55] ? - 6'd1 : - (sfd__h36934[54] ? - 6'd2 : - (sfd__h36934[53] ? - 6'd3 : - (sfd__h36934[52] ? - 6'd4 : - (sfd__h36934[51] ? - 6'd5 : - (sfd__h36934[50] ? - 6'd6 : - (sfd__h36934[49] ? - 6'd7 : - (sfd__h36934[48] ? - 6'd8 : - (sfd__h36934[47] ? - 6'd9 : - (sfd__h36934[46] ? - 6'd10 : - (sfd__h36934[45] ? - 6'd11 : - (sfd__h36934[44] ? - 6'd12 : - (sfd__h36934[43] ? - 6'd13 : - (sfd__h36934[42] ? - 6'd14 : - (sfd__h36934[41] ? - 6'd15 : - (sfd__h36934[40] ? - 6'd16 : - (sfd__h36934[39] ? - 6'd17 : - (sfd__h36934[38] ? - 6'd18 : - (sfd__h36934[37] ? - 6'd19 : - (sfd__h36934[36] ? - 6'd20 : - (sfd__h36934[35] ? - 6'd21 : - (sfd__h36934[34] ? - 6'd22 : - (sfd__h36934[33] ? - 6'd23 : - (sfd__h36934[32] ? - 6'd24 : - (sfd__h36934[31] ? - 6'd25 : - (sfd__h36934[30] ? - 6'd26 : - (sfd__h36934[29] ? - 6'd27 : - (sfd__h36934[28] ? - 6'd28 : - (sfd__h36934[27] ? - 6'd29 : - (sfd__h36934[26] ? - 6'd30 : - (sfd__h36934[25] ? - 6'd31 : - (sfd__h36934[24] ? - 6'd32 : - (sfd__h36934[23] ? - 6'd33 : - (sfd__h36934[22] ? - 6'd34 : - (sfd__h36934[21] ? - 6'd35 : - (sfd__h36934[20] ? - 6'd36 : - (sfd__h36934[19] ? - 6'd37 : - (sfd__h36934[18] ? - 6'd38 : - (sfd__h36934[17] ? - 6'd39 : - (sfd__h36934[16] ? - 6'd40 : - (sfd__h36934[15] ? - 6'd41 : - (sfd__h36934[14] ? - 6'd42 : - (sfd__h36934[13] ? - 6'd43 : - (sfd__h36934[12] ? - 6'd44 : - (sfd__h36934[11] ? - 6'd45 : - (sfd__h36934[10] ? - 6'd46 : - (sfd__h36934[9] ? - 6'd47 : - (sfd__h36934[8] ? - 6'd48 : - (sfd__h36934[7] ? - 6'd49 : - (sfd__h36934[6] ? - 6'd50 : - (sfd__h36934[5] ? - 6'd51 : - (sfd__h36934[4] ? - 6'd52 : - (sfd__h36934[3] ? - 6'd53 : - (sfd__h36934[2] ? - 6'd54 : - (sfd__h36934[1] ? - 6'd55 : - (sfd__h36934[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153 = - (sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h45190, sfdin__h45184[56:5] } ; - assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704 = - (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? - fpu_fState_S3$D_OUT[86] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[4] ; - assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707 = - (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ? - fpu_fState_S3$D_OUT[85] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[3] ; - assign IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 = - { NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 : - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 - - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 : - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 - - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764, - x__h35755, - x__h35759 } ; - assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 = - (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && - !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ? - 63'h7FF8000000000000 : - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 ; - assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 = - (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperand_S0$D_OUT[118]) ? - { fpu_fOperand_S0$D_OUT[130:119], sfd__h3211 } : - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54]) ? - { fpu_fOperand_S0$D_OUT[66:55], sfd__h3214 } : - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137) ; - assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 = - { ((fpu_fOperand_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15[10]}}, - fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 }) + - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16[10]}}, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 }), - x__h18058, - x__h18070 } ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 = - fpu_fOperand_S0$D_OUT[195] ? - fpu_fOperand_S0$D_OUT[193:131] : - 63'd0 ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 = - x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 && - (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148 = - x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 && - !_theResult___fst_sfd__h396[51] || - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_fOperand_S0$D_OUT[118] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54] || - NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 ; - assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62 = - x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51] || - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54] || - x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 || - fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 ; - assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? - (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - 63'd0 : - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735) : - 63'h7FEFFFFFFFFFFFFF ; - assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[83] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[1] ; - assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[82] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[0] ; - assign IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726 = - fpu_fState_S3$D_OUT[151] ? - fpu_fState_S3$D_OUT[86:82] : - { IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704, - IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707, - NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 } ; - assign IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 = - (fpu_fState_S4$D_OUT[128:118] == 11'd0) ? - 13'd7170 : - { {2{fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7[10]}}, - fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 } ; - assign IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 = - (fpu_fState_S4$D_OUT[64:54] == 11'd0) ? - 13'd7170 : - { {2{fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6[10]}}, - fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 } ; - assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 = - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 - - 12'd3074 ; - assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 = - (value__h45122[10:0] == 11'd0) ? - 12'd3074 : - { value5122_BITS_10_TO_0_MINUS_1023__q8[10], - value5122_BITS_10_TO_0_MINUS_1023__q8 } ; - assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 = - (fpu_fState_S8$D_OUT[65:55] == 11'd0 && - sfd__h45855[53:52] == 2'b01) ? - 11'd1 : - fpu_fState_S8$D_OUT[65:55] ; - assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 = - (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[65:55] : - _theResult___fst_exp__h46437 ; - assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261 = - (fpu_fState_S8$D_OUT[67] && - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == - 11'd0 && - ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h46438) == - 52'd0 && - !fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244[0] && - fpu_fState_S8$D_OUT[0]) ? - fpu_fState_S8$D_OUT[70:68] == 3'd3 : - ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[66] : - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14) ; - assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 = - { IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261, - (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[65:3] : - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19, - fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 } ; - assign IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5 = - sfdin__h34758[53] ? 2'd2 : 2'd0 ; - assign IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10 = - sfdin__h45184[4] ? 2'd2 : 2'd0 ; - assign NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 = - (x__h327 != 11'd2047 || !_theResult___fst_sfd__h396[51]) && - (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || - !fpu_fOperand_S0$D_OUT[118]) && - (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || - !fpu_fOperand_S0$D_OUT[54]) && - (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 || - IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 && - !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ; - assign NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124 = - (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] != 11'd0 || - fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && - (fpu_fOperand_S0$D_OUT[129:119] != 11'd0 || - fpu_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperand_S0$D_OUT[54:3] != 52'd0) && - (x__h327 != 11'd2047 || _theResult___fst_sfd__h396 != 52'd0 || - (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_fOperand_S0$D_OUT[118:67] != 52'd0) && - (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_fOperand_S0$D_OUT[54:3] != 52'd0) || - fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) && - IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 ; - assign NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 = - fpu_fOperand_S0$D_OUT[130] != fpu_fOperand_S0$D_OUT[66] ; - assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711 = - !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - fpu_fState_S3$D_OUT[84] : - fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[2]) ; - assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 = - { NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711, - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 : - fpu_fState_S3$D_OUT[83], - !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 || - IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 } ; - assign NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 = - !fpu_fState_S4$D_OUT[130] || - (IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 ^ - 13'h1000) > - (IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 ^ - 13'h1000) || - IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 == - IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 && - sfdBC__h35393 > sfdA__h35392 ; - assign _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 = - ({ 5'd0, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ^ - 12'h800) <= - (IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 = - ({ 6'd0, - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ^ - 12'h800) <= - (IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ^ - 12'h800) ; - assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 = - 13'd7170 - fpu_fState_S3$D_OUT[12:0] ; - assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 = - (_7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ^ - 13'h1000) <= - 13'd4096 ; - assign _theResult___exp__h46359 = - sfd__h45855[53] ? - ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h46444) : - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 ; - assign _theResult___fst__h20642 = - { fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[105:1], - fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[0] | - sfdlsb__h20640 } ; - assign _theResult___fst_exp__h34764 = - sfdBC__h19477[105] ? - _theResult___fst_exp__h34786 : - _theResult___fst_exp__h34849 ; - assign _theResult___fst_exp__h34767 = - (sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h34764 ; - assign _theResult___fst_exp__h34786 = - (din_exp__h34681 == 11'd0) ? 11'd2 : din_exp__h34681 + 11'd1 ; - assign _theResult___fst_exp__h34801 = - (din_exp__h34681 == 11'd0) ? 11'd1 : din_exp__h34681 ; - assign _theResult___fst_exp__h34840 = - din_exp__h34681 - - { 4'd0, - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ; - assign _theResult___fst_exp__h34846 = - (!sfdBC__h19477[105] && !sfdBC__h19477[104] && - !sfdBC__h19477[103] && - !sfdBC__h19477[102] && - !sfdBC__h19477[101] && - !sfdBC__h19477[100] && - !sfdBC__h19477[99] && - !sfdBC__h19477[98] && - !sfdBC__h19477[97] && - !sfdBC__h19477[96] && - !sfdBC__h19477[95] && - !sfdBC__h19477[94] && - !sfdBC__h19477[93] && - !sfdBC__h19477[92] && - !sfdBC__h19477[91] && - !sfdBC__h19477[90] && - !sfdBC__h19477[89] && - !sfdBC__h19477[88] && - !sfdBC__h19477[87] && - !sfdBC__h19477[86] && - !sfdBC__h19477[85] && - !sfdBC__h19477[84] && - !sfdBC__h19477[83] && - !sfdBC__h19477[82] && - !sfdBC__h19477[81] && - !sfdBC__h19477[80] && - !sfdBC__h19477[79] && - !sfdBC__h19477[78] && - !sfdBC__h19477[77] && - !sfdBC__h19477[76] && - !sfdBC__h19477[75] && - !sfdBC__h19477[74] && - !sfdBC__h19477[73] && - !sfdBC__h19477[72] && - !sfdBC__h19477[71] && - !sfdBC__h19477[70] && - !sfdBC__h19477[69] && - !sfdBC__h19477[68] && - !sfdBC__h19477[67] && - !sfdBC__h19477[66] && - !sfdBC__h19477[65] && - !sfdBC__h19477[64] && - !sfdBC__h19477[63] && - !sfdBC__h19477[62] && - !sfdBC__h19477[61] && - !sfdBC__h19477[60] && - !sfdBC__h19477[59] && - !sfdBC__h19477[58] && - !sfdBC__h19477[57] && - !sfdBC__h19477[56] && - !sfdBC__h19477[55] && - !sfdBC__h19477[54] && - !sfdBC__h19477[53] && - !sfdBC__h19477[52] && - !sfdBC__h19477[51] && - !sfdBC__h19477[50] && - !sfdBC__h19477[49] && - !sfdBC__h19477[48] && - !sfdBC__h19477[47] && - !sfdBC__h19477[46] && - !sfdBC__h19477[45] && - !sfdBC__h19477[44] && - !sfdBC__h19477[43] && - !sfdBC__h19477[42] && - !sfdBC__h19477[41] && - !sfdBC__h19477[40] && - !sfdBC__h19477[39] && - !sfdBC__h19477[38] && - !sfdBC__h19477[37] && - !sfdBC__h19477[36] && - !sfdBC__h19477[35] && - !sfdBC__h19477[34] && - !sfdBC__h19477[33] && - !sfdBC__h19477[32] && - !sfdBC__h19477[31] && - !sfdBC__h19477[30] && - !sfdBC__h19477[29] && - !sfdBC__h19477[28] && - !sfdBC__h19477[27] && - !sfdBC__h19477[26] && - !sfdBC__h19477[25] && - !sfdBC__h19477[24] && - !sfdBC__h19477[23] && - !sfdBC__h19477[22] && - !sfdBC__h19477[21] && - !sfdBC__h19477[20] && - !sfdBC__h19477[19] && - !sfdBC__h19477[18] && - !sfdBC__h19477[17] && - !sfdBC__h19477[16] && - !sfdBC__h19477[15] && - !sfdBC__h19477[14] && - !sfdBC__h19477[13] && - !sfdBC__h19477[12] && - !sfdBC__h19477[11] && - !sfdBC__h19477[10] && - !sfdBC__h19477[9] && - !sfdBC__h19477[8] && - !sfdBC__h19477[7] && - !sfdBC__h19477[6] && - !sfdBC__h19477[5] && - !sfdBC__h19477[4] && - !sfdBC__h19477[3] && - !sfdBC__h19477[2] && - !sfdBC__h19477[1] && - !sfdBC__h19477[0] || - !_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664) ? - 11'd0 : - _theResult___fst_exp__h34840 ; - assign _theResult___fst_exp__h34849 = - (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? - _theResult___fst_exp__h34801 : - _theResult___fst_exp__h34846 ; - assign _theResult___fst_exp__h45190 = - sfd__h36934[56] ? - _theResult___fst_exp__h45212 : - _theResult___fst_exp__h45275 ; - assign _theResult___fst_exp__h45193 = - (sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h45190 ; - assign _theResult___fst_exp__h45212 = - (value__h45122[10:0] == 11'd0) ? - 11'd2 : - value__h45122[10:0] + 11'd1 ; - assign _theResult___fst_exp__h45227 = - (value__h45122[10:0] == 11'd0) ? 11'd1 : value__h45122[10:0] ; - assign _theResult___fst_exp__h45266 = - value__h45122[10:0] - - { 5'd0, - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ; - assign _theResult___fst_exp__h45272 = - (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && - !sfd__h36934[53] && - !sfd__h36934[52] && - !sfd__h36934[51] && - !sfd__h36934[50] && - !sfd__h36934[49] && - !sfd__h36934[48] && - !sfd__h36934[47] && - !sfd__h36934[46] && - !sfd__h36934[45] && - !sfd__h36934[44] && - !sfd__h36934[43] && - !sfd__h36934[42] && - !sfd__h36934[41] && - !sfd__h36934[40] && - !sfd__h36934[39] && - !sfd__h36934[38] && - !sfd__h36934[37] && - !sfd__h36934[36] && - !sfd__h36934[35] && - !sfd__h36934[34] && - !sfd__h36934[33] && - !sfd__h36934[32] && - !sfd__h36934[31] && - !sfd__h36934[30] && - !sfd__h36934[29] && - !sfd__h36934[28] && - !sfd__h36934[27] && - !sfd__h36934[26] && - !sfd__h36934[25] && - !sfd__h36934[24] && - !sfd__h36934[23] && - !sfd__h36934[22] && - !sfd__h36934[21] && - !sfd__h36934[20] && - !sfd__h36934[19] && - !sfd__h36934[18] && - !sfd__h36934[17] && - !sfd__h36934[16] && - !sfd__h36934[15] && - !sfd__h36934[14] && - !sfd__h36934[13] && - !sfd__h36934[12] && - !sfd__h36934[11] && - !sfd__h36934[10] && - !sfd__h36934[9] && - !sfd__h36934[8] && - !sfd__h36934[7] && - !sfd__h36934[6] && - !sfd__h36934[5] && - !sfd__h36934[4] && - !sfd__h36934[3] && - !sfd__h36934[2] && - !sfd__h36934[1] && - !sfd__h36934[0] || - !_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105) ? - 11'd0 : - _theResult___fst_exp__h45266 ; - assign _theResult___fst_exp__h45275 = - (!sfd__h36934[56] && sfd__h36934[55]) ? - _theResult___fst_exp__h45227 : - _theResult___fst_exp__h45272 ; - assign _theResult___fst_sfd__h396 = - fpu_fOperand_S0$D_OUT[195] ? - fpu_fOperand_S0$D_OUT[182:131] : - 52'd0 ; - assign _theResult___sfd__h46360 = - sfd__h45855[53] ? - ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ? - 52'd0 : - sfd__h45855[52:1]) : - sfd__h45855[51:0] ; - assign _theResult___snd__h34781 = { sfdBC__h19477[104:0], 1'd0 } ; - assign _theResult___snd__h34795 = - (!sfdBC__h19477[105] && sfdBC__h19477[104]) ? - _theResult___snd__h34797 : - _theResult___snd__h34809 ; - assign _theResult___snd__h34797 = { sfdBC__h19477[103:0], 2'd0 } ; - assign _theResult___snd__h34809 = - (!sfdBC__h19477[105] && !sfdBC__h19477[104] && - !sfdBC__h19477[103] && - !sfdBC__h19477[102] && - !sfdBC__h19477[101] && - !sfdBC__h19477[100] && - !sfdBC__h19477[99] && - !sfdBC__h19477[98] && - !sfdBC__h19477[97] && - !sfdBC__h19477[96] && - !sfdBC__h19477[95] && - !sfdBC__h19477[94] && - !sfdBC__h19477[93] && - !sfdBC__h19477[92] && - !sfdBC__h19477[91] && - !sfdBC__h19477[90] && - !sfdBC__h19477[89] && - !sfdBC__h19477[88] && - !sfdBC__h19477[87] && - !sfdBC__h19477[86] && - !sfdBC__h19477[85] && - !sfdBC__h19477[84] && - !sfdBC__h19477[83] && - !sfdBC__h19477[82] && - !sfdBC__h19477[81] && - !sfdBC__h19477[80] && - !sfdBC__h19477[79] && - !sfdBC__h19477[78] && - !sfdBC__h19477[77] && - !sfdBC__h19477[76] && - !sfdBC__h19477[75] && - !sfdBC__h19477[74] && - !sfdBC__h19477[73] && - !sfdBC__h19477[72] && - !sfdBC__h19477[71] && - !sfdBC__h19477[70] && - !sfdBC__h19477[69] && - !sfdBC__h19477[68] && - !sfdBC__h19477[67] && - !sfdBC__h19477[66] && - !sfdBC__h19477[65] && - !sfdBC__h19477[64] && - !sfdBC__h19477[63] && - !sfdBC__h19477[62] && - !sfdBC__h19477[61] && - !sfdBC__h19477[60] && - !sfdBC__h19477[59] && - !sfdBC__h19477[58] && - !sfdBC__h19477[57] && - !sfdBC__h19477[56] && - !sfdBC__h19477[55] && - !sfdBC__h19477[54] && - !sfdBC__h19477[53] && - !sfdBC__h19477[52] && - !sfdBC__h19477[51] && - !sfdBC__h19477[50] && - !sfdBC__h19477[49] && - !sfdBC__h19477[48] && - !sfdBC__h19477[47] && - !sfdBC__h19477[46] && - !sfdBC__h19477[45] && - !sfdBC__h19477[44] && - !sfdBC__h19477[43] && - !sfdBC__h19477[42] && - !sfdBC__h19477[41] && - !sfdBC__h19477[40] && - !sfdBC__h19477[39] && - !sfdBC__h19477[38] && - !sfdBC__h19477[37] && - !sfdBC__h19477[36] && - !sfdBC__h19477[35] && - !sfdBC__h19477[34] && - !sfdBC__h19477[33] && - !sfdBC__h19477[32] && - !sfdBC__h19477[31] && - !sfdBC__h19477[30] && - !sfdBC__h19477[29] && - !sfdBC__h19477[28] && - !sfdBC__h19477[27] && - !sfdBC__h19477[26] && - !sfdBC__h19477[25] && - !sfdBC__h19477[24] && - !sfdBC__h19477[23] && - !sfdBC__h19477[22] && - !sfdBC__h19477[21] && - !sfdBC__h19477[20] && - !sfdBC__h19477[19] && - !sfdBC__h19477[18] && - !sfdBC__h19477[17] && - !sfdBC__h19477[16] && - !sfdBC__h19477[15] && - !sfdBC__h19477[14] && - !sfdBC__h19477[13] && - !sfdBC__h19477[12] && - !sfdBC__h19477[11] && - !sfdBC__h19477[10] && - !sfdBC__h19477[9] && - !sfdBC__h19477[8] && - !sfdBC__h19477[7] && - !sfdBC__h19477[6] && - !sfdBC__h19477[5] && - !sfdBC__h19477[4] && - !sfdBC__h19477[3] && - !sfdBC__h19477[2] && - !sfdBC__h19477[1] && - !sfdBC__h19477[0]) ? - sfdBC__h19477 : - _theResult___snd__h34815 ; - assign _theResult___snd__h34815 = - { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4[103:0], - 2'd0 } ; - assign _theResult___snd__h34833 = - sfdBC__h19477 << - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ; - assign _theResult___snd__h34838 = - sfdBC__h19477 << - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 ; - assign _theResult___snd__h45207 = { sfd__h36934[55:0], 1'd0 } ; - assign _theResult___snd__h45221 = - (!sfd__h36934[56] && sfd__h36934[55]) ? - _theResult___snd__h45223 : - _theResult___snd__h45235 ; - assign _theResult___snd__h45223 = { sfd__h36934[54:0], 2'd0 } ; - assign _theResult___snd__h45235 = - (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] && - !sfd__h36934[53] && - !sfd__h36934[52] && - !sfd__h36934[51] && - !sfd__h36934[50] && - !sfd__h36934[49] && - !sfd__h36934[48] && - !sfd__h36934[47] && - !sfd__h36934[46] && - !sfd__h36934[45] && - !sfd__h36934[44] && - !sfd__h36934[43] && - !sfd__h36934[42] && - !sfd__h36934[41] && - !sfd__h36934[40] && - !sfd__h36934[39] && - !sfd__h36934[38] && - !sfd__h36934[37] && - !sfd__h36934[36] && - !sfd__h36934[35] && - !sfd__h36934[34] && - !sfd__h36934[33] && - !sfd__h36934[32] && - !sfd__h36934[31] && - !sfd__h36934[30] && - !sfd__h36934[29] && - !sfd__h36934[28] && - !sfd__h36934[27] && - !sfd__h36934[26] && - !sfd__h36934[25] && - !sfd__h36934[24] && - !sfd__h36934[23] && - !sfd__h36934[22] && - !sfd__h36934[21] && - !sfd__h36934[20] && - !sfd__h36934[19] && - !sfd__h36934[18] && - !sfd__h36934[17] && - !sfd__h36934[16] && - !sfd__h36934[15] && - !sfd__h36934[14] && - !sfd__h36934[13] && - !sfd__h36934[12] && - !sfd__h36934[11] && - !sfd__h36934[10] && - !sfd__h36934[9] && - !sfd__h36934[8] && - !sfd__h36934[7] && - !sfd__h36934[6] && - !sfd__h36934[5] && - !sfd__h36934[4] && - !sfd__h36934[3] && - !sfd__h36934[2] && - !sfd__h36934[1] && - !sfd__h36934[0]) ? - sfd__h36934 : - _theResult___snd__h45241 ; - assign _theResult___snd__h45241 = - { IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9[54:0], - 2'd0 } ; - assign _theResult___snd__h45259 = - sfd__h36934 << - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ; - assign _theResult___snd__h45264 = - sfd__h36934 << - IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 ; - assign _theResult___snd_fst__h34866 = - { IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5[1], - { sfdin__h34758[52:0], 52'd0 } != 105'd0 } ; - assign _theResult___snd_fst__h45292 = - { IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10[1], - { sfdin__h45184[3:0], 52'd0 } != 56'd0 } ; - assign _theResult___snd_snd__h35186 = - (fpu_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; - assign _theResult___snd_snd_snd__h35184 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ? - _theResult___snd_snd__h35186 : - guardBC__h19481 ; - assign din_exp4681_MINUS_1023__q3 = din_exp__h34681 - 11'd1023 ; - assign din_exp__h34681 = - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? - value__h34698[10:0] : - 11'd0 ; - assign din_inc___2_exp__h46444 = fpu_fState_S8$D_OUT[65:55] + 11'd1 ; - assign fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 = - fpu_fOperand_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 = - fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 = - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 = - fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || - x__h327 == 11'd0 && _theResult___fst_sfd__h396 == 52'd0 && - (fpu_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0) && - fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 ; - assign fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 = - (fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) == - NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 ; - assign fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213 = - fpu_fProd_S3$D_OUT >> - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; - assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 = - (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; - assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 = - (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; - assign fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702 = - fpu_fState_S3$D_OUT[86:82] | - { 2'd0, - sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023, - _theResult___fst_exp__h34767 == 11'd0 && - guardBC__h19481 != 2'd0, - sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023 } ; - assign fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 = - fpu_fState_S4$D_OUT[128:118] - 11'd1023 ; - assign fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 = - fpu_fState_S4$D_OUT[64:54] - 11'd1023 ; - assign fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816 = - fpu_fState_S5$D_OUT[56:0] >> fpu_fState_S5$D_OUT[126:114] ; - assign fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143 = - fpu_fState_S7$D_OUT[137:133] | - { 2'd0, - sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023, - _theResult___fst_exp__h45193 == 11'd0 && guard__h36938 != 2'd0, - sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023 } ; - assign fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 = - fpu_fState_S8$D_OUT[75:71] | - { 2'd0, - IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 == - 11'd2047 && - ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h46438) == - 52'd0, - 1'd0, - fpu_fState_S8$D_OUT[65:55] != 11'd2047 && - fpu_fState_S8$D_OUT[2:1] != 2'b0 } ; - assign guardBC__h19481 = - (sfdBC__h19477[105] && - IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h34866 ; - assign guard__h36182 = fpu_fState_S5$D_OUT[56:0] << x__h36286 ; - assign guard__h36938 = - (sfd__h36934[56] && - IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h45292 ; - assign out_exp__h46362 = - fpu_fState_S8$D_OUT[3] ? - _theResult___exp__h46359 : - fpu_fState_S8$D_OUT[65:55] ; - assign out_sfd__h46363 = - fpu_fState_S8$D_OUT[3] ? - _theResult___sfd__h46360 : - fpu_fState_S8$D_OUT[54:3] ; - assign result__h36187 = - { fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[56:1], - fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[0] | - guard__h36182 != 57'd0 } ; - assign sfdA__h35392 = - { 1'b0, - fpu_fState_S4$D_OUT[128:118] != 11'd0, - fpu_fState_S4$D_OUT[117:66], - 3'b0 } ; - assign sfdBC__h19477 = - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ? - fpu_fProd_S3$D_OUT : - _theResult___fst__h20642 ; - assign sfdBC__h35393 = - { 1'b0, - fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:0], - 1'b0 } ; - assign sfd__h3208 = { 1'd1, _theResult___fst_sfd__h396[50:0] } ; - assign sfd__h3211 = { 1'd1, fpu_fOperand_S0$D_OUT[117:67] } ; - assign sfd__h3214 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h36934 = - fpu_fState_S7$D_OUT[128] ? - fpu_fState_S7$D_OUT[56:0] : - fpu_fState_S7$D_OUT[113:57] ; - assign sfd__h45855 = - { 1'b0, - fpu_fState_S8$D_OUT[65:55] != 11'd0, - fpu_fState_S8$D_OUT[54:3] } + - 54'd1 ; - assign sfdin__h34758 = - sfdBC__h19477[105] ? - _theResult___snd__h34781 : - _theResult___snd__h34795 ; - assign sfdin__h45184 = - sfd__h36934[56] ? - _theResult___snd__h45207 : - _theResult___snd__h45221 ; - assign sfdlsb__h20640 = x__h20711 != 106'd0 ; - assign value5122_BITS_10_TO_0_MINUS_1023__q8 = - value__h45122[10:0] - 11'd1023 ; - assign value__h34698 = fpu_fState_S3$D_OUT[12:0] + 13'd1023 ; - assign value__h45122 = fpu_fState_S7$D_OUT[126:114] + 13'd1023 ; - assign x__h18058 = - { fpu_fOperand_S0$D_OUT[129:119] != 11'd0, - fpu_fOperand_S0$D_OUT[118:67] } ; - assign x__h18070 = - { fpu_fOperand_S0$D_OUT[65:55] != 11'd0, - fpu_fOperand_S0$D_OUT[54:3] } ; - assign x__h20711 = fpu_fProd_S3$D_OUT << x__h20744 ; - assign x__h20744 = - 13'd106 - - _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ; - assign x__h327 = - fpu_fOperand_S0$D_OUT[195] ? - fpu_fOperand_S0$D_OUT[193:183] : - 11'd0 ; - assign x__h35221 = - fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ? - _theResult___snd_snd_snd__h35184 : - 2'd3 ; - assign x__h35755 = - { 1'b0, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - { fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:0], - 1'b0 } : - { fpu_fState_S4$D_OUT[128:118] != 11'd0, - fpu_fState_S4$D_OUT[117:66], - 3'b0 } } ; - assign x__h35759 = - { 1'b0, - NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ? - { fpu_fState_S4$D_OUT[128:118] != 11'd0, - fpu_fState_S4$D_OUT[117:66], - 3'b0 } : - { fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:0], - 1'b0 } } ; - assign x__h36174 = - fpu_fState_S5$D_OUT[215] ? - fpu_fState_S5$D_OUT[56:0] : - (((fpu_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? - result__h36187 : - ((fpu_fState_S5$D_OUT[56:0] == 57'd0) ? - fpu_fState_S5$D_OUT[56:0] : - 57'd1)) ; - assign x__h36286 = 13'd57 - fpu_fState_S5$D_OUT[126:114] ; - assign x__h36686 = fpu_fState_S6$D_OUT[113:57] + fpu_fState_S6$D_OUT[56:0] ; - assign x__h36695 = fpu_fState_S6$D_OUT[113:57] - fpu_fState_S6$D_OUT[56:0] ; - assign x__h45575 = fpu_fState_S7$D_OUT[202] ? 2'd0 : guard__h36938 ; - always@(fpu_fState_S8$D_OUT or out_sfd__h46363 or _theResult___sfd__h46360) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = - fpu_fState_S8$D_OUT[54:3]; - 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = - out_sfd__h46363; - 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 = - _theResult___sfd__h46360; - endcase - end - always@(fpu_fState_S8$D_OUT or _theResult___sfd__h46360) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = - fpu_fState_S8$D_OUT[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 = - _theResult___sfd__h46360; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 or - _theResult___sfd__h46360) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_sfd__h46438 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1; - 3'd1: - _theResult___fst_sfd__h46438 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2; - 3'd2: - _theResult___fst_sfd__h46438 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? - fpu_fState_S8$D_OUT[54:3] : - _theResult___sfd__h46360; - 3'd3: - _theResult___fst_sfd__h46438 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[54:3] : - (fpu_fState_S8$D_OUT[66] ? - _theResult___sfd__h46360 : - fpu_fState_S8$D_OUT[54:3]); - 3'd4: _theResult___fst_sfd__h46438 = fpu_fState_S8$D_OUT[54:3]; - default: _theResult___fst_sfd__h46438 = 52'd0; - endcase - end - always@(fpu_fState_S8$D_OUT or out_exp__h46362 or _theResult___exp__h46359) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = - fpu_fState_S8$D_OUT[65:55]; - 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = - out_exp__h46362; - 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 = - _theResult___exp__h46359; - endcase - end - always@(fpu_fState_S8$D_OUT or _theResult___exp__h46359) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = - fpu_fState_S8$D_OUT[65:55]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 = - _theResult___exp__h46359; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 or - _theResult___exp__h46359) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_exp__h46437 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11; - 3'd1: - _theResult___fst_exp__h46437 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12; - 3'd2: - _theResult___fst_exp__h46437 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? - fpu_fState_S8$D_OUT[65:55] : - _theResult___exp__h46359; - 3'd3: - _theResult___fst_exp__h46437 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[65:55] : - (fpu_fState_S8$D_OUT[66] ? - _theResult___exp__h46359 : - fpu_fState_S8$D_OUT[65:55]); - 3'd4: _theResult___fst_exp__h46437 = fpu_fState_S8$D_OUT[65:55]; - default: _theResult___fst_exp__h46437 = 11'd0; - endcase - end - always@(fpu_fState_S8$D_OUT) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = - fpu_fState_S8$D_OUT[66]; - 2'd3: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 = - fpu_fState_S8$D_OUT[2:1] == 2'b11 && fpu_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13; - 3'd1: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[66] : - (fpu_fState_S8$D_OUT[2:1] == 2'b01 || - fpu_fState_S8$D_OUT[2:1] == 2'b10 || - fpu_fState_S8$D_OUT[2:1] == 2'b11) && - fpu_fState_S8$D_OUT[66]; - 3'd2, 3'd3: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - fpu_fState_S8$D_OUT[66]; - default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 = - fpu_fState_S8$D_OUT[70:68] == 3'd4 && - fpu_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = - fpu_fState_S8$D_OUT[65:3]; - 2'b10: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = - fpu_fState_S8$D_OUT[3] ? - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : - fpu_fState_S8$D_OUT[65:3]; - 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 = - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; - endcase - end - always@(fpu_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) - begin - case (fpu_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = - fpu_fState_S8$D_OUT[65:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 = - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; - endcase - end - always@(fpu_fState_S8$D_OUT or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 or - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 or - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266) - begin - case (fpu_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17; - 3'd1: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18; - 3'd2: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ? - fpu_fState_S8$D_OUT[65:3] : - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266; - 3'd3: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - (fpu_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_fState_S8$D_OUT[65:3] : - (fpu_fState_S8$D_OUT[66] ? - IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 : - fpu_fState_S8$D_OUT[65:3]); - 3'd4: - CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = - fpu_fState_S8$D_OUT[65:3]; - default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = 63'd0; - endcase - end + // submodule fpu + assign fpu$request_put = request_put ; + assign fpu$EN_request_put = EN_request_put ; + assign fpu$EN_response_get = EN_response_get ; endmodule // mkDoubleFMA diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v index 9ba65dd..8b1becd 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v @@ -7,16 +7,15 @@ // Ports: // Name I/O size props // RDY_request_put O 1 -// response_get O 69 reg -// RDY_response_get O 1 reg +// response_get O 69 +// RDY_response_get O 1 // CLK I 1 clock // RST_N I 1 reset -// request_put I 67 reg +// request_put I 67 // EN_request_put I 1 // EN_response_get I 1 // -// Combinational paths from inputs to outputs: -// EN_response_get -> RDY_request_put +// No combinational paths from inputs to outputs // // @@ -60,5579 +59,44 @@ module mkDoubleSqrt(CLK, wire [68 : 0] response_get; wire RDY_request_put, RDY_response_get; - // ports of submodule fpu_fOperand_S0 - wire [66 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT; - wire fpu_fOperand_S0$CLR, - fpu_fOperand_S0$DEQ, - fpu_fOperand_S0$EMPTY_N, - fpu_fOperand_S0$ENQ, - fpu_fOperand_S0$FULL_N; - - // ports of submodule fpu_fResult_S5 - wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT; - wire fpu_fResult_S5$CLR, - fpu_fResult_S5$DEQ, - fpu_fResult_S5$EMPTY_N, - fpu_fResult_S5$ENQ, - fpu_fResult_S5$FULL_N; - - // ports of submodule fpu_fState_S1 - wire [194 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT; - wire fpu_fState_S1$CLR, - fpu_fState_S1$DEQ, - fpu_fState_S1$EMPTY_N, - fpu_fState_S1$ENQ, - fpu_fState_S1$FULL_N; - - // ports of submodule fpu_fState_S2 - wire [136 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT; - wire fpu_fState_S2$CLR, - fpu_fState_S2$DEQ, - fpu_fState_S2$EMPTY_N, - fpu_fState_S2$ENQ, - fpu_fState_S2$FULL_N; - - // ports of submodule fpu_fState_S3 - wire [195 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT; - wire fpu_fState_S3$CLR, - fpu_fState_S3$DEQ, - fpu_fState_S3$EMPTY_N, - fpu_fState_S3$ENQ, - fpu_fState_S3$FULL_N; - - // ports of submodule fpu_fState_S4 - wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT; - wire fpu_fState_S4$CLR, - fpu_fState_S4$DEQ, - fpu_fState_S4$EMPTY_N, - fpu_fState_S4$ENQ, - fpu_fState_S4$FULL_N; - - // ports of submodule int_sqrt_fFirst - wire [464 : 0] int_sqrt_fFirst$D_IN, int_sqrt_fFirst$D_OUT; - wire int_sqrt_fFirst$CLR, - int_sqrt_fFirst$DEQ, - int_sqrt_fFirst$EMPTY_N, - int_sqrt_fFirst$ENQ, - int_sqrt_fFirst$FULL_N; - - // ports of submodule int_sqrt_fNext_0 - wire [464 : 0] int_sqrt_fNext_0$D_IN, int_sqrt_fNext_0$D_OUT; - wire int_sqrt_fNext_0$CLR, - int_sqrt_fNext_0$DEQ, - int_sqrt_fNext_0$EMPTY_N, - int_sqrt_fNext_0$ENQ, - int_sqrt_fNext_0$FULL_N; - - // ports of submodule int_sqrt_fNext_1 - wire [464 : 0] int_sqrt_fNext_1$D_IN, int_sqrt_fNext_1$D_OUT; - wire int_sqrt_fNext_1$CLR, - int_sqrt_fNext_1$DEQ, - int_sqrt_fNext_1$EMPTY_N, - int_sqrt_fNext_1$ENQ, - int_sqrt_fNext_1$FULL_N; - - // ports of submodule int_sqrt_fNext_10 - wire [464 : 0] int_sqrt_fNext_10$D_IN, int_sqrt_fNext_10$D_OUT; - wire int_sqrt_fNext_10$CLR, - int_sqrt_fNext_10$DEQ, - int_sqrt_fNext_10$EMPTY_N, - int_sqrt_fNext_10$ENQ, - int_sqrt_fNext_10$FULL_N; - - // ports of submodule int_sqrt_fNext_11 - wire [464 : 0] int_sqrt_fNext_11$D_IN, int_sqrt_fNext_11$D_OUT; - wire int_sqrt_fNext_11$CLR, - int_sqrt_fNext_11$DEQ, - int_sqrt_fNext_11$EMPTY_N, - int_sqrt_fNext_11$ENQ, - int_sqrt_fNext_11$FULL_N; - - // ports of submodule int_sqrt_fNext_12 - wire [464 : 0] int_sqrt_fNext_12$D_IN, int_sqrt_fNext_12$D_OUT; - wire int_sqrt_fNext_12$CLR, - int_sqrt_fNext_12$DEQ, - int_sqrt_fNext_12$EMPTY_N, - int_sqrt_fNext_12$ENQ, - int_sqrt_fNext_12$FULL_N; - - // ports of submodule int_sqrt_fNext_13 - wire [464 : 0] int_sqrt_fNext_13$D_IN, int_sqrt_fNext_13$D_OUT; - wire int_sqrt_fNext_13$CLR, - int_sqrt_fNext_13$DEQ, - int_sqrt_fNext_13$EMPTY_N, - int_sqrt_fNext_13$ENQ, - int_sqrt_fNext_13$FULL_N; - - // ports of submodule int_sqrt_fNext_14 - wire [464 : 0] int_sqrt_fNext_14$D_IN, int_sqrt_fNext_14$D_OUT; - wire int_sqrt_fNext_14$CLR, - int_sqrt_fNext_14$DEQ, - int_sqrt_fNext_14$EMPTY_N, - int_sqrt_fNext_14$ENQ, - int_sqrt_fNext_14$FULL_N; - - // ports of submodule int_sqrt_fNext_15 - wire [464 : 0] int_sqrt_fNext_15$D_IN, int_sqrt_fNext_15$D_OUT; - wire int_sqrt_fNext_15$CLR, - int_sqrt_fNext_15$DEQ, - int_sqrt_fNext_15$EMPTY_N, - int_sqrt_fNext_15$ENQ, - int_sqrt_fNext_15$FULL_N; - - // ports of submodule int_sqrt_fNext_16 - wire [464 : 0] int_sqrt_fNext_16$D_IN, int_sqrt_fNext_16$D_OUT; - wire int_sqrt_fNext_16$CLR, - int_sqrt_fNext_16$DEQ, - int_sqrt_fNext_16$EMPTY_N, - int_sqrt_fNext_16$ENQ, - int_sqrt_fNext_16$FULL_N; - - // ports of submodule int_sqrt_fNext_17 - wire [464 : 0] int_sqrt_fNext_17$D_IN, int_sqrt_fNext_17$D_OUT; - wire int_sqrt_fNext_17$CLR, - int_sqrt_fNext_17$DEQ, - int_sqrt_fNext_17$EMPTY_N, - int_sqrt_fNext_17$ENQ, - int_sqrt_fNext_17$FULL_N; - - // ports of submodule int_sqrt_fNext_18 - wire [464 : 0] int_sqrt_fNext_18$D_IN, int_sqrt_fNext_18$D_OUT; - wire int_sqrt_fNext_18$CLR, - int_sqrt_fNext_18$DEQ, - int_sqrt_fNext_18$EMPTY_N, - int_sqrt_fNext_18$ENQ, - int_sqrt_fNext_18$FULL_N; - - // ports of submodule int_sqrt_fNext_19 - wire [464 : 0] int_sqrt_fNext_19$D_IN, int_sqrt_fNext_19$D_OUT; - wire int_sqrt_fNext_19$CLR, - int_sqrt_fNext_19$DEQ, - int_sqrt_fNext_19$EMPTY_N, - int_sqrt_fNext_19$ENQ, - int_sqrt_fNext_19$FULL_N; - - // ports of submodule int_sqrt_fNext_2 - wire [464 : 0] int_sqrt_fNext_2$D_IN, int_sqrt_fNext_2$D_OUT; - wire int_sqrt_fNext_2$CLR, - int_sqrt_fNext_2$DEQ, - int_sqrt_fNext_2$EMPTY_N, - int_sqrt_fNext_2$ENQ, - int_sqrt_fNext_2$FULL_N; - - // ports of submodule int_sqrt_fNext_20 - wire [464 : 0] int_sqrt_fNext_20$D_IN, int_sqrt_fNext_20$D_OUT; - wire int_sqrt_fNext_20$CLR, - int_sqrt_fNext_20$DEQ, - int_sqrt_fNext_20$EMPTY_N, - int_sqrt_fNext_20$ENQ, - int_sqrt_fNext_20$FULL_N; - - // ports of submodule int_sqrt_fNext_21 - wire [464 : 0] int_sqrt_fNext_21$D_IN, int_sqrt_fNext_21$D_OUT; - wire int_sqrt_fNext_21$CLR, - int_sqrt_fNext_21$DEQ, - int_sqrt_fNext_21$EMPTY_N, - int_sqrt_fNext_21$ENQ, - int_sqrt_fNext_21$FULL_N; - - // ports of submodule int_sqrt_fNext_22 - wire [464 : 0] int_sqrt_fNext_22$D_IN, int_sqrt_fNext_22$D_OUT; - wire int_sqrt_fNext_22$CLR, - int_sqrt_fNext_22$DEQ, - int_sqrt_fNext_22$EMPTY_N, - int_sqrt_fNext_22$ENQ, - int_sqrt_fNext_22$FULL_N; - - // ports of submodule int_sqrt_fNext_23 - wire [464 : 0] int_sqrt_fNext_23$D_IN, int_sqrt_fNext_23$D_OUT; - wire int_sqrt_fNext_23$CLR, - int_sqrt_fNext_23$DEQ, - int_sqrt_fNext_23$EMPTY_N, - int_sqrt_fNext_23$ENQ, - int_sqrt_fNext_23$FULL_N; - - // ports of submodule int_sqrt_fNext_24 - wire [464 : 0] int_sqrt_fNext_24$D_IN, int_sqrt_fNext_24$D_OUT; - wire int_sqrt_fNext_24$CLR, - int_sqrt_fNext_24$DEQ, - int_sqrt_fNext_24$EMPTY_N, - int_sqrt_fNext_24$ENQ, - int_sqrt_fNext_24$FULL_N; - - // ports of submodule int_sqrt_fNext_25 - wire [464 : 0] int_sqrt_fNext_25$D_IN, int_sqrt_fNext_25$D_OUT; - wire int_sqrt_fNext_25$CLR, - int_sqrt_fNext_25$DEQ, - int_sqrt_fNext_25$EMPTY_N, - int_sqrt_fNext_25$ENQ, - int_sqrt_fNext_25$FULL_N; - - // ports of submodule int_sqrt_fNext_26 - wire [464 : 0] int_sqrt_fNext_26$D_IN, int_sqrt_fNext_26$D_OUT; - wire int_sqrt_fNext_26$CLR, - int_sqrt_fNext_26$DEQ, - int_sqrt_fNext_26$EMPTY_N, - int_sqrt_fNext_26$ENQ, - int_sqrt_fNext_26$FULL_N; - - // ports of submodule int_sqrt_fNext_27 - wire [464 : 0] int_sqrt_fNext_27$D_IN, int_sqrt_fNext_27$D_OUT; - wire int_sqrt_fNext_27$CLR, - int_sqrt_fNext_27$DEQ, - int_sqrt_fNext_27$EMPTY_N, - int_sqrt_fNext_27$ENQ, - int_sqrt_fNext_27$FULL_N; - - // ports of submodule int_sqrt_fNext_28 - wire [464 : 0] int_sqrt_fNext_28$D_IN, int_sqrt_fNext_28$D_OUT; - wire int_sqrt_fNext_28$CLR, - int_sqrt_fNext_28$DEQ, - int_sqrt_fNext_28$EMPTY_N, - int_sqrt_fNext_28$ENQ, - int_sqrt_fNext_28$FULL_N; - - // ports of submodule int_sqrt_fNext_29 - wire [464 : 0] int_sqrt_fNext_29$D_IN, int_sqrt_fNext_29$D_OUT; - wire int_sqrt_fNext_29$CLR, - int_sqrt_fNext_29$DEQ, - int_sqrt_fNext_29$EMPTY_N, - int_sqrt_fNext_29$ENQ, - int_sqrt_fNext_29$FULL_N; - - // ports of submodule int_sqrt_fNext_3 - wire [464 : 0] int_sqrt_fNext_3$D_IN, int_sqrt_fNext_3$D_OUT; - wire int_sqrt_fNext_3$CLR, - int_sqrt_fNext_3$DEQ, - int_sqrt_fNext_3$EMPTY_N, - int_sqrt_fNext_3$ENQ, - int_sqrt_fNext_3$FULL_N; - - // ports of submodule int_sqrt_fNext_30 - wire [464 : 0] int_sqrt_fNext_30$D_IN, int_sqrt_fNext_30$D_OUT; - wire int_sqrt_fNext_30$CLR, - int_sqrt_fNext_30$DEQ, - int_sqrt_fNext_30$EMPTY_N, - int_sqrt_fNext_30$ENQ, - int_sqrt_fNext_30$FULL_N; - - // ports of submodule int_sqrt_fNext_31 - wire [464 : 0] int_sqrt_fNext_31$D_IN, int_sqrt_fNext_31$D_OUT; - wire int_sqrt_fNext_31$CLR, - int_sqrt_fNext_31$DEQ, - int_sqrt_fNext_31$EMPTY_N, - int_sqrt_fNext_31$ENQ, - int_sqrt_fNext_31$FULL_N; - - // ports of submodule int_sqrt_fNext_32 - wire [464 : 0] int_sqrt_fNext_32$D_IN, int_sqrt_fNext_32$D_OUT; - wire int_sqrt_fNext_32$CLR, - int_sqrt_fNext_32$DEQ, - int_sqrt_fNext_32$EMPTY_N, - int_sqrt_fNext_32$ENQ, - int_sqrt_fNext_32$FULL_N; - - // ports of submodule int_sqrt_fNext_33 - wire [464 : 0] int_sqrt_fNext_33$D_IN, int_sqrt_fNext_33$D_OUT; - wire int_sqrt_fNext_33$CLR, - int_sqrt_fNext_33$DEQ, - int_sqrt_fNext_33$EMPTY_N, - int_sqrt_fNext_33$ENQ, - int_sqrt_fNext_33$FULL_N; - - // ports of submodule int_sqrt_fNext_34 - wire [464 : 0] int_sqrt_fNext_34$D_IN, int_sqrt_fNext_34$D_OUT; - wire int_sqrt_fNext_34$CLR, - int_sqrt_fNext_34$DEQ, - int_sqrt_fNext_34$EMPTY_N, - int_sqrt_fNext_34$ENQ, - int_sqrt_fNext_34$FULL_N; - - // ports of submodule int_sqrt_fNext_35 - wire [464 : 0] int_sqrt_fNext_35$D_IN, int_sqrt_fNext_35$D_OUT; - wire int_sqrt_fNext_35$CLR, - int_sqrt_fNext_35$DEQ, - int_sqrt_fNext_35$EMPTY_N, - int_sqrt_fNext_35$ENQ, - int_sqrt_fNext_35$FULL_N; - - // ports of submodule int_sqrt_fNext_36 - wire [464 : 0] int_sqrt_fNext_36$D_IN, int_sqrt_fNext_36$D_OUT; - wire int_sqrt_fNext_36$CLR, - int_sqrt_fNext_36$DEQ, - int_sqrt_fNext_36$EMPTY_N, - int_sqrt_fNext_36$ENQ, - int_sqrt_fNext_36$FULL_N; - - // ports of submodule int_sqrt_fNext_37 - wire [464 : 0] int_sqrt_fNext_37$D_IN, int_sqrt_fNext_37$D_OUT; - wire int_sqrt_fNext_37$CLR, - int_sqrt_fNext_37$DEQ, - int_sqrt_fNext_37$EMPTY_N, - int_sqrt_fNext_37$ENQ, - int_sqrt_fNext_37$FULL_N; - - // ports of submodule int_sqrt_fNext_38 - wire [464 : 0] int_sqrt_fNext_38$D_IN, int_sqrt_fNext_38$D_OUT; - wire int_sqrt_fNext_38$CLR, - int_sqrt_fNext_38$DEQ, - int_sqrt_fNext_38$EMPTY_N, - int_sqrt_fNext_38$ENQ, - int_sqrt_fNext_38$FULL_N; - - // ports of submodule int_sqrt_fNext_39 - wire [464 : 0] int_sqrt_fNext_39$D_IN, int_sqrt_fNext_39$D_OUT; - wire int_sqrt_fNext_39$CLR, - int_sqrt_fNext_39$DEQ, - int_sqrt_fNext_39$EMPTY_N, - int_sqrt_fNext_39$ENQ, - int_sqrt_fNext_39$FULL_N; - - // ports of submodule int_sqrt_fNext_4 - wire [464 : 0] int_sqrt_fNext_4$D_IN, int_sqrt_fNext_4$D_OUT; - wire int_sqrt_fNext_4$CLR, - int_sqrt_fNext_4$DEQ, - int_sqrt_fNext_4$EMPTY_N, - int_sqrt_fNext_4$ENQ, - int_sqrt_fNext_4$FULL_N; - - // ports of submodule int_sqrt_fNext_40 - wire [464 : 0] int_sqrt_fNext_40$D_IN, int_sqrt_fNext_40$D_OUT; - wire int_sqrt_fNext_40$CLR, - int_sqrt_fNext_40$DEQ, - int_sqrt_fNext_40$EMPTY_N, - int_sqrt_fNext_40$ENQ, - int_sqrt_fNext_40$FULL_N; - - // ports of submodule int_sqrt_fNext_41 - wire [464 : 0] int_sqrt_fNext_41$D_IN, int_sqrt_fNext_41$D_OUT; - wire int_sqrt_fNext_41$CLR, - int_sqrt_fNext_41$DEQ, - int_sqrt_fNext_41$EMPTY_N, - int_sqrt_fNext_41$ENQ, - int_sqrt_fNext_41$FULL_N; - - // ports of submodule int_sqrt_fNext_42 - wire [464 : 0] int_sqrt_fNext_42$D_IN, int_sqrt_fNext_42$D_OUT; - wire int_sqrt_fNext_42$CLR, - int_sqrt_fNext_42$DEQ, - int_sqrt_fNext_42$EMPTY_N, - int_sqrt_fNext_42$ENQ, - int_sqrt_fNext_42$FULL_N; - - // ports of submodule int_sqrt_fNext_43 - wire [464 : 0] int_sqrt_fNext_43$D_IN, int_sqrt_fNext_43$D_OUT; - wire int_sqrt_fNext_43$CLR, - int_sqrt_fNext_43$DEQ, - int_sqrt_fNext_43$EMPTY_N, - int_sqrt_fNext_43$ENQ, - int_sqrt_fNext_43$FULL_N; - - // ports of submodule int_sqrt_fNext_44 - wire [464 : 0] int_sqrt_fNext_44$D_IN, int_sqrt_fNext_44$D_OUT; - wire int_sqrt_fNext_44$CLR, - int_sqrt_fNext_44$DEQ, - int_sqrt_fNext_44$EMPTY_N, - int_sqrt_fNext_44$ENQ, - int_sqrt_fNext_44$FULL_N; - - // ports of submodule int_sqrt_fNext_45 - wire [464 : 0] int_sqrt_fNext_45$D_IN, int_sqrt_fNext_45$D_OUT; - wire int_sqrt_fNext_45$CLR, - int_sqrt_fNext_45$DEQ, - int_sqrt_fNext_45$EMPTY_N, - int_sqrt_fNext_45$ENQ, - int_sqrt_fNext_45$FULL_N; - - // ports of submodule int_sqrt_fNext_46 - wire [464 : 0] int_sqrt_fNext_46$D_IN, int_sqrt_fNext_46$D_OUT; - wire int_sqrt_fNext_46$CLR, - int_sqrt_fNext_46$DEQ, - int_sqrt_fNext_46$EMPTY_N, - int_sqrt_fNext_46$ENQ, - int_sqrt_fNext_46$FULL_N; - - // ports of submodule int_sqrt_fNext_47 - wire [464 : 0] int_sqrt_fNext_47$D_IN, int_sqrt_fNext_47$D_OUT; - wire int_sqrt_fNext_47$CLR, - int_sqrt_fNext_47$DEQ, - int_sqrt_fNext_47$EMPTY_N, - int_sqrt_fNext_47$ENQ, - int_sqrt_fNext_47$FULL_N; - - // ports of submodule int_sqrt_fNext_48 - wire [464 : 0] int_sqrt_fNext_48$D_IN, int_sqrt_fNext_48$D_OUT; - wire int_sqrt_fNext_48$CLR, - int_sqrt_fNext_48$DEQ, - int_sqrt_fNext_48$EMPTY_N, - int_sqrt_fNext_48$ENQ, - int_sqrt_fNext_48$FULL_N; - - // ports of submodule int_sqrt_fNext_49 - wire [464 : 0] int_sqrt_fNext_49$D_IN, int_sqrt_fNext_49$D_OUT; - wire int_sqrt_fNext_49$CLR, - int_sqrt_fNext_49$DEQ, - int_sqrt_fNext_49$EMPTY_N, - int_sqrt_fNext_49$ENQ, - int_sqrt_fNext_49$FULL_N; - - // ports of submodule int_sqrt_fNext_5 - wire [464 : 0] int_sqrt_fNext_5$D_IN, int_sqrt_fNext_5$D_OUT; - wire int_sqrt_fNext_5$CLR, - int_sqrt_fNext_5$DEQ, - int_sqrt_fNext_5$EMPTY_N, - int_sqrt_fNext_5$ENQ, - int_sqrt_fNext_5$FULL_N; - - // ports of submodule int_sqrt_fNext_50 - wire [464 : 0] int_sqrt_fNext_50$D_IN, int_sqrt_fNext_50$D_OUT; - wire int_sqrt_fNext_50$CLR, - int_sqrt_fNext_50$DEQ, - int_sqrt_fNext_50$EMPTY_N, - int_sqrt_fNext_50$ENQ, - int_sqrt_fNext_50$FULL_N; - - // ports of submodule int_sqrt_fNext_51 - wire [464 : 0] int_sqrt_fNext_51$D_IN, int_sqrt_fNext_51$D_OUT; - wire int_sqrt_fNext_51$CLR, - int_sqrt_fNext_51$DEQ, - int_sqrt_fNext_51$EMPTY_N, - int_sqrt_fNext_51$ENQ, - int_sqrt_fNext_51$FULL_N; - - // ports of submodule int_sqrt_fNext_52 - wire [464 : 0] int_sqrt_fNext_52$D_IN, int_sqrt_fNext_52$D_OUT; - wire int_sqrt_fNext_52$CLR, - int_sqrt_fNext_52$DEQ, - int_sqrt_fNext_52$EMPTY_N, - int_sqrt_fNext_52$ENQ, - int_sqrt_fNext_52$FULL_N; - - // ports of submodule int_sqrt_fNext_53 - wire [464 : 0] int_sqrt_fNext_53$D_IN, int_sqrt_fNext_53$D_OUT; - wire int_sqrt_fNext_53$CLR, - int_sqrt_fNext_53$DEQ, - int_sqrt_fNext_53$EMPTY_N, - int_sqrt_fNext_53$ENQ, - int_sqrt_fNext_53$FULL_N; - - // ports of submodule int_sqrt_fNext_54 - wire [464 : 0] int_sqrt_fNext_54$D_IN, int_sqrt_fNext_54$D_OUT; - wire int_sqrt_fNext_54$CLR, - int_sqrt_fNext_54$DEQ, - int_sqrt_fNext_54$EMPTY_N, - int_sqrt_fNext_54$ENQ, - int_sqrt_fNext_54$FULL_N; - - // ports of submodule int_sqrt_fNext_55 - wire [464 : 0] int_sqrt_fNext_55$D_IN, int_sqrt_fNext_55$D_OUT; - wire int_sqrt_fNext_55$CLR, - int_sqrt_fNext_55$DEQ, - int_sqrt_fNext_55$EMPTY_N, - int_sqrt_fNext_55$ENQ, - int_sqrt_fNext_55$FULL_N; - - // ports of submodule int_sqrt_fNext_56 - wire [464 : 0] int_sqrt_fNext_56$D_IN, int_sqrt_fNext_56$D_OUT; - wire int_sqrt_fNext_56$CLR, - int_sqrt_fNext_56$DEQ, - int_sqrt_fNext_56$EMPTY_N, - int_sqrt_fNext_56$ENQ, - int_sqrt_fNext_56$FULL_N; - - // ports of submodule int_sqrt_fNext_57 - wire [464 : 0] int_sqrt_fNext_57$D_IN, int_sqrt_fNext_57$D_OUT; - wire int_sqrt_fNext_57$CLR, - int_sqrt_fNext_57$DEQ, - int_sqrt_fNext_57$EMPTY_N, - int_sqrt_fNext_57$ENQ, - int_sqrt_fNext_57$FULL_N; - - // ports of submodule int_sqrt_fNext_58 - wire [464 : 0] int_sqrt_fNext_58$D_IN, int_sqrt_fNext_58$D_OUT; - wire int_sqrt_fNext_58$CLR, - int_sqrt_fNext_58$DEQ, - int_sqrt_fNext_58$EMPTY_N, - int_sqrt_fNext_58$ENQ, - int_sqrt_fNext_58$FULL_N; - - // ports of submodule int_sqrt_fNext_6 - wire [464 : 0] int_sqrt_fNext_6$D_IN, int_sqrt_fNext_6$D_OUT; - wire int_sqrt_fNext_6$CLR, - int_sqrt_fNext_6$DEQ, - int_sqrt_fNext_6$EMPTY_N, - int_sqrt_fNext_6$ENQ, - int_sqrt_fNext_6$FULL_N; - - // ports of submodule int_sqrt_fNext_7 - wire [464 : 0] int_sqrt_fNext_7$D_IN, int_sqrt_fNext_7$D_OUT; - wire int_sqrt_fNext_7$CLR, - int_sqrt_fNext_7$DEQ, - int_sqrt_fNext_7$EMPTY_N, - int_sqrt_fNext_7$ENQ, - int_sqrt_fNext_7$FULL_N; - - // ports of submodule int_sqrt_fNext_8 - wire [464 : 0] int_sqrt_fNext_8$D_IN, int_sqrt_fNext_8$D_OUT; - wire int_sqrt_fNext_8$CLR, - int_sqrt_fNext_8$DEQ, - int_sqrt_fNext_8$EMPTY_N, - int_sqrt_fNext_8$ENQ, - int_sqrt_fNext_8$FULL_N; - - // ports of submodule int_sqrt_fNext_9 - wire [464 : 0] int_sqrt_fNext_9$D_IN, int_sqrt_fNext_9$D_OUT; - wire int_sqrt_fNext_9$CLR, - int_sqrt_fNext_9$DEQ, - int_sqrt_fNext_9$EMPTY_N, - int_sqrt_fNext_9$ENQ, - int_sqrt_fNext_9$FULL_N; - - // ports of submodule int_sqrt_fRequest - wire [115 : 0] int_sqrt_fRequest$D_IN, int_sqrt_fRequest$D_OUT; - wire int_sqrt_fRequest$CLR, - int_sqrt_fRequest$DEQ, - int_sqrt_fRequest$EMPTY_N, - int_sqrt_fRequest$ENQ, - int_sqrt_fRequest$FULL_N; - - // ports of submodule int_sqrt_fResponse - wire [116 : 0] int_sqrt_fResponse$D_IN, int_sqrt_fResponse$D_OUT; - wire int_sqrt_fResponse$CLR, - int_sqrt_fResponse$DEQ, - int_sqrt_fResponse$EMPTY_N, - int_sqrt_fResponse$ENQ, - int_sqrt_fResponse$FULL_N; + // ports of submodule fpu + wire [68 : 0] fpu$response_get; + wire [66 : 0] fpu$request_put; + wire fpu$EN_request_put, + fpu$EN_response_get, + fpu$RDY_request_put, + fpu$RDY_response_get; // rule scheduling signals - wire CAN_FIRE_RL_fpu_s1_stage, - CAN_FIRE_RL_fpu_s2_stage, - CAN_FIRE_RL_fpu_s3_stage, - CAN_FIRE_RL_fpu_s4_stage, - CAN_FIRE_RL_fpu_s5_stage, - CAN_FIRE_RL_int_sqrt_finish, - CAN_FIRE_RL_int_sqrt_start, - CAN_FIRE_RL_int_sqrt_work, - CAN_FIRE_RL_int_sqrt_work_1, - CAN_FIRE_RL_int_sqrt_work_10, - CAN_FIRE_RL_int_sqrt_work_11, - CAN_FIRE_RL_int_sqrt_work_12, - CAN_FIRE_RL_int_sqrt_work_13, - CAN_FIRE_RL_int_sqrt_work_14, - CAN_FIRE_RL_int_sqrt_work_15, - CAN_FIRE_RL_int_sqrt_work_16, - CAN_FIRE_RL_int_sqrt_work_17, - CAN_FIRE_RL_int_sqrt_work_18, - CAN_FIRE_RL_int_sqrt_work_19, - CAN_FIRE_RL_int_sqrt_work_2, - CAN_FIRE_RL_int_sqrt_work_20, - CAN_FIRE_RL_int_sqrt_work_21, - CAN_FIRE_RL_int_sqrt_work_22, - CAN_FIRE_RL_int_sqrt_work_23, - CAN_FIRE_RL_int_sqrt_work_24, - CAN_FIRE_RL_int_sqrt_work_25, - CAN_FIRE_RL_int_sqrt_work_26, - CAN_FIRE_RL_int_sqrt_work_27, - CAN_FIRE_RL_int_sqrt_work_28, - CAN_FIRE_RL_int_sqrt_work_29, - CAN_FIRE_RL_int_sqrt_work_3, - CAN_FIRE_RL_int_sqrt_work_30, - CAN_FIRE_RL_int_sqrt_work_31, - CAN_FIRE_RL_int_sqrt_work_32, - CAN_FIRE_RL_int_sqrt_work_33, - CAN_FIRE_RL_int_sqrt_work_34, - CAN_FIRE_RL_int_sqrt_work_35, - CAN_FIRE_RL_int_sqrt_work_36, - CAN_FIRE_RL_int_sqrt_work_37, - CAN_FIRE_RL_int_sqrt_work_38, - CAN_FIRE_RL_int_sqrt_work_39, - CAN_FIRE_RL_int_sqrt_work_4, - CAN_FIRE_RL_int_sqrt_work_40, - CAN_FIRE_RL_int_sqrt_work_41, - CAN_FIRE_RL_int_sqrt_work_42, - CAN_FIRE_RL_int_sqrt_work_43, - CAN_FIRE_RL_int_sqrt_work_44, - CAN_FIRE_RL_int_sqrt_work_45, - CAN_FIRE_RL_int_sqrt_work_46, - CAN_FIRE_RL_int_sqrt_work_47, - CAN_FIRE_RL_int_sqrt_work_48, - CAN_FIRE_RL_int_sqrt_work_49, - CAN_FIRE_RL_int_sqrt_work_5, - CAN_FIRE_RL_int_sqrt_work_50, - CAN_FIRE_RL_int_sqrt_work_51, - CAN_FIRE_RL_int_sqrt_work_52, - CAN_FIRE_RL_int_sqrt_work_53, - CAN_FIRE_RL_int_sqrt_work_54, - CAN_FIRE_RL_int_sqrt_work_55, - CAN_FIRE_RL_int_sqrt_work_56, - CAN_FIRE_RL_int_sqrt_work_57, - CAN_FIRE_RL_int_sqrt_work_58, - CAN_FIRE_RL_int_sqrt_work_6, - CAN_FIRE_RL_int_sqrt_work_7, - CAN_FIRE_RL_int_sqrt_work_8, - CAN_FIRE_RL_int_sqrt_work_9, - CAN_FIRE_request_put, + wire CAN_FIRE_request_put, CAN_FIRE_response_get, - WILL_FIRE_RL_fpu_s1_stage, - WILL_FIRE_RL_fpu_s2_stage, - WILL_FIRE_RL_fpu_s3_stage, - WILL_FIRE_RL_fpu_s4_stage, - WILL_FIRE_RL_fpu_s5_stage, - WILL_FIRE_RL_int_sqrt_finish, - WILL_FIRE_RL_int_sqrt_start, - WILL_FIRE_RL_int_sqrt_work, - WILL_FIRE_RL_int_sqrt_work_1, - WILL_FIRE_RL_int_sqrt_work_10, - WILL_FIRE_RL_int_sqrt_work_11, - WILL_FIRE_RL_int_sqrt_work_12, - WILL_FIRE_RL_int_sqrt_work_13, - WILL_FIRE_RL_int_sqrt_work_14, - WILL_FIRE_RL_int_sqrt_work_15, - WILL_FIRE_RL_int_sqrt_work_16, - WILL_FIRE_RL_int_sqrt_work_17, - WILL_FIRE_RL_int_sqrt_work_18, - WILL_FIRE_RL_int_sqrt_work_19, - WILL_FIRE_RL_int_sqrt_work_2, - WILL_FIRE_RL_int_sqrt_work_20, - WILL_FIRE_RL_int_sqrt_work_21, - WILL_FIRE_RL_int_sqrt_work_22, - WILL_FIRE_RL_int_sqrt_work_23, - WILL_FIRE_RL_int_sqrt_work_24, - WILL_FIRE_RL_int_sqrt_work_25, - WILL_FIRE_RL_int_sqrt_work_26, - WILL_FIRE_RL_int_sqrt_work_27, - WILL_FIRE_RL_int_sqrt_work_28, - WILL_FIRE_RL_int_sqrt_work_29, - WILL_FIRE_RL_int_sqrt_work_3, - WILL_FIRE_RL_int_sqrt_work_30, - WILL_FIRE_RL_int_sqrt_work_31, - WILL_FIRE_RL_int_sqrt_work_32, - WILL_FIRE_RL_int_sqrt_work_33, - WILL_FIRE_RL_int_sqrt_work_34, - WILL_FIRE_RL_int_sqrt_work_35, - WILL_FIRE_RL_int_sqrt_work_36, - WILL_FIRE_RL_int_sqrt_work_37, - WILL_FIRE_RL_int_sqrt_work_38, - WILL_FIRE_RL_int_sqrt_work_39, - WILL_FIRE_RL_int_sqrt_work_4, - WILL_FIRE_RL_int_sqrt_work_40, - WILL_FIRE_RL_int_sqrt_work_41, - WILL_FIRE_RL_int_sqrt_work_42, - WILL_FIRE_RL_int_sqrt_work_43, - WILL_FIRE_RL_int_sqrt_work_44, - WILL_FIRE_RL_int_sqrt_work_45, - WILL_FIRE_RL_int_sqrt_work_46, - WILL_FIRE_RL_int_sqrt_work_47, - WILL_FIRE_RL_int_sqrt_work_48, - WILL_FIRE_RL_int_sqrt_work_49, - WILL_FIRE_RL_int_sqrt_work_5, - WILL_FIRE_RL_int_sqrt_work_50, - WILL_FIRE_RL_int_sqrt_work_51, - WILL_FIRE_RL_int_sqrt_work_52, - WILL_FIRE_RL_int_sqrt_work_53, - WILL_FIRE_RL_int_sqrt_work_54, - WILL_FIRE_RL_int_sqrt_work_55, - WILL_FIRE_RL_int_sqrt_work_56, - WILL_FIRE_RL_int_sqrt_work_57, - WILL_FIRE_RL_int_sqrt_work_58, - WILL_FIRE_RL_int_sqrt_work_6, - WILL_FIRE_RL_int_sqrt_work_7, - WILL_FIRE_RL_int_sqrt_work_8, - WILL_FIRE_RL_int_sqrt_work_9, WILL_FIRE_request_put, WILL_FIRE_response_get; - // remaining internal signals - reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15; - reg [62 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11; - reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2, - _theResult___fst_sfd__h76507; - reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4, - _theResult___fst_exp__h76506; - reg CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10; - wire [194 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477; - wire [115 : 0] _theResult___snd_fst__h25299, - _theResult___snd_fst__h25701, - _theResult___snd_fst__h26101, - _theResult___snd_fst__h26501, - _theResult___snd_fst__h26901, - _theResult___snd_fst__h27301, - _theResult___snd_fst__h27701, - _theResult___snd_fst__h28101, - _theResult___snd_fst__h28501, - _theResult___snd_fst__h28901, - _theResult___snd_fst__h29301, - _theResult___snd_fst__h29701, - _theResult___snd_fst__h30101, - _theResult___snd_fst__h30501, - _theResult___snd_fst__h30901, - _theResult___snd_fst__h31301, - _theResult___snd_fst__h31701, - _theResult___snd_fst__h32101, - _theResult___snd_fst__h32501, - _theResult___snd_fst__h32901, - _theResult___snd_fst__h33301, - _theResult___snd_fst__h33701, - _theResult___snd_fst__h34101, - _theResult___snd_fst__h34501, - _theResult___snd_fst__h34901, - _theResult___snd_fst__h35301, - _theResult___snd_fst__h35701, - _theResult___snd_fst__h36101, - _theResult___snd_fst__h36501, - _theResult___snd_fst__h36901, - _theResult___snd_fst__h37301, - _theResult___snd_fst__h37701, - _theResult___snd_fst__h38101, - _theResult___snd_fst__h38501, - _theResult___snd_fst__h38901, - _theResult___snd_fst__h39301, - _theResult___snd_fst__h39701, - _theResult___snd_fst__h40101, - _theResult___snd_fst__h40501, - _theResult___snd_fst__h40901, - _theResult___snd_fst__h41301, - _theResult___snd_fst__h41701, - _theResult___snd_fst__h42101, - _theResult___snd_fst__h42501, - _theResult___snd_fst__h42901, - _theResult___snd_fst__h43301, - _theResult___snd_fst__h43701, - _theResult___snd_fst__h44101, - _theResult___snd_fst__h44501, - _theResult___snd_fst__h44901, - _theResult___snd_fst__h45301, - _theResult___snd_fst__h45701, - _theResult___snd_fst__h46101, - _theResult___snd_fst__h46501, - _theResult___snd_fst__h46901, - _theResult___snd_fst__h47301, - _theResult___snd_fst__h47701, - _theResult___snd_fst__h48101, - _theResult___snd_fst__h48501, - _theResult___snd_snd__h25377, - _theResult___snd_snd__h25777, - _theResult___snd_snd__h26177, - _theResult___snd_snd__h26577, - _theResult___snd_snd__h26977, - _theResult___snd_snd__h27377, - _theResult___snd_snd__h27777, - _theResult___snd_snd__h28177, - _theResult___snd_snd__h28577, - _theResult___snd_snd__h28977, - _theResult___snd_snd__h29377, - _theResult___snd_snd__h29777, - _theResult___snd_snd__h30177, - _theResult___snd_snd__h30577, - _theResult___snd_snd__h30977, - _theResult___snd_snd__h31377, - _theResult___snd_snd__h31777, - _theResult___snd_snd__h32177, - _theResult___snd_snd__h32577, - _theResult___snd_snd__h32977, - _theResult___snd_snd__h33377, - _theResult___snd_snd__h33777, - _theResult___snd_snd__h34177, - _theResult___snd_snd__h34577, - _theResult___snd_snd__h34977, - _theResult___snd_snd__h35377, - _theResult___snd_snd__h35777, - _theResult___snd_snd__h36177, - _theResult___snd_snd__h36577, - _theResult___snd_snd__h36977, - _theResult___snd_snd__h37377, - _theResult___snd_snd__h37777, - _theResult___snd_snd__h38177, - _theResult___snd_snd__h38577, - _theResult___snd_snd__h38977, - _theResult___snd_snd__h39377, - _theResult___snd_snd__h39777, - _theResult___snd_snd__h40177, - _theResult___snd_snd__h40577, - _theResult___snd_snd__h40977, - _theResult___snd_snd__h41377, - _theResult___snd_snd__h41777, - _theResult___snd_snd__h42177, - _theResult___snd_snd__h42577, - _theResult___snd_snd__h42977, - _theResult___snd_snd__h43377, - _theResult___snd_snd__h43777, - _theResult___snd_snd__h44177, - _theResult___snd_snd__h44577, - _theResult___snd_snd__h44977, - _theResult___snd_snd__h45377, - _theResult___snd_snd__h45777, - _theResult___snd_snd__h46177, - _theResult___snd_snd__h46577, - _theResult___snd_snd__h46977, - _theResult___snd_snd__h47377, - _theResult___snd_snd__h47777, - _theResult___snd_snd__h48177, - _theResult___snd_snd__h48577, - b___1__h16687, - b__h25374, - b__h25774, - b__h26174, - b__h26574, - b__h26974, - b__h27374, - b__h27774, - b__h28174, - b__h28574, - b__h28974, - b__h29374, - b__h29774, - b__h30174, - b__h30574, - b__h30974, - b__h31374, - b__h31774, - b__h32174, - b__h32574, - b__h32974, - b__h33374, - b__h33774, - b__h34174, - b__h34574, - b__h34974, - b__h35374, - b__h35774, - b__h36174, - b__h36574, - b__h36974, - b__h37374, - b__h37774, - b__h38174, - b__h38574, - b__h38974, - b__h39374, - b__h39774, - b__h40174, - b__h40574, - b__h40974, - b__h41374, - b__h41774, - b__h42174, - b__h42574, - b__h42974, - b__h43374, - b__h43774, - b__h44174, - b__h44574, - b__h44974, - b__h45374, - b__h45774, - b__h46174, - b__h46574, - b__h46974, - b__h47374, - b__h47774, - b__h48174, - b__h48574, - b__h48712, - r__h25386, - r__h25394, - r__h25786, - r__h25794, - r__h26186, - r__h26194, - r__h26586, - r__h26594, - r__h26986, - r__h26994, - r__h27386, - r__h27394, - r__h27786, - r__h27794, - r__h28186, - r__h28194, - r__h28586, - r__h28594, - r__h28986, - r__h28994, - r__h29386, - r__h29394, - r__h29786, - r__h29794, - r__h30186, - r__h30194, - r__h30586, - r__h30594, - r__h30986, - r__h30994, - r__h31386, - r__h31394, - r__h31786, - r__h31794, - r__h32186, - r__h32194, - r__h32586, - r__h32594, - r__h32986, - r__h32994, - r__h33386, - r__h33394, - r__h33786, - r__h33794, - r__h34186, - r__h34194, - r__h34586, - r__h34594, - r__h34986, - r__h34994, - r__h35386, - r__h35394, - r__h35786, - r__h35794, - r__h36186, - r__h36194, - r__h36586, - r__h36594, - r__h36986, - r__h36994, - r__h37386, - r__h37394, - r__h37786, - r__h37794, - r__h38186, - r__h38194, - r__h38586, - r__h38594, - r__h38986, - r__h38994, - r__h39386, - r__h39394, - r__h39786, - r__h39794, - r__h40186, - r__h40194, - r__h40586, - r__h40594, - r__h40986, - r__h40994, - r__h41386, - r__h41394, - r__h41786, - r__h41794, - r__h42186, - r__h42194, - r__h42586, - r__h42594, - r__h42986, - r__h42994, - r__h43386, - r__h43394, - r__h43786, - r__h43794, - r__h44186, - r__h44194, - r__h44586, - r__h44594, - r__h44986, - r__h44994, - r__h45386, - r__h45394, - r__h45786, - r__h45794, - r__h46186, - r__h46194, - r__h46586, - r__h46594, - r__h46986, - r__h46994, - r__h47386, - r__h47394, - r__h47786, - r__h47794, - r__h48186, - r__h48194, - r__h48586, - r__h48594, - s__h25385, - s__h25785, - s__h26185, - s__h26585, - s__h26985, - s__h27385, - s__h27785, - s__h28185, - s__h28585, - s__h28985, - s__h29385, - s__h29785, - s__h30185, - s__h30585, - s__h30985, - s__h31385, - s__h31785, - s__h32185, - s__h32585, - s__h32985, - s__h33385, - s__h33785, - s__h34185, - s__h34585, - s__h34985, - s__h35385, - s__h35785, - s__h36185, - s__h36585, - s__h36985, - s__h37385, - s__h37785, - s__h38185, - s__h38585, - s__h38985, - s__h39385, - s__h39785, - s__h40185, - s__h40585, - s__h40985, - s__h41385, - s__h41785, - s__h42185, - s__h42585, - s__h42985, - s__h43385, - s__h43785, - s__h44185, - s__h44585, - s__h44985, - s__h45385, - s__h45785, - s__h46185, - s__h46585, - s__h46985, - s__h47385, - s__h47785, - s__h48185, - s__h48585, - sum__h25372, - sum__h25772, - sum__h26172, - sum__h26572, - sum__h26972, - sum__h27372, - sum__h27772, - sum__h28172, - sum__h28572, - sum__h28972, - sum__h29372, - sum__h29772, - sum__h30172, - sum__h30572, - sum__h30972, - sum__h31372, - sum__h31772, - sum__h32172, - sum__h32572, - sum__h32972, - sum__h33372, - sum__h33772, - sum__h34172, - sum__h34572, - sum__h34972, - sum__h35372, - sum__h35772, - sum__h36172, - sum__h36572, - sum__h36972, - sum__h37372, - sum__h37772, - sum__h38172, - sum__h38572, - sum__h38972, - sum__h39372, - sum__h39772, - sum__h40172, - sum__h40572, - sum__h40972, - sum__h41372, - sum__h41772, - sum__h42172, - sum__h42572, - sum__h42972, - sum__h43372, - sum__h43772, - sum__h44172, - sum__h44572, - sum__h44972, - sum__h45372, - sum__h45772, - sum__h46172, - sum__h46572, - sum__h46972, - sum__h47372, - sum__h47772, - sum__h48172, - sum__h48572, - x__h402; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866, - IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820; - wire [58 : 0] IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6, - _theResult___snd__h75283, - _theResult___snd__h75298, - _theResult___snd__h75300, - _theResult___snd__h75313, - _theResult___snd__h75319, - _theResult___snd__h75337, - _theResult___snd__h75342, - result__h66451, - sfdin__h75260, - x__h66665; - wire [57 : 0] sfd___1__h65692, sfd__h49936, sfd__h49938, x__h65683; - wire [53 : 0] sfd__h75932, value__h58164; - wire [51 : 0] _theResult___fst_sfd__h76510, - _theResult___sfd__h76429, - out_sfd__h76432, - sfd__h49989; - wire [12 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460, - x__h57541, - x__h57559; - wire [11 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9, - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531, - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774; - wire [10 : 0] IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, - _theResult___exp__h76428, - _theResult___fst_exp__h75266, - _theResult___fst_exp__h75269, - _theResult___fst_exp__h75289, - _theResult___fst_exp__h75305, - _theResult___fst_exp__h75344, - _theResult___fst_exp__h75350, - _theResult___fst_exp__h75353, - _theResult___fst_exp__h76509, - din_inc___2_exp__h76519, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8, - fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5, - out_exp__h76431; - wire [6 : 0] IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237, - x__h24992; - wire [5 : 0] IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458, - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772, - x__h65722; - wire [2 : 0] IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813; - wire [1 : 0] IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7, - _theResult___snd_fst__h75372, - guard__h66951, - x__h75654; - wire _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775, - int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264, - int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299, - int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649, - int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684, - int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719, - int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754, - int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789, - int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824, - int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859, - int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894, - int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929, - int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964, - int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334, - int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999, - int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034, - int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069, - int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104, - int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139, - int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174, - int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209, - int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244, - int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279, - int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314, - int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369, - int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349, - int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384, - int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419, - int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454, - int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489, - int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524, - int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559, - int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594, - int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629, - int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664, - int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404, - int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699, - int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734, - int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769, - int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804, - int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839, - int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874, - int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909, - int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944, - int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979, - int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014, - int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439, - int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049, - int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084, - int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119, - int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154, - int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189, - int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224, - int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259, - int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294, - int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474, - int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509, - int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544, - int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579, - int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614, - value_BIT_52___h58260; - // action method request_put - assign RDY_request_put = fpu_fOperand_S0$FULL_N ; - assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ; + assign RDY_request_put = fpu$RDY_request_put ; + assign CAN_FIRE_request_put = fpu$RDY_request_put ; assign WILL_FIRE_request_put = EN_request_put ; // actionvalue method response_get - assign response_get = fpu_fResult_S5$D_OUT ; - assign RDY_response_get = fpu_fResult_S5$EMPTY_N ; - assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ; + assign response_get = fpu$response_get ; + assign RDY_response_get = fpu$RDY_response_get ; + assign CAN_FIRE_response_get = fpu$RDY_response_get ; assign WILL_FIRE_response_get = EN_response_get ; - // submodule fpu_fOperand_S0 - FIFOL1 #(.width(32'd67)) fpu_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fOperand_S0$D_IN), - .ENQ(fpu_fOperand_S0$ENQ), - .DEQ(fpu_fOperand_S0$DEQ), - .CLR(fpu_fOperand_S0$CLR), - .D_OUT(fpu_fOperand_S0$D_OUT), - .FULL_N(fpu_fOperand_S0$FULL_N), - .EMPTY_N(fpu_fOperand_S0$EMPTY_N)); - - // submodule fpu_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fResult_S5$D_IN), - .ENQ(fpu_fResult_S5$ENQ), - .DEQ(fpu_fResult_S5$DEQ), - .CLR(fpu_fResult_S5$CLR), - .D_OUT(fpu_fResult_S5$D_OUT), - .FULL_N(fpu_fResult_S5$FULL_N), - .EMPTY_N(fpu_fResult_S5$EMPTY_N)); - - // submodule fpu_fState_S1 - FIFOL1 #(.width(32'd195)) fpu_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S1$D_IN), - .ENQ(fpu_fState_S1$ENQ), - .DEQ(fpu_fState_S1$DEQ), - .CLR(fpu_fState_S1$CLR), - .D_OUT(fpu_fState_S1$D_OUT), - .FULL_N(fpu_fState_S1$FULL_N), - .EMPTY_N(fpu_fState_S1$EMPTY_N)); - - // submodule fpu_fState_S2 - FIFOL1 #(.width(32'd137)) fpu_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S2$D_IN), - .ENQ(fpu_fState_S2$ENQ), - .DEQ(fpu_fState_S2$DEQ), - .CLR(fpu_fState_S2$CLR), - .D_OUT(fpu_fState_S2$D_OUT), - .FULL_N(fpu_fState_S2$FULL_N), - .EMPTY_N(fpu_fState_S2$EMPTY_N)); - - // submodule fpu_fState_S3 - FIFOL1 #(.width(32'd196)) fpu_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S3$D_IN), - .ENQ(fpu_fState_S3$ENQ), - .DEQ(fpu_fState_S3$DEQ), - .CLR(fpu_fState_S3$CLR), - .D_OUT(fpu_fState_S3$D_OUT), - .FULL_N(fpu_fState_S3$FULL_N), - .EMPTY_N(fpu_fState_S3$EMPTY_N)); - - // submodule fpu_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_fState_S4$D_IN), - .ENQ(fpu_fState_S4$ENQ), - .DEQ(fpu_fState_S4$DEQ), - .CLR(fpu_fState_S4$CLR), - .D_OUT(fpu_fState_S4$D_OUT), - .FULL_N(fpu_fState_S4$FULL_N), - .EMPTY_N(fpu_fState_S4$EMPTY_N)); - - // submodule int_sqrt_fFirst - FIFOL1 #(.width(32'd465)) int_sqrt_fFirst(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fFirst$D_IN), - .ENQ(int_sqrt_fFirst$ENQ), - .DEQ(int_sqrt_fFirst$DEQ), - .CLR(int_sqrt_fFirst$CLR), - .D_OUT(int_sqrt_fFirst$D_OUT), - .FULL_N(int_sqrt_fFirst$FULL_N), - .EMPTY_N(int_sqrt_fFirst$EMPTY_N)); - - // submodule int_sqrt_fNext_0 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_0(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_0$D_IN), - .ENQ(int_sqrt_fNext_0$ENQ), - .DEQ(int_sqrt_fNext_0$DEQ), - .CLR(int_sqrt_fNext_0$CLR), - .D_OUT(int_sqrt_fNext_0$D_OUT), - .FULL_N(int_sqrt_fNext_0$FULL_N), - .EMPTY_N(int_sqrt_fNext_0$EMPTY_N)); - - // submodule int_sqrt_fNext_1 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_1(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_1$D_IN), - .ENQ(int_sqrt_fNext_1$ENQ), - .DEQ(int_sqrt_fNext_1$DEQ), - .CLR(int_sqrt_fNext_1$CLR), - .D_OUT(int_sqrt_fNext_1$D_OUT), - .FULL_N(int_sqrt_fNext_1$FULL_N), - .EMPTY_N(int_sqrt_fNext_1$EMPTY_N)); - - // submodule int_sqrt_fNext_10 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_10(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_10$D_IN), - .ENQ(int_sqrt_fNext_10$ENQ), - .DEQ(int_sqrt_fNext_10$DEQ), - .CLR(int_sqrt_fNext_10$CLR), - .D_OUT(int_sqrt_fNext_10$D_OUT), - .FULL_N(int_sqrt_fNext_10$FULL_N), - .EMPTY_N(int_sqrt_fNext_10$EMPTY_N)); - - // submodule int_sqrt_fNext_11 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_11(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_11$D_IN), - .ENQ(int_sqrt_fNext_11$ENQ), - .DEQ(int_sqrt_fNext_11$DEQ), - .CLR(int_sqrt_fNext_11$CLR), - .D_OUT(int_sqrt_fNext_11$D_OUT), - .FULL_N(int_sqrt_fNext_11$FULL_N), - .EMPTY_N(int_sqrt_fNext_11$EMPTY_N)); - - // submodule int_sqrt_fNext_12 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_12(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_12$D_IN), - .ENQ(int_sqrt_fNext_12$ENQ), - .DEQ(int_sqrt_fNext_12$DEQ), - .CLR(int_sqrt_fNext_12$CLR), - .D_OUT(int_sqrt_fNext_12$D_OUT), - .FULL_N(int_sqrt_fNext_12$FULL_N), - .EMPTY_N(int_sqrt_fNext_12$EMPTY_N)); - - // submodule int_sqrt_fNext_13 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_13(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_13$D_IN), - .ENQ(int_sqrt_fNext_13$ENQ), - .DEQ(int_sqrt_fNext_13$DEQ), - .CLR(int_sqrt_fNext_13$CLR), - .D_OUT(int_sqrt_fNext_13$D_OUT), - .FULL_N(int_sqrt_fNext_13$FULL_N), - .EMPTY_N(int_sqrt_fNext_13$EMPTY_N)); - - // submodule int_sqrt_fNext_14 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_14(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_14$D_IN), - .ENQ(int_sqrt_fNext_14$ENQ), - .DEQ(int_sqrt_fNext_14$DEQ), - .CLR(int_sqrt_fNext_14$CLR), - .D_OUT(int_sqrt_fNext_14$D_OUT), - .FULL_N(int_sqrt_fNext_14$FULL_N), - .EMPTY_N(int_sqrt_fNext_14$EMPTY_N)); - - // submodule int_sqrt_fNext_15 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_15(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_15$D_IN), - .ENQ(int_sqrt_fNext_15$ENQ), - .DEQ(int_sqrt_fNext_15$DEQ), - .CLR(int_sqrt_fNext_15$CLR), - .D_OUT(int_sqrt_fNext_15$D_OUT), - .FULL_N(int_sqrt_fNext_15$FULL_N), - .EMPTY_N(int_sqrt_fNext_15$EMPTY_N)); - - // submodule int_sqrt_fNext_16 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_16(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_16$D_IN), - .ENQ(int_sqrt_fNext_16$ENQ), - .DEQ(int_sqrt_fNext_16$DEQ), - .CLR(int_sqrt_fNext_16$CLR), - .D_OUT(int_sqrt_fNext_16$D_OUT), - .FULL_N(int_sqrt_fNext_16$FULL_N), - .EMPTY_N(int_sqrt_fNext_16$EMPTY_N)); - - // submodule int_sqrt_fNext_17 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_17(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_17$D_IN), - .ENQ(int_sqrt_fNext_17$ENQ), - .DEQ(int_sqrt_fNext_17$DEQ), - .CLR(int_sqrt_fNext_17$CLR), - .D_OUT(int_sqrt_fNext_17$D_OUT), - .FULL_N(int_sqrt_fNext_17$FULL_N), - .EMPTY_N(int_sqrt_fNext_17$EMPTY_N)); - - // submodule int_sqrt_fNext_18 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_18(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_18$D_IN), - .ENQ(int_sqrt_fNext_18$ENQ), - .DEQ(int_sqrt_fNext_18$DEQ), - .CLR(int_sqrt_fNext_18$CLR), - .D_OUT(int_sqrt_fNext_18$D_OUT), - .FULL_N(int_sqrt_fNext_18$FULL_N), - .EMPTY_N(int_sqrt_fNext_18$EMPTY_N)); - - // submodule int_sqrt_fNext_19 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_19(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_19$D_IN), - .ENQ(int_sqrt_fNext_19$ENQ), - .DEQ(int_sqrt_fNext_19$DEQ), - .CLR(int_sqrt_fNext_19$CLR), - .D_OUT(int_sqrt_fNext_19$D_OUT), - .FULL_N(int_sqrt_fNext_19$FULL_N), - .EMPTY_N(int_sqrt_fNext_19$EMPTY_N)); - - // submodule int_sqrt_fNext_2 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_2(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_2$D_IN), - .ENQ(int_sqrt_fNext_2$ENQ), - .DEQ(int_sqrt_fNext_2$DEQ), - .CLR(int_sqrt_fNext_2$CLR), - .D_OUT(int_sqrt_fNext_2$D_OUT), - .FULL_N(int_sqrt_fNext_2$FULL_N), - .EMPTY_N(int_sqrt_fNext_2$EMPTY_N)); - - // submodule int_sqrt_fNext_20 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_20(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_20$D_IN), - .ENQ(int_sqrt_fNext_20$ENQ), - .DEQ(int_sqrt_fNext_20$DEQ), - .CLR(int_sqrt_fNext_20$CLR), - .D_OUT(int_sqrt_fNext_20$D_OUT), - .FULL_N(int_sqrt_fNext_20$FULL_N), - .EMPTY_N(int_sqrt_fNext_20$EMPTY_N)); - - // submodule int_sqrt_fNext_21 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_21(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_21$D_IN), - .ENQ(int_sqrt_fNext_21$ENQ), - .DEQ(int_sqrt_fNext_21$DEQ), - .CLR(int_sqrt_fNext_21$CLR), - .D_OUT(int_sqrt_fNext_21$D_OUT), - .FULL_N(int_sqrt_fNext_21$FULL_N), - .EMPTY_N(int_sqrt_fNext_21$EMPTY_N)); - - // submodule int_sqrt_fNext_22 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_22(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_22$D_IN), - .ENQ(int_sqrt_fNext_22$ENQ), - .DEQ(int_sqrt_fNext_22$DEQ), - .CLR(int_sqrt_fNext_22$CLR), - .D_OUT(int_sqrt_fNext_22$D_OUT), - .FULL_N(int_sqrt_fNext_22$FULL_N), - .EMPTY_N(int_sqrt_fNext_22$EMPTY_N)); - - // submodule int_sqrt_fNext_23 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_23(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_23$D_IN), - .ENQ(int_sqrt_fNext_23$ENQ), - .DEQ(int_sqrt_fNext_23$DEQ), - .CLR(int_sqrt_fNext_23$CLR), - .D_OUT(int_sqrt_fNext_23$D_OUT), - .FULL_N(int_sqrt_fNext_23$FULL_N), - .EMPTY_N(int_sqrt_fNext_23$EMPTY_N)); - - // submodule int_sqrt_fNext_24 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_24(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_24$D_IN), - .ENQ(int_sqrt_fNext_24$ENQ), - .DEQ(int_sqrt_fNext_24$DEQ), - .CLR(int_sqrt_fNext_24$CLR), - .D_OUT(int_sqrt_fNext_24$D_OUT), - .FULL_N(int_sqrt_fNext_24$FULL_N), - .EMPTY_N(int_sqrt_fNext_24$EMPTY_N)); - - // submodule int_sqrt_fNext_25 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_25(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_25$D_IN), - .ENQ(int_sqrt_fNext_25$ENQ), - .DEQ(int_sqrt_fNext_25$DEQ), - .CLR(int_sqrt_fNext_25$CLR), - .D_OUT(int_sqrt_fNext_25$D_OUT), - .FULL_N(int_sqrt_fNext_25$FULL_N), - .EMPTY_N(int_sqrt_fNext_25$EMPTY_N)); - - // submodule int_sqrt_fNext_26 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_26(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_26$D_IN), - .ENQ(int_sqrt_fNext_26$ENQ), - .DEQ(int_sqrt_fNext_26$DEQ), - .CLR(int_sqrt_fNext_26$CLR), - .D_OUT(int_sqrt_fNext_26$D_OUT), - .FULL_N(int_sqrt_fNext_26$FULL_N), - .EMPTY_N(int_sqrt_fNext_26$EMPTY_N)); - - // submodule int_sqrt_fNext_27 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_27(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_27$D_IN), - .ENQ(int_sqrt_fNext_27$ENQ), - .DEQ(int_sqrt_fNext_27$DEQ), - .CLR(int_sqrt_fNext_27$CLR), - .D_OUT(int_sqrt_fNext_27$D_OUT), - .FULL_N(int_sqrt_fNext_27$FULL_N), - .EMPTY_N(int_sqrt_fNext_27$EMPTY_N)); - - // submodule int_sqrt_fNext_28 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_28(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_28$D_IN), - .ENQ(int_sqrt_fNext_28$ENQ), - .DEQ(int_sqrt_fNext_28$DEQ), - .CLR(int_sqrt_fNext_28$CLR), - .D_OUT(int_sqrt_fNext_28$D_OUT), - .FULL_N(int_sqrt_fNext_28$FULL_N), - .EMPTY_N(int_sqrt_fNext_28$EMPTY_N)); - - // submodule int_sqrt_fNext_29 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_29(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_29$D_IN), - .ENQ(int_sqrt_fNext_29$ENQ), - .DEQ(int_sqrt_fNext_29$DEQ), - .CLR(int_sqrt_fNext_29$CLR), - .D_OUT(int_sqrt_fNext_29$D_OUT), - .FULL_N(int_sqrt_fNext_29$FULL_N), - .EMPTY_N(int_sqrt_fNext_29$EMPTY_N)); - - // submodule int_sqrt_fNext_3 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_3(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_3$D_IN), - .ENQ(int_sqrt_fNext_3$ENQ), - .DEQ(int_sqrt_fNext_3$DEQ), - .CLR(int_sqrt_fNext_3$CLR), - .D_OUT(int_sqrt_fNext_3$D_OUT), - .FULL_N(int_sqrt_fNext_3$FULL_N), - .EMPTY_N(int_sqrt_fNext_3$EMPTY_N)); - - // submodule int_sqrt_fNext_30 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_30(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_30$D_IN), - .ENQ(int_sqrt_fNext_30$ENQ), - .DEQ(int_sqrt_fNext_30$DEQ), - .CLR(int_sqrt_fNext_30$CLR), - .D_OUT(int_sqrt_fNext_30$D_OUT), - .FULL_N(int_sqrt_fNext_30$FULL_N), - .EMPTY_N(int_sqrt_fNext_30$EMPTY_N)); - - // submodule int_sqrt_fNext_31 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_31(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_31$D_IN), - .ENQ(int_sqrt_fNext_31$ENQ), - .DEQ(int_sqrt_fNext_31$DEQ), - .CLR(int_sqrt_fNext_31$CLR), - .D_OUT(int_sqrt_fNext_31$D_OUT), - .FULL_N(int_sqrt_fNext_31$FULL_N), - .EMPTY_N(int_sqrt_fNext_31$EMPTY_N)); - - // submodule int_sqrt_fNext_32 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_32(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_32$D_IN), - .ENQ(int_sqrt_fNext_32$ENQ), - .DEQ(int_sqrt_fNext_32$DEQ), - .CLR(int_sqrt_fNext_32$CLR), - .D_OUT(int_sqrt_fNext_32$D_OUT), - .FULL_N(int_sqrt_fNext_32$FULL_N), - .EMPTY_N(int_sqrt_fNext_32$EMPTY_N)); - - // submodule int_sqrt_fNext_33 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_33(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_33$D_IN), - .ENQ(int_sqrt_fNext_33$ENQ), - .DEQ(int_sqrt_fNext_33$DEQ), - .CLR(int_sqrt_fNext_33$CLR), - .D_OUT(int_sqrt_fNext_33$D_OUT), - .FULL_N(int_sqrt_fNext_33$FULL_N), - .EMPTY_N(int_sqrt_fNext_33$EMPTY_N)); - - // submodule int_sqrt_fNext_34 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_34(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_34$D_IN), - .ENQ(int_sqrt_fNext_34$ENQ), - .DEQ(int_sqrt_fNext_34$DEQ), - .CLR(int_sqrt_fNext_34$CLR), - .D_OUT(int_sqrt_fNext_34$D_OUT), - .FULL_N(int_sqrt_fNext_34$FULL_N), - .EMPTY_N(int_sqrt_fNext_34$EMPTY_N)); - - // submodule int_sqrt_fNext_35 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_35(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_35$D_IN), - .ENQ(int_sqrt_fNext_35$ENQ), - .DEQ(int_sqrt_fNext_35$DEQ), - .CLR(int_sqrt_fNext_35$CLR), - .D_OUT(int_sqrt_fNext_35$D_OUT), - .FULL_N(int_sqrt_fNext_35$FULL_N), - .EMPTY_N(int_sqrt_fNext_35$EMPTY_N)); - - // submodule int_sqrt_fNext_36 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_36(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_36$D_IN), - .ENQ(int_sqrt_fNext_36$ENQ), - .DEQ(int_sqrt_fNext_36$DEQ), - .CLR(int_sqrt_fNext_36$CLR), - .D_OUT(int_sqrt_fNext_36$D_OUT), - .FULL_N(int_sqrt_fNext_36$FULL_N), - .EMPTY_N(int_sqrt_fNext_36$EMPTY_N)); - - // submodule int_sqrt_fNext_37 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_37(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_37$D_IN), - .ENQ(int_sqrt_fNext_37$ENQ), - .DEQ(int_sqrt_fNext_37$DEQ), - .CLR(int_sqrt_fNext_37$CLR), - .D_OUT(int_sqrt_fNext_37$D_OUT), - .FULL_N(int_sqrt_fNext_37$FULL_N), - .EMPTY_N(int_sqrt_fNext_37$EMPTY_N)); - - // submodule int_sqrt_fNext_38 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_38(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_38$D_IN), - .ENQ(int_sqrt_fNext_38$ENQ), - .DEQ(int_sqrt_fNext_38$DEQ), - .CLR(int_sqrt_fNext_38$CLR), - .D_OUT(int_sqrt_fNext_38$D_OUT), - .FULL_N(int_sqrt_fNext_38$FULL_N), - .EMPTY_N(int_sqrt_fNext_38$EMPTY_N)); - - // submodule int_sqrt_fNext_39 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_39(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_39$D_IN), - .ENQ(int_sqrt_fNext_39$ENQ), - .DEQ(int_sqrt_fNext_39$DEQ), - .CLR(int_sqrt_fNext_39$CLR), - .D_OUT(int_sqrt_fNext_39$D_OUT), - .FULL_N(int_sqrt_fNext_39$FULL_N), - .EMPTY_N(int_sqrt_fNext_39$EMPTY_N)); - - // submodule int_sqrt_fNext_4 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_4(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_4$D_IN), - .ENQ(int_sqrt_fNext_4$ENQ), - .DEQ(int_sqrt_fNext_4$DEQ), - .CLR(int_sqrt_fNext_4$CLR), - .D_OUT(int_sqrt_fNext_4$D_OUT), - .FULL_N(int_sqrt_fNext_4$FULL_N), - .EMPTY_N(int_sqrt_fNext_4$EMPTY_N)); - - // submodule int_sqrt_fNext_40 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_40(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_40$D_IN), - .ENQ(int_sqrt_fNext_40$ENQ), - .DEQ(int_sqrt_fNext_40$DEQ), - .CLR(int_sqrt_fNext_40$CLR), - .D_OUT(int_sqrt_fNext_40$D_OUT), - .FULL_N(int_sqrt_fNext_40$FULL_N), - .EMPTY_N(int_sqrt_fNext_40$EMPTY_N)); - - // submodule int_sqrt_fNext_41 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_41(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_41$D_IN), - .ENQ(int_sqrt_fNext_41$ENQ), - .DEQ(int_sqrt_fNext_41$DEQ), - .CLR(int_sqrt_fNext_41$CLR), - .D_OUT(int_sqrt_fNext_41$D_OUT), - .FULL_N(int_sqrt_fNext_41$FULL_N), - .EMPTY_N(int_sqrt_fNext_41$EMPTY_N)); - - // submodule int_sqrt_fNext_42 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_42(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_42$D_IN), - .ENQ(int_sqrt_fNext_42$ENQ), - .DEQ(int_sqrt_fNext_42$DEQ), - .CLR(int_sqrt_fNext_42$CLR), - .D_OUT(int_sqrt_fNext_42$D_OUT), - .FULL_N(int_sqrt_fNext_42$FULL_N), - .EMPTY_N(int_sqrt_fNext_42$EMPTY_N)); - - // submodule int_sqrt_fNext_43 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_43(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_43$D_IN), - .ENQ(int_sqrt_fNext_43$ENQ), - .DEQ(int_sqrt_fNext_43$DEQ), - .CLR(int_sqrt_fNext_43$CLR), - .D_OUT(int_sqrt_fNext_43$D_OUT), - .FULL_N(int_sqrt_fNext_43$FULL_N), - .EMPTY_N(int_sqrt_fNext_43$EMPTY_N)); - - // submodule int_sqrt_fNext_44 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_44(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_44$D_IN), - .ENQ(int_sqrt_fNext_44$ENQ), - .DEQ(int_sqrt_fNext_44$DEQ), - .CLR(int_sqrt_fNext_44$CLR), - .D_OUT(int_sqrt_fNext_44$D_OUT), - .FULL_N(int_sqrt_fNext_44$FULL_N), - .EMPTY_N(int_sqrt_fNext_44$EMPTY_N)); - - // submodule int_sqrt_fNext_45 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_45(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_45$D_IN), - .ENQ(int_sqrt_fNext_45$ENQ), - .DEQ(int_sqrt_fNext_45$DEQ), - .CLR(int_sqrt_fNext_45$CLR), - .D_OUT(int_sqrt_fNext_45$D_OUT), - .FULL_N(int_sqrt_fNext_45$FULL_N), - .EMPTY_N(int_sqrt_fNext_45$EMPTY_N)); - - // submodule int_sqrt_fNext_46 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_46(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_46$D_IN), - .ENQ(int_sqrt_fNext_46$ENQ), - .DEQ(int_sqrt_fNext_46$DEQ), - .CLR(int_sqrt_fNext_46$CLR), - .D_OUT(int_sqrt_fNext_46$D_OUT), - .FULL_N(int_sqrt_fNext_46$FULL_N), - .EMPTY_N(int_sqrt_fNext_46$EMPTY_N)); - - // submodule int_sqrt_fNext_47 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_47(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_47$D_IN), - .ENQ(int_sqrt_fNext_47$ENQ), - .DEQ(int_sqrt_fNext_47$DEQ), - .CLR(int_sqrt_fNext_47$CLR), - .D_OUT(int_sqrt_fNext_47$D_OUT), - .FULL_N(int_sqrt_fNext_47$FULL_N), - .EMPTY_N(int_sqrt_fNext_47$EMPTY_N)); - - // submodule int_sqrt_fNext_48 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_48(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_48$D_IN), - .ENQ(int_sqrt_fNext_48$ENQ), - .DEQ(int_sqrt_fNext_48$DEQ), - .CLR(int_sqrt_fNext_48$CLR), - .D_OUT(int_sqrt_fNext_48$D_OUT), - .FULL_N(int_sqrt_fNext_48$FULL_N), - .EMPTY_N(int_sqrt_fNext_48$EMPTY_N)); - - // submodule int_sqrt_fNext_49 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_49(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_49$D_IN), - .ENQ(int_sqrt_fNext_49$ENQ), - .DEQ(int_sqrt_fNext_49$DEQ), - .CLR(int_sqrt_fNext_49$CLR), - .D_OUT(int_sqrt_fNext_49$D_OUT), - .FULL_N(int_sqrt_fNext_49$FULL_N), - .EMPTY_N(int_sqrt_fNext_49$EMPTY_N)); - - // submodule int_sqrt_fNext_5 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_5(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_5$D_IN), - .ENQ(int_sqrt_fNext_5$ENQ), - .DEQ(int_sqrt_fNext_5$DEQ), - .CLR(int_sqrt_fNext_5$CLR), - .D_OUT(int_sqrt_fNext_5$D_OUT), - .FULL_N(int_sqrt_fNext_5$FULL_N), - .EMPTY_N(int_sqrt_fNext_5$EMPTY_N)); - - // submodule int_sqrt_fNext_50 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_50(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_50$D_IN), - .ENQ(int_sqrt_fNext_50$ENQ), - .DEQ(int_sqrt_fNext_50$DEQ), - .CLR(int_sqrt_fNext_50$CLR), - .D_OUT(int_sqrt_fNext_50$D_OUT), - .FULL_N(int_sqrt_fNext_50$FULL_N), - .EMPTY_N(int_sqrt_fNext_50$EMPTY_N)); - - // submodule int_sqrt_fNext_51 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_51(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_51$D_IN), - .ENQ(int_sqrt_fNext_51$ENQ), - .DEQ(int_sqrt_fNext_51$DEQ), - .CLR(int_sqrt_fNext_51$CLR), - .D_OUT(int_sqrt_fNext_51$D_OUT), - .FULL_N(int_sqrt_fNext_51$FULL_N), - .EMPTY_N(int_sqrt_fNext_51$EMPTY_N)); - - // submodule int_sqrt_fNext_52 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_52(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_52$D_IN), - .ENQ(int_sqrt_fNext_52$ENQ), - .DEQ(int_sqrt_fNext_52$DEQ), - .CLR(int_sqrt_fNext_52$CLR), - .D_OUT(int_sqrt_fNext_52$D_OUT), - .FULL_N(int_sqrt_fNext_52$FULL_N), - .EMPTY_N(int_sqrt_fNext_52$EMPTY_N)); - - // submodule int_sqrt_fNext_53 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_53(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_53$D_IN), - .ENQ(int_sqrt_fNext_53$ENQ), - .DEQ(int_sqrt_fNext_53$DEQ), - .CLR(int_sqrt_fNext_53$CLR), - .D_OUT(int_sqrt_fNext_53$D_OUT), - .FULL_N(int_sqrt_fNext_53$FULL_N), - .EMPTY_N(int_sqrt_fNext_53$EMPTY_N)); - - // submodule int_sqrt_fNext_54 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_54(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_54$D_IN), - .ENQ(int_sqrt_fNext_54$ENQ), - .DEQ(int_sqrt_fNext_54$DEQ), - .CLR(int_sqrt_fNext_54$CLR), - .D_OUT(int_sqrt_fNext_54$D_OUT), - .FULL_N(int_sqrt_fNext_54$FULL_N), - .EMPTY_N(int_sqrt_fNext_54$EMPTY_N)); - - // submodule int_sqrt_fNext_55 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_55(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_55$D_IN), - .ENQ(int_sqrt_fNext_55$ENQ), - .DEQ(int_sqrt_fNext_55$DEQ), - .CLR(int_sqrt_fNext_55$CLR), - .D_OUT(int_sqrt_fNext_55$D_OUT), - .FULL_N(int_sqrt_fNext_55$FULL_N), - .EMPTY_N(int_sqrt_fNext_55$EMPTY_N)); - - // submodule int_sqrt_fNext_56 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_56(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_56$D_IN), - .ENQ(int_sqrt_fNext_56$ENQ), - .DEQ(int_sqrt_fNext_56$DEQ), - .CLR(int_sqrt_fNext_56$CLR), - .D_OUT(int_sqrt_fNext_56$D_OUT), - .FULL_N(int_sqrt_fNext_56$FULL_N), - .EMPTY_N(int_sqrt_fNext_56$EMPTY_N)); - - // submodule int_sqrt_fNext_57 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_57(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_57$D_IN), - .ENQ(int_sqrt_fNext_57$ENQ), - .DEQ(int_sqrt_fNext_57$DEQ), - .CLR(int_sqrt_fNext_57$CLR), - .D_OUT(int_sqrt_fNext_57$D_OUT), - .FULL_N(int_sqrt_fNext_57$FULL_N), - .EMPTY_N(int_sqrt_fNext_57$EMPTY_N)); - - // submodule int_sqrt_fNext_58 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_58(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_58$D_IN), - .ENQ(int_sqrt_fNext_58$ENQ), - .DEQ(int_sqrt_fNext_58$DEQ), - .CLR(int_sqrt_fNext_58$CLR), - .D_OUT(int_sqrt_fNext_58$D_OUT), - .FULL_N(int_sqrt_fNext_58$FULL_N), - .EMPTY_N(int_sqrt_fNext_58$EMPTY_N)); - - // submodule int_sqrt_fNext_6 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_6(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_6$D_IN), - .ENQ(int_sqrt_fNext_6$ENQ), - .DEQ(int_sqrt_fNext_6$DEQ), - .CLR(int_sqrt_fNext_6$CLR), - .D_OUT(int_sqrt_fNext_6$D_OUT), - .FULL_N(int_sqrt_fNext_6$FULL_N), - .EMPTY_N(int_sqrt_fNext_6$EMPTY_N)); - - // submodule int_sqrt_fNext_7 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_7(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_7$D_IN), - .ENQ(int_sqrt_fNext_7$ENQ), - .DEQ(int_sqrt_fNext_7$DEQ), - .CLR(int_sqrt_fNext_7$CLR), - .D_OUT(int_sqrt_fNext_7$D_OUT), - .FULL_N(int_sqrt_fNext_7$FULL_N), - .EMPTY_N(int_sqrt_fNext_7$EMPTY_N)); - - // submodule int_sqrt_fNext_8 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_8(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_8$D_IN), - .ENQ(int_sqrt_fNext_8$ENQ), - .DEQ(int_sqrt_fNext_8$DEQ), - .CLR(int_sqrt_fNext_8$CLR), - .D_OUT(int_sqrt_fNext_8$D_OUT), - .FULL_N(int_sqrt_fNext_8$FULL_N), - .EMPTY_N(int_sqrt_fNext_8$EMPTY_N)); - - // submodule int_sqrt_fNext_9 - FIFOL1 #(.width(32'd465)) int_sqrt_fNext_9(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fNext_9$D_IN), - .ENQ(int_sqrt_fNext_9$ENQ), - .DEQ(int_sqrt_fNext_9$DEQ), - .CLR(int_sqrt_fNext_9$CLR), - .D_OUT(int_sqrt_fNext_9$D_OUT), - .FULL_N(int_sqrt_fNext_9$FULL_N), - .EMPTY_N(int_sqrt_fNext_9$EMPTY_N)); - - // submodule int_sqrt_fRequest - FIFOL1 #(.width(32'd116)) int_sqrt_fRequest(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fRequest$D_IN), - .ENQ(int_sqrt_fRequest$ENQ), - .DEQ(int_sqrt_fRequest$DEQ), - .CLR(int_sqrt_fRequest$CLR), - .D_OUT(int_sqrt_fRequest$D_OUT), - .FULL_N(int_sqrt_fRequest$FULL_N), - .EMPTY_N(int_sqrt_fRequest$EMPTY_N)); - - // submodule int_sqrt_fResponse - FIFOL1 #(.width(32'd117)) int_sqrt_fResponse(.RST(RST_N), - .CLK(CLK), - .D_IN(int_sqrt_fResponse$D_IN), - .ENQ(int_sqrt_fResponse$ENQ), - .DEQ(int_sqrt_fResponse$DEQ), - .CLR(int_sqrt_fResponse$CLR), - .D_OUT(int_sqrt_fResponse$D_OUT), - .FULL_N(int_sqrt_fResponse$FULL_N), - .EMPTY_N(int_sqrt_fResponse$EMPTY_N)); - - // rule RL_fpu_s5_stage - assign CAN_FIRE_RL_fpu_s5_stage = - fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ; - - // rule RL_fpu_s4_stage - assign CAN_FIRE_RL_fpu_s4_stage = - fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ; - - // rule RL_fpu_s3_stage - assign CAN_FIRE_RL_fpu_s3_stage = - fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N && - (fpu_fState_S2$D_OUT[136] || int_sqrt_fResponse$EMPTY_N) ; - assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ; - - // rule RL_int_sqrt_finish - assign CAN_FIRE_RL_int_sqrt_finish = - int_sqrt_fNext_58$EMPTY_N && int_sqrt_fResponse$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_finish = CAN_FIRE_RL_int_sqrt_finish ; - - // rule RL_int_sqrt_work_58 - assign CAN_FIRE_RL_int_sqrt_work_58 = - int_sqrt_fNext_57$EMPTY_N && int_sqrt_fNext_58$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_58 = CAN_FIRE_RL_int_sqrt_work_58 ; - - // rule RL_int_sqrt_work_57 - assign CAN_FIRE_RL_int_sqrt_work_57 = - int_sqrt_fNext_56$EMPTY_N && int_sqrt_fNext_57$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_57 = CAN_FIRE_RL_int_sqrt_work_57 ; - - // rule RL_int_sqrt_work_56 - assign CAN_FIRE_RL_int_sqrt_work_56 = - int_sqrt_fNext_55$EMPTY_N && int_sqrt_fNext_56$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_56 = CAN_FIRE_RL_int_sqrt_work_56 ; - - // rule RL_int_sqrt_work_55 - assign CAN_FIRE_RL_int_sqrt_work_55 = - int_sqrt_fNext_54$EMPTY_N && int_sqrt_fNext_55$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_55 = CAN_FIRE_RL_int_sqrt_work_55 ; - - // rule RL_int_sqrt_work_54 - assign CAN_FIRE_RL_int_sqrt_work_54 = - int_sqrt_fNext_53$EMPTY_N && int_sqrt_fNext_54$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_54 = CAN_FIRE_RL_int_sqrt_work_54 ; - - // rule RL_int_sqrt_work_53 - assign CAN_FIRE_RL_int_sqrt_work_53 = - int_sqrt_fNext_52$EMPTY_N && int_sqrt_fNext_53$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_53 = CAN_FIRE_RL_int_sqrt_work_53 ; - - // rule RL_int_sqrt_work_52 - assign CAN_FIRE_RL_int_sqrt_work_52 = - int_sqrt_fNext_51$EMPTY_N && int_sqrt_fNext_52$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_52 = CAN_FIRE_RL_int_sqrt_work_52 ; - - // rule RL_int_sqrt_work_51 - assign CAN_FIRE_RL_int_sqrt_work_51 = - int_sqrt_fNext_50$EMPTY_N && int_sqrt_fNext_51$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_51 = CAN_FIRE_RL_int_sqrt_work_51 ; - - // rule RL_int_sqrt_work_50 - assign CAN_FIRE_RL_int_sqrt_work_50 = - int_sqrt_fNext_49$EMPTY_N && int_sqrt_fNext_50$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_50 = CAN_FIRE_RL_int_sqrt_work_50 ; - - // rule RL_int_sqrt_work_49 - assign CAN_FIRE_RL_int_sqrt_work_49 = - int_sqrt_fNext_48$EMPTY_N && int_sqrt_fNext_49$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_49 = CAN_FIRE_RL_int_sqrt_work_49 ; - - // rule RL_int_sqrt_work_48 - assign CAN_FIRE_RL_int_sqrt_work_48 = - int_sqrt_fNext_47$EMPTY_N && int_sqrt_fNext_48$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_48 = CAN_FIRE_RL_int_sqrt_work_48 ; - - // rule RL_int_sqrt_work_47 - assign CAN_FIRE_RL_int_sqrt_work_47 = - int_sqrt_fNext_46$EMPTY_N && int_sqrt_fNext_47$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_47 = CAN_FIRE_RL_int_sqrt_work_47 ; - - // rule RL_int_sqrt_work_46 - assign CAN_FIRE_RL_int_sqrt_work_46 = - int_sqrt_fNext_45$EMPTY_N && int_sqrt_fNext_46$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_46 = CAN_FIRE_RL_int_sqrt_work_46 ; - - // rule RL_int_sqrt_work_45 - assign CAN_FIRE_RL_int_sqrt_work_45 = - int_sqrt_fNext_44$EMPTY_N && int_sqrt_fNext_45$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_45 = CAN_FIRE_RL_int_sqrt_work_45 ; - - // rule RL_int_sqrt_work_44 - assign CAN_FIRE_RL_int_sqrt_work_44 = - int_sqrt_fNext_43$EMPTY_N && int_sqrt_fNext_44$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_44 = CAN_FIRE_RL_int_sqrt_work_44 ; - - // rule RL_int_sqrt_work_43 - assign CAN_FIRE_RL_int_sqrt_work_43 = - int_sqrt_fNext_42$EMPTY_N && int_sqrt_fNext_43$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_43 = CAN_FIRE_RL_int_sqrt_work_43 ; - - // rule RL_int_sqrt_work_42 - assign CAN_FIRE_RL_int_sqrt_work_42 = - int_sqrt_fNext_41$EMPTY_N && int_sqrt_fNext_42$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_42 = CAN_FIRE_RL_int_sqrt_work_42 ; - - // rule RL_int_sqrt_work_41 - assign CAN_FIRE_RL_int_sqrt_work_41 = - int_sqrt_fNext_40$EMPTY_N && int_sqrt_fNext_41$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_41 = CAN_FIRE_RL_int_sqrt_work_41 ; - - // rule RL_int_sqrt_work_40 - assign CAN_FIRE_RL_int_sqrt_work_40 = - int_sqrt_fNext_39$EMPTY_N && int_sqrt_fNext_40$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_40 = CAN_FIRE_RL_int_sqrt_work_40 ; - - // rule RL_int_sqrt_work_39 - assign CAN_FIRE_RL_int_sqrt_work_39 = - int_sqrt_fNext_38$EMPTY_N && int_sqrt_fNext_39$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_39 = CAN_FIRE_RL_int_sqrt_work_39 ; - - // rule RL_int_sqrt_work_38 - assign CAN_FIRE_RL_int_sqrt_work_38 = - int_sqrt_fNext_37$EMPTY_N && int_sqrt_fNext_38$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_38 = CAN_FIRE_RL_int_sqrt_work_38 ; - - // rule RL_int_sqrt_work_37 - assign CAN_FIRE_RL_int_sqrt_work_37 = - int_sqrt_fNext_36$EMPTY_N && int_sqrt_fNext_37$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_37 = CAN_FIRE_RL_int_sqrt_work_37 ; - - // rule RL_int_sqrt_work_36 - assign CAN_FIRE_RL_int_sqrt_work_36 = - int_sqrt_fNext_35$EMPTY_N && int_sqrt_fNext_36$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_36 = CAN_FIRE_RL_int_sqrt_work_36 ; - - // rule RL_int_sqrt_work_35 - assign CAN_FIRE_RL_int_sqrt_work_35 = - int_sqrt_fNext_34$EMPTY_N && int_sqrt_fNext_35$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_35 = CAN_FIRE_RL_int_sqrt_work_35 ; - - // rule RL_int_sqrt_work_34 - assign CAN_FIRE_RL_int_sqrt_work_34 = - int_sqrt_fNext_33$EMPTY_N && int_sqrt_fNext_34$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_34 = CAN_FIRE_RL_int_sqrt_work_34 ; - - // rule RL_int_sqrt_work_33 - assign CAN_FIRE_RL_int_sqrt_work_33 = - int_sqrt_fNext_32$EMPTY_N && int_sqrt_fNext_33$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_33 = CAN_FIRE_RL_int_sqrt_work_33 ; - - // rule RL_int_sqrt_work_32 - assign CAN_FIRE_RL_int_sqrt_work_32 = - int_sqrt_fNext_31$EMPTY_N && int_sqrt_fNext_32$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_32 = CAN_FIRE_RL_int_sqrt_work_32 ; - - // rule RL_int_sqrt_work_31 - assign CAN_FIRE_RL_int_sqrt_work_31 = - int_sqrt_fNext_30$EMPTY_N && int_sqrt_fNext_31$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_31 = CAN_FIRE_RL_int_sqrt_work_31 ; - - // rule RL_int_sqrt_work_30 - assign CAN_FIRE_RL_int_sqrt_work_30 = - int_sqrt_fNext_29$EMPTY_N && int_sqrt_fNext_30$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_30 = CAN_FIRE_RL_int_sqrt_work_30 ; - - // rule RL_int_sqrt_work_29 - assign CAN_FIRE_RL_int_sqrt_work_29 = - int_sqrt_fNext_28$EMPTY_N && int_sqrt_fNext_29$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_29 = CAN_FIRE_RL_int_sqrt_work_29 ; - - // rule RL_int_sqrt_work_28 - assign CAN_FIRE_RL_int_sqrt_work_28 = - int_sqrt_fNext_27$EMPTY_N && int_sqrt_fNext_28$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_28 = CAN_FIRE_RL_int_sqrt_work_28 ; - - // rule RL_int_sqrt_work_27 - assign CAN_FIRE_RL_int_sqrt_work_27 = - int_sqrt_fNext_26$EMPTY_N && int_sqrt_fNext_27$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_27 = CAN_FIRE_RL_int_sqrt_work_27 ; - - // rule RL_int_sqrt_work_26 - assign CAN_FIRE_RL_int_sqrt_work_26 = - int_sqrt_fNext_25$EMPTY_N && int_sqrt_fNext_26$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_26 = CAN_FIRE_RL_int_sqrt_work_26 ; - - // rule RL_int_sqrt_work_25 - assign CAN_FIRE_RL_int_sqrt_work_25 = - int_sqrt_fNext_24$EMPTY_N && int_sqrt_fNext_25$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_25 = CAN_FIRE_RL_int_sqrt_work_25 ; - - // rule RL_int_sqrt_work_24 - assign CAN_FIRE_RL_int_sqrt_work_24 = - int_sqrt_fNext_23$EMPTY_N && int_sqrt_fNext_24$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_24 = CAN_FIRE_RL_int_sqrt_work_24 ; - - // rule RL_int_sqrt_work_23 - assign CAN_FIRE_RL_int_sqrt_work_23 = - int_sqrt_fNext_22$EMPTY_N && int_sqrt_fNext_23$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_23 = CAN_FIRE_RL_int_sqrt_work_23 ; - - // rule RL_int_sqrt_work_22 - assign CAN_FIRE_RL_int_sqrt_work_22 = - int_sqrt_fNext_21$EMPTY_N && int_sqrt_fNext_22$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_22 = CAN_FIRE_RL_int_sqrt_work_22 ; - - // rule RL_int_sqrt_work_21 - assign CAN_FIRE_RL_int_sqrt_work_21 = - int_sqrt_fNext_20$EMPTY_N && int_sqrt_fNext_21$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_21 = CAN_FIRE_RL_int_sqrt_work_21 ; - - // rule RL_int_sqrt_work_20 - assign CAN_FIRE_RL_int_sqrt_work_20 = - int_sqrt_fNext_19$EMPTY_N && int_sqrt_fNext_20$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_20 = CAN_FIRE_RL_int_sqrt_work_20 ; - - // rule RL_int_sqrt_work_19 - assign CAN_FIRE_RL_int_sqrt_work_19 = - int_sqrt_fNext_18$EMPTY_N && int_sqrt_fNext_19$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_19 = CAN_FIRE_RL_int_sqrt_work_19 ; - - // rule RL_int_sqrt_work_18 - assign CAN_FIRE_RL_int_sqrt_work_18 = - int_sqrt_fNext_17$EMPTY_N && int_sqrt_fNext_18$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_18 = CAN_FIRE_RL_int_sqrt_work_18 ; - - // rule RL_int_sqrt_work_17 - assign CAN_FIRE_RL_int_sqrt_work_17 = - int_sqrt_fNext_16$EMPTY_N && int_sqrt_fNext_17$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_17 = CAN_FIRE_RL_int_sqrt_work_17 ; - - // rule RL_int_sqrt_work_16 - assign CAN_FIRE_RL_int_sqrt_work_16 = - int_sqrt_fNext_15$EMPTY_N && int_sqrt_fNext_16$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_16 = CAN_FIRE_RL_int_sqrt_work_16 ; - - // rule RL_int_sqrt_work_15 - assign CAN_FIRE_RL_int_sqrt_work_15 = - int_sqrt_fNext_14$EMPTY_N && int_sqrt_fNext_15$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_15 = CAN_FIRE_RL_int_sqrt_work_15 ; - - // rule RL_int_sqrt_work_14 - assign CAN_FIRE_RL_int_sqrt_work_14 = - int_sqrt_fNext_13$EMPTY_N && int_sqrt_fNext_14$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_14 = CAN_FIRE_RL_int_sqrt_work_14 ; - - // rule RL_int_sqrt_work_13 - assign CAN_FIRE_RL_int_sqrt_work_13 = - int_sqrt_fNext_12$EMPTY_N && int_sqrt_fNext_13$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_13 = CAN_FIRE_RL_int_sqrt_work_13 ; - - // rule RL_int_sqrt_work_12 - assign CAN_FIRE_RL_int_sqrt_work_12 = - int_sqrt_fNext_11$EMPTY_N && int_sqrt_fNext_12$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_12 = CAN_FIRE_RL_int_sqrt_work_12 ; - - // rule RL_int_sqrt_work_11 - assign CAN_FIRE_RL_int_sqrt_work_11 = - int_sqrt_fNext_10$EMPTY_N && int_sqrt_fNext_11$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_11 = CAN_FIRE_RL_int_sqrt_work_11 ; - - // rule RL_int_sqrt_work_10 - assign CAN_FIRE_RL_int_sqrt_work_10 = - int_sqrt_fNext_9$EMPTY_N && int_sqrt_fNext_10$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_10 = CAN_FIRE_RL_int_sqrt_work_10 ; - - // rule RL_int_sqrt_work_9 - assign CAN_FIRE_RL_int_sqrt_work_9 = - int_sqrt_fNext_8$EMPTY_N && int_sqrt_fNext_9$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_9 = CAN_FIRE_RL_int_sqrt_work_9 ; - - // rule RL_int_sqrt_work_8 - assign CAN_FIRE_RL_int_sqrt_work_8 = - int_sqrt_fNext_7$EMPTY_N && int_sqrt_fNext_8$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_8 = CAN_FIRE_RL_int_sqrt_work_8 ; - - // rule RL_int_sqrt_work_7 - assign CAN_FIRE_RL_int_sqrt_work_7 = - int_sqrt_fNext_6$EMPTY_N && int_sqrt_fNext_7$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_7 = CAN_FIRE_RL_int_sqrt_work_7 ; - - // rule RL_int_sqrt_work_6 - assign CAN_FIRE_RL_int_sqrt_work_6 = - int_sqrt_fNext_5$EMPTY_N && int_sqrt_fNext_6$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_6 = CAN_FIRE_RL_int_sqrt_work_6 ; - - // rule RL_int_sqrt_work_5 - assign CAN_FIRE_RL_int_sqrt_work_5 = - int_sqrt_fNext_4$EMPTY_N && int_sqrt_fNext_5$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_5 = CAN_FIRE_RL_int_sqrt_work_5 ; - - // rule RL_int_sqrt_work_4 - assign CAN_FIRE_RL_int_sqrt_work_4 = - int_sqrt_fNext_3$EMPTY_N && int_sqrt_fNext_4$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_4 = CAN_FIRE_RL_int_sqrt_work_4 ; - - // rule RL_int_sqrt_work_3 - assign CAN_FIRE_RL_int_sqrt_work_3 = - int_sqrt_fNext_2$EMPTY_N && int_sqrt_fNext_3$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_3 = CAN_FIRE_RL_int_sqrt_work_3 ; - - // rule RL_int_sqrt_work_2 - assign CAN_FIRE_RL_int_sqrt_work_2 = - int_sqrt_fNext_1$EMPTY_N && int_sqrt_fNext_2$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_2 = CAN_FIRE_RL_int_sqrt_work_2 ; - - // rule RL_int_sqrt_work_1 - assign CAN_FIRE_RL_int_sqrt_work_1 = - int_sqrt_fNext_0$EMPTY_N && int_sqrt_fNext_1$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work_1 = CAN_FIRE_RL_int_sqrt_work_1 ; - - // rule RL_int_sqrt_work - assign CAN_FIRE_RL_int_sqrt_work = - int_sqrt_fFirst$EMPTY_N && int_sqrt_fNext_0$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_work = CAN_FIRE_RL_int_sqrt_work ; - - // rule RL_int_sqrt_start - assign CAN_FIRE_RL_int_sqrt_start = - int_sqrt_fRequest$EMPTY_N && int_sqrt_fFirst$FULL_N ; - assign WILL_FIRE_RL_int_sqrt_start = CAN_FIRE_RL_int_sqrt_start ; - - // rule RL_fpu_s2_stage - assign CAN_FIRE_RL_fpu_s2_stage = - fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N && - (fpu_fState_S1$D_OUT[194] || int_sqrt_fRequest$FULL_N) ; - assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ; - - // rule RL_fpu_s1_stage - assign CAN_FIRE_RL_fpu_s1_stage = - fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ; - - // submodule fpu_fOperand_S0 - assign fpu_fOperand_S0$D_IN = request_put ; - assign fpu_fOperand_S0$ENQ = EN_request_put ; - assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_fResult_S5 - assign fpu_fResult_S5$D_IN = - fpu_fState_S4$D_OUT[138] ? - fpu_fState_S4$D_OUT[137:69] : - { (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[65:2] : - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15, - fpu_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h76509 == 11'd2047 && - _theResult___fst_sfd__h76510 == 52'd0, - 1'd0, - fpu_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fResult_S5$DEQ = EN_response_get ; - assign fpu_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_fState_S1 - assign fpu_fState_S1$D_IN = - (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_fOperand_S0$D_OUT[54]) ? - { 1'd1, - fpu_fOperand_S0$D_OUT[66:55], - sfd__h49989, - 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 ; - assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ; - assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S1$CLR = 1'b0 ; - - // submodule fpu_fState_S2 - assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[194:58] ; - assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ; - assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S2$CLR = 1'b0 ; - - // submodule fpu_fState_S3 - assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT, x__h66665 } ; - assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ; - assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S3$CLR = 1'b0 ; - - // submodule fpu_fState_S4 - assign fpu_fState_S4$D_IN = - { fpu_fState_S3$D_OUT[195:131], - fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[130], - fpu_fState_S3$D_OUT[195] && fpu_fState_S3$D_OUT[129], - IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813, - fpu_fState_S3$D_OUT[125:122], - fpu_fState_S3$D_OUT[195] ? - fpu_fState_S3$D_OUT[121:59] : - IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820, - x__h75654 } ; - assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ; - assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ; - assign fpu_fState_S4$CLR = 1'b0 ; - - // submodule int_sqrt_fFirst - assign int_sqrt_fFirst$D_IN = - { 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - int_sqrt_fRequest$D_OUT, - 116'd0, - x__h402 } ; - assign int_sqrt_fFirst$ENQ = CAN_FIRE_RL_int_sqrt_start ; - assign int_sqrt_fFirst$DEQ = CAN_FIRE_RL_int_sqrt_work ; - assign int_sqrt_fFirst$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_0 - assign int_sqrt_fNext_0$D_IN = - { int_sqrt_fFirst$D_OUT[464] || - int_sqrt_fFirst$D_OUT[115:0] == 116'd0, - int_sqrt_fFirst$D_OUT[464] ? - int_sqrt_fFirst$D_OUT[463:348] : - ((int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? - int_sqrt_fFirst$D_OUT[231:116] : - int_sqrt_fFirst$D_OUT[463:348]), - int_sqrt_fFirst$D_OUT[464] ? - int_sqrt_fFirst$D_OUT[347:0] : - { _theResult___snd_fst__h25299, - (int_sqrt_fFirst$D_OUT[115:0] == 116'd0) ? - int_sqrt_fFirst$D_OUT[231:0] : - { _theResult___snd_snd__h25377, b__h25374 } } } ; - assign int_sqrt_fNext_0$ENQ = CAN_FIRE_RL_int_sqrt_work ; - assign int_sqrt_fNext_0$DEQ = CAN_FIRE_RL_int_sqrt_work_1 ; - assign int_sqrt_fNext_0$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_1 - assign int_sqrt_fNext_1$D_IN = - { int_sqrt_fNext_0$D_OUT[464] || - int_sqrt_fNext_0$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_0$D_OUT[464] ? - int_sqrt_fNext_0$D_OUT[463:348] : - ((int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_0$D_OUT[231:116] : - int_sqrt_fNext_0$D_OUT[463:348]), - int_sqrt_fNext_0$D_OUT[464] ? - int_sqrt_fNext_0$D_OUT[347:0] : - { _theResult___snd_fst__h25701, - (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_0$D_OUT[231:0] : - { _theResult___snd_snd__h25777, b__h25774 } } } ; - assign int_sqrt_fNext_1$ENQ = CAN_FIRE_RL_int_sqrt_work_1 ; - assign int_sqrt_fNext_1$DEQ = CAN_FIRE_RL_int_sqrt_work_2 ; - assign int_sqrt_fNext_1$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_10 - assign int_sqrt_fNext_10$D_IN = - { int_sqrt_fNext_9$D_OUT[464] || - int_sqrt_fNext_9$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_9$D_OUT[464] ? - int_sqrt_fNext_9$D_OUT[463:348] : - ((int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_9$D_OUT[231:116] : - int_sqrt_fNext_9$D_OUT[463:348]), - int_sqrt_fNext_9$D_OUT[464] ? - int_sqrt_fNext_9$D_OUT[347:0] : - { _theResult___snd_fst__h29301, - (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_9$D_OUT[231:0] : - { _theResult___snd_snd__h29377, b__h29374 } } } ; - assign int_sqrt_fNext_10$ENQ = CAN_FIRE_RL_int_sqrt_work_10 ; - assign int_sqrt_fNext_10$DEQ = CAN_FIRE_RL_int_sqrt_work_11 ; - assign int_sqrt_fNext_10$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_11 - assign int_sqrt_fNext_11$D_IN = - { int_sqrt_fNext_10$D_OUT[464] || - int_sqrt_fNext_10$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_10$D_OUT[464] ? - int_sqrt_fNext_10$D_OUT[463:348] : - ((int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_10$D_OUT[231:116] : - int_sqrt_fNext_10$D_OUT[463:348]), - int_sqrt_fNext_10$D_OUT[464] ? - int_sqrt_fNext_10$D_OUT[347:0] : - { _theResult___snd_fst__h29701, - (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_10$D_OUT[231:0] : - { _theResult___snd_snd__h29777, b__h29774 } } } ; - assign int_sqrt_fNext_11$ENQ = CAN_FIRE_RL_int_sqrt_work_11 ; - assign int_sqrt_fNext_11$DEQ = CAN_FIRE_RL_int_sqrt_work_12 ; - assign int_sqrt_fNext_11$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_12 - assign int_sqrt_fNext_12$D_IN = - { int_sqrt_fNext_11$D_OUT[464] || - int_sqrt_fNext_11$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_11$D_OUT[464] ? - int_sqrt_fNext_11$D_OUT[463:348] : - ((int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_11$D_OUT[231:116] : - int_sqrt_fNext_11$D_OUT[463:348]), - int_sqrt_fNext_11$D_OUT[464] ? - int_sqrt_fNext_11$D_OUT[347:0] : - { _theResult___snd_fst__h30101, - (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_11$D_OUT[231:0] : - { _theResult___snd_snd__h30177, b__h30174 } } } ; - assign int_sqrt_fNext_12$ENQ = CAN_FIRE_RL_int_sqrt_work_12 ; - assign int_sqrt_fNext_12$DEQ = CAN_FIRE_RL_int_sqrt_work_13 ; - assign int_sqrt_fNext_12$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_13 - assign int_sqrt_fNext_13$D_IN = - { int_sqrt_fNext_12$D_OUT[464] || - int_sqrt_fNext_12$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_12$D_OUT[464] ? - int_sqrt_fNext_12$D_OUT[463:348] : - ((int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_12$D_OUT[231:116] : - int_sqrt_fNext_12$D_OUT[463:348]), - int_sqrt_fNext_12$D_OUT[464] ? - int_sqrt_fNext_12$D_OUT[347:0] : - { _theResult___snd_fst__h30501, - (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_12$D_OUT[231:0] : - { _theResult___snd_snd__h30577, b__h30574 } } } ; - assign int_sqrt_fNext_13$ENQ = CAN_FIRE_RL_int_sqrt_work_13 ; - assign int_sqrt_fNext_13$DEQ = CAN_FIRE_RL_int_sqrt_work_14 ; - assign int_sqrt_fNext_13$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_14 - assign int_sqrt_fNext_14$D_IN = - { int_sqrt_fNext_13$D_OUT[464] || - int_sqrt_fNext_13$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_13$D_OUT[464] ? - int_sqrt_fNext_13$D_OUT[463:348] : - ((int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_13$D_OUT[231:116] : - int_sqrt_fNext_13$D_OUT[463:348]), - int_sqrt_fNext_13$D_OUT[464] ? - int_sqrt_fNext_13$D_OUT[347:0] : - { _theResult___snd_fst__h30901, - (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_13$D_OUT[231:0] : - { _theResult___snd_snd__h30977, b__h30974 } } } ; - assign int_sqrt_fNext_14$ENQ = CAN_FIRE_RL_int_sqrt_work_14 ; - assign int_sqrt_fNext_14$DEQ = CAN_FIRE_RL_int_sqrt_work_15 ; - assign int_sqrt_fNext_14$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_15 - assign int_sqrt_fNext_15$D_IN = - { int_sqrt_fNext_14$D_OUT[464] || - int_sqrt_fNext_14$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_14$D_OUT[464] ? - int_sqrt_fNext_14$D_OUT[463:348] : - ((int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_14$D_OUT[231:116] : - int_sqrt_fNext_14$D_OUT[463:348]), - int_sqrt_fNext_14$D_OUT[464] ? - int_sqrt_fNext_14$D_OUT[347:0] : - { _theResult___snd_fst__h31301, - (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_14$D_OUT[231:0] : - { _theResult___snd_snd__h31377, b__h31374 } } } ; - assign int_sqrt_fNext_15$ENQ = CAN_FIRE_RL_int_sqrt_work_15 ; - assign int_sqrt_fNext_15$DEQ = CAN_FIRE_RL_int_sqrt_work_16 ; - assign int_sqrt_fNext_15$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_16 - assign int_sqrt_fNext_16$D_IN = - { int_sqrt_fNext_15$D_OUT[464] || - int_sqrt_fNext_15$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_15$D_OUT[464] ? - int_sqrt_fNext_15$D_OUT[463:348] : - ((int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_15$D_OUT[231:116] : - int_sqrt_fNext_15$D_OUT[463:348]), - int_sqrt_fNext_15$D_OUT[464] ? - int_sqrt_fNext_15$D_OUT[347:0] : - { _theResult___snd_fst__h31701, - (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_15$D_OUT[231:0] : - { _theResult___snd_snd__h31777, b__h31774 } } } ; - assign int_sqrt_fNext_16$ENQ = CAN_FIRE_RL_int_sqrt_work_16 ; - assign int_sqrt_fNext_16$DEQ = CAN_FIRE_RL_int_sqrt_work_17 ; - assign int_sqrt_fNext_16$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_17 - assign int_sqrt_fNext_17$D_IN = - { int_sqrt_fNext_16$D_OUT[464] || - int_sqrt_fNext_16$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_16$D_OUT[464] ? - int_sqrt_fNext_16$D_OUT[463:348] : - ((int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_16$D_OUT[231:116] : - int_sqrt_fNext_16$D_OUT[463:348]), - int_sqrt_fNext_16$D_OUT[464] ? - int_sqrt_fNext_16$D_OUT[347:0] : - { _theResult___snd_fst__h32101, - (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_16$D_OUT[231:0] : - { _theResult___snd_snd__h32177, b__h32174 } } } ; - assign int_sqrt_fNext_17$ENQ = CAN_FIRE_RL_int_sqrt_work_17 ; - assign int_sqrt_fNext_17$DEQ = CAN_FIRE_RL_int_sqrt_work_18 ; - assign int_sqrt_fNext_17$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_18 - assign int_sqrt_fNext_18$D_IN = - { int_sqrt_fNext_17$D_OUT[464] || - int_sqrt_fNext_17$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_17$D_OUT[464] ? - int_sqrt_fNext_17$D_OUT[463:348] : - ((int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_17$D_OUT[231:116] : - int_sqrt_fNext_17$D_OUT[463:348]), - int_sqrt_fNext_17$D_OUT[464] ? - int_sqrt_fNext_17$D_OUT[347:0] : - { _theResult___snd_fst__h32501, - (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_17$D_OUT[231:0] : - { _theResult___snd_snd__h32577, b__h32574 } } } ; - assign int_sqrt_fNext_18$ENQ = CAN_FIRE_RL_int_sqrt_work_18 ; - assign int_sqrt_fNext_18$DEQ = CAN_FIRE_RL_int_sqrt_work_19 ; - assign int_sqrt_fNext_18$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_19 - assign int_sqrt_fNext_19$D_IN = - { int_sqrt_fNext_18$D_OUT[464] || - int_sqrt_fNext_18$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_18$D_OUT[464] ? - int_sqrt_fNext_18$D_OUT[463:348] : - ((int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_18$D_OUT[231:116] : - int_sqrt_fNext_18$D_OUT[463:348]), - int_sqrt_fNext_18$D_OUT[464] ? - int_sqrt_fNext_18$D_OUT[347:0] : - { _theResult___snd_fst__h32901, - (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_18$D_OUT[231:0] : - { _theResult___snd_snd__h32977, b__h32974 } } } ; - assign int_sqrt_fNext_19$ENQ = CAN_FIRE_RL_int_sqrt_work_19 ; - assign int_sqrt_fNext_19$DEQ = CAN_FIRE_RL_int_sqrt_work_20 ; - assign int_sqrt_fNext_19$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_2 - assign int_sqrt_fNext_2$D_IN = - { int_sqrt_fNext_1$D_OUT[464] || - int_sqrt_fNext_1$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_1$D_OUT[464] ? - int_sqrt_fNext_1$D_OUT[463:348] : - ((int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_1$D_OUT[231:116] : - int_sqrt_fNext_1$D_OUT[463:348]), - int_sqrt_fNext_1$D_OUT[464] ? - int_sqrt_fNext_1$D_OUT[347:0] : - { _theResult___snd_fst__h26101, - (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_1$D_OUT[231:0] : - { _theResult___snd_snd__h26177, b__h26174 } } } ; - assign int_sqrt_fNext_2$ENQ = CAN_FIRE_RL_int_sqrt_work_2 ; - assign int_sqrt_fNext_2$DEQ = CAN_FIRE_RL_int_sqrt_work_3 ; - assign int_sqrt_fNext_2$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_20 - assign int_sqrt_fNext_20$D_IN = - { int_sqrt_fNext_19$D_OUT[464] || - int_sqrt_fNext_19$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_19$D_OUT[464] ? - int_sqrt_fNext_19$D_OUT[463:348] : - ((int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_19$D_OUT[231:116] : - int_sqrt_fNext_19$D_OUT[463:348]), - int_sqrt_fNext_19$D_OUT[464] ? - int_sqrt_fNext_19$D_OUT[347:0] : - { _theResult___snd_fst__h33301, - (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_19$D_OUT[231:0] : - { _theResult___snd_snd__h33377, b__h33374 } } } ; - assign int_sqrt_fNext_20$ENQ = CAN_FIRE_RL_int_sqrt_work_20 ; - assign int_sqrt_fNext_20$DEQ = CAN_FIRE_RL_int_sqrt_work_21 ; - assign int_sqrt_fNext_20$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_21 - assign int_sqrt_fNext_21$D_IN = - { int_sqrt_fNext_20$D_OUT[464] || - int_sqrt_fNext_20$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_20$D_OUT[464] ? - int_sqrt_fNext_20$D_OUT[463:348] : - ((int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_20$D_OUT[231:116] : - int_sqrt_fNext_20$D_OUT[463:348]), - int_sqrt_fNext_20$D_OUT[464] ? - int_sqrt_fNext_20$D_OUT[347:0] : - { _theResult___snd_fst__h33701, - (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_20$D_OUT[231:0] : - { _theResult___snd_snd__h33777, b__h33774 } } } ; - assign int_sqrt_fNext_21$ENQ = CAN_FIRE_RL_int_sqrt_work_21 ; - assign int_sqrt_fNext_21$DEQ = CAN_FIRE_RL_int_sqrt_work_22 ; - assign int_sqrt_fNext_21$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_22 - assign int_sqrt_fNext_22$D_IN = - { int_sqrt_fNext_21$D_OUT[464] || - int_sqrt_fNext_21$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_21$D_OUT[464] ? - int_sqrt_fNext_21$D_OUT[463:348] : - ((int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_21$D_OUT[231:116] : - int_sqrt_fNext_21$D_OUT[463:348]), - int_sqrt_fNext_21$D_OUT[464] ? - int_sqrt_fNext_21$D_OUT[347:0] : - { _theResult___snd_fst__h34101, - (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_21$D_OUT[231:0] : - { _theResult___snd_snd__h34177, b__h34174 } } } ; - assign int_sqrt_fNext_22$ENQ = CAN_FIRE_RL_int_sqrt_work_22 ; - assign int_sqrt_fNext_22$DEQ = CAN_FIRE_RL_int_sqrt_work_23 ; - assign int_sqrt_fNext_22$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_23 - assign int_sqrt_fNext_23$D_IN = - { int_sqrt_fNext_22$D_OUT[464] || - int_sqrt_fNext_22$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_22$D_OUT[464] ? - int_sqrt_fNext_22$D_OUT[463:348] : - ((int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_22$D_OUT[231:116] : - int_sqrt_fNext_22$D_OUT[463:348]), - int_sqrt_fNext_22$D_OUT[464] ? - int_sqrt_fNext_22$D_OUT[347:0] : - { _theResult___snd_fst__h34501, - (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_22$D_OUT[231:0] : - { _theResult___snd_snd__h34577, b__h34574 } } } ; - assign int_sqrt_fNext_23$ENQ = CAN_FIRE_RL_int_sqrt_work_23 ; - assign int_sqrt_fNext_23$DEQ = CAN_FIRE_RL_int_sqrt_work_24 ; - assign int_sqrt_fNext_23$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_24 - assign int_sqrt_fNext_24$D_IN = - { int_sqrt_fNext_23$D_OUT[464] || - int_sqrt_fNext_23$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_23$D_OUT[464] ? - int_sqrt_fNext_23$D_OUT[463:348] : - ((int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_23$D_OUT[231:116] : - int_sqrt_fNext_23$D_OUT[463:348]), - int_sqrt_fNext_23$D_OUT[464] ? - int_sqrt_fNext_23$D_OUT[347:0] : - { _theResult___snd_fst__h34901, - (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_23$D_OUT[231:0] : - { _theResult___snd_snd__h34977, b__h34974 } } } ; - assign int_sqrt_fNext_24$ENQ = CAN_FIRE_RL_int_sqrt_work_24 ; - assign int_sqrt_fNext_24$DEQ = CAN_FIRE_RL_int_sqrt_work_25 ; - assign int_sqrt_fNext_24$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_25 - assign int_sqrt_fNext_25$D_IN = - { int_sqrt_fNext_24$D_OUT[464] || - int_sqrt_fNext_24$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_24$D_OUT[464] ? - int_sqrt_fNext_24$D_OUT[463:348] : - ((int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_24$D_OUT[231:116] : - int_sqrt_fNext_24$D_OUT[463:348]), - int_sqrt_fNext_24$D_OUT[464] ? - int_sqrt_fNext_24$D_OUT[347:0] : - { _theResult___snd_fst__h35301, - (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_24$D_OUT[231:0] : - { _theResult___snd_snd__h35377, b__h35374 } } } ; - assign int_sqrt_fNext_25$ENQ = CAN_FIRE_RL_int_sqrt_work_25 ; - assign int_sqrt_fNext_25$DEQ = CAN_FIRE_RL_int_sqrt_work_26 ; - assign int_sqrt_fNext_25$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_26 - assign int_sqrt_fNext_26$D_IN = - { int_sqrt_fNext_25$D_OUT[464] || - int_sqrt_fNext_25$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_25$D_OUT[464] ? - int_sqrt_fNext_25$D_OUT[463:348] : - ((int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_25$D_OUT[231:116] : - int_sqrt_fNext_25$D_OUT[463:348]), - int_sqrt_fNext_25$D_OUT[464] ? - int_sqrt_fNext_25$D_OUT[347:0] : - { _theResult___snd_fst__h35701, - (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_25$D_OUT[231:0] : - { _theResult___snd_snd__h35777, b__h35774 } } } ; - assign int_sqrt_fNext_26$ENQ = CAN_FIRE_RL_int_sqrt_work_26 ; - assign int_sqrt_fNext_26$DEQ = CAN_FIRE_RL_int_sqrt_work_27 ; - assign int_sqrt_fNext_26$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_27 - assign int_sqrt_fNext_27$D_IN = - { int_sqrt_fNext_26$D_OUT[464] || - int_sqrt_fNext_26$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_26$D_OUT[464] ? - int_sqrt_fNext_26$D_OUT[463:348] : - ((int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_26$D_OUT[231:116] : - int_sqrt_fNext_26$D_OUT[463:348]), - int_sqrt_fNext_26$D_OUT[464] ? - int_sqrt_fNext_26$D_OUT[347:0] : - { _theResult___snd_fst__h36101, - (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_26$D_OUT[231:0] : - { _theResult___snd_snd__h36177, b__h36174 } } } ; - assign int_sqrt_fNext_27$ENQ = CAN_FIRE_RL_int_sqrt_work_27 ; - assign int_sqrt_fNext_27$DEQ = CAN_FIRE_RL_int_sqrt_work_28 ; - assign int_sqrt_fNext_27$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_28 - assign int_sqrt_fNext_28$D_IN = - { int_sqrt_fNext_27$D_OUT[464] || - int_sqrt_fNext_27$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_27$D_OUT[464] ? - int_sqrt_fNext_27$D_OUT[463:348] : - ((int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_27$D_OUT[231:116] : - int_sqrt_fNext_27$D_OUT[463:348]), - int_sqrt_fNext_27$D_OUT[464] ? - int_sqrt_fNext_27$D_OUT[347:0] : - { _theResult___snd_fst__h36501, - (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_27$D_OUT[231:0] : - { _theResult___snd_snd__h36577, b__h36574 } } } ; - assign int_sqrt_fNext_28$ENQ = CAN_FIRE_RL_int_sqrt_work_28 ; - assign int_sqrt_fNext_28$DEQ = CAN_FIRE_RL_int_sqrt_work_29 ; - assign int_sqrt_fNext_28$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_29 - assign int_sqrt_fNext_29$D_IN = - { int_sqrt_fNext_28$D_OUT[464] || - int_sqrt_fNext_28$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_28$D_OUT[464] ? - int_sqrt_fNext_28$D_OUT[463:348] : - ((int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_28$D_OUT[231:116] : - int_sqrt_fNext_28$D_OUT[463:348]), - int_sqrt_fNext_28$D_OUT[464] ? - int_sqrt_fNext_28$D_OUT[347:0] : - { _theResult___snd_fst__h36901, - (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_28$D_OUT[231:0] : - { _theResult___snd_snd__h36977, b__h36974 } } } ; - assign int_sqrt_fNext_29$ENQ = CAN_FIRE_RL_int_sqrt_work_29 ; - assign int_sqrt_fNext_29$DEQ = CAN_FIRE_RL_int_sqrt_work_30 ; - assign int_sqrt_fNext_29$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_3 - assign int_sqrt_fNext_3$D_IN = - { int_sqrt_fNext_2$D_OUT[464] || - int_sqrt_fNext_2$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_2$D_OUT[464] ? - int_sqrt_fNext_2$D_OUT[463:348] : - ((int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_2$D_OUT[231:116] : - int_sqrt_fNext_2$D_OUT[463:348]), - int_sqrt_fNext_2$D_OUT[464] ? - int_sqrt_fNext_2$D_OUT[347:0] : - { _theResult___snd_fst__h26501, - (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_2$D_OUT[231:0] : - { _theResult___snd_snd__h26577, b__h26574 } } } ; - assign int_sqrt_fNext_3$ENQ = CAN_FIRE_RL_int_sqrt_work_3 ; - assign int_sqrt_fNext_3$DEQ = CAN_FIRE_RL_int_sqrt_work_4 ; - assign int_sqrt_fNext_3$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_30 - assign int_sqrt_fNext_30$D_IN = - { int_sqrt_fNext_29$D_OUT[464] || - int_sqrt_fNext_29$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_29$D_OUT[464] ? - int_sqrt_fNext_29$D_OUT[463:348] : - ((int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_29$D_OUT[231:116] : - int_sqrt_fNext_29$D_OUT[463:348]), - int_sqrt_fNext_29$D_OUT[464] ? - int_sqrt_fNext_29$D_OUT[347:0] : - { _theResult___snd_fst__h37301, - (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_29$D_OUT[231:0] : - { _theResult___snd_snd__h37377, b__h37374 } } } ; - assign int_sqrt_fNext_30$ENQ = CAN_FIRE_RL_int_sqrt_work_30 ; - assign int_sqrt_fNext_30$DEQ = CAN_FIRE_RL_int_sqrt_work_31 ; - assign int_sqrt_fNext_30$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_31 - assign int_sqrt_fNext_31$D_IN = - { int_sqrt_fNext_30$D_OUT[464] || - int_sqrt_fNext_30$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_30$D_OUT[464] ? - int_sqrt_fNext_30$D_OUT[463:348] : - ((int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_30$D_OUT[231:116] : - int_sqrt_fNext_30$D_OUT[463:348]), - int_sqrt_fNext_30$D_OUT[464] ? - int_sqrt_fNext_30$D_OUT[347:0] : - { _theResult___snd_fst__h37701, - (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_30$D_OUT[231:0] : - { _theResult___snd_snd__h37777, b__h37774 } } } ; - assign int_sqrt_fNext_31$ENQ = CAN_FIRE_RL_int_sqrt_work_31 ; - assign int_sqrt_fNext_31$DEQ = CAN_FIRE_RL_int_sqrt_work_32 ; - assign int_sqrt_fNext_31$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_32 - assign int_sqrt_fNext_32$D_IN = - { int_sqrt_fNext_31$D_OUT[464] || - int_sqrt_fNext_31$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_31$D_OUT[464] ? - int_sqrt_fNext_31$D_OUT[463:348] : - ((int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_31$D_OUT[231:116] : - int_sqrt_fNext_31$D_OUT[463:348]), - int_sqrt_fNext_31$D_OUT[464] ? - int_sqrt_fNext_31$D_OUT[347:0] : - { _theResult___snd_fst__h38101, - (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_31$D_OUT[231:0] : - { _theResult___snd_snd__h38177, b__h38174 } } } ; - assign int_sqrt_fNext_32$ENQ = CAN_FIRE_RL_int_sqrt_work_32 ; - assign int_sqrt_fNext_32$DEQ = CAN_FIRE_RL_int_sqrt_work_33 ; - assign int_sqrt_fNext_32$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_33 - assign int_sqrt_fNext_33$D_IN = - { int_sqrt_fNext_32$D_OUT[464] || - int_sqrt_fNext_32$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_32$D_OUT[464] ? - int_sqrt_fNext_32$D_OUT[463:348] : - ((int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_32$D_OUT[231:116] : - int_sqrt_fNext_32$D_OUT[463:348]), - int_sqrt_fNext_32$D_OUT[464] ? - int_sqrt_fNext_32$D_OUT[347:0] : - { _theResult___snd_fst__h38501, - (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_32$D_OUT[231:0] : - { _theResult___snd_snd__h38577, b__h38574 } } } ; - assign int_sqrt_fNext_33$ENQ = CAN_FIRE_RL_int_sqrt_work_33 ; - assign int_sqrt_fNext_33$DEQ = CAN_FIRE_RL_int_sqrt_work_34 ; - assign int_sqrt_fNext_33$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_34 - assign int_sqrt_fNext_34$D_IN = - { int_sqrt_fNext_33$D_OUT[464] || - int_sqrt_fNext_33$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_33$D_OUT[464] ? - int_sqrt_fNext_33$D_OUT[463:348] : - ((int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_33$D_OUT[231:116] : - int_sqrt_fNext_33$D_OUT[463:348]), - int_sqrt_fNext_33$D_OUT[464] ? - int_sqrt_fNext_33$D_OUT[347:0] : - { _theResult___snd_fst__h38901, - (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_33$D_OUT[231:0] : - { _theResult___snd_snd__h38977, b__h38974 } } } ; - assign int_sqrt_fNext_34$ENQ = CAN_FIRE_RL_int_sqrt_work_34 ; - assign int_sqrt_fNext_34$DEQ = CAN_FIRE_RL_int_sqrt_work_35 ; - assign int_sqrt_fNext_34$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_35 - assign int_sqrt_fNext_35$D_IN = - { int_sqrt_fNext_34$D_OUT[464] || - int_sqrt_fNext_34$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_34$D_OUT[464] ? - int_sqrt_fNext_34$D_OUT[463:348] : - ((int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_34$D_OUT[231:116] : - int_sqrt_fNext_34$D_OUT[463:348]), - int_sqrt_fNext_34$D_OUT[464] ? - int_sqrt_fNext_34$D_OUT[347:0] : - { _theResult___snd_fst__h39301, - (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_34$D_OUT[231:0] : - { _theResult___snd_snd__h39377, b__h39374 } } } ; - assign int_sqrt_fNext_35$ENQ = CAN_FIRE_RL_int_sqrt_work_35 ; - assign int_sqrt_fNext_35$DEQ = CAN_FIRE_RL_int_sqrt_work_36 ; - assign int_sqrt_fNext_35$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_36 - assign int_sqrt_fNext_36$D_IN = - { int_sqrt_fNext_35$D_OUT[464] || - int_sqrt_fNext_35$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_35$D_OUT[464] ? - int_sqrt_fNext_35$D_OUT[463:348] : - ((int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_35$D_OUT[231:116] : - int_sqrt_fNext_35$D_OUT[463:348]), - int_sqrt_fNext_35$D_OUT[464] ? - int_sqrt_fNext_35$D_OUT[347:0] : - { _theResult___snd_fst__h39701, - (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_35$D_OUT[231:0] : - { _theResult___snd_snd__h39777, b__h39774 } } } ; - assign int_sqrt_fNext_36$ENQ = CAN_FIRE_RL_int_sqrt_work_36 ; - assign int_sqrt_fNext_36$DEQ = CAN_FIRE_RL_int_sqrt_work_37 ; - assign int_sqrt_fNext_36$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_37 - assign int_sqrt_fNext_37$D_IN = - { int_sqrt_fNext_36$D_OUT[464] || - int_sqrt_fNext_36$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_36$D_OUT[464] ? - int_sqrt_fNext_36$D_OUT[463:348] : - ((int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_36$D_OUT[231:116] : - int_sqrt_fNext_36$D_OUT[463:348]), - int_sqrt_fNext_36$D_OUT[464] ? - int_sqrt_fNext_36$D_OUT[347:0] : - { _theResult___snd_fst__h40101, - (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_36$D_OUT[231:0] : - { _theResult___snd_snd__h40177, b__h40174 } } } ; - assign int_sqrt_fNext_37$ENQ = CAN_FIRE_RL_int_sqrt_work_37 ; - assign int_sqrt_fNext_37$DEQ = CAN_FIRE_RL_int_sqrt_work_38 ; - assign int_sqrt_fNext_37$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_38 - assign int_sqrt_fNext_38$D_IN = - { int_sqrt_fNext_37$D_OUT[464] || - int_sqrt_fNext_37$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_37$D_OUT[464] ? - int_sqrt_fNext_37$D_OUT[463:348] : - ((int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_37$D_OUT[231:116] : - int_sqrt_fNext_37$D_OUT[463:348]), - int_sqrt_fNext_37$D_OUT[464] ? - int_sqrt_fNext_37$D_OUT[347:0] : - { _theResult___snd_fst__h40501, - (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_37$D_OUT[231:0] : - { _theResult___snd_snd__h40577, b__h40574 } } } ; - assign int_sqrt_fNext_38$ENQ = CAN_FIRE_RL_int_sqrt_work_38 ; - assign int_sqrt_fNext_38$DEQ = CAN_FIRE_RL_int_sqrt_work_39 ; - assign int_sqrt_fNext_38$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_39 - assign int_sqrt_fNext_39$D_IN = - { int_sqrt_fNext_38$D_OUT[464] || - int_sqrt_fNext_38$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_38$D_OUT[464] ? - int_sqrt_fNext_38$D_OUT[463:348] : - ((int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_38$D_OUT[231:116] : - int_sqrt_fNext_38$D_OUT[463:348]), - int_sqrt_fNext_38$D_OUT[464] ? - int_sqrt_fNext_38$D_OUT[347:0] : - { _theResult___snd_fst__h40901, - (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_38$D_OUT[231:0] : - { _theResult___snd_snd__h40977, b__h40974 } } } ; - assign int_sqrt_fNext_39$ENQ = CAN_FIRE_RL_int_sqrt_work_39 ; - assign int_sqrt_fNext_39$DEQ = CAN_FIRE_RL_int_sqrt_work_40 ; - assign int_sqrt_fNext_39$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_4 - assign int_sqrt_fNext_4$D_IN = - { int_sqrt_fNext_3$D_OUT[464] || - int_sqrt_fNext_3$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_3$D_OUT[464] ? - int_sqrt_fNext_3$D_OUT[463:348] : - ((int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_3$D_OUT[231:116] : - int_sqrt_fNext_3$D_OUT[463:348]), - int_sqrt_fNext_3$D_OUT[464] ? - int_sqrt_fNext_3$D_OUT[347:0] : - { _theResult___snd_fst__h26901, - (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_3$D_OUT[231:0] : - { _theResult___snd_snd__h26977, b__h26974 } } } ; - assign int_sqrt_fNext_4$ENQ = CAN_FIRE_RL_int_sqrt_work_4 ; - assign int_sqrt_fNext_4$DEQ = CAN_FIRE_RL_int_sqrt_work_5 ; - assign int_sqrt_fNext_4$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_40 - assign int_sqrt_fNext_40$D_IN = - { int_sqrt_fNext_39$D_OUT[464] || - int_sqrt_fNext_39$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_39$D_OUT[464] ? - int_sqrt_fNext_39$D_OUT[463:348] : - ((int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_39$D_OUT[231:116] : - int_sqrt_fNext_39$D_OUT[463:348]), - int_sqrt_fNext_39$D_OUT[464] ? - int_sqrt_fNext_39$D_OUT[347:0] : - { _theResult___snd_fst__h41301, - (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_39$D_OUT[231:0] : - { _theResult___snd_snd__h41377, b__h41374 } } } ; - assign int_sqrt_fNext_40$ENQ = CAN_FIRE_RL_int_sqrt_work_40 ; - assign int_sqrt_fNext_40$DEQ = CAN_FIRE_RL_int_sqrt_work_41 ; - assign int_sqrt_fNext_40$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_41 - assign int_sqrt_fNext_41$D_IN = - { int_sqrt_fNext_40$D_OUT[464] || - int_sqrt_fNext_40$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_40$D_OUT[464] ? - int_sqrt_fNext_40$D_OUT[463:348] : - ((int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_40$D_OUT[231:116] : - int_sqrt_fNext_40$D_OUT[463:348]), - int_sqrt_fNext_40$D_OUT[464] ? - int_sqrt_fNext_40$D_OUT[347:0] : - { _theResult___snd_fst__h41701, - (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_40$D_OUT[231:0] : - { _theResult___snd_snd__h41777, b__h41774 } } } ; - assign int_sqrt_fNext_41$ENQ = CAN_FIRE_RL_int_sqrt_work_41 ; - assign int_sqrt_fNext_41$DEQ = CAN_FIRE_RL_int_sqrt_work_42 ; - assign int_sqrt_fNext_41$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_42 - assign int_sqrt_fNext_42$D_IN = - { int_sqrt_fNext_41$D_OUT[464] || - int_sqrt_fNext_41$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_41$D_OUT[464] ? - int_sqrt_fNext_41$D_OUT[463:348] : - ((int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_41$D_OUT[231:116] : - int_sqrt_fNext_41$D_OUT[463:348]), - int_sqrt_fNext_41$D_OUT[464] ? - int_sqrt_fNext_41$D_OUT[347:0] : - { _theResult___snd_fst__h42101, - (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_41$D_OUT[231:0] : - { _theResult___snd_snd__h42177, b__h42174 } } } ; - assign int_sqrt_fNext_42$ENQ = CAN_FIRE_RL_int_sqrt_work_42 ; - assign int_sqrt_fNext_42$DEQ = CAN_FIRE_RL_int_sqrt_work_43 ; - assign int_sqrt_fNext_42$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_43 - assign int_sqrt_fNext_43$D_IN = - { int_sqrt_fNext_42$D_OUT[464] || - int_sqrt_fNext_42$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_42$D_OUT[464] ? - int_sqrt_fNext_42$D_OUT[463:348] : - ((int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_42$D_OUT[231:116] : - int_sqrt_fNext_42$D_OUT[463:348]), - int_sqrt_fNext_42$D_OUT[464] ? - int_sqrt_fNext_42$D_OUT[347:0] : - { _theResult___snd_fst__h42501, - (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_42$D_OUT[231:0] : - { _theResult___snd_snd__h42577, b__h42574 } } } ; - assign int_sqrt_fNext_43$ENQ = CAN_FIRE_RL_int_sqrt_work_43 ; - assign int_sqrt_fNext_43$DEQ = CAN_FIRE_RL_int_sqrt_work_44 ; - assign int_sqrt_fNext_43$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_44 - assign int_sqrt_fNext_44$D_IN = - { int_sqrt_fNext_43$D_OUT[464] || - int_sqrt_fNext_43$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_43$D_OUT[464] ? - int_sqrt_fNext_43$D_OUT[463:348] : - ((int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_43$D_OUT[231:116] : - int_sqrt_fNext_43$D_OUT[463:348]), - int_sqrt_fNext_43$D_OUT[464] ? - int_sqrt_fNext_43$D_OUT[347:0] : - { _theResult___snd_fst__h42901, - (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_43$D_OUT[231:0] : - { _theResult___snd_snd__h42977, b__h42974 } } } ; - assign int_sqrt_fNext_44$ENQ = CAN_FIRE_RL_int_sqrt_work_44 ; - assign int_sqrt_fNext_44$DEQ = CAN_FIRE_RL_int_sqrt_work_45 ; - assign int_sqrt_fNext_44$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_45 - assign int_sqrt_fNext_45$D_IN = - { int_sqrt_fNext_44$D_OUT[464] || - int_sqrt_fNext_44$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_44$D_OUT[464] ? - int_sqrt_fNext_44$D_OUT[463:348] : - ((int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_44$D_OUT[231:116] : - int_sqrt_fNext_44$D_OUT[463:348]), - int_sqrt_fNext_44$D_OUT[464] ? - int_sqrt_fNext_44$D_OUT[347:0] : - { _theResult___snd_fst__h43301, - (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_44$D_OUT[231:0] : - { _theResult___snd_snd__h43377, b__h43374 } } } ; - assign int_sqrt_fNext_45$ENQ = CAN_FIRE_RL_int_sqrt_work_45 ; - assign int_sqrt_fNext_45$DEQ = CAN_FIRE_RL_int_sqrt_work_46 ; - assign int_sqrt_fNext_45$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_46 - assign int_sqrt_fNext_46$D_IN = - { int_sqrt_fNext_45$D_OUT[464] || - int_sqrt_fNext_45$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_45$D_OUT[464] ? - int_sqrt_fNext_45$D_OUT[463:348] : - ((int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_45$D_OUT[231:116] : - int_sqrt_fNext_45$D_OUT[463:348]), - int_sqrt_fNext_45$D_OUT[464] ? - int_sqrt_fNext_45$D_OUT[347:0] : - { _theResult___snd_fst__h43701, - (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_45$D_OUT[231:0] : - { _theResult___snd_snd__h43777, b__h43774 } } } ; - assign int_sqrt_fNext_46$ENQ = CAN_FIRE_RL_int_sqrt_work_46 ; - assign int_sqrt_fNext_46$DEQ = CAN_FIRE_RL_int_sqrt_work_47 ; - assign int_sqrt_fNext_46$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_47 - assign int_sqrt_fNext_47$D_IN = - { int_sqrt_fNext_46$D_OUT[464] || - int_sqrt_fNext_46$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_46$D_OUT[464] ? - int_sqrt_fNext_46$D_OUT[463:348] : - ((int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_46$D_OUT[231:116] : - int_sqrt_fNext_46$D_OUT[463:348]), - int_sqrt_fNext_46$D_OUT[464] ? - int_sqrt_fNext_46$D_OUT[347:0] : - { _theResult___snd_fst__h44101, - (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_46$D_OUT[231:0] : - { _theResult___snd_snd__h44177, b__h44174 } } } ; - assign int_sqrt_fNext_47$ENQ = CAN_FIRE_RL_int_sqrt_work_47 ; - assign int_sqrt_fNext_47$DEQ = CAN_FIRE_RL_int_sqrt_work_48 ; - assign int_sqrt_fNext_47$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_48 - assign int_sqrt_fNext_48$D_IN = - { int_sqrt_fNext_47$D_OUT[464] || - int_sqrt_fNext_47$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_47$D_OUT[464] ? - int_sqrt_fNext_47$D_OUT[463:348] : - ((int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_47$D_OUT[231:116] : - int_sqrt_fNext_47$D_OUT[463:348]), - int_sqrt_fNext_47$D_OUT[464] ? - int_sqrt_fNext_47$D_OUT[347:0] : - { _theResult___snd_fst__h44501, - (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_47$D_OUT[231:0] : - { _theResult___snd_snd__h44577, b__h44574 } } } ; - assign int_sqrt_fNext_48$ENQ = CAN_FIRE_RL_int_sqrt_work_48 ; - assign int_sqrt_fNext_48$DEQ = CAN_FIRE_RL_int_sqrt_work_49 ; - assign int_sqrt_fNext_48$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_49 - assign int_sqrt_fNext_49$D_IN = - { int_sqrt_fNext_48$D_OUT[464] || - int_sqrt_fNext_48$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_48$D_OUT[464] ? - int_sqrt_fNext_48$D_OUT[463:348] : - ((int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_48$D_OUT[231:116] : - int_sqrt_fNext_48$D_OUT[463:348]), - int_sqrt_fNext_48$D_OUT[464] ? - int_sqrt_fNext_48$D_OUT[347:0] : - { _theResult___snd_fst__h44901, - (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_48$D_OUT[231:0] : - { _theResult___snd_snd__h44977, b__h44974 } } } ; - assign int_sqrt_fNext_49$ENQ = CAN_FIRE_RL_int_sqrt_work_49 ; - assign int_sqrt_fNext_49$DEQ = CAN_FIRE_RL_int_sqrt_work_50 ; - assign int_sqrt_fNext_49$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_5 - assign int_sqrt_fNext_5$D_IN = - { int_sqrt_fNext_4$D_OUT[464] || - int_sqrt_fNext_4$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_4$D_OUT[464] ? - int_sqrt_fNext_4$D_OUT[463:348] : - ((int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_4$D_OUT[231:116] : - int_sqrt_fNext_4$D_OUT[463:348]), - int_sqrt_fNext_4$D_OUT[464] ? - int_sqrt_fNext_4$D_OUT[347:0] : - { _theResult___snd_fst__h27301, - (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_4$D_OUT[231:0] : - { _theResult___snd_snd__h27377, b__h27374 } } } ; - assign int_sqrt_fNext_5$ENQ = CAN_FIRE_RL_int_sqrt_work_5 ; - assign int_sqrt_fNext_5$DEQ = CAN_FIRE_RL_int_sqrt_work_6 ; - assign int_sqrt_fNext_5$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_50 - assign int_sqrt_fNext_50$D_IN = - { int_sqrt_fNext_49$D_OUT[464] || - int_sqrt_fNext_49$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_49$D_OUT[464] ? - int_sqrt_fNext_49$D_OUT[463:348] : - ((int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_49$D_OUT[231:116] : - int_sqrt_fNext_49$D_OUT[463:348]), - int_sqrt_fNext_49$D_OUT[464] ? - int_sqrt_fNext_49$D_OUT[347:0] : - { _theResult___snd_fst__h45301, - (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_49$D_OUT[231:0] : - { _theResult___snd_snd__h45377, b__h45374 } } } ; - assign int_sqrt_fNext_50$ENQ = CAN_FIRE_RL_int_sqrt_work_50 ; - assign int_sqrt_fNext_50$DEQ = CAN_FIRE_RL_int_sqrt_work_51 ; - assign int_sqrt_fNext_50$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_51 - assign int_sqrt_fNext_51$D_IN = - { int_sqrt_fNext_50$D_OUT[464] || - int_sqrt_fNext_50$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_50$D_OUT[464] ? - int_sqrt_fNext_50$D_OUT[463:348] : - ((int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_50$D_OUT[231:116] : - int_sqrt_fNext_50$D_OUT[463:348]), - int_sqrt_fNext_50$D_OUT[464] ? - int_sqrt_fNext_50$D_OUT[347:0] : - { _theResult___snd_fst__h45701, - (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_50$D_OUT[231:0] : - { _theResult___snd_snd__h45777, b__h45774 } } } ; - assign int_sqrt_fNext_51$ENQ = CAN_FIRE_RL_int_sqrt_work_51 ; - assign int_sqrt_fNext_51$DEQ = CAN_FIRE_RL_int_sqrt_work_52 ; - assign int_sqrt_fNext_51$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_52 - assign int_sqrt_fNext_52$D_IN = - { int_sqrt_fNext_51$D_OUT[464] || - int_sqrt_fNext_51$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_51$D_OUT[464] ? - int_sqrt_fNext_51$D_OUT[463:348] : - ((int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_51$D_OUT[231:116] : - int_sqrt_fNext_51$D_OUT[463:348]), - int_sqrt_fNext_51$D_OUT[464] ? - int_sqrt_fNext_51$D_OUT[347:0] : - { _theResult___snd_fst__h46101, - (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_51$D_OUT[231:0] : - { _theResult___snd_snd__h46177, b__h46174 } } } ; - assign int_sqrt_fNext_52$ENQ = CAN_FIRE_RL_int_sqrt_work_52 ; - assign int_sqrt_fNext_52$DEQ = CAN_FIRE_RL_int_sqrt_work_53 ; - assign int_sqrt_fNext_52$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_53 - assign int_sqrt_fNext_53$D_IN = - { int_sqrt_fNext_52$D_OUT[464] || - int_sqrt_fNext_52$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_52$D_OUT[464] ? - int_sqrt_fNext_52$D_OUT[463:348] : - ((int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_52$D_OUT[231:116] : - int_sqrt_fNext_52$D_OUT[463:348]), - int_sqrt_fNext_52$D_OUT[464] ? - int_sqrt_fNext_52$D_OUT[347:0] : - { _theResult___snd_fst__h46501, - (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_52$D_OUT[231:0] : - { _theResult___snd_snd__h46577, b__h46574 } } } ; - assign int_sqrt_fNext_53$ENQ = CAN_FIRE_RL_int_sqrt_work_53 ; - assign int_sqrt_fNext_53$DEQ = CAN_FIRE_RL_int_sqrt_work_54 ; - assign int_sqrt_fNext_53$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_54 - assign int_sqrt_fNext_54$D_IN = - { int_sqrt_fNext_53$D_OUT[464] || - int_sqrt_fNext_53$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_53$D_OUT[464] ? - int_sqrt_fNext_53$D_OUT[463:348] : - ((int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_53$D_OUT[231:116] : - int_sqrt_fNext_53$D_OUT[463:348]), - int_sqrt_fNext_53$D_OUT[464] ? - int_sqrt_fNext_53$D_OUT[347:0] : - { _theResult___snd_fst__h46901, - (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_53$D_OUT[231:0] : - { _theResult___snd_snd__h46977, b__h46974 } } } ; - assign int_sqrt_fNext_54$ENQ = CAN_FIRE_RL_int_sqrt_work_54 ; - assign int_sqrt_fNext_54$DEQ = CAN_FIRE_RL_int_sqrt_work_55 ; - assign int_sqrt_fNext_54$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_55 - assign int_sqrt_fNext_55$D_IN = - { int_sqrt_fNext_54$D_OUT[464] || - int_sqrt_fNext_54$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_54$D_OUT[464] ? - int_sqrt_fNext_54$D_OUT[463:348] : - ((int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_54$D_OUT[231:116] : - int_sqrt_fNext_54$D_OUT[463:348]), - int_sqrt_fNext_54$D_OUT[464] ? - int_sqrt_fNext_54$D_OUT[347:0] : - { _theResult___snd_fst__h47301, - (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_54$D_OUT[231:0] : - { _theResult___snd_snd__h47377, b__h47374 } } } ; - assign int_sqrt_fNext_55$ENQ = CAN_FIRE_RL_int_sqrt_work_55 ; - assign int_sqrt_fNext_55$DEQ = CAN_FIRE_RL_int_sqrt_work_56 ; - assign int_sqrt_fNext_55$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_56 - assign int_sqrt_fNext_56$D_IN = - { int_sqrt_fNext_55$D_OUT[464] || - int_sqrt_fNext_55$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_55$D_OUT[464] ? - int_sqrt_fNext_55$D_OUT[463:348] : - ((int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_55$D_OUT[231:116] : - int_sqrt_fNext_55$D_OUT[463:348]), - int_sqrt_fNext_55$D_OUT[464] ? - int_sqrt_fNext_55$D_OUT[347:0] : - { _theResult___snd_fst__h47701, - (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_55$D_OUT[231:0] : - { _theResult___snd_snd__h47777, b__h47774 } } } ; - assign int_sqrt_fNext_56$ENQ = CAN_FIRE_RL_int_sqrt_work_56 ; - assign int_sqrt_fNext_56$DEQ = CAN_FIRE_RL_int_sqrt_work_57 ; - assign int_sqrt_fNext_56$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_57 - assign int_sqrt_fNext_57$D_IN = - { int_sqrt_fNext_56$D_OUT[464] || - int_sqrt_fNext_56$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_56$D_OUT[464] ? - int_sqrt_fNext_56$D_OUT[463:348] : - ((int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_56$D_OUT[231:116] : - int_sqrt_fNext_56$D_OUT[463:348]), - int_sqrt_fNext_56$D_OUT[464] ? - int_sqrt_fNext_56$D_OUT[347:0] : - { _theResult___snd_fst__h48101, - (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_56$D_OUT[231:0] : - { _theResult___snd_snd__h48177, b__h48174 } } } ; - assign int_sqrt_fNext_57$ENQ = CAN_FIRE_RL_int_sqrt_work_57 ; - assign int_sqrt_fNext_57$DEQ = CAN_FIRE_RL_int_sqrt_work_58 ; - assign int_sqrt_fNext_57$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_58 - assign int_sqrt_fNext_58$D_IN = - { int_sqrt_fNext_57$D_OUT[464] || - int_sqrt_fNext_57$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_57$D_OUT[464] ? - int_sqrt_fNext_57$D_OUT[463:348] : - ((int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_57$D_OUT[231:116] : - int_sqrt_fNext_57$D_OUT[463:348]), - int_sqrt_fNext_57$D_OUT[464] ? - int_sqrt_fNext_57$D_OUT[347:0] : - { _theResult___snd_fst__h48501, - (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_57$D_OUT[231:0] : - { _theResult___snd_snd__h48577, b__h48574 } } } ; - assign int_sqrt_fNext_58$ENQ = CAN_FIRE_RL_int_sqrt_work_58 ; - assign int_sqrt_fNext_58$DEQ = CAN_FIRE_RL_int_sqrt_finish ; - assign int_sqrt_fNext_58$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_6 - assign int_sqrt_fNext_6$D_IN = - { int_sqrt_fNext_5$D_OUT[464] || - int_sqrt_fNext_5$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_5$D_OUT[464] ? - int_sqrt_fNext_5$D_OUT[463:348] : - ((int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_5$D_OUT[231:116] : - int_sqrt_fNext_5$D_OUT[463:348]), - int_sqrt_fNext_5$D_OUT[464] ? - int_sqrt_fNext_5$D_OUT[347:0] : - { _theResult___snd_fst__h27701, - (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_5$D_OUT[231:0] : - { _theResult___snd_snd__h27777, b__h27774 } } } ; - assign int_sqrt_fNext_6$ENQ = CAN_FIRE_RL_int_sqrt_work_6 ; - assign int_sqrt_fNext_6$DEQ = CAN_FIRE_RL_int_sqrt_work_7 ; - assign int_sqrt_fNext_6$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_7 - assign int_sqrt_fNext_7$D_IN = - { int_sqrt_fNext_6$D_OUT[464] || - int_sqrt_fNext_6$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_6$D_OUT[464] ? - int_sqrt_fNext_6$D_OUT[463:348] : - ((int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_6$D_OUT[231:116] : - int_sqrt_fNext_6$D_OUT[463:348]), - int_sqrt_fNext_6$D_OUT[464] ? - int_sqrt_fNext_6$D_OUT[347:0] : - { _theResult___snd_fst__h28101, - (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_6$D_OUT[231:0] : - { _theResult___snd_snd__h28177, b__h28174 } } } ; - assign int_sqrt_fNext_7$ENQ = CAN_FIRE_RL_int_sqrt_work_7 ; - assign int_sqrt_fNext_7$DEQ = CAN_FIRE_RL_int_sqrt_work_8 ; - assign int_sqrt_fNext_7$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_8 - assign int_sqrt_fNext_8$D_IN = - { int_sqrt_fNext_7$D_OUT[464] || - int_sqrt_fNext_7$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_7$D_OUT[464] ? - int_sqrt_fNext_7$D_OUT[463:348] : - ((int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_7$D_OUT[231:116] : - int_sqrt_fNext_7$D_OUT[463:348]), - int_sqrt_fNext_7$D_OUT[464] ? - int_sqrt_fNext_7$D_OUT[347:0] : - { _theResult___snd_fst__h28501, - (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_7$D_OUT[231:0] : - { _theResult___snd_snd__h28577, b__h28574 } } } ; - assign int_sqrt_fNext_8$ENQ = CAN_FIRE_RL_int_sqrt_work_8 ; - assign int_sqrt_fNext_8$DEQ = CAN_FIRE_RL_int_sqrt_work_9 ; - assign int_sqrt_fNext_8$CLR = 1'b0 ; - - // submodule int_sqrt_fNext_9 - assign int_sqrt_fNext_9$D_IN = - { int_sqrt_fNext_8$D_OUT[464] || - int_sqrt_fNext_8$D_OUT[115:0] == 116'd0, - int_sqrt_fNext_8$D_OUT[464] ? - int_sqrt_fNext_8$D_OUT[463:348] : - ((int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_8$D_OUT[231:116] : - int_sqrt_fNext_8$D_OUT[463:348]), - int_sqrt_fNext_8$D_OUT[464] ? - int_sqrt_fNext_8$D_OUT[347:0] : - { _theResult___snd_fst__h28901, - (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0) ? - int_sqrt_fNext_8$D_OUT[231:0] : - { _theResult___snd_snd__h28977, b__h28974 } } } ; - assign int_sqrt_fNext_9$ENQ = CAN_FIRE_RL_int_sqrt_work_9 ; - assign int_sqrt_fNext_9$DEQ = CAN_FIRE_RL_int_sqrt_work_10 ; - assign int_sqrt_fNext_9$CLR = 1'b0 ; - - // submodule int_sqrt_fRequest - assign int_sqrt_fRequest$D_IN = { fpu_fState_S1$D_OUT[57:0], 58'd0 } ; - assign int_sqrt_fRequest$ENQ = - WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[194] ; - assign int_sqrt_fRequest$DEQ = CAN_FIRE_RL_int_sqrt_start ; - assign int_sqrt_fRequest$CLR = 1'b0 ; - - // submodule int_sqrt_fResponse - assign int_sqrt_fResponse$D_IN = - { b__h48712, int_sqrt_fNext_58$D_OUT[347:232] != 116'd0 } ; - assign int_sqrt_fResponse$ENQ = CAN_FIRE_RL_int_sqrt_finish ; - assign int_sqrt_fResponse$DEQ = - WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[136] ; - assign int_sqrt_fResponse$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6 = - _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 ? - _theResult___snd__h75342 : - _theResult___snd__h75337 ; - assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 = - sfd__h75932[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h76519, sfd__h75932[52:1] }) : - { IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863, - sfd__h75932[51:0] } ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 = - (fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? - (fpu_fOperand_S0$D_OUT[54] ? - 6'd2 : - (fpu_fOperand_S0$D_OUT[53] ? - 6'd3 : - (fpu_fOperand_S0$D_OUT[52] ? - 6'd4 : - (fpu_fOperand_S0$D_OUT[51] ? - 6'd5 : - (fpu_fOperand_S0$D_OUT[50] ? - 6'd6 : - (fpu_fOperand_S0$D_OUT[49] ? - 6'd7 : - (fpu_fOperand_S0$D_OUT[48] ? - 6'd8 : - (fpu_fOperand_S0$D_OUT[47] ? - 6'd9 : - (fpu_fOperand_S0$D_OUT[46] ? - 6'd10 : - (fpu_fOperand_S0$D_OUT[45] ? - 6'd11 : - (fpu_fOperand_S0$D_OUT[44] ? - 6'd12 : - (fpu_fOperand_S0$D_OUT[43] ? - 6'd13 : - (fpu_fOperand_S0$D_OUT[42] ? - 6'd14 : - (fpu_fOperand_S0$D_OUT[41] ? - 6'd15 : - (fpu_fOperand_S0$D_OUT[40] ? - 6'd16 : - (fpu_fOperand_S0$D_OUT[39] ? - 6'd17 : - (fpu_fOperand_S0$D_OUT[38] ? - 6'd18 : - (fpu_fOperand_S0$D_OUT[37] ? - 6'd19 : - (fpu_fOperand_S0$D_OUT[36] ? - 6'd20 : - (fpu_fOperand_S0$D_OUT[35] ? - 6'd21 : - (fpu_fOperand_S0$D_OUT[34] ? - 6'd22 : - (fpu_fOperand_S0$D_OUT[33] ? - 6'd23 : - (fpu_fOperand_S0$D_OUT[32] ? - 6'd24 : - (fpu_fOperand_S0$D_OUT[31] ? - 6'd25 : - (fpu_fOperand_S0$D_OUT[30] ? - 6'd26 : - (fpu_fOperand_S0$D_OUT[29] ? - 6'd27 : - (fpu_fOperand_S0$D_OUT[28] ? - 6'd28 : - (fpu_fOperand_S0$D_OUT[27] ? - 6'd29 : - (fpu_fOperand_S0$D_OUT[26] ? - 6'd30 : - (fpu_fOperand_S0$D_OUT[25] ? - 6'd31 : - (fpu_fOperand_S0$D_OUT[24] ? - 6'd32 : - (fpu_fOperand_S0$D_OUT[23] ? - 6'd33 : - (fpu_fOperand_S0$D_OUT[22] ? - 6'd34 : - (fpu_fOperand_S0$D_OUT[21] ? - 6'd35 : - (fpu_fOperand_S0$D_OUT[20] ? - 6'd36 : - (fpu_fOperand_S0$D_OUT[19] ? - 6'd37 : - (fpu_fOperand_S0$D_OUT[18] ? - 6'd38 : - (fpu_fOperand_S0$D_OUT[17] ? - 6'd39 : - (fpu_fOperand_S0$D_OUT[16] ? - 6'd40 : - (fpu_fOperand_S0$D_OUT[15] ? - 6'd41 : - (fpu_fOperand_S0$D_OUT[14] ? - 6'd42 : - (fpu_fOperand_S0$D_OUT[13] ? - 6'd43 : - (fpu_fOperand_S0$D_OUT[12] ? - 6'd44 : - (fpu_fOperand_S0$D_OUT[11] ? - 6'd45 : - (fpu_fOperand_S0$D_OUT[10] ? - 6'd46 : - (fpu_fOperand_S0$D_OUT[9] ? - 6'd47 : - (fpu_fOperand_S0$D_OUT[8] ? - 6'd48 : - (fpu_fOperand_S0$D_OUT[7] ? - 6'd49 : - (fpu_fOperand_S0$D_OUT[6] ? - 6'd50 : - (fpu_fOperand_S0$D_OUT[5] ? - 6'd51 : - (fpu_fOperand_S0$D_OUT[4] ? - 6'd52 : - (fpu_fOperand_S0$D_OUT[3] ? - 6'd53 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1 ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460 = - ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8[10]}}, - fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 }) - - { 7'd0, - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 } ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2477 = - (fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54] || - fpu_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_fOperand_S0$D_OUT[54:3] == 52'd0 && - !fpu_fOperand_S0$D_OUT[66]) ? - { 1'd1, - fpu_fOperand_S0$D_OUT[66:3], - 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - (fpu_fOperand_S0$D_OUT[66] ? - 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - { 70'h155555555555555540, - fpu_fOperand_S0$D_OUT[2:0], - fpu_fOperand_S0$D_OUT[66], - x__h57541[10:0], - fpu_fOperand_S0$D_OUT[54:3], - x__h65683 }) ; - assign IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 = - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[12:1] ; - assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 = - (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? - 12'd3074 : - { fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5[10], - fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 } ; - assign IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 = - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 - - 12'd3074 ; - assign IF_fpu_fState_S3_first__517_BIT_195_518_THEN_f_ETC___d2813 = - fpu_fState_S3$D_OUT[195] ? - fpu_fState_S3$D_OUT[128:126] : - { fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023, - _theResult___fst_exp__h75269 == 11'd0 && - guard__h66951 != 2'd0, - fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023 } ; - assign IF_fpu_fState_S3_first__517_BIT_58_526_AND_IF__ETC___d2820 = - (fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h75266, sfdin__h75260[58:7] } ; - assign IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 = - (fpu_fState_S3$D_OUT[58] ? - 6'd0 : - (fpu_fState_S3$D_OUT[57] ? - 6'd1 : - (fpu_fState_S3$D_OUT[56] ? - 6'd2 : - (fpu_fState_S3$D_OUT[55] ? - 6'd3 : - (fpu_fState_S3$D_OUT[54] ? - 6'd4 : - (fpu_fState_S3$D_OUT[53] ? - 6'd5 : - (fpu_fState_S3$D_OUT[52] ? - 6'd6 : - (fpu_fState_S3$D_OUT[51] ? - 6'd7 : - (fpu_fState_S3$D_OUT[50] ? - 6'd8 : - (fpu_fState_S3$D_OUT[49] ? - 6'd9 : - (fpu_fState_S3$D_OUT[48] ? - 6'd10 : - (fpu_fState_S3$D_OUT[47] ? - 6'd11 : - (fpu_fState_S3$D_OUT[46] ? - 6'd12 : - (fpu_fState_S3$D_OUT[45] ? - 6'd13 : - (fpu_fState_S3$D_OUT[44] ? - 6'd14 : - (fpu_fState_S3$D_OUT[43] ? - 6'd15 : - (fpu_fState_S3$D_OUT[42] ? - 6'd16 : - (fpu_fState_S3$D_OUT[41] ? - 6'd17 : - (fpu_fState_S3$D_OUT[40] ? - 6'd18 : - (fpu_fState_S3$D_OUT[39] ? - 6'd19 : - (fpu_fState_S3$D_OUT[38] ? - 6'd20 : - (fpu_fState_S3$D_OUT[37] ? - 6'd21 : - (fpu_fState_S3$D_OUT[36] ? - 6'd22 : - (fpu_fState_S3$D_OUT[35] ? - 6'd23 : - (fpu_fState_S3$D_OUT[34] ? - 6'd24 : - (fpu_fState_S3$D_OUT[33] ? - 6'd25 : - (fpu_fState_S3$D_OUT[32] ? - 6'd26 : - (fpu_fState_S3$D_OUT[31] ? - 6'd27 : - (fpu_fState_S3$D_OUT[30] ? - 6'd28 : - (fpu_fState_S3$D_OUT[29] ? - 6'd29 : - (fpu_fState_S3$D_OUT[28] ? - 6'd30 : - (fpu_fState_S3$D_OUT[27] ? - 6'd31 : - (fpu_fState_S3$D_OUT[26] ? - 6'd32 : - (fpu_fState_S3$D_OUT[25] ? - 6'd33 : - (fpu_fState_S3$D_OUT[24] ? - 6'd34 : - (fpu_fState_S3$D_OUT[23] ? - 6'd35 : - (fpu_fState_S3$D_OUT[22] ? - 6'd36 : - (fpu_fState_S3$D_OUT[21] ? - 6'd37 : - (fpu_fState_S3$D_OUT[20] ? - 6'd38 : - (fpu_fState_S3$D_OUT[19] ? - 6'd39 : - (fpu_fState_S3$D_OUT[18] ? - 6'd40 : - (fpu_fState_S3$D_OUT[17] ? - 6'd41 : - (fpu_fState_S3$D_OUT[16] ? - 6'd42 : - (fpu_fState_S3$D_OUT[15] ? - 6'd43 : - (fpu_fState_S3$D_OUT[14] ? - 6'd44 : - (fpu_fState_S3$D_OUT[13] ? - 6'd45 : - (fpu_fState_S3$D_OUT[12] ? - 6'd46 : - (fpu_fState_S3$D_OUT[11] ? - 6'd47 : - (fpu_fState_S3$D_OUT[10] ? - 6'd48 : - (fpu_fState_S3$D_OUT[9] ? - 6'd49 : - (fpu_fState_S3$D_OUT[8] ? - 6'd50 : - (fpu_fState_S3$D_OUT[7] ? - 6'd51 : - (fpu_fState_S3$D_OUT[6] ? - 6'd52 : - (fpu_fState_S3$D_OUT[5] ? - 6'd53 : - (fpu_fState_S3$D_OUT[4] ? - 6'd54 : - (fpu_fState_S3$D_OUT[3] ? - 6'd55 : - (fpu_fState_S3$D_OUT[2] ? - 6'd56 : - (fpu_fState_S3$D_OUT[1] ? - 6'd57 : - (fpu_fState_S3$D_OUT[0] ? - 6'd58 : - 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 = - (fpu_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h75932[53:52] == 2'b01) ? - 11'd1 : - fpu_fState_S4$D_OUT[64:54] ; - assign IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 = - (int_sqrt_fRequest$D_OUT[115] ? - 7'd0 : - (int_sqrt_fRequest$D_OUT[114] ? - 7'd1 : - (int_sqrt_fRequest$D_OUT[113] ? - 7'd2 : - (int_sqrt_fRequest$D_OUT[112] ? - 7'd3 : - (int_sqrt_fRequest$D_OUT[111] ? - 7'd4 : - (int_sqrt_fRequest$D_OUT[110] ? - 7'd5 : - (int_sqrt_fRequest$D_OUT[109] ? - 7'd6 : - (int_sqrt_fRequest$D_OUT[108] ? - 7'd7 : - (int_sqrt_fRequest$D_OUT[107] ? - 7'd8 : - (int_sqrt_fRequest$D_OUT[106] ? - 7'd9 : - (int_sqrt_fRequest$D_OUT[105] ? - 7'd10 : - (int_sqrt_fRequest$D_OUT[104] ? - 7'd11 : - (int_sqrt_fRequest$D_OUT[103] ? - 7'd12 : - (int_sqrt_fRequest$D_OUT[102] ? - 7'd13 : - (int_sqrt_fRequest$D_OUT[101] ? - 7'd14 : - (int_sqrt_fRequest$D_OUT[100] ? - 7'd15 : - (int_sqrt_fRequest$D_OUT[99] ? - 7'd16 : - (int_sqrt_fRequest$D_OUT[98] ? - 7'd17 : - (int_sqrt_fRequest$D_OUT[97] ? - 7'd18 : - (int_sqrt_fRequest$D_OUT[96] ? - 7'd19 : - (int_sqrt_fRequest$D_OUT[95] ? - 7'd20 : - (int_sqrt_fRequest$D_OUT[94] ? - 7'd21 : - (int_sqrt_fRequest$D_OUT[93] ? - 7'd22 : - (int_sqrt_fRequest$D_OUT[92] ? - 7'd23 : - (int_sqrt_fRequest$D_OUT[91] ? - 7'd24 : - (int_sqrt_fRequest$D_OUT[90] ? - 7'd25 : - (int_sqrt_fRequest$D_OUT[89] ? - 7'd26 : - (int_sqrt_fRequest$D_OUT[88] ? - 7'd27 : - (int_sqrt_fRequest$D_OUT[87] ? - 7'd28 : - (int_sqrt_fRequest$D_OUT[86] ? - 7'd29 : - (int_sqrt_fRequest$D_OUT[85] ? - 7'd30 : - (int_sqrt_fRequest$D_OUT[84] ? - 7'd31 : - (int_sqrt_fRequest$D_OUT[83] ? - 7'd32 : - (int_sqrt_fRequest$D_OUT[82] ? - 7'd33 : - (int_sqrt_fRequest$D_OUT[81] ? - 7'd34 : - (int_sqrt_fRequest$D_OUT[80] ? - 7'd35 : - (int_sqrt_fRequest$D_OUT[79] ? - 7'd36 : - (int_sqrt_fRequest$D_OUT[78] ? - 7'd37 : - (int_sqrt_fRequest$D_OUT[77] ? - 7'd38 : - (int_sqrt_fRequest$D_OUT[76] ? - 7'd39 : - (int_sqrt_fRequest$D_OUT[75] ? - 7'd40 : - (int_sqrt_fRequest$D_OUT[74] ? - 7'd41 : - (int_sqrt_fRequest$D_OUT[73] ? - 7'd42 : - (int_sqrt_fRequest$D_OUT[72] ? - 7'd43 : - (int_sqrt_fRequest$D_OUT[71] ? - 7'd44 : - (int_sqrt_fRequest$D_OUT[70] ? - 7'd45 : - (int_sqrt_fRequest$D_OUT[69] ? - 7'd46 : - (int_sqrt_fRequest$D_OUT[68] ? - 7'd47 : - (int_sqrt_fRequest$D_OUT[67] ? - 7'd48 : - (int_sqrt_fRequest$D_OUT[66] ? - 7'd49 : - (int_sqrt_fRequest$D_OUT[65] ? - 7'd50 : - (int_sqrt_fRequest$D_OUT[64] ? - 7'd51 : - (int_sqrt_fRequest$D_OUT[63] ? - 7'd52 : - (int_sqrt_fRequest$D_OUT[62] ? - 7'd53 : - (int_sqrt_fRequest$D_OUT[61] ? - 7'd54 : - (int_sqrt_fRequest$D_OUT[60] ? - 7'd55 : - (int_sqrt_fRequest$D_OUT[59] ? - 7'd56 : - (int_sqrt_fRequest$D_OUT[58] ? - 7'd57 : - (int_sqrt_fRequest$D_OUT[57] ? - 7'd58 : - (int_sqrt_fRequest$D_OUT[56] ? - 7'd59 : - (int_sqrt_fRequest$D_OUT[55] ? - 7'd60 : - (int_sqrt_fRequest$D_OUT[54] ? - 7'd61 : - (int_sqrt_fRequest$D_OUT[53] ? - 7'd62 : - (int_sqrt_fRequest$D_OUT[52] ? - 7'd63 : - (int_sqrt_fRequest$D_OUT[51] ? - 7'd64 : - (int_sqrt_fRequest$D_OUT[50] ? - 7'd65 : - (int_sqrt_fRequest$D_OUT[49] ? - 7'd66 : - (int_sqrt_fRequest$D_OUT[48] ? - 7'd67 : - (int_sqrt_fRequest$D_OUT[47] ? - 7'd68 : - (int_sqrt_fRequest$D_OUT[46] ? - 7'd69 : - (int_sqrt_fRequest$D_OUT[45] ? - 7'd70 : - (int_sqrt_fRequest$D_OUT[44] ? - 7'd71 : - (int_sqrt_fRequest$D_OUT[43] ? - 7'd72 : - (int_sqrt_fRequest$D_OUT[42] ? - 7'd73 : - (int_sqrt_fRequest$D_OUT[41] ? - 7'd74 : - (int_sqrt_fRequest$D_OUT[40] ? - 7'd75 : - (int_sqrt_fRequest$D_OUT[39] ? - 7'd76 : - (int_sqrt_fRequest$D_OUT[38] ? - 7'd77 : - (int_sqrt_fRequest$D_OUT[37] ? - 7'd78 : - (int_sqrt_fRequest$D_OUT[36] ? - 7'd79 : - (int_sqrt_fRequest$D_OUT[35] ? - 7'd80 : - (int_sqrt_fRequest$D_OUT[34] ? - 7'd81 : - (int_sqrt_fRequest$D_OUT[33] ? - 7'd82 : - (int_sqrt_fRequest$D_OUT[32] ? - 7'd83 : - (int_sqrt_fRequest$D_OUT[31] ? - 7'd84 : - (int_sqrt_fRequest$D_OUT[30] ? - 7'd85 : - (int_sqrt_fRequest$D_OUT[29] ? - 7'd86 : - (int_sqrt_fRequest$D_OUT[28] ? - 7'd87 : - (int_sqrt_fRequest$D_OUT[27] ? - 7'd88 : - (int_sqrt_fRequest$D_OUT[26] ? - 7'd89 : - (int_sqrt_fRequest$D_OUT[25] ? - 7'd90 : - (int_sqrt_fRequest$D_OUT[24] ? - 7'd91 : - (int_sqrt_fRequest$D_OUT[23] ? - 7'd92 : - (int_sqrt_fRequest$D_OUT[22] ? - 7'd93 : - (int_sqrt_fRequest$D_OUT[21] ? - 7'd94 : - (int_sqrt_fRequest$D_OUT[20] ? - 7'd95 : - (int_sqrt_fRequest$D_OUT[19] ? - 7'd96 : - (int_sqrt_fRequest$D_OUT[18] ? - 7'd97 : - (int_sqrt_fRequest$D_OUT[17] ? - 7'd98 : - (int_sqrt_fRequest$D_OUT[16] ? - 7'd99 : - (int_sqrt_fRequest$D_OUT[15] ? - 7'd100 : - (int_sqrt_fRequest$D_OUT[14] ? - 7'd101 : - (int_sqrt_fRequest$D_OUT[13] ? - 7'd102 : - (int_sqrt_fRequest$D_OUT[12] ? - 7'd103 : - (int_sqrt_fRequest$D_OUT[11] ? - 7'd104 : - (int_sqrt_fRequest$D_OUT[10] ? - 7'd105 : - (int_sqrt_fRequest$D_OUT[9] ? - 7'd106 : - (int_sqrt_fRequest$D_OUT[8] ? - 7'd107 : - (int_sqrt_fRequest$D_OUT[7] ? - 7'd108 : - (int_sqrt_fRequest$D_OUT[6] ? - 7'd109 : - (int_sqrt_fRequest$D_OUT[5] ? - 7'd110 : - (int_sqrt_fRequest$D_OUT[4] ? - 7'd111 : - (int_sqrt_fRequest$D_OUT[3] ? - 7'd112 : - (int_sqrt_fRequest$D_OUT[2] ? - 7'd113 : - (int_sqrt_fRequest$D_OUT[1] ? - 7'd114 : - (int_sqrt_fRequest$D_OUT[0] ? - 7'd115 : - 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7 = - sfdin__h75260[6] ? 2'd2 : 2'd0 ; - assign _0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775 = - ({ 6'd0, - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ^ - 12'h800) <= - (IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ^ - 12'h800) ; - assign _theResult___exp__h76428 = - sfd__h75932[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h76519) : - IF_fpu_fState_S4_first__829_BITS_64_TO_54_832__ETC___d2863 ; - assign _theResult___fst_exp__h75266 = - fpu_fState_S3$D_OUT[58] ? - _theResult___fst_exp__h75289 : - _theResult___fst_exp__h75353 ; - assign _theResult___fst_exp__h75269 = - (fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h75266 ; - assign _theResult___fst_exp__h75289 = - (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd2 : - fpu_fState_S3$D_OUT[121:111] + 11'd1 ; - assign _theResult___fst_exp__h75305 = - (fpu_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd1 : - fpu_fState_S3$D_OUT[121:111] ; - assign _theResult___fst_exp__h75344 = - fpu_fState_S3$D_OUT[121:111] - - { 5'd0, - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 } ; - assign _theResult___fst_exp__h75350 = - (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && - !fpu_fState_S3$D_OUT[56] && - !fpu_fState_S3$D_OUT[55] && - !fpu_fState_S3$D_OUT[54] && - !fpu_fState_S3$D_OUT[53] && - !fpu_fState_S3$D_OUT[52] && - !fpu_fState_S3$D_OUT[51] && - !fpu_fState_S3$D_OUT[50] && - !fpu_fState_S3$D_OUT[49] && - !fpu_fState_S3$D_OUT[48] && - !fpu_fState_S3$D_OUT[47] && - !fpu_fState_S3$D_OUT[46] && - !fpu_fState_S3$D_OUT[45] && - !fpu_fState_S3$D_OUT[44] && - !fpu_fState_S3$D_OUT[43] && - !fpu_fState_S3$D_OUT[42] && - !fpu_fState_S3$D_OUT[41] && - !fpu_fState_S3$D_OUT[40] && - !fpu_fState_S3$D_OUT[39] && - !fpu_fState_S3$D_OUT[38] && - !fpu_fState_S3$D_OUT[37] && - !fpu_fState_S3$D_OUT[36] && - !fpu_fState_S3$D_OUT[35] && - !fpu_fState_S3$D_OUT[34] && - !fpu_fState_S3$D_OUT[33] && - !fpu_fState_S3$D_OUT[32] && - !fpu_fState_S3$D_OUT[31] && - !fpu_fState_S3$D_OUT[30] && - !fpu_fState_S3$D_OUT[29] && - !fpu_fState_S3$D_OUT[28] && - !fpu_fState_S3$D_OUT[27] && - !fpu_fState_S3$D_OUT[26] && - !fpu_fState_S3$D_OUT[25] && - !fpu_fState_S3$D_OUT[24] && - !fpu_fState_S3$D_OUT[23] && - !fpu_fState_S3$D_OUT[22] && - !fpu_fState_S3$D_OUT[21] && - !fpu_fState_S3$D_OUT[20] && - !fpu_fState_S3$D_OUT[19] && - !fpu_fState_S3$D_OUT[18] && - !fpu_fState_S3$D_OUT[17] && - !fpu_fState_S3$D_OUT[16] && - !fpu_fState_S3$D_OUT[15] && - !fpu_fState_S3$D_OUT[14] && - !fpu_fState_S3$D_OUT[13] && - !fpu_fState_S3$D_OUT[12] && - !fpu_fState_S3$D_OUT[11] && - !fpu_fState_S3$D_OUT[10] && - !fpu_fState_S3$D_OUT[9] && - !fpu_fState_S3$D_OUT[8] && - !fpu_fState_S3$D_OUT[7] && - !fpu_fState_S3$D_OUT[6] && - !fpu_fState_S3$D_OUT[5] && - !fpu_fState_S3$D_OUT[4] && - !fpu_fState_S3$D_OUT[3] && - !fpu_fState_S3$D_OUT[2] && - !fpu_fState_S3$D_OUT[1] && - !fpu_fState_S3$D_OUT[0] || - !_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_52_ETC___d2775) ? - 11'd0 : - _theResult___fst_exp__h75344 ; - assign _theResult___fst_exp__h75353 = - (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? - _theResult___fst_exp__h75305 : - _theResult___fst_exp__h75350 ; - assign _theResult___fst_exp__h76509 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h76506 ; - assign _theResult___fst_sfd__h76510 = - (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h76507 ; - assign _theResult___sfd__h76429 = - sfd__h75932[53] ? - ((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h75932[52:1]) : - sfd__h75932[51:0] ; - assign _theResult___snd__h75283 = { fpu_fState_S3$D_OUT[57:0], 1'd0 } ; - assign _theResult___snd__h75298 = - (!fpu_fState_S3$D_OUT[58] && fpu_fState_S3$D_OUT[57]) ? - _theResult___snd__h75300 : - _theResult___snd__h75313 ; - assign _theResult___snd__h75300 = { fpu_fState_S3$D_OUT[56:0], 2'd0 } ; - assign _theResult___snd__h75313 = - (!fpu_fState_S3$D_OUT[58] && !fpu_fState_S3$D_OUT[57] && - !fpu_fState_S3$D_OUT[56] && - !fpu_fState_S3$D_OUT[55] && - !fpu_fState_S3$D_OUT[54] && - !fpu_fState_S3$D_OUT[53] && - !fpu_fState_S3$D_OUT[52] && - !fpu_fState_S3$D_OUT[51] && - !fpu_fState_S3$D_OUT[50] && - !fpu_fState_S3$D_OUT[49] && - !fpu_fState_S3$D_OUT[48] && - !fpu_fState_S3$D_OUT[47] && - !fpu_fState_S3$D_OUT[46] && - !fpu_fState_S3$D_OUT[45] && - !fpu_fState_S3$D_OUT[44] && - !fpu_fState_S3$D_OUT[43] && - !fpu_fState_S3$D_OUT[42] && - !fpu_fState_S3$D_OUT[41] && - !fpu_fState_S3$D_OUT[40] && - !fpu_fState_S3$D_OUT[39] && - !fpu_fState_S3$D_OUT[38] && - !fpu_fState_S3$D_OUT[37] && - !fpu_fState_S3$D_OUT[36] && - !fpu_fState_S3$D_OUT[35] && - !fpu_fState_S3$D_OUT[34] && - !fpu_fState_S3$D_OUT[33] && - !fpu_fState_S3$D_OUT[32] && - !fpu_fState_S3$D_OUT[31] && - !fpu_fState_S3$D_OUT[30] && - !fpu_fState_S3$D_OUT[29] && - !fpu_fState_S3$D_OUT[28] && - !fpu_fState_S3$D_OUT[27] && - !fpu_fState_S3$D_OUT[26] && - !fpu_fState_S3$D_OUT[25] && - !fpu_fState_S3$D_OUT[24] && - !fpu_fState_S3$D_OUT[23] && - !fpu_fState_S3$D_OUT[22] && - !fpu_fState_S3$D_OUT[21] && - !fpu_fState_S3$D_OUT[20] && - !fpu_fState_S3$D_OUT[19] && - !fpu_fState_S3$D_OUT[18] && - !fpu_fState_S3$D_OUT[17] && - !fpu_fState_S3$D_OUT[16] && - !fpu_fState_S3$D_OUT[15] && - !fpu_fState_S3$D_OUT[14] && - !fpu_fState_S3$D_OUT[13] && - !fpu_fState_S3$D_OUT[12] && - !fpu_fState_S3$D_OUT[11] && - !fpu_fState_S3$D_OUT[10] && - !fpu_fState_S3$D_OUT[9] && - !fpu_fState_S3$D_OUT[8] && - !fpu_fState_S3$D_OUT[7] && - !fpu_fState_S3$D_OUT[6] && - !fpu_fState_S3$D_OUT[5] && - !fpu_fState_S3$D_OUT[4] && - !fpu_fState_S3$D_OUT[3] && - !fpu_fState_S3$D_OUT[2] && - !fpu_fState_S3$D_OUT[1] && - !fpu_fState_S3$D_OUT[0]) ? - fpu_fState_S3$D_OUT[58:0] : - _theResult___snd__h75319 ; - assign _theResult___snd__h75319 = - { IF_0_CONCAT_IF_fpu_fState_S3_first__517_BIT_58_ETC__q6[56:0], - 2'd0 } ; - assign _theResult___snd__h75337 = - fpu_fState_S3$D_OUT[58:0] << - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2774 ; - assign _theResult___snd__h75342 = - fpu_fState_S3$D_OUT[58:0] << - IF_fpu_fState_S3_first__517_BIT_58_526_THEN_0__ETC___d2772 ; - assign _theResult___snd_fst__h25299 = - (int_sqrt_fFirst$D_OUT[115:0] == 116'd0 || - int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264) ? - int_sqrt_fFirst$D_OUT[347:232] : - s__h25385 ; - assign _theResult___snd_fst__h25701 = - (int_sqrt_fNext_0$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299) ? - int_sqrt_fNext_0$D_OUT[347:232] : - s__h25785 ; - assign _theResult___snd_fst__h26101 = - (int_sqrt_fNext_1$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334) ? - int_sqrt_fNext_1$D_OUT[347:232] : - s__h26185 ; - assign _theResult___snd_fst__h26501 = - (int_sqrt_fNext_2$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369) ? - int_sqrt_fNext_2$D_OUT[347:232] : - s__h26585 ; - assign _theResult___snd_fst__h26901 = - (int_sqrt_fNext_3$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404) ? - int_sqrt_fNext_3$D_OUT[347:232] : - s__h26985 ; - assign _theResult___snd_fst__h27301 = - (int_sqrt_fNext_4$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439) ? - int_sqrt_fNext_4$D_OUT[347:232] : - s__h27385 ; - assign _theResult___snd_fst__h27701 = - (int_sqrt_fNext_5$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474) ? - int_sqrt_fNext_5$D_OUT[347:232] : - s__h27785 ; - assign _theResult___snd_fst__h28101 = - (int_sqrt_fNext_6$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509) ? - int_sqrt_fNext_6$D_OUT[347:232] : - s__h28185 ; - assign _theResult___snd_fst__h28501 = - (int_sqrt_fNext_7$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544) ? - int_sqrt_fNext_7$D_OUT[347:232] : - s__h28585 ; - assign _theResult___snd_fst__h28901 = - (int_sqrt_fNext_8$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579) ? - int_sqrt_fNext_8$D_OUT[347:232] : - s__h28985 ; - assign _theResult___snd_fst__h29301 = - (int_sqrt_fNext_9$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614) ? - int_sqrt_fNext_9$D_OUT[347:232] : - s__h29385 ; - assign _theResult___snd_fst__h29701 = - (int_sqrt_fNext_10$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649) ? - int_sqrt_fNext_10$D_OUT[347:232] : - s__h29785 ; - assign _theResult___snd_fst__h30101 = - (int_sqrt_fNext_11$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684) ? - int_sqrt_fNext_11$D_OUT[347:232] : - s__h30185 ; - assign _theResult___snd_fst__h30501 = - (int_sqrt_fNext_12$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719) ? - int_sqrt_fNext_12$D_OUT[347:232] : - s__h30585 ; - assign _theResult___snd_fst__h30901 = - (int_sqrt_fNext_13$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754) ? - int_sqrt_fNext_13$D_OUT[347:232] : - s__h30985 ; - assign _theResult___snd_fst__h31301 = - (int_sqrt_fNext_14$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789) ? - int_sqrt_fNext_14$D_OUT[347:232] : - s__h31385 ; - assign _theResult___snd_fst__h31701 = - (int_sqrt_fNext_15$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824) ? - int_sqrt_fNext_15$D_OUT[347:232] : - s__h31785 ; - assign _theResult___snd_fst__h32101 = - (int_sqrt_fNext_16$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859) ? - int_sqrt_fNext_16$D_OUT[347:232] : - s__h32185 ; - assign _theResult___snd_fst__h32501 = - (int_sqrt_fNext_17$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894) ? - int_sqrt_fNext_17$D_OUT[347:232] : - s__h32585 ; - assign _theResult___snd_fst__h32901 = - (int_sqrt_fNext_18$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929) ? - int_sqrt_fNext_18$D_OUT[347:232] : - s__h32985 ; - assign _theResult___snd_fst__h33301 = - (int_sqrt_fNext_19$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964) ? - int_sqrt_fNext_19$D_OUT[347:232] : - s__h33385 ; - assign _theResult___snd_fst__h33701 = - (int_sqrt_fNext_20$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999) ? - int_sqrt_fNext_20$D_OUT[347:232] : - s__h33785 ; - assign _theResult___snd_fst__h34101 = - (int_sqrt_fNext_21$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034) ? - int_sqrt_fNext_21$D_OUT[347:232] : - s__h34185 ; - assign _theResult___snd_fst__h34501 = - (int_sqrt_fNext_22$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069) ? - int_sqrt_fNext_22$D_OUT[347:232] : - s__h34585 ; - assign _theResult___snd_fst__h34901 = - (int_sqrt_fNext_23$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104) ? - int_sqrt_fNext_23$D_OUT[347:232] : - s__h34985 ; - assign _theResult___snd_fst__h35301 = - (int_sqrt_fNext_24$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139) ? - int_sqrt_fNext_24$D_OUT[347:232] : - s__h35385 ; - assign _theResult___snd_fst__h35701 = - (int_sqrt_fNext_25$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174) ? - int_sqrt_fNext_25$D_OUT[347:232] : - s__h35785 ; - assign _theResult___snd_fst__h36101 = - (int_sqrt_fNext_26$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209) ? - int_sqrt_fNext_26$D_OUT[347:232] : - s__h36185 ; - assign _theResult___snd_fst__h36501 = - (int_sqrt_fNext_27$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244) ? - int_sqrt_fNext_27$D_OUT[347:232] : - s__h36585 ; - assign _theResult___snd_fst__h36901 = - (int_sqrt_fNext_28$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279) ? - int_sqrt_fNext_28$D_OUT[347:232] : - s__h36985 ; - assign _theResult___snd_fst__h37301 = - (int_sqrt_fNext_29$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314) ? - int_sqrt_fNext_29$D_OUT[347:232] : - s__h37385 ; - assign _theResult___snd_fst__h37701 = - (int_sqrt_fNext_30$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349) ? - int_sqrt_fNext_30$D_OUT[347:232] : - s__h37785 ; - assign _theResult___snd_fst__h38101 = - (int_sqrt_fNext_31$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384) ? - int_sqrt_fNext_31$D_OUT[347:232] : - s__h38185 ; - assign _theResult___snd_fst__h38501 = - (int_sqrt_fNext_32$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419) ? - int_sqrt_fNext_32$D_OUT[347:232] : - s__h38585 ; - assign _theResult___snd_fst__h38901 = - (int_sqrt_fNext_33$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454) ? - int_sqrt_fNext_33$D_OUT[347:232] : - s__h38985 ; - assign _theResult___snd_fst__h39301 = - (int_sqrt_fNext_34$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489) ? - int_sqrt_fNext_34$D_OUT[347:232] : - s__h39385 ; - assign _theResult___snd_fst__h39701 = - (int_sqrt_fNext_35$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524) ? - int_sqrt_fNext_35$D_OUT[347:232] : - s__h39785 ; - assign _theResult___snd_fst__h40101 = - (int_sqrt_fNext_36$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559) ? - int_sqrt_fNext_36$D_OUT[347:232] : - s__h40185 ; - assign _theResult___snd_fst__h40501 = - (int_sqrt_fNext_37$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594) ? - int_sqrt_fNext_37$D_OUT[347:232] : - s__h40585 ; - assign _theResult___snd_fst__h40901 = - (int_sqrt_fNext_38$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629) ? - int_sqrt_fNext_38$D_OUT[347:232] : - s__h40985 ; - assign _theResult___snd_fst__h41301 = - (int_sqrt_fNext_39$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664) ? - int_sqrt_fNext_39$D_OUT[347:232] : - s__h41385 ; - assign _theResult___snd_fst__h41701 = - (int_sqrt_fNext_40$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699) ? - int_sqrt_fNext_40$D_OUT[347:232] : - s__h41785 ; - assign _theResult___snd_fst__h42101 = - (int_sqrt_fNext_41$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734) ? - int_sqrt_fNext_41$D_OUT[347:232] : - s__h42185 ; - assign _theResult___snd_fst__h42501 = - (int_sqrt_fNext_42$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769) ? - int_sqrt_fNext_42$D_OUT[347:232] : - s__h42585 ; - assign _theResult___snd_fst__h42901 = - (int_sqrt_fNext_43$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804) ? - int_sqrt_fNext_43$D_OUT[347:232] : - s__h42985 ; - assign _theResult___snd_fst__h43301 = - (int_sqrt_fNext_44$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839) ? - int_sqrt_fNext_44$D_OUT[347:232] : - s__h43385 ; - assign _theResult___snd_fst__h43701 = - (int_sqrt_fNext_45$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874) ? - int_sqrt_fNext_45$D_OUT[347:232] : - s__h43785 ; - assign _theResult___snd_fst__h44101 = - (int_sqrt_fNext_46$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909) ? - int_sqrt_fNext_46$D_OUT[347:232] : - s__h44185 ; - assign _theResult___snd_fst__h44501 = - (int_sqrt_fNext_47$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944) ? - int_sqrt_fNext_47$D_OUT[347:232] : - s__h44585 ; - assign _theResult___snd_fst__h44901 = - (int_sqrt_fNext_48$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979) ? - int_sqrt_fNext_48$D_OUT[347:232] : - s__h44985 ; - assign _theResult___snd_fst__h45301 = - (int_sqrt_fNext_49$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014) ? - int_sqrt_fNext_49$D_OUT[347:232] : - s__h45385 ; - assign _theResult___snd_fst__h45701 = - (int_sqrt_fNext_50$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049) ? - int_sqrt_fNext_50$D_OUT[347:232] : - s__h45785 ; - assign _theResult___snd_fst__h46101 = - (int_sqrt_fNext_51$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084) ? - int_sqrt_fNext_51$D_OUT[347:232] : - s__h46185 ; - assign _theResult___snd_fst__h46501 = - (int_sqrt_fNext_52$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119) ? - int_sqrt_fNext_52$D_OUT[347:232] : - s__h46585 ; - assign _theResult___snd_fst__h46901 = - (int_sqrt_fNext_53$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154) ? - int_sqrt_fNext_53$D_OUT[347:232] : - s__h46985 ; - assign _theResult___snd_fst__h47301 = - (int_sqrt_fNext_54$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189) ? - int_sqrt_fNext_54$D_OUT[347:232] : - s__h47385 ; - assign _theResult___snd_fst__h47701 = - (int_sqrt_fNext_55$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224) ? - int_sqrt_fNext_55$D_OUT[347:232] : - s__h47785 ; - assign _theResult___snd_fst__h48101 = - (int_sqrt_fNext_56$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259) ? - int_sqrt_fNext_56$D_OUT[347:232] : - s__h48185 ; - assign _theResult___snd_fst__h48501 = - (int_sqrt_fNext_57$D_OUT[115:0] == 116'd0 || - int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294) ? - int_sqrt_fNext_57$D_OUT[347:232] : - s__h48585 ; - assign _theResult___snd_fst__h75372 = - { IF_sfdin5260_BIT_6_THEN_2_ELSE_0__q7[1], - { sfdin__h75260[5:0], 52'd0 } != 58'd0 } ; - assign _theResult___snd_snd__h25377 = - int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 ? - r__h25394 : - r__h25386 ; - assign _theResult___snd_snd__h25777 = - int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 ? - r__h25794 : - r__h25786 ; - assign _theResult___snd_snd__h26177 = - int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 ? - r__h26194 : - r__h26186 ; - assign _theResult___snd_snd__h26577 = - int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 ? - r__h26594 : - r__h26586 ; - assign _theResult___snd_snd__h26977 = - int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 ? - r__h26994 : - r__h26986 ; - assign _theResult___snd_snd__h27377 = - int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 ? - r__h27394 : - r__h27386 ; - assign _theResult___snd_snd__h27777 = - int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 ? - r__h27794 : - r__h27786 ; - assign _theResult___snd_snd__h28177 = - int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 ? - r__h28194 : - r__h28186 ; - assign _theResult___snd_snd__h28577 = - int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 ? - r__h28594 : - r__h28586 ; - assign _theResult___snd_snd__h28977 = - int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 ? - r__h28994 : - r__h28986 ; - assign _theResult___snd_snd__h29377 = - int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 ? - r__h29394 : - r__h29386 ; - assign _theResult___snd_snd__h29777 = - int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 ? - r__h29794 : - r__h29786 ; - assign _theResult___snd_snd__h30177 = - int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 ? - r__h30194 : - r__h30186 ; - assign _theResult___snd_snd__h30577 = - int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 ? - r__h30594 : - r__h30586 ; - assign _theResult___snd_snd__h30977 = - int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 ? - r__h30994 : - r__h30986 ; - assign _theResult___snd_snd__h31377 = - int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 ? - r__h31394 : - r__h31386 ; - assign _theResult___snd_snd__h31777 = - int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 ? - r__h31794 : - r__h31786 ; - assign _theResult___snd_snd__h32177 = - int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 ? - r__h32194 : - r__h32186 ; - assign _theResult___snd_snd__h32577 = - int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 ? - r__h32594 : - r__h32586 ; - assign _theResult___snd_snd__h32977 = - int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 ? - r__h32994 : - r__h32986 ; - assign _theResult___snd_snd__h33377 = - int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 ? - r__h33394 : - r__h33386 ; - assign _theResult___snd_snd__h33777 = - int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 ? - r__h33794 : - r__h33786 ; - assign _theResult___snd_snd__h34177 = - int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 ? - r__h34194 : - r__h34186 ; - assign _theResult___snd_snd__h34577 = - int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 ? - r__h34594 : - r__h34586 ; - assign _theResult___snd_snd__h34977 = - int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 ? - r__h34994 : - r__h34986 ; - assign _theResult___snd_snd__h35377 = - int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 ? - r__h35394 : - r__h35386 ; - assign _theResult___snd_snd__h35777 = - int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 ? - r__h35794 : - r__h35786 ; - assign _theResult___snd_snd__h36177 = - int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 ? - r__h36194 : - r__h36186 ; - assign _theResult___snd_snd__h36577 = - int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 ? - r__h36594 : - r__h36586 ; - assign _theResult___snd_snd__h36977 = - int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 ? - r__h36994 : - r__h36986 ; - assign _theResult___snd_snd__h37377 = - int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 ? - r__h37394 : - r__h37386 ; - assign _theResult___snd_snd__h37777 = - int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 ? - r__h37794 : - r__h37786 ; - assign _theResult___snd_snd__h38177 = - int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 ? - r__h38194 : - r__h38186 ; - assign _theResult___snd_snd__h38577 = - int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 ? - r__h38594 : - r__h38586 ; - assign _theResult___snd_snd__h38977 = - int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 ? - r__h38994 : - r__h38986 ; - assign _theResult___snd_snd__h39377 = - int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 ? - r__h39394 : - r__h39386 ; - assign _theResult___snd_snd__h39777 = - int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 ? - r__h39794 : - r__h39786 ; - assign _theResult___snd_snd__h40177 = - int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 ? - r__h40194 : - r__h40186 ; - assign _theResult___snd_snd__h40577 = - int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 ? - r__h40594 : - r__h40586 ; - assign _theResult___snd_snd__h40977 = - int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 ? - r__h40994 : - r__h40986 ; - assign _theResult___snd_snd__h41377 = - int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 ? - r__h41394 : - r__h41386 ; - assign _theResult___snd_snd__h41777 = - int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 ? - r__h41794 : - r__h41786 ; - assign _theResult___snd_snd__h42177 = - int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 ? - r__h42194 : - r__h42186 ; - assign _theResult___snd_snd__h42577 = - int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 ? - r__h42594 : - r__h42586 ; - assign _theResult___snd_snd__h42977 = - int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 ? - r__h42994 : - r__h42986 ; - assign _theResult___snd_snd__h43377 = - int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 ? - r__h43394 : - r__h43386 ; - assign _theResult___snd_snd__h43777 = - int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 ? - r__h43794 : - r__h43786 ; - assign _theResult___snd_snd__h44177 = - int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 ? - r__h44194 : - r__h44186 ; - assign _theResult___snd_snd__h44577 = - int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 ? - r__h44594 : - r__h44586 ; - assign _theResult___snd_snd__h44977 = - int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 ? - r__h44994 : - r__h44986 ; - assign _theResult___snd_snd__h45377 = - int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 ? - r__h45394 : - r__h45386 ; - assign _theResult___snd_snd__h45777 = - int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 ? - r__h45794 : - r__h45786 ; - assign _theResult___snd_snd__h46177 = - int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 ? - r__h46194 : - r__h46186 ; - assign _theResult___snd_snd__h46577 = - int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 ? - r__h46594 : - r__h46586 ; - assign _theResult___snd_snd__h46977 = - int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 ? - r__h46994 : - r__h46986 ; - assign _theResult___snd_snd__h47377 = - int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 ? - r__h47394 : - r__h47386 ; - assign _theResult___snd_snd__h47777 = - int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 ? - r__h47794 : - r__h47786 ; - assign _theResult___snd_snd__h48177 = - int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 ? - r__h48194 : - r__h48186 ; - assign _theResult___snd_snd__h48577 = - int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 ? - r__h48594 : - r__h48586 ; - assign b___1__h16687 = 116'h40000000000000000000000000000 >> x__h24992 ; - assign b__h25374 = { 2'd0, int_sqrt_fFirst$D_OUT[115:2] } ; - assign b__h25774 = { 2'd0, int_sqrt_fNext_0$D_OUT[115:2] } ; - assign b__h26174 = { 2'd0, int_sqrt_fNext_1$D_OUT[115:2] } ; - assign b__h26574 = { 2'd0, int_sqrt_fNext_2$D_OUT[115:2] } ; - assign b__h26974 = { 2'd0, int_sqrt_fNext_3$D_OUT[115:2] } ; - assign b__h27374 = { 2'd0, int_sqrt_fNext_4$D_OUT[115:2] } ; - assign b__h27774 = { 2'd0, int_sqrt_fNext_5$D_OUT[115:2] } ; - assign b__h28174 = { 2'd0, int_sqrt_fNext_6$D_OUT[115:2] } ; - assign b__h28574 = { 2'd0, int_sqrt_fNext_7$D_OUT[115:2] } ; - assign b__h28974 = { 2'd0, int_sqrt_fNext_8$D_OUT[115:2] } ; - assign b__h29374 = { 2'd0, int_sqrt_fNext_9$D_OUT[115:2] } ; - assign b__h29774 = { 2'd0, int_sqrt_fNext_10$D_OUT[115:2] } ; - assign b__h30174 = { 2'd0, int_sqrt_fNext_11$D_OUT[115:2] } ; - assign b__h30574 = { 2'd0, int_sqrt_fNext_12$D_OUT[115:2] } ; - assign b__h30974 = { 2'd0, int_sqrt_fNext_13$D_OUT[115:2] } ; - assign b__h31374 = { 2'd0, int_sqrt_fNext_14$D_OUT[115:2] } ; - assign b__h31774 = { 2'd0, int_sqrt_fNext_15$D_OUT[115:2] } ; - assign b__h32174 = { 2'd0, int_sqrt_fNext_16$D_OUT[115:2] } ; - assign b__h32574 = { 2'd0, int_sqrt_fNext_17$D_OUT[115:2] } ; - assign b__h32974 = { 2'd0, int_sqrt_fNext_18$D_OUT[115:2] } ; - assign b__h33374 = { 2'd0, int_sqrt_fNext_19$D_OUT[115:2] } ; - assign b__h33774 = { 2'd0, int_sqrt_fNext_20$D_OUT[115:2] } ; - assign b__h34174 = { 2'd0, int_sqrt_fNext_21$D_OUT[115:2] } ; - assign b__h34574 = { 2'd0, int_sqrt_fNext_22$D_OUT[115:2] } ; - assign b__h34974 = { 2'd0, int_sqrt_fNext_23$D_OUT[115:2] } ; - assign b__h35374 = { 2'd0, int_sqrt_fNext_24$D_OUT[115:2] } ; - assign b__h35774 = { 2'd0, int_sqrt_fNext_25$D_OUT[115:2] } ; - assign b__h36174 = { 2'd0, int_sqrt_fNext_26$D_OUT[115:2] } ; - assign b__h36574 = { 2'd0, int_sqrt_fNext_27$D_OUT[115:2] } ; - assign b__h36974 = { 2'd0, int_sqrt_fNext_28$D_OUT[115:2] } ; - assign b__h37374 = { 2'd0, int_sqrt_fNext_29$D_OUT[115:2] } ; - assign b__h37774 = { 2'd0, int_sqrt_fNext_30$D_OUT[115:2] } ; - assign b__h38174 = { 2'd0, int_sqrt_fNext_31$D_OUT[115:2] } ; - assign b__h38574 = { 2'd0, int_sqrt_fNext_32$D_OUT[115:2] } ; - assign b__h38974 = { 2'd0, int_sqrt_fNext_33$D_OUT[115:2] } ; - assign b__h39374 = { 2'd0, int_sqrt_fNext_34$D_OUT[115:2] } ; - assign b__h39774 = { 2'd0, int_sqrt_fNext_35$D_OUT[115:2] } ; - assign b__h40174 = { 2'd0, int_sqrt_fNext_36$D_OUT[115:2] } ; - assign b__h40574 = { 2'd0, int_sqrt_fNext_37$D_OUT[115:2] } ; - assign b__h40974 = { 2'd0, int_sqrt_fNext_38$D_OUT[115:2] } ; - assign b__h41374 = { 2'd0, int_sqrt_fNext_39$D_OUT[115:2] } ; - assign b__h41774 = { 2'd0, int_sqrt_fNext_40$D_OUT[115:2] } ; - assign b__h42174 = { 2'd0, int_sqrt_fNext_41$D_OUT[115:2] } ; - assign b__h42574 = { 2'd0, int_sqrt_fNext_42$D_OUT[115:2] } ; - assign b__h42974 = { 2'd0, int_sqrt_fNext_43$D_OUT[115:2] } ; - assign b__h43374 = { 2'd0, int_sqrt_fNext_44$D_OUT[115:2] } ; - assign b__h43774 = { 2'd0, int_sqrt_fNext_45$D_OUT[115:2] } ; - assign b__h44174 = { 2'd0, int_sqrt_fNext_46$D_OUT[115:2] } ; - assign b__h44574 = { 2'd0, int_sqrt_fNext_47$D_OUT[115:2] } ; - assign b__h44974 = { 2'd0, int_sqrt_fNext_48$D_OUT[115:2] } ; - assign b__h45374 = { 2'd0, int_sqrt_fNext_49$D_OUT[115:2] } ; - assign b__h45774 = { 2'd0, int_sqrt_fNext_50$D_OUT[115:2] } ; - assign b__h46174 = { 2'd0, int_sqrt_fNext_51$D_OUT[115:2] } ; - assign b__h46574 = { 2'd0, int_sqrt_fNext_52$D_OUT[115:2] } ; - assign b__h46974 = { 2'd0, int_sqrt_fNext_53$D_OUT[115:2] } ; - assign b__h47374 = { 2'd0, int_sqrt_fNext_54$D_OUT[115:2] } ; - assign b__h47774 = { 2'd0, int_sqrt_fNext_55$D_OUT[115:2] } ; - assign b__h48174 = { 2'd0, int_sqrt_fNext_56$D_OUT[115:2] } ; - assign b__h48574 = { 2'd0, int_sqrt_fNext_57$D_OUT[115:2] } ; - assign b__h48712 = - int_sqrt_fNext_58$D_OUT[464] ? - int_sqrt_fNext_58$D_OUT[463:348] : - 116'd0 ; - assign din_inc___2_exp__h76519 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ; - assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q8 = - fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_fState_S3D_OUT_BITS_121_TO_111_MINUS_1023__q5 = - fpu_fState_S3$D_OUT[121:111] - 11'd1023 ; - assign guard__h66951 = x__h75654 ; - assign int_sqrt_fFirst_first__48_BITS_347_TO_232_62_U_ETC___d264 = - int_sqrt_fFirst$D_OUT[347:232] < sum__h25372 ; - assign int_sqrt_fNext_0_first__83_BITS_347_TO_232_97__ETC___d299 = - int_sqrt_fNext_0$D_OUT[347:232] < sum__h25772 ; - assign int_sqrt_fNext_10_first__33_BITS_347_TO_232_47_ETC___d649 = - int_sqrt_fNext_10$D_OUT[347:232] < sum__h29772 ; - assign int_sqrt_fNext_11_first__68_BITS_347_TO_232_82_ETC___d684 = - int_sqrt_fNext_11$D_OUT[347:232] < sum__h30172 ; - assign int_sqrt_fNext_12_first__03_BITS_347_TO_232_17_ETC___d719 = - int_sqrt_fNext_12$D_OUT[347:232] < sum__h30572 ; - assign int_sqrt_fNext_13_first__38_BITS_347_TO_232_52_ETC___d754 = - int_sqrt_fNext_13$D_OUT[347:232] < sum__h30972 ; - assign int_sqrt_fNext_14_first__73_BITS_347_TO_232_87_ETC___d789 = - int_sqrt_fNext_14$D_OUT[347:232] < sum__h31372 ; - assign int_sqrt_fNext_15_first__08_BITS_347_TO_232_22_ETC___d824 = - int_sqrt_fNext_15$D_OUT[347:232] < sum__h31772 ; - assign int_sqrt_fNext_16_first__43_BITS_347_TO_232_57_ETC___d859 = - int_sqrt_fNext_16$D_OUT[347:232] < sum__h32172 ; - assign int_sqrt_fNext_17_first__78_BITS_347_TO_232_92_ETC___d894 = - int_sqrt_fNext_17$D_OUT[347:232] < sum__h32572 ; - assign int_sqrt_fNext_18_first__13_BITS_347_TO_232_27_ETC___d929 = - int_sqrt_fNext_18$D_OUT[347:232] < sum__h32972 ; - assign int_sqrt_fNext_19_first__48_BITS_347_TO_232_62_ETC___d964 = - int_sqrt_fNext_19$D_OUT[347:232] < sum__h33372 ; - assign int_sqrt_fNext_1_first__18_BITS_347_TO_232_32__ETC___d334 = - int_sqrt_fNext_1$D_OUT[347:232] < sum__h26172 ; - assign int_sqrt_fNext_20_first__83_BITS_347_TO_232_97_ETC___d999 = - int_sqrt_fNext_20$D_OUT[347:232] < sum__h33772 ; - assign int_sqrt_fNext_21_first__018_BITS_347_TO_232_0_ETC___d1034 = - int_sqrt_fNext_21$D_OUT[347:232] < sum__h34172 ; - assign int_sqrt_fNext_22_first__053_BITS_347_TO_232_0_ETC___d1069 = - int_sqrt_fNext_22$D_OUT[347:232] < sum__h34572 ; - assign int_sqrt_fNext_23_first__088_BITS_347_TO_232_1_ETC___d1104 = - int_sqrt_fNext_23$D_OUT[347:232] < sum__h34972 ; - assign int_sqrt_fNext_24_first__123_BITS_347_TO_232_1_ETC___d1139 = - int_sqrt_fNext_24$D_OUT[347:232] < sum__h35372 ; - assign int_sqrt_fNext_25_first__158_BITS_347_TO_232_1_ETC___d1174 = - int_sqrt_fNext_25$D_OUT[347:232] < sum__h35772 ; - assign int_sqrt_fNext_26_first__193_BITS_347_TO_232_2_ETC___d1209 = - int_sqrt_fNext_26$D_OUT[347:232] < sum__h36172 ; - assign int_sqrt_fNext_27_first__228_BITS_347_TO_232_2_ETC___d1244 = - int_sqrt_fNext_27$D_OUT[347:232] < sum__h36572 ; - assign int_sqrt_fNext_28_first__263_BITS_347_TO_232_2_ETC___d1279 = - int_sqrt_fNext_28$D_OUT[347:232] < sum__h36972 ; - assign int_sqrt_fNext_29_first__298_BITS_347_TO_232_3_ETC___d1314 = - int_sqrt_fNext_29$D_OUT[347:232] < sum__h37372 ; - assign int_sqrt_fNext_2_first__53_BITS_347_TO_232_67__ETC___d369 = - int_sqrt_fNext_2$D_OUT[347:232] < sum__h26572 ; - assign int_sqrt_fNext_30_first__333_BITS_347_TO_232_3_ETC___d1349 = - int_sqrt_fNext_30$D_OUT[347:232] < sum__h37772 ; - assign int_sqrt_fNext_31_first__368_BITS_347_TO_232_3_ETC___d1384 = - int_sqrt_fNext_31$D_OUT[347:232] < sum__h38172 ; - assign int_sqrt_fNext_32_first__403_BITS_347_TO_232_4_ETC___d1419 = - int_sqrt_fNext_32$D_OUT[347:232] < sum__h38572 ; - assign int_sqrt_fNext_33_first__438_BITS_347_TO_232_4_ETC___d1454 = - int_sqrt_fNext_33$D_OUT[347:232] < sum__h38972 ; - assign int_sqrt_fNext_34_first__473_BITS_347_TO_232_4_ETC___d1489 = - int_sqrt_fNext_34$D_OUT[347:232] < sum__h39372 ; - assign int_sqrt_fNext_35_first__508_BITS_347_TO_232_5_ETC___d1524 = - int_sqrt_fNext_35$D_OUT[347:232] < sum__h39772 ; - assign int_sqrt_fNext_36_first__543_BITS_347_TO_232_5_ETC___d1559 = - int_sqrt_fNext_36$D_OUT[347:232] < sum__h40172 ; - assign int_sqrt_fNext_37_first__578_BITS_347_TO_232_5_ETC___d1594 = - int_sqrt_fNext_37$D_OUT[347:232] < sum__h40572 ; - assign int_sqrt_fNext_38_first__613_BITS_347_TO_232_6_ETC___d1629 = - int_sqrt_fNext_38$D_OUT[347:232] < sum__h40972 ; - assign int_sqrt_fNext_39_first__648_BITS_347_TO_232_6_ETC___d1664 = - int_sqrt_fNext_39$D_OUT[347:232] < sum__h41372 ; - assign int_sqrt_fNext_3_first__88_BITS_347_TO_232_02__ETC___d404 = - int_sqrt_fNext_3$D_OUT[347:232] < sum__h26972 ; - assign int_sqrt_fNext_40_first__683_BITS_347_TO_232_6_ETC___d1699 = - int_sqrt_fNext_40$D_OUT[347:232] < sum__h41772 ; - assign int_sqrt_fNext_41_first__718_BITS_347_TO_232_7_ETC___d1734 = - int_sqrt_fNext_41$D_OUT[347:232] < sum__h42172 ; - assign int_sqrt_fNext_42_first__753_BITS_347_TO_232_7_ETC___d1769 = - int_sqrt_fNext_42$D_OUT[347:232] < sum__h42572 ; - assign int_sqrt_fNext_43_first__788_BITS_347_TO_232_8_ETC___d1804 = - int_sqrt_fNext_43$D_OUT[347:232] < sum__h42972 ; - assign int_sqrt_fNext_44_first__823_BITS_347_TO_232_8_ETC___d1839 = - int_sqrt_fNext_44$D_OUT[347:232] < sum__h43372 ; - assign int_sqrt_fNext_45_first__858_BITS_347_TO_232_8_ETC___d1874 = - int_sqrt_fNext_45$D_OUT[347:232] < sum__h43772 ; - assign int_sqrt_fNext_46_first__893_BITS_347_TO_232_9_ETC___d1909 = - int_sqrt_fNext_46$D_OUT[347:232] < sum__h44172 ; - assign int_sqrt_fNext_47_first__928_BITS_347_TO_232_9_ETC___d1944 = - int_sqrt_fNext_47$D_OUT[347:232] < sum__h44572 ; - assign int_sqrt_fNext_48_first__963_BITS_347_TO_232_9_ETC___d1979 = - int_sqrt_fNext_48$D_OUT[347:232] < sum__h44972 ; - assign int_sqrt_fNext_49_first__998_BITS_347_TO_232_0_ETC___d2014 = - int_sqrt_fNext_49$D_OUT[347:232] < sum__h45372 ; - assign int_sqrt_fNext_4_first__23_BITS_347_TO_232_37__ETC___d439 = - int_sqrt_fNext_4$D_OUT[347:232] < sum__h27372 ; - assign int_sqrt_fNext_50_first__033_BITS_347_TO_232_0_ETC___d2049 = - int_sqrt_fNext_50$D_OUT[347:232] < sum__h45772 ; - assign int_sqrt_fNext_51_first__068_BITS_347_TO_232_0_ETC___d2084 = - int_sqrt_fNext_51$D_OUT[347:232] < sum__h46172 ; - assign int_sqrt_fNext_52_first__103_BITS_347_TO_232_1_ETC___d2119 = - int_sqrt_fNext_52$D_OUT[347:232] < sum__h46572 ; - assign int_sqrt_fNext_53_first__138_BITS_347_TO_232_1_ETC___d2154 = - int_sqrt_fNext_53$D_OUT[347:232] < sum__h46972 ; - assign int_sqrt_fNext_54_first__173_BITS_347_TO_232_1_ETC___d2189 = - int_sqrt_fNext_54$D_OUT[347:232] < sum__h47372 ; - assign int_sqrt_fNext_55_first__208_BITS_347_TO_232_2_ETC___d2224 = - int_sqrt_fNext_55$D_OUT[347:232] < sum__h47772 ; - assign int_sqrt_fNext_56_first__243_BITS_347_TO_232_2_ETC___d2259 = - int_sqrt_fNext_56$D_OUT[347:232] < sum__h48172 ; - assign int_sqrt_fNext_57_first__278_BITS_347_TO_232_2_ETC___d2294 = - int_sqrt_fNext_57$D_OUT[347:232] < sum__h48572 ; - assign int_sqrt_fNext_5_first__58_BITS_347_TO_232_72__ETC___d474 = - int_sqrt_fNext_5$D_OUT[347:232] < sum__h27772 ; - assign int_sqrt_fNext_6_first__93_BITS_347_TO_232_07__ETC___d509 = - int_sqrt_fNext_6$D_OUT[347:232] < sum__h28172 ; - assign int_sqrt_fNext_7_first__28_BITS_347_TO_232_42__ETC___d544 = - int_sqrt_fNext_7$D_OUT[347:232] < sum__h28572 ; - assign int_sqrt_fNext_8_first__63_BITS_347_TO_232_77__ETC___d579 = - int_sqrt_fNext_8$D_OUT[347:232] < sum__h28972 ; - assign int_sqrt_fNext_9_first__98_BITS_347_TO_232_12__ETC___d614 = - int_sqrt_fNext_9$D_OUT[347:232] < sum__h29372 ; - assign out_exp__h76431 = - fpu_fState_S4$D_OUT[2] ? - _theResult___exp__h76428 : - fpu_fState_S4$D_OUT[64:54] ; - assign out_sfd__h76432 = - fpu_fState_S4$D_OUT[2] ? - _theResult___sfd__h76429 : - fpu_fState_S4$D_OUT[53:2] ; - assign r__h25386 = r__h25394 + int_sqrt_fFirst$D_OUT[115:0] ; - assign r__h25394 = { 1'd0, int_sqrt_fFirst$D_OUT[231:117] } ; - assign r__h25786 = r__h25794 + int_sqrt_fNext_0$D_OUT[115:0] ; - assign r__h25794 = { 1'd0, int_sqrt_fNext_0$D_OUT[231:117] } ; - assign r__h26186 = r__h26194 + int_sqrt_fNext_1$D_OUT[115:0] ; - assign r__h26194 = { 1'd0, int_sqrt_fNext_1$D_OUT[231:117] } ; - assign r__h26586 = r__h26594 + int_sqrt_fNext_2$D_OUT[115:0] ; - assign r__h26594 = { 1'd0, int_sqrt_fNext_2$D_OUT[231:117] } ; - assign r__h26986 = r__h26994 + int_sqrt_fNext_3$D_OUT[115:0] ; - assign r__h26994 = { 1'd0, int_sqrt_fNext_3$D_OUT[231:117] } ; - assign r__h27386 = r__h27394 + int_sqrt_fNext_4$D_OUT[115:0] ; - assign r__h27394 = { 1'd0, int_sqrt_fNext_4$D_OUT[231:117] } ; - assign r__h27786 = r__h27794 + int_sqrt_fNext_5$D_OUT[115:0] ; - assign r__h27794 = { 1'd0, int_sqrt_fNext_5$D_OUT[231:117] } ; - assign r__h28186 = r__h28194 + int_sqrt_fNext_6$D_OUT[115:0] ; - assign r__h28194 = { 1'd0, int_sqrt_fNext_6$D_OUT[231:117] } ; - assign r__h28586 = r__h28594 + int_sqrt_fNext_7$D_OUT[115:0] ; - assign r__h28594 = { 1'd0, int_sqrt_fNext_7$D_OUT[231:117] } ; - assign r__h28986 = r__h28994 + int_sqrt_fNext_8$D_OUT[115:0] ; - assign r__h28994 = { 1'd0, int_sqrt_fNext_8$D_OUT[231:117] } ; - assign r__h29386 = r__h29394 + int_sqrt_fNext_9$D_OUT[115:0] ; - assign r__h29394 = { 1'd0, int_sqrt_fNext_9$D_OUT[231:117] } ; - assign r__h29786 = r__h29794 + int_sqrt_fNext_10$D_OUT[115:0] ; - assign r__h29794 = { 1'd0, int_sqrt_fNext_10$D_OUT[231:117] } ; - assign r__h30186 = r__h30194 + int_sqrt_fNext_11$D_OUT[115:0] ; - assign r__h30194 = { 1'd0, int_sqrt_fNext_11$D_OUT[231:117] } ; - assign r__h30586 = r__h30594 + int_sqrt_fNext_12$D_OUT[115:0] ; - assign r__h30594 = { 1'd0, int_sqrt_fNext_12$D_OUT[231:117] } ; - assign r__h30986 = r__h30994 + int_sqrt_fNext_13$D_OUT[115:0] ; - assign r__h30994 = { 1'd0, int_sqrt_fNext_13$D_OUT[231:117] } ; - assign r__h31386 = r__h31394 + int_sqrt_fNext_14$D_OUT[115:0] ; - assign r__h31394 = { 1'd0, int_sqrt_fNext_14$D_OUT[231:117] } ; - assign r__h31786 = r__h31794 + int_sqrt_fNext_15$D_OUT[115:0] ; - assign r__h31794 = { 1'd0, int_sqrt_fNext_15$D_OUT[231:117] } ; - assign r__h32186 = r__h32194 + int_sqrt_fNext_16$D_OUT[115:0] ; - assign r__h32194 = { 1'd0, int_sqrt_fNext_16$D_OUT[231:117] } ; - assign r__h32586 = r__h32594 + int_sqrt_fNext_17$D_OUT[115:0] ; - assign r__h32594 = { 1'd0, int_sqrt_fNext_17$D_OUT[231:117] } ; - assign r__h32986 = r__h32994 + int_sqrt_fNext_18$D_OUT[115:0] ; - assign r__h32994 = { 1'd0, int_sqrt_fNext_18$D_OUT[231:117] } ; - assign r__h33386 = r__h33394 + int_sqrt_fNext_19$D_OUT[115:0] ; - assign r__h33394 = { 1'd0, int_sqrt_fNext_19$D_OUT[231:117] } ; - assign r__h33786 = r__h33794 + int_sqrt_fNext_20$D_OUT[115:0] ; - assign r__h33794 = { 1'd0, int_sqrt_fNext_20$D_OUT[231:117] } ; - assign r__h34186 = r__h34194 + int_sqrt_fNext_21$D_OUT[115:0] ; - assign r__h34194 = { 1'd0, int_sqrt_fNext_21$D_OUT[231:117] } ; - assign r__h34586 = r__h34594 + int_sqrt_fNext_22$D_OUT[115:0] ; - assign r__h34594 = { 1'd0, int_sqrt_fNext_22$D_OUT[231:117] } ; - assign r__h34986 = r__h34994 + int_sqrt_fNext_23$D_OUT[115:0] ; - assign r__h34994 = { 1'd0, int_sqrt_fNext_23$D_OUT[231:117] } ; - assign r__h35386 = r__h35394 + int_sqrt_fNext_24$D_OUT[115:0] ; - assign r__h35394 = { 1'd0, int_sqrt_fNext_24$D_OUT[231:117] } ; - assign r__h35786 = r__h35794 + int_sqrt_fNext_25$D_OUT[115:0] ; - assign r__h35794 = { 1'd0, int_sqrt_fNext_25$D_OUT[231:117] } ; - assign r__h36186 = r__h36194 + int_sqrt_fNext_26$D_OUT[115:0] ; - assign r__h36194 = { 1'd0, int_sqrt_fNext_26$D_OUT[231:117] } ; - assign r__h36586 = r__h36594 + int_sqrt_fNext_27$D_OUT[115:0] ; - assign r__h36594 = { 1'd0, int_sqrt_fNext_27$D_OUT[231:117] } ; - assign r__h36986 = r__h36994 + int_sqrt_fNext_28$D_OUT[115:0] ; - assign r__h36994 = { 1'd0, int_sqrt_fNext_28$D_OUT[231:117] } ; - assign r__h37386 = r__h37394 + int_sqrt_fNext_29$D_OUT[115:0] ; - assign r__h37394 = { 1'd0, int_sqrt_fNext_29$D_OUT[231:117] } ; - assign r__h37786 = r__h37794 + int_sqrt_fNext_30$D_OUT[115:0] ; - assign r__h37794 = { 1'd0, int_sqrt_fNext_30$D_OUT[231:117] } ; - assign r__h38186 = r__h38194 + int_sqrt_fNext_31$D_OUT[115:0] ; - assign r__h38194 = { 1'd0, int_sqrt_fNext_31$D_OUT[231:117] } ; - assign r__h38586 = r__h38594 + int_sqrt_fNext_32$D_OUT[115:0] ; - assign r__h38594 = { 1'd0, int_sqrt_fNext_32$D_OUT[231:117] } ; - assign r__h38986 = r__h38994 + int_sqrt_fNext_33$D_OUT[115:0] ; - assign r__h38994 = { 1'd0, int_sqrt_fNext_33$D_OUT[231:117] } ; - assign r__h39386 = r__h39394 + int_sqrt_fNext_34$D_OUT[115:0] ; - assign r__h39394 = { 1'd0, int_sqrt_fNext_34$D_OUT[231:117] } ; - assign r__h39786 = r__h39794 + int_sqrt_fNext_35$D_OUT[115:0] ; - assign r__h39794 = { 1'd0, int_sqrt_fNext_35$D_OUT[231:117] } ; - assign r__h40186 = r__h40194 + int_sqrt_fNext_36$D_OUT[115:0] ; - assign r__h40194 = { 1'd0, int_sqrt_fNext_36$D_OUT[231:117] } ; - assign r__h40586 = r__h40594 + int_sqrt_fNext_37$D_OUT[115:0] ; - assign r__h40594 = { 1'd0, int_sqrt_fNext_37$D_OUT[231:117] } ; - assign r__h40986 = r__h40994 + int_sqrt_fNext_38$D_OUT[115:0] ; - assign r__h40994 = { 1'd0, int_sqrt_fNext_38$D_OUT[231:117] } ; - assign r__h41386 = r__h41394 + int_sqrt_fNext_39$D_OUT[115:0] ; - assign r__h41394 = { 1'd0, int_sqrt_fNext_39$D_OUT[231:117] } ; - assign r__h41786 = r__h41794 + int_sqrt_fNext_40$D_OUT[115:0] ; - assign r__h41794 = { 1'd0, int_sqrt_fNext_40$D_OUT[231:117] } ; - assign r__h42186 = r__h42194 + int_sqrt_fNext_41$D_OUT[115:0] ; - assign r__h42194 = { 1'd0, int_sqrt_fNext_41$D_OUT[231:117] } ; - assign r__h42586 = r__h42594 + int_sqrt_fNext_42$D_OUT[115:0] ; - assign r__h42594 = { 1'd0, int_sqrt_fNext_42$D_OUT[231:117] } ; - assign r__h42986 = r__h42994 + int_sqrt_fNext_43$D_OUT[115:0] ; - assign r__h42994 = { 1'd0, int_sqrt_fNext_43$D_OUT[231:117] } ; - assign r__h43386 = r__h43394 + int_sqrt_fNext_44$D_OUT[115:0] ; - assign r__h43394 = { 1'd0, int_sqrt_fNext_44$D_OUT[231:117] } ; - assign r__h43786 = r__h43794 + int_sqrt_fNext_45$D_OUT[115:0] ; - assign r__h43794 = { 1'd0, int_sqrt_fNext_45$D_OUT[231:117] } ; - assign r__h44186 = r__h44194 + int_sqrt_fNext_46$D_OUT[115:0] ; - assign r__h44194 = { 1'd0, int_sqrt_fNext_46$D_OUT[231:117] } ; - assign r__h44586 = r__h44594 + int_sqrt_fNext_47$D_OUT[115:0] ; - assign r__h44594 = { 1'd0, int_sqrt_fNext_47$D_OUT[231:117] } ; - assign r__h44986 = r__h44994 + int_sqrt_fNext_48$D_OUT[115:0] ; - assign r__h44994 = { 1'd0, int_sqrt_fNext_48$D_OUT[231:117] } ; - assign r__h45386 = r__h45394 + int_sqrt_fNext_49$D_OUT[115:0] ; - assign r__h45394 = { 1'd0, int_sqrt_fNext_49$D_OUT[231:117] } ; - assign r__h45786 = r__h45794 + int_sqrt_fNext_50$D_OUT[115:0] ; - assign r__h45794 = { 1'd0, int_sqrt_fNext_50$D_OUT[231:117] } ; - assign r__h46186 = r__h46194 + int_sqrt_fNext_51$D_OUT[115:0] ; - assign r__h46194 = { 1'd0, int_sqrt_fNext_51$D_OUT[231:117] } ; - assign r__h46586 = r__h46594 + int_sqrt_fNext_52$D_OUT[115:0] ; - assign r__h46594 = { 1'd0, int_sqrt_fNext_52$D_OUT[231:117] } ; - assign r__h46986 = r__h46994 + int_sqrt_fNext_53$D_OUT[115:0] ; - assign r__h46994 = { 1'd0, int_sqrt_fNext_53$D_OUT[231:117] } ; - assign r__h47386 = r__h47394 + int_sqrt_fNext_54$D_OUT[115:0] ; - assign r__h47394 = { 1'd0, int_sqrt_fNext_54$D_OUT[231:117] } ; - assign r__h47786 = r__h47794 + int_sqrt_fNext_55$D_OUT[115:0] ; - assign r__h47794 = { 1'd0, int_sqrt_fNext_55$D_OUT[231:117] } ; - assign r__h48186 = r__h48194 + int_sqrt_fNext_56$D_OUT[115:0] ; - assign r__h48194 = { 1'd0, int_sqrt_fNext_56$D_OUT[231:117] } ; - assign r__h48586 = r__h48594 + int_sqrt_fNext_57$D_OUT[115:0] ; - assign r__h48594 = { 1'd0, int_sqrt_fNext_57$D_OUT[231:117] } ; - assign result__h66451 = { int_sqrt_fResponse$D_OUT[59:2], 1'd1 } ; - assign s__h25385 = int_sqrt_fFirst$D_OUT[347:232] - sum__h25372 ; - assign s__h25785 = int_sqrt_fNext_0$D_OUT[347:232] - sum__h25772 ; - assign s__h26185 = int_sqrt_fNext_1$D_OUT[347:232] - sum__h26172 ; - assign s__h26585 = int_sqrt_fNext_2$D_OUT[347:232] - sum__h26572 ; - assign s__h26985 = int_sqrt_fNext_3$D_OUT[347:232] - sum__h26972 ; - assign s__h27385 = int_sqrt_fNext_4$D_OUT[347:232] - sum__h27372 ; - assign s__h27785 = int_sqrt_fNext_5$D_OUT[347:232] - sum__h27772 ; - assign s__h28185 = int_sqrt_fNext_6$D_OUT[347:232] - sum__h28172 ; - assign s__h28585 = int_sqrt_fNext_7$D_OUT[347:232] - sum__h28572 ; - assign s__h28985 = int_sqrt_fNext_8$D_OUT[347:232] - sum__h28972 ; - assign s__h29385 = int_sqrt_fNext_9$D_OUT[347:232] - sum__h29372 ; - assign s__h29785 = int_sqrt_fNext_10$D_OUT[347:232] - sum__h29772 ; - assign s__h30185 = int_sqrt_fNext_11$D_OUT[347:232] - sum__h30172 ; - assign s__h30585 = int_sqrt_fNext_12$D_OUT[347:232] - sum__h30572 ; - assign s__h30985 = int_sqrt_fNext_13$D_OUT[347:232] - sum__h30972 ; - assign s__h31385 = int_sqrt_fNext_14$D_OUT[347:232] - sum__h31372 ; - assign s__h31785 = int_sqrt_fNext_15$D_OUT[347:232] - sum__h31772 ; - assign s__h32185 = int_sqrt_fNext_16$D_OUT[347:232] - sum__h32172 ; - assign s__h32585 = int_sqrt_fNext_17$D_OUT[347:232] - sum__h32572 ; - assign s__h32985 = int_sqrt_fNext_18$D_OUT[347:232] - sum__h32972 ; - assign s__h33385 = int_sqrt_fNext_19$D_OUT[347:232] - sum__h33372 ; - assign s__h33785 = int_sqrt_fNext_20$D_OUT[347:232] - sum__h33772 ; - assign s__h34185 = int_sqrt_fNext_21$D_OUT[347:232] - sum__h34172 ; - assign s__h34585 = int_sqrt_fNext_22$D_OUT[347:232] - sum__h34572 ; - assign s__h34985 = int_sqrt_fNext_23$D_OUT[347:232] - sum__h34972 ; - assign s__h35385 = int_sqrt_fNext_24$D_OUT[347:232] - sum__h35372 ; - assign s__h35785 = int_sqrt_fNext_25$D_OUT[347:232] - sum__h35772 ; - assign s__h36185 = int_sqrt_fNext_26$D_OUT[347:232] - sum__h36172 ; - assign s__h36585 = int_sqrt_fNext_27$D_OUT[347:232] - sum__h36572 ; - assign s__h36985 = int_sqrt_fNext_28$D_OUT[347:232] - sum__h36972 ; - assign s__h37385 = int_sqrt_fNext_29$D_OUT[347:232] - sum__h37372 ; - assign s__h37785 = int_sqrt_fNext_30$D_OUT[347:232] - sum__h37772 ; - assign s__h38185 = int_sqrt_fNext_31$D_OUT[347:232] - sum__h38172 ; - assign s__h38585 = int_sqrt_fNext_32$D_OUT[347:232] - sum__h38572 ; - assign s__h38985 = int_sqrt_fNext_33$D_OUT[347:232] - sum__h38972 ; - assign s__h39385 = int_sqrt_fNext_34$D_OUT[347:232] - sum__h39372 ; - assign s__h39785 = int_sqrt_fNext_35$D_OUT[347:232] - sum__h39772 ; - assign s__h40185 = int_sqrt_fNext_36$D_OUT[347:232] - sum__h40172 ; - assign s__h40585 = int_sqrt_fNext_37$D_OUT[347:232] - sum__h40572 ; - assign s__h40985 = int_sqrt_fNext_38$D_OUT[347:232] - sum__h40972 ; - assign s__h41385 = int_sqrt_fNext_39$D_OUT[347:232] - sum__h41372 ; - assign s__h41785 = int_sqrt_fNext_40$D_OUT[347:232] - sum__h41772 ; - assign s__h42185 = int_sqrt_fNext_41$D_OUT[347:232] - sum__h42172 ; - assign s__h42585 = int_sqrt_fNext_42$D_OUT[347:232] - sum__h42572 ; - assign s__h42985 = int_sqrt_fNext_43$D_OUT[347:232] - sum__h42972 ; - assign s__h43385 = int_sqrt_fNext_44$D_OUT[347:232] - sum__h43372 ; - assign s__h43785 = int_sqrt_fNext_45$D_OUT[347:232] - sum__h43772 ; - assign s__h44185 = int_sqrt_fNext_46$D_OUT[347:232] - sum__h44172 ; - assign s__h44585 = int_sqrt_fNext_47$D_OUT[347:232] - sum__h44572 ; - assign s__h44985 = int_sqrt_fNext_48$D_OUT[347:232] - sum__h44972 ; - assign s__h45385 = int_sqrt_fNext_49$D_OUT[347:232] - sum__h45372 ; - assign s__h45785 = int_sqrt_fNext_50$D_OUT[347:232] - sum__h45772 ; - assign s__h46185 = int_sqrt_fNext_51$D_OUT[347:232] - sum__h46172 ; - assign s__h46585 = int_sqrt_fNext_52$D_OUT[347:232] - sum__h46572 ; - assign s__h46985 = int_sqrt_fNext_53$D_OUT[347:232] - sum__h46972 ; - assign s__h47385 = int_sqrt_fNext_54$D_OUT[347:232] - sum__h47372 ; - assign s__h47785 = int_sqrt_fNext_55$D_OUT[347:232] - sum__h47772 ; - assign s__h48185 = int_sqrt_fNext_56$D_OUT[347:232] - sum__h48172 ; - assign s__h48585 = int_sqrt_fNext_57$D_OUT[347:232] - sum__h48572 ; - assign sfd___1__h65692 = { 1'd0, sfd__h49938[57:1] } ; - assign sfd__h49936 = { value__h58164, 4'd0 } ; - assign sfd__h49938 = sfd__h49936 << x__h65722 ; - assign sfd__h49989 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h75932 = - { 1'b0, - fpu_fState_S4$D_OUT[64:54] != 11'd0, - fpu_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfdin__h75260 = - fpu_fState_S3$D_OUT[58] ? - _theResult___snd__h75283 : - _theResult___snd__h75298 ; - assign sum__h25372 = - int_sqrt_fFirst$D_OUT[231:116] + int_sqrt_fFirst$D_OUT[115:0] ; - assign sum__h25772 = - int_sqrt_fNext_0$D_OUT[231:116] + int_sqrt_fNext_0$D_OUT[115:0] ; - assign sum__h26172 = - int_sqrt_fNext_1$D_OUT[231:116] + int_sqrt_fNext_1$D_OUT[115:0] ; - assign sum__h26572 = - int_sqrt_fNext_2$D_OUT[231:116] + int_sqrt_fNext_2$D_OUT[115:0] ; - assign sum__h26972 = - int_sqrt_fNext_3$D_OUT[231:116] + int_sqrt_fNext_3$D_OUT[115:0] ; - assign sum__h27372 = - int_sqrt_fNext_4$D_OUT[231:116] + int_sqrt_fNext_4$D_OUT[115:0] ; - assign sum__h27772 = - int_sqrt_fNext_5$D_OUT[231:116] + int_sqrt_fNext_5$D_OUT[115:0] ; - assign sum__h28172 = - int_sqrt_fNext_6$D_OUT[231:116] + int_sqrt_fNext_6$D_OUT[115:0] ; - assign sum__h28572 = - int_sqrt_fNext_7$D_OUT[231:116] + int_sqrt_fNext_7$D_OUT[115:0] ; - assign sum__h28972 = - int_sqrt_fNext_8$D_OUT[231:116] + int_sqrt_fNext_8$D_OUT[115:0] ; - assign sum__h29372 = - int_sqrt_fNext_9$D_OUT[231:116] + int_sqrt_fNext_9$D_OUT[115:0] ; - assign sum__h29772 = - int_sqrt_fNext_10$D_OUT[231:116] + - int_sqrt_fNext_10$D_OUT[115:0] ; - assign sum__h30172 = - int_sqrt_fNext_11$D_OUT[231:116] + - int_sqrt_fNext_11$D_OUT[115:0] ; - assign sum__h30572 = - int_sqrt_fNext_12$D_OUT[231:116] + - int_sqrt_fNext_12$D_OUT[115:0] ; - assign sum__h30972 = - int_sqrt_fNext_13$D_OUT[231:116] + - int_sqrt_fNext_13$D_OUT[115:0] ; - assign sum__h31372 = - int_sqrt_fNext_14$D_OUT[231:116] + - int_sqrt_fNext_14$D_OUT[115:0] ; - assign sum__h31772 = - int_sqrt_fNext_15$D_OUT[231:116] + - int_sqrt_fNext_15$D_OUT[115:0] ; - assign sum__h32172 = - int_sqrt_fNext_16$D_OUT[231:116] + - int_sqrt_fNext_16$D_OUT[115:0] ; - assign sum__h32572 = - int_sqrt_fNext_17$D_OUT[231:116] + - int_sqrt_fNext_17$D_OUT[115:0] ; - assign sum__h32972 = - int_sqrt_fNext_18$D_OUT[231:116] + - int_sqrt_fNext_18$D_OUT[115:0] ; - assign sum__h33372 = - int_sqrt_fNext_19$D_OUT[231:116] + - int_sqrt_fNext_19$D_OUT[115:0] ; - assign sum__h33772 = - int_sqrt_fNext_20$D_OUT[231:116] + - int_sqrt_fNext_20$D_OUT[115:0] ; - assign sum__h34172 = - int_sqrt_fNext_21$D_OUT[231:116] + - int_sqrt_fNext_21$D_OUT[115:0] ; - assign sum__h34572 = - int_sqrt_fNext_22$D_OUT[231:116] + - int_sqrt_fNext_22$D_OUT[115:0] ; - assign sum__h34972 = - int_sqrt_fNext_23$D_OUT[231:116] + - int_sqrt_fNext_23$D_OUT[115:0] ; - assign sum__h35372 = - int_sqrt_fNext_24$D_OUT[231:116] + - int_sqrt_fNext_24$D_OUT[115:0] ; - assign sum__h35772 = - int_sqrt_fNext_25$D_OUT[231:116] + - int_sqrt_fNext_25$D_OUT[115:0] ; - assign sum__h36172 = - int_sqrt_fNext_26$D_OUT[231:116] + - int_sqrt_fNext_26$D_OUT[115:0] ; - assign sum__h36572 = - int_sqrt_fNext_27$D_OUT[231:116] + - int_sqrt_fNext_27$D_OUT[115:0] ; - assign sum__h36972 = - int_sqrt_fNext_28$D_OUT[231:116] + - int_sqrt_fNext_28$D_OUT[115:0] ; - assign sum__h37372 = - int_sqrt_fNext_29$D_OUT[231:116] + - int_sqrt_fNext_29$D_OUT[115:0] ; - assign sum__h37772 = - int_sqrt_fNext_30$D_OUT[231:116] + - int_sqrt_fNext_30$D_OUT[115:0] ; - assign sum__h38172 = - int_sqrt_fNext_31$D_OUT[231:116] + - int_sqrt_fNext_31$D_OUT[115:0] ; - assign sum__h38572 = - int_sqrt_fNext_32$D_OUT[231:116] + - int_sqrt_fNext_32$D_OUT[115:0] ; - assign sum__h38972 = - int_sqrt_fNext_33$D_OUT[231:116] + - int_sqrt_fNext_33$D_OUT[115:0] ; - assign sum__h39372 = - int_sqrt_fNext_34$D_OUT[231:116] + - int_sqrt_fNext_34$D_OUT[115:0] ; - assign sum__h39772 = - int_sqrt_fNext_35$D_OUT[231:116] + - int_sqrt_fNext_35$D_OUT[115:0] ; - assign sum__h40172 = - int_sqrt_fNext_36$D_OUT[231:116] + - int_sqrt_fNext_36$D_OUT[115:0] ; - assign sum__h40572 = - int_sqrt_fNext_37$D_OUT[231:116] + - int_sqrt_fNext_37$D_OUT[115:0] ; - assign sum__h40972 = - int_sqrt_fNext_38$D_OUT[231:116] + - int_sqrt_fNext_38$D_OUT[115:0] ; - assign sum__h41372 = - int_sqrt_fNext_39$D_OUT[231:116] + - int_sqrt_fNext_39$D_OUT[115:0] ; - assign sum__h41772 = - int_sqrt_fNext_40$D_OUT[231:116] + - int_sqrt_fNext_40$D_OUT[115:0] ; - assign sum__h42172 = - int_sqrt_fNext_41$D_OUT[231:116] + - int_sqrt_fNext_41$D_OUT[115:0] ; - assign sum__h42572 = - int_sqrt_fNext_42$D_OUT[231:116] + - int_sqrt_fNext_42$D_OUT[115:0] ; - assign sum__h42972 = - int_sqrt_fNext_43$D_OUT[231:116] + - int_sqrt_fNext_43$D_OUT[115:0] ; - assign sum__h43372 = - int_sqrt_fNext_44$D_OUT[231:116] + - int_sqrt_fNext_44$D_OUT[115:0] ; - assign sum__h43772 = - int_sqrt_fNext_45$D_OUT[231:116] + - int_sqrt_fNext_45$D_OUT[115:0] ; - assign sum__h44172 = - int_sqrt_fNext_46$D_OUT[231:116] + - int_sqrt_fNext_46$D_OUT[115:0] ; - assign sum__h44572 = - int_sqrt_fNext_47$D_OUT[231:116] + - int_sqrt_fNext_47$D_OUT[115:0] ; - assign sum__h44972 = - int_sqrt_fNext_48$D_OUT[231:116] + - int_sqrt_fNext_48$D_OUT[115:0] ; - assign sum__h45372 = - int_sqrt_fNext_49$D_OUT[231:116] + - int_sqrt_fNext_49$D_OUT[115:0] ; - assign sum__h45772 = - int_sqrt_fNext_50$D_OUT[231:116] + - int_sqrt_fNext_50$D_OUT[115:0] ; - assign sum__h46172 = - int_sqrt_fNext_51$D_OUT[231:116] + - int_sqrt_fNext_51$D_OUT[115:0] ; - assign sum__h46572 = - int_sqrt_fNext_52$D_OUT[231:116] + - int_sqrt_fNext_52$D_OUT[115:0] ; - assign sum__h46972 = - int_sqrt_fNext_53$D_OUT[231:116] + - int_sqrt_fNext_53$D_OUT[115:0] ; - assign sum__h47372 = - int_sqrt_fNext_54$D_OUT[231:116] + - int_sqrt_fNext_54$D_OUT[115:0] ; - assign sum__h47772 = - int_sqrt_fNext_55$D_OUT[231:116] + - int_sqrt_fNext_55$D_OUT[115:0] ; - assign sum__h48172 = - int_sqrt_fNext_56$D_OUT[231:116] + - int_sqrt_fNext_56$D_OUT[115:0] ; - assign sum__h48572 = - int_sqrt_fNext_57$D_OUT[231:116] + - int_sqrt_fNext_57$D_OUT[115:0] ; - assign value_BIT_52___h58260 = fpu_fOperand_S0$D_OUT[65:55] != 11'd0 ; - assign value__h58164 = - { 1'b0, value_BIT_52___h58260, fpu_fOperand_S0$D_OUT[54:3] } ; - assign x__h24992 = - IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237[0] ? - IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 + - 7'd1 : - IF_int_sqrt_fRequest_first_BIT_115_THEN_0_ELSE_ETC___d237 ; - assign x__h402 = - int_sqrt_fRequest$D_OUT[115] ? - 116'h40000000000000000000000000000 : - b___1__h16687 ; - assign x__h57541 = x__h57559 + 13'd1024 ; - assign x__h57559 = - { IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9[11], - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC__q9 } ; - assign x__h65683 = - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2460[0] ? - sfd__h49938 : - sfd___1__h65692 ; - assign x__h65722 = - IF_fpu_fOperand_S0_first__324_BITS_65_TO_55_32_ETC___d2458 - - 6'd1 ; - assign x__h66665 = - int_sqrt_fResponse$D_OUT[0] ? - result__h66451 : - int_sqrt_fResponse$D_OUT[59:1] ; - assign x__h75654 = - (fpu_fState_S3$D_OUT[58] && - IF_fpu_fState_S3_first__517_BITS_121_TO_111_52_ETC___d2531 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h75372 ; - always@(fpu_fState_S4$D_OUT or out_sfd__h76432 or _theResult___sfd__h76429) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - fpu_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - out_sfd__h76432; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 = - _theResult___sfd__h76429; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___sfd__h76429) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - fpu_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 = - _theResult___sfd__h76429; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or - _theResult___sfd__h76429) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h76507 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1; - 3'd1: - _theResult___fst_sfd__h76507 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2; - 3'd2: - _theResult___fst_sfd__h76507 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[53:2] : - _theResult___sfd__h76429; - 3'd3: - _theResult___fst_sfd__h76507 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[53:2] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___sfd__h76429 : - fpu_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h76507 = fpu_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h76507 = 52'd0; - endcase - end - always@(fpu_fState_S4$D_OUT or out_exp__h76431 or _theResult___exp__h76428) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = - fpu_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = - out_exp__h76431; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 = - _theResult___exp__h76428; - endcase - end - always@(fpu_fState_S4$D_OUT or _theResult___exp__h76428) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = - fpu_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 = - _theResult___exp__h76428; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4 or - _theResult___exp__h76428) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h76506 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q3; - 3'd1: - _theResult___fst_exp__h76506 = - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q4; - 3'd2: - _theResult___fst_exp__h76506 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:54] : - _theResult___exp__h76428; - 3'd3: - _theResult___fst_exp__h76506 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:54] : - (fpu_fState_S4$D_OUT[65] ? - _theResult___exp__h76428 : - fpu_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h76506 = fpu_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h76506 = 11'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = - fpu_fState_S4$D_OUT[65]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 = - fpu_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ? - fpu_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; - 3'd3: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[64:2] : - (fpu_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : - fpu_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = - fpu_fState_S4$D_OUT[64:2]; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 = 63'd0; - endcase - end - always@(fpu_fState_S4$D_OUT) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = - fpu_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 = - fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - fpu_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866 : - fpu_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; - endcase - end - always@(fpu_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866) - begin - case (fpu_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 = - IF_0b0_CONCAT_NOT_fpu_fState_S4_first__829_BIT_ETC___d2866; - endcase - end - always@(fpu_fState_S4$D_OUT or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10 or - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14) - begin - case (fpu_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = - { CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q12, - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 }; - 3'd1: - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = - (fpu_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_fState_S4$D_OUT[65:2] : - { (fpu_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_fState_S4$D_OUT[65], - CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q14 }; - default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q15 = - { CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q10, - CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q11 }; - endcase - end + // submodule fpu + mkXilinxFpSqrt fpu(.CLK(CLK), + .RST_N(RST_N), + .request_put(fpu$request_put), + .EN_request_put(fpu$EN_request_put), + .EN_response_get(fpu$EN_response_get), + .RDY_request_put(fpu$RDY_request_put), + .response_get(fpu$response_get), + .RDY_response_get(fpu$RDY_response_get)); + + // submodule fpu + assign fpu$request_put = request_put ; + assign fpu$EN_request_put = EN_request_put ; + assign fpu$EN_response_get = EN_response_get ; endmodule // mkDoubleSqrt diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 1e25443..d10f5a0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1828,52 +1828,52 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h4212; - reg [31 : 0] v__h4385; - reg [31 : 0] v__h4649; - reg [31 : 0] v__h6688; - reg [31 : 0] v__h2488; - reg [31 : 0] v__h6989; - reg [31 : 0] v__h7482; - reg [31 : 0] v__h7645; - reg [31 : 0] v__h111446; - reg [31 : 0] v__h111613; - reg [31 : 0] v__h113716; - reg [31 : 0] v__h131062; - reg [31 : 0] v__h110827; - reg [31 : 0] v__h137757; - reg [31 : 0] v__h138265; - reg [31 : 0] v__h2482; - reg [31 : 0] v__h4206; - reg [31 : 0] v__h4379; - reg [31 : 0] v__h4643; - reg [31 : 0] v__h6682; - reg [31 : 0] v__h6983; - reg [31 : 0] v__h7476; - reg [31 : 0] v__h7639; - reg [31 : 0] v__h110821; - reg [31 : 0] v__h111440; - reg [31 : 0] v__h111607; - reg [31 : 0] v__h113710; - reg [31 : 0] v__h131056; - reg [31 : 0] v__h137751; - reg [31 : 0] v__h138259; + reg [31 : 0] v__h4198; + reg [31 : 0] v__h4371; + reg [31 : 0] v__h4635; + reg [31 : 0] v__h6674; + reg [31 : 0] v__h2474; + reg [31 : 0] v__h6975; + reg [31 : 0] v__h7468; + reg [31 : 0] v__h7631; + reg [31 : 0] v__h111433; + reg [31 : 0] v__h111600; + reg [31 : 0] v__h113703; + reg [31 : 0] v__h131049; + reg [31 : 0] v__h110814; + reg [31 : 0] v__h137744; + reg [31 : 0] v__h138252; + reg [31 : 0] v__h2468; + reg [31 : 0] v__h4192; + reg [31 : 0] v__h4365; + reg [31 : 0] v__h4629; + reg [31 : 0] v__h6668; + reg [31 : 0] v__h6969; + reg [31 : 0] v__h7462; + reg [31 : 0] v__h7625; + reg [31 : 0] v__h110808; + reg [31 : 0] v__h111427; + reg [31 : 0] v__h111594; + reg [31 : 0] v__h113697; + reg [31 : 0] v__h131043; + reg [31 : 0] v__h137738; + reg [31 : 0] v__h138246; // synopsys translate_on // remaining internal signals reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6, CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26, - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23, + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26, + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818, @@ -1883,34 +1883,34 @@ module mkProc(CLK, IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876, IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844, IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846, - data64__h124886, - ld_data__h108620, - w1__h45369, - w1__h45374, - w2__h45370, - w2__h45376, - x__h45365; + data64__h124873, + ld_data__h108607, + w1__h45356, + w1__h45361, + w2__h45357, + w2__h45363, + x__h45352; reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d944; - reg [7 : 0] strb8__h124887; + reg [7 : 0] strb8__h124874; reg [5 : 0] IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442; - reg [2 : 0] x__h59083; - reg [1 : 0] CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; + reg [2 : 0] x__h59070; + reg [1 : 0] CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11, - CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, - CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12, + CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12, SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050, SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319, - x__h59090, - x__h79808; + x__h59077, + x__h79795; wire [579 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270; wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418; wire [513 : 0] IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1269; wire [511 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - new_cline__h111749; + new_cline__h111736; wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394; wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360; @@ -1929,82 +1929,82 @@ module mkProc(CLK, IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_1_ETC___d603, IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155, IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193, - data__h29459, - failed_testnum__h139655, - mem_req_rd_addr_araddr__h111047, - mem_req_wr_addr_awaddr__h124971, - mmioPlatform_fromHostQ_data_0__h40159, - mmioPlatform_mtime__h34773, - mmioPlatform_reqData__h45961, - n__read_addr__h58951, - n__read_addr__h59036, - n__read_addr__h77570, - n__read_addr__h77649, - n__read_snd_addr__h91741, - newData__h29540, - newData__h32470, - op_result__h45977, - op_result__h46507, - op_result__h46512, - op_result__h46517, + data__h29445, + failed_testnum__h139642, + mem_req_rd_addr_araddr__h111034, + mem_req_wr_addr_awaddr__h124958, + mmioPlatform_fromHostQ_data_0__h40146, + mmioPlatform_mtime__h34759, + mmioPlatform_reqData__h45948, + n__read_addr__h58938, + n__read_addr__h59023, + n__read_addr__h77557, + n__read_addr__h77636, + n__read_snd_addr__h91728, + newData__h29526, + newData__h32456, + op_result__h45964, + op_result__h46494, + op_result__h46499, + op_result__h46504, + op_result__h46509, + op_result__h46515, op_result__h46522, op_result__h46528, - op_result__h46535, - op_result__h46541, - result__h45420, - result__h45544, - result__h45572, - result__h45600, - result__h45628, - result__h45656, - result__h45684, - result__h45712, - result__h45740, - result__h45785, - result__h45813, - result__h45841, - result__h45869, - result__h45910, - result__h45938, - result__h46064, - result__h46091, - result__h46118, - result__h46145, - result__h46172, - result__h46199, - result__h46226, - result__h46253, - result__h46297, - result__h46324, - result__h46351, - result__h46378, - result__h46418, - result__h46445, - result__h46562, - result__h46628, - result__h46694, - result__h46760, - result__h46826, - result__h46892, - result__h46958, - result__h47020, - result__h47065, - result__h47131, - result__h47197, - result__h47255, - result__h47300, - w1___1__h45479, - w2___1__h45480, - x1_avValue_data__h37831, - x1_avValue_data__h42298, - x__h29651, - x__h32561, - x__h34921, - x__h38349, - x__h38360, - x__h40369, - x__h40380, - x__h47477; + result__h45407, + result__h45531, + result__h45559, + result__h45587, + result__h45615, + result__h45643, + result__h45671, + result__h45699, + result__h45727, + result__h45772, + result__h45800, + result__h45828, + result__h45856, + result__h45897, + result__h45925, + result__h46051, + result__h46078, + result__h46105, + result__h46132, + result__h46159, + result__h46186, + result__h46213, + result__h46240, + result__h46284, + result__h46311, + result__h46338, + result__h46365, + result__h46405, + result__h46432, + result__h46549, + result__h46615, + result__h46681, + result__h46747, + result__h46813, + result__h46879, + result__h46945, + result__h47007, + result__h47052, + result__h47118, + result__h47184, + result__h47242, + result__h47287, + w1___1__h45466, + w2___1__h45467, + x1_avValue_data__h37818, + x1_avValue_data__h42285, + x__h29637, + x__h32547, + x__h34907, + x__h38336, + x__h38347, + x__h40356, + x__h40367, + x__h47464; wire [47 : 0] IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d505, IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d570, IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d671; @@ -2016,16 +2016,16 @@ module mkProc(CLK, mmioPlatform_mtime_BITS_63_TO_32__q3, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1, - v__h29252, - v__h29289, - w15369_BITS_31_TO_0__q7, - w25370_BITS_31_TO_0__q8, - x_data__h28042; + v__h29238, + v__h29275, + w15356_BITS_31_TO_0__q7, + w25357_BITS_31_TO_0__q8, + x_data__h28028; wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121; - wire [5 : 0] x__h111082, x__h124996; + wire [5 : 0] x__h111069, x__h124983; wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120; - wire [3 : 0] b__h110754, b__h2382; - wire [2 : 0] n__read_id__h58955, n__read_id__h59040; + wire [3 : 0] b__h110741, b__h2368; + wire [2 : 0] n__read_id__h58942, n__read_id__h59027; wire [1 : 0] IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1246, IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073, IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083, @@ -2084,22 +2084,22 @@ module mkProc(CLK, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296, mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577, mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322, - mmioPlatform_reqBE_BIT_0___h27667, - mmioPlatform_reqBE_BIT_4___h27627, + mmioPlatform_reqBE_BIT_0___h27653, + mmioPlatform_reqBE_BIT_4___h27613, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d532, mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d597, mmioPlatform_toHostQ_enqReq_dummy2_2_read__06__ETC___d218, - n__read_child__h58956, - n__read_child__h59041, - n__read_child__h77573, - n__read_child__h77652, - n__read_snd_id__h91742, + n__read_child__h58943, + n__read_child__h59028, + n__read_child__h77560, + n__read_child__h77639, + n__read_snd_id__h91729, propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093, propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097, - x__h58769, - x__h72321, - x__h77392; + x__h58756, + x__h72308, + x__h77379; // action method hart0_server_reset_request_put assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -3183,13 +3183,13 @@ module mkProc(CLK, !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read && mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 && - b__h2382 == 4'd0 ; + b__h2368 == 4'd0 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ; // rule RL_mmio_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp = - b__h2382 != 4'd0 && + b__h2368 != 4'd0 && mmio_axi4_adapter_master_xactor_crg_wr_resp_full && (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 || mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; @@ -3301,7 +3301,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h40369 == 64'd0 || + x__h40356 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3478,13 +3478,13 @@ module mkProc(CLK, (llc_axi4_adapter_rg_rd_req_beat != 3'd7 || llc$RDY_to_mem_toM_deq) && !llc$to_mem_toM_first[640] && - b__h110754 == 4'd0 ; + b__h110741 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; // rule RL_llc_axi4_adapter_rl_discard_write_rsp assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = - b__h110754 != 4'd0 && + b__h110741 != 4'd0 && llc_axi4_adapter_master_xactor_crg_wr_resp_full && (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 || llc_axi4_adapter_f_pending_writes$EMPTY_N) ; @@ -3576,7 +3576,7 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? mmioPlatform_reqData[31:0] : - x_data__h28042 } ; + x_data__h28028 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && @@ -3616,7 +3616,7 @@ module mkProc(CLK, IF_mmio_axi4_adapter_f_rsps_to_core_first__17__ETC___d952 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 3'd5, mmioPlatform_amoResp } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29459 } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h29445 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { mmioPlatform_reqFunc[5:4] != 2'd0, (mmioPlatform_reqFunc[5:4] == 2'd0) ? @@ -3730,7 +3730,7 @@ module mkProc(CLK, { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - x__h45365 } ; + x__h45352 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_ETC___d442, @@ -3739,53 +3739,53 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { x__h47477, 78'h1AAAAAAAAAAAAAAAAAAA } ; + { x__h47464, 78'h1AAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40369 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h40356 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h40369 != 64'd0 ; + x__h40356 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h38349 == 64'd0 ; + x__h38336 == 64'd0 ; assign propDstIdx_0_lat_1$whas = NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && IF_SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_ETC___d1126 ; assign propDstIdx_1_lat_1$whas = NOT_enqDst_0_dummy2_0_read__040_041_OR_NOT_enq_ETC___d1056 && - x__h58769 ; + x__h58756 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15, + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15, SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 } ; assign propDstIdx_1_0_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_A_ETC___d1423 ; assign propDstIdx_1_1_lat_1$whas = NOT_enqDst_1_0_dummy2_0_read__309_310_OR_NOT_e_ETC___d1325 && - x__h77392 ; + x__h77379 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26, + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26, SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 } ; assign enqDst_0_lat_0_1$wget = - { 1'd1, n__read_snd_addr__h91741, n__read_snd_id__h91742 } ; + { 1'd1, n__read_snd_addr__h91728, n__read_snd_id__h91729 } ; assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write = mmio_axi4_adapter_master_xactor_crg_wr_addr_full && master1_awready ; @@ -3834,11 +3834,11 @@ module mkProc(CLK, assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h2382 - 4'd1 ; + b__h2368 - 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h2382 ; + b__h2368 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = CAN_FIRE_RL_rl_reset ? 4'd0 : @@ -3891,11 +3891,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h110754 - 4'd1 ; + b__h110741 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h110754 ; + b__h110741 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read = CAN_FIRE_RL_rl_reset ? 4'd0 : @@ -3970,7 +3970,7 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_rd_addr assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN = - { 4'd0, mem_req_rd_addr_araddr__h111047, 29'd851968 } ; + { 4'd0, mem_req_rd_addr_araddr__h111034, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3981,13 +3981,13 @@ module mkProc(CLK, // register llc_axi4_adapter_master_xactor_rg_wr_addr assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN = - { 4'd0, mem_req_wr_addr_awaddr__h124971, 29'd851968 } ; + { 4'd0, mem_req_wr_addr_awaddr__h124958, 29'd851968 } ; assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; // register llc_axi4_adapter_master_xactor_rg_wr_data assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN = - { 4'd0, data64__h124886, strb8__h124887, 1'd1 } ; + { 4'd0, data64__h124873, strb8__h124874, 1'd1 } ; assign llc_axi4_adapter_master_xactor_rg_wr_data$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3999,7 +3999,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ; // register llc_axi4_adapter_rg_cline - assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h111749 ; + assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h111736 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -4136,7 +4136,7 @@ module mkProc(CLK, // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h32470 : + newData__h32456 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4145,7 +4145,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h29540 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h29526 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4567,7 +4567,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h108620, llc$dma_respLd_first[3] } ; + { ld_data__h108607, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -4710,7 +4710,7 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 } ; assign llc$to_mem_rsFromM_enq_x = - { new_cline__h111749, + { new_cline__h111736, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -4971,47 +4971,47 @@ module mkProc(CLK, // remaining internal signals module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), - .amoExec_current_data(x__h34921), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h29651)); + .amoExec_current_data(x__h34907), + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h29637)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), - .amoExec_current_data(mmioPlatform_mtime__h34773), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h32561)); + .amoExec_current_data(mmioPlatform_mtime__h34759), + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h32547)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), - .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40159), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h38360)); + .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40146), + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h38347)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h27627 && - mmioPlatform_reqBE_BIT_0___h27667, + mmioPlatform_reqBE_BIT_4___h27613 && + mmioPlatform_reqBE_BIT_0___h27653, 2'd0 }), .amoExec_current_data(64'd0), - .amoExec_in_data(mmioPlatform_reqData__h45961), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27627 && - !mmioPlatform_reqBE_BIT_0___h27667), - .amoExec(x__h40380)); + .amoExec_in_data(mmioPlatform_reqData__h45948), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27613 && + !mmioPlatform_reqBE_BIT_0___h27653), + .amoExec(x__h40367)); assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_01_BIT_ETC___d645 = { 1'h0, (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h37831 } } ; + x1_avValue_data__h37818 } } ; assign IF_IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4__ETC___d520 = (IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 && !mmioPlatform_mtip_0 || @@ -5027,7 +5027,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; assign IF_NOT_mmioPlatform_reqFunc_01_BITS_5_TO_4_02__ETC___d515 = - newData__h29540 <= mmioPlatform_mtime ; + newData__h29526 <= mmioPlatform_mtime ; assign IF_NOT_propDstIdx_0_dummy2_1_read__019_020_OR__ETC___d1054 = NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ? propDstIdx_1_dummy2_1$Q_OUT && @@ -5096,7 +5096,7 @@ module mkProc(CLK, CAN_FIRE_RL_doEnq_1 ? 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1261, - x__h72321 } ; + x__h72308 } ; assign IF_enqDst_1_0_lat_1_whas__223_THEN_enqDst_1_0__ETC___d1270 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : @@ -5241,11 +5241,11 @@ module mkProc(CLK, assign IF_mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_2_ETC___d684 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? { mmioPlatform_fromHostQ_empty ? - x__h40369 == 64'd0 : - x__h38349 == 64'd0, + x__h40356 == 64'd0 : + x__h38336 == 64'd0, 64'hAAAAAAAAAAAAAAAA } : { mmioPlatform_reqFunc[5:4] == 2'd1, - x1_avValue_data__h42298 } ; + x1_avValue_data__h42285 } ; assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__56__ETC___d165 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : @@ -5475,55 +5475,55 @@ module mkProc(CLK, !propDstIdx_1_0_dummy2_1$Q_OUT || !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; assign SEL_ARR_IF_propDstData_0_dummy2_1_read__057_TH_ETC___d1121 = - { CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, + { CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13, + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14, SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 } ; assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__326__ETC___d1418 = - { CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, - !CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, + { CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24, + !CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25, SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411, - x__h79808 } ; + x__h79795 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360 = - { CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; + { CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1360, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1377, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ; assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1411 = { SEL_ARR_IF_propDstData_1_0_lat_0_whas__150_THE_ETC___d1394, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22, + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ; assign SEL_ARR_propDstData_0_dummy2_1_read__057_AND_I_ETC___d1120 = - { CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12, - x__h59083, - x__h59090 } ; - assign b__h110754 = + { CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12, + x__h59070, + x__h59077 } ; + assign b__h110741 = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign b__h2382 = + assign b__h2368 = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign data__h29459 = + assign data__h29445 = mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h29252, 32'd0 } ; - assign failed_testnum__h139655 = + { v__h29238, 32'd0 } ; + assign failed_testnum__h139642 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign mem_req_rd_addr_araddr__h111047 = - { llc$to_mem_toM_first[68:11], x__h111082 } ; - assign mem_req_wr_addr_awaddr__h124971 = - { llc$to_mem_toM_first[639:582], x__h124996 } ; + assign mem_req_rd_addr_araddr__h111034 = + { llc$to_mem_toM_first[68:11], x__h111069 } ; + assign mem_req_wr_addr_awaddr__h124958 = + { llc$to_mem_toM_first[639:582], x__h124983 } ; assign mmioPlatform_cycle_12_ULT_99___d313 = mmioPlatform_cycle < 7'd99 ; assign mmioPlatform_fetchingWay_26_ULT_mmioPlatform_r_ETC___d936 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; - assign mmioPlatform_fromHostQ_data_0__h40159 = + assign mmioPlatform_fromHostQ_data_0__h40146 = mmioPlatform_fromHostQ_data_0 ; assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d296 = mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT && @@ -5534,18 +5534,18 @@ module mkProc(CLK, mmioPlatform_fromHostQ_full ; assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h34773 = mmioPlatform_mtime ; + assign mmioPlatform_mtime__h34759 = mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_21_ULE_IF_NOT_mmioPlat_ETC___d577 = - mmioPlatform_mtimecmp_0 <= newData__h32470 ; + mmioPlatform_mtimecmp_0 <= newData__h32456 ; assign mmioPlatform_mtimecmp_0_21_ULE_mmioPlatform_mt_ETC___d322 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_reqBE_BIT_0___h27667 = mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqBE_BIT_4___h27627 = mmioPlatform_reqBE[4] ; - assign mmioPlatform_reqData__h45961 = mmioPlatform_reqData ; + assign mmioPlatform_reqBE_BIT_0___h27653 = mmioPlatform_reqBE[0] ; + assign mmioPlatform_reqBE_BIT_4___h27613 = mmioPlatform_reqBE[4] ; + assign mmioPlatform_reqData__h45948 = mmioPlatform_reqData ; assign mmioPlatform_reqFunc_01_BITS_5_TO_4_02_EQ_0_03_ETC___d428 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && @@ -5572,104 +5572,104 @@ module mkProc(CLK, !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl) && mmioPlatform_toHostQ_full ; - assign n__read_addr__h58951 = + assign n__read_addr__h58938 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]) : 64'd0 ; - assign n__read_addr__h59036 = + assign n__read_addr__h59023 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]) : 64'd0 ; - assign n__read_addr__h77570 = + assign n__read_addr__h77557 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1155 : 64'd0 ; - assign n__read_addr__h77649 = + assign n__read_addr__h77636 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1193 : 64'd0 ; - assign n__read_child__h58956 = + assign n__read_child__h58943 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]) ; - assign n__read_child__h59041 = + assign n__read_child__h59028 = propDstData_1_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]) ; - assign n__read_child__h77573 = + assign n__read_child__h77560 = propDstData_1_0_dummy2_1$Q_OUT && IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1181 ; - assign n__read_child__h77652 = + assign n__read_child__h77639 = propDstData_1_1_dummy2_1$Q_OUT && IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1219 ; - assign n__read_id__h58955 = + assign n__read_id__h58942 = propDstData_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]) : 3'd0 ; - assign n__read_id__h59040 = + assign n__read_id__h59027 = propDstData_1_dummy2_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]) : 3'd0 ; - assign n__read_snd_addr__h91741 = + assign n__read_snd_addr__h91728 = propDstData_0_dummy2_1_1$Q_OUT ? (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[64:1] : propDstData_0_rl_1[64:1]) : 64'd0 ; - assign n__read_snd_id__h91742 = + assign n__read_snd_id__h91729 = propDstData_0_dummy2_1_1$Q_OUT && (CAN_FIRE_RL_srcPropose_4 ? core_0$tlbToMem_memReq_first[0] : propDstData_0_rl_1[0]) ; - assign newData__h29540 = + assign newData__h29526 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h29651 : + x__h29637 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d513 ; - assign newData__h32470 = + assign newData__h32456 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h32561 : + x__h32547 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d575 ; - assign new_cline__h111749 = + assign new_cline__h111736 = { llc_axi4_adapter_master_xactor_rg_rd_data[66:3], llc_axi4_adapter_rg_cline[511:64] } ; - assign op_result__h45977 = + assign op_result__h45964 = IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 + IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ; - assign op_result__h46507 = w1__h45374 ^ w2__h45376 ; - assign op_result__h46512 = w1__h45374 & w2__h45376 ; - assign op_result__h46517 = w1__h45374 | w2__h45376 ; + assign op_result__h46494 = w1__h45361 ^ w2__h45363 ; + assign op_result__h46499 = w1__h45361 & w2__h45363 ; + assign op_result__h46504 = w1__h45361 | w2__h45363 ; + assign op_result__h46509 = + (w1__h45361 < w2__h45363) ? w1__h45361 : w2__h45363 ; + assign op_result__h46515 = + (w1__h45361 <= w2__h45363) ? w2__h45363 : w1__h45361 ; assign op_result__h46522 = - (w1__h45374 < w2__h45376) ? w1__h45374 : w2__h45376 ; - assign op_result__h46528 = - (w1__h45374 <= w2__h45376) ? w2__h45376 : w1__h45374 ; - assign op_result__h46535 = ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ 64'h8000000000000000) < (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ 64'h8000000000000000)) ? - w1__h45374 : - w2__h45376 ; - assign op_result__h46541 = + w1__h45361 : + w2__h45363 ; + assign op_result__h46528 = ((IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 ^ 64'h8000000000000000) <= (IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 ^ 64'h8000000000000000)) ? - w2__h45376 : - w1__h45374 ; + w2__h45363 : + w1__h45361 ; assign propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 = propDstData_0_dummy2_1$Q_OUT && (CAN_FIRE_RL_srcPropose ? @@ -5680,126 +5680,126 @@ module mkProc(CLK, (CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]) ; - assign result__h45420 = + assign result__h45407 = { mmioPlatform_reqData[63:8], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0] } ; - assign result__h45544 = { 56'd0, mmioPlatform_reqData[7:0] } ; - assign result__h45572 = { 56'd0, mmioPlatform_reqData[15:8] } ; - assign result__h45600 = { 56'd0, mmioPlatform_reqData[23:16] } ; - assign result__h45628 = { 56'd0, mmioPlatform_reqData[31:24] } ; - assign result__h45656 = { 56'd0, mmioPlatform_reqData[39:32] } ; - assign result__h45684 = { 56'd0, mmioPlatform_reqData[47:40] } ; - assign result__h45712 = { 56'd0, mmioPlatform_reqData[55:48] } ; - assign result__h45740 = { 56'd0, mmioPlatform_reqData[63:56] } ; - assign result__h45785 = { 48'd0, mmioPlatform_reqData[15:0] } ; - assign result__h45813 = { 48'd0, mmioPlatform_reqData[31:16] } ; - assign result__h45841 = { 48'd0, mmioPlatform_reqData[47:32] } ; - assign result__h45869 = { 48'd0, mmioPlatform_reqData[63:48] } ; - assign result__h45910 = { 32'd0, mmioPlatform_reqData[31:0] } ; - assign result__h45938 = { 32'd0, mmioPlatform_reqData[63:32] } ; - assign result__h46064 = + assign result__h45531 = { 56'd0, mmioPlatform_reqData[7:0] } ; + assign result__h45559 = { 56'd0, mmioPlatform_reqData[15:8] } ; + assign result__h45587 = { 56'd0, mmioPlatform_reqData[23:16] } ; + assign result__h45615 = { 56'd0, mmioPlatform_reqData[31:24] } ; + assign result__h45643 = { 56'd0, mmioPlatform_reqData[39:32] } ; + assign result__h45671 = { 56'd0, mmioPlatform_reqData[47:40] } ; + assign result__h45699 = { 56'd0, mmioPlatform_reqData[55:48] } ; + assign result__h45727 = { 56'd0, mmioPlatform_reqData[63:56] } ; + assign result__h45772 = { 48'd0, mmioPlatform_reqData[15:0] } ; + assign result__h45800 = { 48'd0, mmioPlatform_reqData[31:16] } ; + assign result__h45828 = { 48'd0, mmioPlatform_reqData[47:32] } ; + assign result__h45856 = { 48'd0, mmioPlatform_reqData[63:48] } ; + assign result__h45897 = { 32'd0, mmioPlatform_reqData[31:0] } ; + assign result__h45925 = { 32'd0, mmioPlatform_reqData[63:32] } ; + assign result__h46051 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ; - assign result__h46091 = + assign result__h46078 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ; - assign result__h46118 = + assign result__h46105 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ; - assign result__h46145 = + assign result__h46132 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ; - assign result__h46172 = + assign result__h46159 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ; - assign result__h46199 = + assign result__h46186 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ; - assign result__h46226 = + assign result__h46213 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ; - assign result__h46253 = + assign result__h46240 = { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ; - assign result__h46297 = + assign result__h46284 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ; - assign result__h46324 = + assign result__h46311 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ; - assign result__h46351 = + assign result__h46338 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ; - assign result__h46378 = + assign result__h46365 = { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ; - assign result__h46418 = + assign result__h46405 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ; - assign result__h46445 = + assign result__h46432 = { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ; - assign result__h46562 = + assign result__h46549 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[7:0] } ; - assign result__h46628 = + assign result__h46615 = { mmioPlatform_reqData[63:24], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[15:0] } ; - assign result__h46694 = + assign result__h46681 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[23:0] } ; - assign result__h46760 = + assign result__h46747 = { mmioPlatform_reqData[63:40], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[31:0] } ; - assign result__h46826 = + assign result__h46813 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[39:0] } ; - assign result__h46892 = + assign result__h46879 = { mmioPlatform_reqData[63:56], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[47:0] } ; - assign result__h46958 = + assign result__h46945 = { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[7:0], mmioPlatform_reqData[55:0] } ; - assign result__h47020 = + assign result__h47007 = { mmioPlatform_reqData[63:16], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0] } ; - assign result__h47065 = + assign result__h47052 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], mmioPlatform_reqData[15:0] } ; - assign result__h47131 = + assign result__h47118 = { mmioPlatform_reqData[63:48], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], mmioPlatform_reqData[31:0] } ; - assign result__h47197 = + assign result__h47184 = { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[15:0], mmioPlatform_reqData[47:0] } ; - assign result__h47255 = + assign result__h47242 = { mmioPlatform_reqData[63:32], IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0] } ; - assign result__h47300 = + assign result__h47287 = { IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876[31:0], mmioPlatform_reqData[31:0] } ; - assign v__h29252 = mmioPlatform_waitUpperMSIPCRs ? v__h29289 : 32'd0 ; - assign v__h29289 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign w15369_BITS_31_TO_0__q7 = w1__h45369[31:0] ; - assign w1___1__h45479 = { 32'd0, w1__h45369[31:0] } ; - assign w25370_BITS_31_TO_0__q8 = w2__h45370[31:0] ; - assign w2___1__h45480 = { 32'd0, w2__h45370[31:0] } ; - assign x1_avValue_data__h37831 = + assign v__h29238 = mmioPlatform_waitUpperMSIPCRs ? v__h29275 : 32'd0 ; + assign v__h29275 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign w15356_BITS_31_TO_0__q7 = w1__h45356[31:0] ; + assign w1___1__h45466 = { 32'd0, w1__h45356[31:0] } ; + assign w25357_BITS_31_TO_0__q8 = w2__h45357[31:0] ; + assign w2___1__h45467 = { 32'd0, w2__h45357[31:0] } ; + assign x1_avValue_data__h37818 = mmioPlatform_toHostQ_empty ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign x1_avValue_data__h42298 = + assign x1_avValue_data__h42285 = mmioPlatform_fromHostQ_empty ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign x__h111082 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; - assign x__h124996 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; - assign x__h34921 = mmioPlatform_mtimecmp_0 ; - assign x__h38349 = + assign x__h111069 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ; + assign x__h124983 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ; + assign x__h34907 = mmioPlatform_mtimecmp_0 ; + assign x__h38336 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h38360 : + x__h38347 : IF_mmioPlatform_reqBE_04_BIT_7_80_THEN_mmioPla_ETC___d676 ; - assign x__h40369 = + assign x__h40356 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - x__h40380 : + x__h40367 : { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0, mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0, mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0, @@ -5808,123 +5808,123 @@ module mkProc(CLK, mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0, mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0, mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ; - assign x__h47477 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign x__h58769 = + assign x__h47464 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign x__h58756 = SEL_ARR_propDstIdx_0_dummy2_1_read__019_AND_IF_ETC___d1050 ? srcRR_0 : NOT_propDstIdx_0_dummy2_1_read__019_020_OR_IF__ETC___d1053 ; - assign x__h72321 = + assign x__h72308 = !CAN_FIRE_RL_doEnq_1 && IF_enqDst_1_0_lat_0_whas__226_THEN_enqDst_1_0__ETC___d1267 ; - assign x__h77392 = + assign x__h77379 = SEL_ARR_propDstIdx_1_0_dummy2_1_read__278_AND__ETC___d1319 ? srcRR_1_0 : NOT_propDstIdx_1_0_dummy2_1_read__278_279_OR_I_ETC___d1322 ; - assign x_data__h28042 = { 31'd0, mmioPlatform_reqData[0] } ; + assign x_data__h28028 = { 31'd0, mmioPlatform_reqData[0] } ; always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h108620 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h108620 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h108620 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h108620 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h108620 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h108620 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h108620 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h108620 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h108607 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h108607 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h108607 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h108607 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h108607 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h108607 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h108607 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h108607 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h124886 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h124886 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h124886 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h124886 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h124886 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h124886 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h124886 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h124886 = llc$to_mem_toM_first[511:448]; + 3'd0: data64__h124873 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h124873 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h124873 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h124873 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h124873 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h124873 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h124873 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h124873 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h124887 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h124887 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h124887 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h124887 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h124887 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h124887 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h124887 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h124887 = llc$to_mem_toM_first[575:568]; + 3'd0: strb8__h124874 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h124874 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h124874 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h124874 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h124874 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h124874 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h124874 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h124874 = llc$to_mem_toM_first[575:568]; endcase end always@(mmioPlatform_curReq or - result__h45544 or - result__h45572 or - result__h45600 or - result__h45628 or - result__h45656 or - result__h45684 or result__h45712 or result__h45740) + result__h45531 or + result__h45559 or + result__h45587 or + result__h45615 or + result__h45643 or + result__h45671 or result__h45699 or result__h45727) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45544; + result__h45531; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45572; + result__h45559; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45600; + result__h45587; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45628; + result__h45615; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45656; + result__h45643; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45684; + result__h45671; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45712; + result__h45699; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 = - result__h45740; + result__h45727; endcase end always@(mmioPlatform_curReq or - result__h45785 or - result__h45813 or result__h45841 or result__h45869) + result__h45772 or + result__h45800 or result__h45828 or result__h45856) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45785; + result__h45772; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45813; + result__h45800; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45841; + result__h45828; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = - result__h45869; + result__h45856; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 = 64'd0; endcase end - always@(mmioPlatform_curReq or result__h45910 or result__h45938) + always@(mmioPlatform_curReq or result__h45897 or result__h45925) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h45910; + result__h45897; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = - result__h45938; + result__h45925; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0; endcase end @@ -5936,102 +5936,102 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w2__h45370 = + w2__h45357 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; 2'b01: - w2__h45370 = + w2__h45357 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; 2'b10: - w2__h45370 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; + w2__h45357 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5; 2'b11: - w2__h45370 = + w2__h45357 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w2___1__h45480 or + w2___1__h45467 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) begin case (mmioPlatform_reqSz) 2'b0: - w2__h45376 = + w2__h45363 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766; 2'b01: - w2__h45376 = + w2__h45363 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; - 2'b10: w2__h45376 = w2___1__h45480; + 2'b10: w2__h45363 = w2___1__h45467; 2'b11: - w2__h45376 = + w2__h45363 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end always@(mmioPlatform_curReq or - result__h46297 or - result__h46324 or result__h46351 or result__h46378) + result__h46284 or + result__h46311 or result__h46338 or result__h46365) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46297; + result__h46284; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46324; + result__h46311; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46351; + result__h46338; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = - result__h46378; + result__h46365; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h46064 or - result__h46091 or - result__h46118 or - result__h46145 or - result__h46172 or - result__h46199 or result__h46226 or result__h46253) + result__h46051 or + result__h46078 or + result__h46105 or + result__h46132 or + result__h46159 or + result__h46186 or result__h46213 or result__h46240) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46064; + result__h46051; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46091; + result__h46078; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46118; + result__h46105; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46145; + result__h46132; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46172; + result__h46159; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46199; + result__h46186; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46226; + result__h46213; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 = - result__h46253; + result__h46240; endcase end - always@(mmioPlatform_curReq or result__h46418 or result__h46445) + always@(mmioPlatform_curReq or result__h46405 or result__h46432) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46418; + result__h46405; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = - result__h46445; + result__h46432; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0; endcase end @@ -6043,41 +6043,41 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - w1__h45369 = + w1__h45356 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; 2'b01: - w1__h45369 = + w1__h45356 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; 2'b10: - w1__h45369 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; + w1__h45356 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6; 2'b11: - w1__h45369 = + w1__h45356 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w1___1__h45479 or + w1___1__h45466 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) begin case (mmioPlatform_reqSz) 2'b0: - w1__h45374 = + w1__h45361 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818; 2'b01: - w1__h45374 = + w1__h45361 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; - 2'b10: w1__h45374 = w1___1__h45479; + 2'b10: w1__h45361 = w1___1__h45466; 2'b11: - w1__h45374 = + w1__h45361 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; endcase end always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d818 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830 or - w15369_BITS_31_TO_0__q7 or + w15356_BITS_31_TO_0__q7 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837) begin case (mmioPlatform_reqSz) @@ -6089,7 +6089,7 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d830; 2'b10: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = - { {32{w15369_BITS_31_TO_0__q7[31]}}, w15369_BITS_31_TO_0__q7 }; + { {32{w15356_BITS_31_TO_0__q7[31]}}, w15356_BITS_31_TO_0__q7 }; 2'b11: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d844 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d837; @@ -6098,7 +6098,7 @@ module mkProc(CLK, always@(mmioPlatform_reqSz or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d766 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779 or - w25370_BITS_31_TO_0__q8 or + w25357_BITS_31_TO_0__q8 or IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786) begin case (mmioPlatform_reqSz) @@ -6110,115 +6110,115 @@ module mkProc(CLK, IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d779; 2'b10: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = - { {32{w25370_BITS_31_TO_0__q8[31]}}, w25370_BITS_31_TO_0__q8 }; + { {32{w25357_BITS_31_TO_0__q8[31]}}, w25357_BITS_31_TO_0__q8 }; 2'b11: IF_mmioPlatform_reqSz_36_EQ_0b10_43_THEN_SEXT__ETC___d846 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end always@(mmioPlatform_reqAmofunc or - op_result__h46541 or - w2__h45376 or - op_result__h45977 or - op_result__h46507 or - op_result__h46512 or - op_result__h46517 or - op_result__h46535 or op_result__h46522 or op_result__h46528) + op_result__h46528 or + w2__h45363 or + op_result__h45964 or + op_result__h46494 or + op_result__h46499 or + op_result__h46504 or + op_result__h46522 or op_result__h46509 or op_result__h46515) begin case (mmioPlatform_reqAmofunc) 4'd0: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - w2__h45376; + w2__h45363; 4'd1: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h45977; + op_result__h45964; 4'd2: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46507; + op_result__h46494; 4'd3: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46512; + op_result__h46499; 4'd4: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46517; + op_result__h46504; 4'd5: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46535; + op_result__h46522; 4'd7: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46522; + op_result__h46509; 4'd8: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46528; + op_result__h46515; default: IF_mmioPlatform_reqAmofunc_41_EQ_0_42_THEN_IF__ETC___d876 = - op_result__h46541; + op_result__h46528; endcase end always@(mmioPlatform_curReq or - result__h47020 or - result__h47065 or result__h47131 or result__h47197) + result__h47007 or + result__h47052 or result__h47118 or result__h47184) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47020; + result__h47007; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47065; + result__h47052; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47131; + result__h47118; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = - result__h47197; + result__h47184; default: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909 = 64'd0; endcase end always@(mmioPlatform_curReq or - result__h45420 or - result__h46562 or - result__h46628 or - result__h46694 or - result__h46760 or - result__h46826 or result__h46892 or result__h46958) + result__h45407 or + result__h46549 or + result__h46615 or + result__h46681 or + result__h46747 or + result__h46813 or result__h46879 or result__h46945) begin case (mmioPlatform_curReq[2:0]) 3'h0: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h45420; + result__h45407; 3'h1: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46562; + result__h46549; 3'h2: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46628; + result__h46615; 3'h3: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46694; + result__h46681; 3'h4: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46760; + result__h46747; 3'h5: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46826; + result__h46813; 3'h6: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46892; + result__h46879; 3'h7: IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900 = - result__h46958; + result__h46945; endcase end - always@(mmioPlatform_curReq or result__h47255 or result__h47300) + always@(mmioPlatform_curReq or result__h47242 or result__h47287) begin case (mmioPlatform_curReq[2:0]) 3'h0: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47255; + result__h47242; 3'h4: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = - result__h47300; + result__h47287; default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0; endcase end @@ -6230,15 +6230,15 @@ module mkProc(CLK, begin case (mmioPlatform_reqSz) 2'b0: - x__h45365 = + x__h45352 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d900; 2'b01: - x__h45365 = + x__h45352 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d909; 2'b10: - x__h45365 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; + x__h45352 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9; 2'b11: - x__h45365 = + x__h45352 = IF_mmioPlatform_curReq_96_BITS_2_TO_0_38_EQ_0x_ETC___d786; endcase end @@ -6322,278 +6322,278 @@ module mkProc(CLK, IF_propDstIdx_1_1_lat_0_whas__142_THEN_propDst_ETC___d1145; endcase end - always@(x__h58769 or n__read_id__h58955 or n__read_id__h59040) + always@(x__h58756 or n__read_id__h58942 or n__read_id__h59027) begin - case (x__h58769) - 1'd0: x__h59083 = n__read_id__h58955; - 1'd1: x__h59083 = n__read_id__h59040; + case (x__h58756) + 1'd0: x__h59070 = n__read_id__h58942; + 1'd1: x__h59070 = n__read_id__h59027; endcase end - always@(x__h58769 or n__read_child__h58956 or n__read_child__h59041) + always@(x__h58756 or n__read_child__h58943 or n__read_child__h59028) begin - case (x__h58769) - 1'd0: x__h59090 = n__read_child__h58956; - 1'd1: x__h59090 = n__read_child__h59041; + case (x__h58756) + 1'd0: x__h59077 = n__read_child__h58943; + 1'd1: x__h59077 = n__read_child__h59028; endcase end - always@(x__h58769 or + always@(x__h58756 or propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093 or propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12 = + CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12 = propDstData_0_dummy2_1_read__057_AND_IF_propDs_ETC___d1093; 1'd1: - CASE_x8769_0_propDstData_0_dummy2_1_read__057__ETC__q12 = + CASE_x8756_0_propDstData_0_dummy2_1_read__057__ETC__q12 = propDstData_1_dummy2_1_read__062_AND_IF_propDs_ETC___d1097; endcase end - always@(x__h58769 or + always@(x__h58756 or IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073 or IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1073; 1'd1: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 = IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1077; endcase end - always@(x__h58769 or + always@(x__h58756 or IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083 or IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = IF_propDstData_0_dummy2_1_read__057_THEN_IF_pr_ETC___d1083; 1'd1: - CASE_x8769_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = + CASE_x8756_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 = IF_propDstData_1_dummy2_1_read__062_THEN_IF_pr_ETC___d1087; endcase end - always@(x__h58769 or n__read_addr__h58951 or n__read_addr__h59036) + always@(x__h58756 or n__read_addr__h58938 or n__read_addr__h59023) begin - case (x__h58769) + case (x__h58756) 1'd0: - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15 = - n__read_addr__h58951; + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15 = + n__read_addr__h58938; 1'd1: - CASE_x8769_0_n__read_addr8951_1_n__read_addr90_ETC__q15 = - n__read_addr__h59036; + CASE_x8756_0_n__read_addr8938_1_n__read_addr90_ETC__q15 = + n__read_addr__h59023; endcase end - always@(x__h77392 or n__read_child__h77573 or n__read_child__h77652) + always@(x__h77379 or n__read_child__h77560 or n__read_child__h77639) begin - case (x__h77392) - 1'd0: x__h79808 = n__read_child__h77573; - 1'd1: x__h79808 = n__read_child__h77652; + case (x__h77379) + 1'd0: x__h79795 = n__read_child__h77560; + 1'd1: x__h79795 = n__read_child__h77639; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h77392 or + always@(x__h77379 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x7392_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = + CASE_x7379_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h77392 or + always@(x__h77379 or propDstData_1_0_dummy2_1$Q_OUT or IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 or propDstData_1_1_dummy2_1$Q_OUT or IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_0_dummy2_1$Q_OUT ? IF_propDstData_1_0_lat_0_whas__150_THEN_propDs_ETC___d1160 : 2'd0; 1'd1: - CASE_x7392_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = + CASE_x7379_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 = propDstData_1_1_dummy2_1$Q_OUT ? IF_propDstData_1_1_lat_0_whas__188_THEN_propDs_ETC___d1198 : 2'd0; endcase end - always@(x__h77392 or + always@(x__h77379 or NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338 or NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_0_dummy2_1_read__326_337_OR__ETC___d1338; 1'd1: - CASE_x7392_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = + CASE_x7379_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 = NOT_propDstData_1_1_dummy2_1_read__328_339_OR__ETC___d1340; endcase end - always@(x__h77392 or n__read_addr__h77570 or n__read_addr__h77649) + always@(x__h77379 or n__read_addr__h77557 or n__read_addr__h77636) begin - case (x__h77392) + case (x__h77379) 1'd0: - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26 = - n__read_addr__h77570; + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26 = + n__read_addr__h77557; 1'd1: - CASE_x7392_0_n__read_addr7570_1_n__read_addr76_ETC__q26 = - n__read_addr__h77649; + CASE_x7379_0_n__read_addr7557_1_n__read_addr76_ETC__q26 = + n__read_addr__h77636; endcase end @@ -7001,7 +7001,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h139655); + $display("FAIL %0d", failed_testnum__h139642); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -7009,14 +7009,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4212 = $stime; + v__h4198 = $stime; #0; end - v__h4206 = v__h4212 / 32'd10; + v__h4192 = v__h4198 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4206); + $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4192); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7076,16 +7076,16 @@ module mkProc(CLK, mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h4385 = $stime; + v__h4371 = $stime; #0; end - v__h4379 = v__h4385 / 32'd10; + v__h4365 = v__h4371 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error", - v__h4379); + v__h4365); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_cfg_verbosity != 4'd0 && @@ -7189,15 +7189,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h4649 = $stime; + v__h4635 = $stime; #0; end - v__h4643 = v__h4649 / 32'd10; + v__h4629 = v__h4635 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:", - v__h4643); + v__h4629); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7366,14 +7366,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h6688 = $stime; + v__h6674 = $stime; #0; end - v__h6682 = v__h6688 / 32'd10; + v__h6668 = v__h6674 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h6682); + $display("%0d: ERROR: CreditCounter: overflow", v__h6668); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -7526,15 +7526,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h2488 = $stime; + v__h2474 = $stime; #0; end - v__h2482 = v__h2488 / 32'd10; + v__h2468 = v__h2474 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request", - v__h2482); + v__h2468); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7799,14 +7799,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h6989 = $stime; + v__h6975 = $stime; #0; end - v__h6983 = v__h6989 / 32'd10; + v__h6969 = v__h6975 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6983); + $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h6969); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -7843,15 +7843,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h7482 = $stime; + v__h7468 = $stime; #0; end - v__h7476 = v__h7482 / 32'd10; + v__h7462 = v__h7468 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h7476); + v__h7462); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) @@ -7891,14 +7891,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h7645 = $stime; + v__h7631 = $stime; #0; end - v__h7639 = v__h7645 / 32'd10; + v__h7625 = v__h7631 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St", - v__h7639); + v__h7625); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -8085,15 +8085,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) begin - v__h111446 = $stime; + v__h111433 = $stime; #0; end - v__h111440 = v__h111446 / 32'd10; + v__h111427 = v__h111433 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h111440, + v__h111427, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -8153,15 +8153,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) begin - v__h111613 = $stime; + v__h111600 = $stime; #0; end - v__h111607 = v__h111613 / 32'd10; + v__h111594 = v__h111600 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h111607); + v__h111594); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0) @@ -8342,16 +8342,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h113716 = $stime; + v__h113703 = $stime; #0; end - v__h113710 = v__h113716 / 32'd10; + v__h113697 = v__h113703 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h113710); + v__h113697); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -9549,14 +9549,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h131062 = $stime; + v__h131049 = $stime; #0; end - v__h131056 = v__h131062 / 32'd10; + v__h131043 = v__h131049 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h131056); + $display("%0d: ERROR: CreditCounter: overflow", v__h131043); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) @@ -9580,7 +9580,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", mem_req_wr_addr_awaddr__h124971); + $write("'h%h", mem_req_wr_addr_awaddr__h124958); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9676,7 +9676,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", data64__h124886); + $write("'h%h", data64__h124873); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9684,7 +9684,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", strb8__h124887); + $write("'h%h", strb8__h124874); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9710,16 +9710,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) begin - v__h110827 = $stime; + v__h110814 = $stime; #0; end - v__h110821 = v__h110827 / 32'd10; + v__h110808 = v__h110814 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_rd_req_beat == 3'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d", - v__h110821, + v__h110808, llc_axi4_adapter_rg_rd_req_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -9807,7 +9807,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) - $write("'h%h", mem_req_rd_addr_araddr__h111047); + $write("'h%h", mem_req_rd_addr_araddr__h111034); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) @@ -9888,15 +9888,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) begin - v__h137757 = $stime; + v__h137744 = $stime; #0; end - v__h137751 = v__h137757 / 32'd10; + v__h137738 = v__h137744 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && NOT_llc_axi4_adapter_cfg_verbosity_read__599_U_ETC___d1616) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", - v__h137751, + v__h137738, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && @@ -9934,15 +9934,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) begin - v__h138265 = $stime; + v__h138252 = $stime; #0; end - v__h138259 = v__h138265 / 32'd10; + v__h138246 = v__h138252 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h138259); + v__h138246); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)