From bb62b703c8c901f08ee30c55f09a400c72fb6a2e Mon Sep 17 00:00:00 2001
From: Alexandre Joannou <aj443@cam.ac.uk>
Date: Thu, 30 Sep 2021 13:30:12 +0100
Subject: [PATCH] Address some rebase nonsense

---
 README.md                        |  2 +-
 src_Core/Core/CoreW.bsv          | 30 ++++++++++++++++++++----------
 src_SSITH_P3/src_BSV/P3_Core.bsv |  1 -
 src_Testbench/SoC/SoC_Top.bsv    |  2 +-
 4 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/README.md b/README.md
index 72e657c..adbf59b 100644
--- a/README.md
+++ b/README.md
@@ -92,7 +92,7 @@ library RTL can be found in the directory `src_bsc_lib_RTL`.
 **Bluespec BSV** source code (which was used to generate the Verilog RTL) can be found in:
 
 - `src_Core/`, for the CPU core, with sub-directories:
-   - `Core/`: the top-level of the CPU Core (specifically, the files CoreW_IFC.bsv and CoreW.bsv)
+   - `Core/`: the top-level of the CPU Core (specifically, CoreW.bsv)
    - `CPU/`: more CPU core sources
    - `RISCY_OOO/`: the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
    - `ISA/`:  generic types/constants/functions for the RISC-V ISA (not CPU-implementation-specific)
diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv
index 8e3e844..00627f1 100644
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -112,8 +112,10 @@ import DM_CPU_Req_Rsp ::*;
 // ================================================================
 // The Core module
 
-typedef WindCoreMid #( // AXI manager 0 port parameters
-                       TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
+typedef WindCoreMid #( // AXI lite subordinate control port parameters
+                       21, 32, 0, 0, 0, 0, 0
+                       // AXI manager 0 port parameters
+                     , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
                        // AXI manager 1 port parameters
                      , TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
                        // AXI subordinate 0 port parameters
@@ -241,6 +243,13 @@ module mkCoreW_reset #(Reset porReset)
    TV_Encode_IFC tv_encode <- mkTV_Encode;
 `endif
 
+   function do_release (restartRunning) = action
+      plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
+                         zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
+      proc.start (restartRunning, soc_map_struct.pc_reset_value, 0, 0);
+      //proc.set_verbosity (verbosity);
+   endaction;
+
    // ================================================================
    // Hart-reset from DM
 
@@ -485,6 +494,14 @@ module mkCoreW_reset #(Reset porReset)
       ndm_reset_restart_running <= restartRunning;
       fromDbgReset.send;
    endrule
+   rule rl_debug_module_count_reset_delay (ndm_reset_delay > 1);
+      ndm_reset_delay <= ndm_reset_delay - 1;
+   endrule
+   rule rl_debug_module_ack_reset (ndm_reset_delay == 1);
+      debug_module.ndm_reset_client.response.put (ndm_reset_restart_running);
+      do_release (ndm_reset_restart_running);
+      ndm_reset_delay <= 0;
+   endrule
 
    // ================================================================
    // Connect external interrupts to the PLIC and Proc
@@ -517,16 +534,9 @@ module mkCoreW_reset #(Reset porReset)
    let f_ctrl_reqs <- mkFIFO1;
    let f_ctrl_rsps <- mkFIFO1;
 
-   function do_release = action
-      plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
-                         zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
-      proc.start (True, soc_map_struct.pc_reset_value, 0, 0);
-      //proc.set_verbosity (verbosity);
-   endaction;
-
    rule rl_ctrl_req;
       case (f_ctrl_reqs.first) matches
-         tagged ReleaseReq: do_release;
+         tagged ReleaseReq: do_release (False);
          tagged StatusReq: $display ("StatusReq not supported in Toooba");
       endcase
       f_ctrl_reqs.deq;
diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index ef5be3e..6567511 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -44,7 +44,6 @@ import Fabric_Defs :: *;
 import PowerOnReset :: *;
 
 // The basic core
-import CoreW_IFC :: *;
 import CoreW     :: *;
 
 // External interrupt request interface
diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv
index daf6de8..414c3a7 100644
--- a/src_Testbench/SoC/SoC_Top.bsv
+++ b/src_Testbench/SoC/SoC_Top.bsv
@@ -59,7 +59,7 @@ import SoC_Map     :: *;
 
 import WindCoreInterface :: *;
 import CoreW     :: *;
-import PLIC      :: *;    // For interface to PLIC interrupt sources, in CoreW_IFC
+import PLIC      :: *;
 
 import Boot_ROM       :: *;
 import Mem_Controller :: *;